TC58FVM7(T/B)5B(TG/XG)65 TOSHIBA MOS DIGITAL INTEGRATE CIRCUIT SILICON GATE CMOS 128M (8M x 16 BITS) CMOS FLASH MEMORY 1. DESCRIPTION Lead-Free The TC58FVM7(T/B)5B is a 134217728-bit, 3V read-only electrically erasable and programmable flash memory organized as 8388608 x 16 bits. The TC58FVM7(T/B)5B features commands for Read, Program and Erase operations to allow easy interfacing with microprocessors. The commands are based on the JEDEC standard. The Program and Erase operations are automatically executed in the chip. The TC58FVM7(T/B)5B also features a Simultaneous Read/Write operation so that data can be read during a Write or Erase operation. 2. FEATURES * * * * Power supply voltage VDD = 2.7V to 3.6V Operating ambient temperature Ta = -40C to 85C Organization 8M x 16 Bits Functions Simultaneous Read/Write Page Read Auto Program, Auto Page Program Auto Block Erase, Auto Chip Erase Fast Program Mode/Acceleration Mode Program Suspend/Resume Erase Suspend/Resume Data polling/Toggle bit Password block protection Block protection/ Boot block protection Automatic Sleep, support for hidden ROM area Common Flash memory Interface (CFI) * * * * * * * * * * Block erase architecture 8 x 8 Kbytes / 255 x 64 Kbytes Bank architecture 8M Bits x 16 Bank Boot Block architecture TC58FVM7T5B ... top boot block TC58FVM7B5B ... bottom boot block Mode control Compatible with JEDEC standard commands Erase/Program cycles 105 cycles typ Access Time (Random/Page) 65ns / 25ns (CL=30pF) 70ns / 30ns (CL=100pF) Page Length: 8 words Power consumption 10 A (Standby) 15mA (Program/Erase operation) 5mA (Page Read operation) 55mA (Random Read operation) 11mA (Address Increment Read operation) Package TC58FVM7(T/B)5BTG TSOP 56-P-1420-0.50 (weight: 0.60g) TC58FVM7(T/B)5BXG P-TFBGA80-0810-0.80AZ (weight: 0.157g) Lead-Free 2006-05-10 1/88 TC58FVM7(T/B)5B(TG/XG)65 TABLE OF CONTENTS 128M (8M x 16 BITS) CMOS FLASH MEMORY ................................................................................................................................ 1 1. DESCRIPTION................................................................................................................................................................................. 1 2. FEATURES ...................................................................................................................................................................................... 1 3. ORDERING INFORMATION.......................................................................................................................................................... 3 4. PIN ASSIGNMENT (TOP VIEW) ................................................................................................................................................... 4 5. BLOCK DIAGRAM........................................................................................................................................................................... 5 6. MODE SELECTION ........................................................................................................................................................................ 6 7. ID CODE TABLE ............................................................................................................................................................................. 6 8. COMMAND SEQUENCES .............................................................................................................................................................. 7 9. SIMULTANEOUS READ/WRITE OPERATION............................................................................................................................ 9 10. OPERATION MODES.................................................................................................................................................................. 10 10.1. Read Mode.............................................................................................................................................................................. 10 10.2. ID Read Mode......................................................................................................................................................................... 10 10.3. Standby Mode ........................................................................................................................................................................ 10 10.4. Auto-Sleep Mode .................................................................................................................................................................... 10 10.5. Output Disable Mode............................................................................................................................................................. 10 10.6. Command Write ......................................................................................................................................................................11 10.7. Software Reset: Read/Reset Command..................................................................................................................................11 10.8. Hardware Reset ......................................................................................................................................................................11 10.9. Comparison between Software Reset and Hardware Reset..................................................................................................11 10.10. Auto-Program Mode............................................................................................................................................................. 12 10.11. Auto-Page Program Mode .................................................................................................................................................... 12 10.12. Fast Program Mode ............................................................................................................................................................. 12 10.13. Acceleration Mode ................................................................................................................................................................ 12 10.14. Program Suspend/Resume Mode ........................................................................................................................................ 13 10.15. Auto Chip Erase Mode ......................................................................................................................................................... 13 10.16. Auto Block Erase/Auto Multi-Block Erase Modes .............................................................................................................. 13 10.17. Erase Suspend/Erase Resume Modes ................................................................................................................................. 14 10.18. Block Protection ................................................................................................................................................................... 15 10.19. Hidden ROM Area................................................................................................................................................................ 20 10.20. CFI (Common Flash memory Interface) ............................................................................................................................. 21 10.21. HARDWARE SEQUENCE FLAGS..................................................................................................................................... 24 11. DATA PROTECTION................................................................................................................................................................... 26 11.1. Protection against Program/Erase Caused by Low Supply Voltage .................................................................................... 26 11.2. Protection against Malfunction Caused by Glitches ............................................................................................................ 26 11.3. Protection against Malfunction at Power-on ........................................................................................................................ 26 12. ABSOLUTE MAXIMUM RATINGS............................................................................................................................................ 27 13. CAPACITANCE (TA = 25C, F = 1 MHZ) ..................................................................................................................................... 27 14. RECOMMENDED DC OPERATING CONDITIONS................................................................................................................. 27 15. DC CHARACTERISTICS............................................................................................................................................................. 28 16. AC TEST CONDITIONS.............................................................................................................................................................. 28 17. AC CHARACTERISTICS AND OPERATING CONDITIONS ................................................................................................... 29 17.1. Read Cycle.............................................................................................................................................................................. 29 17.2. Block Protect .......................................................................................................................................................................... 30 17.3. Program and Erase characteristics....................................................................................................................................... 30 17.4. Command Write/Program/Erase cycle .................................................................................................................................. 31 18. TIMING DIAGRAMS ................................................................................................................................................................... 32 19. FLOWCHARTS ............................................................................................................................................................................ 48 20. BLOCK ADDRESS TABLES ....................................................................................................................................................... 65 20.1. TC58FVM7T5B (Top Boot Block) 1/9 ................................................................................................................................. 65 20.2. TC58FVM7B5B (Bottom Boot Block) 1/9 ........................................................................................................................... 74 21. BLOCK SIZE TABLE................................................................................................................................................................... 83 21.1. TC58FVM7T5B (Top Boot Block) .......................................................................................................................................... 83 21.2. TC58FVM7B5B (Bottom Boot Block).................................................................................................................................... 84 22. PACKAGE DIMENSIONS........................................................................................................................................................... 85 2006-05-10 2/88 TC58FVM7(T/B)5B(TG/XG)65 3. ORDERING INFORMATION TC58 F V M7 T 5 B XG 65 Speed version 65 = 65ns Package TG = TSOP XG = BGA Design rule B = 0.13 m Function/Bank size 4 = Page/Burst /8M Uniform bank 5 = Page/8M Uniform bank Boot block architecture T = Top boot block B = Bottom boot block Capacity M7 = 128Mbits Supply Voltage V = 3 V system Y = 1.8 V system Device type F = NOR Flash memory 2 Toshiba CMOS E PROM Ordering type Function Boot Block TC58FVM7T5BXG65 Top TC58FVM7B5BXG65 Bottom TC58FVM7T5BTG65 TC58FVM7B5BTG65 Page Top Bottom Speed version Package P-TFBGA80-0810-0.80AZ (Lead-free) 65 ns TSOPI56-P-1420-0.50 (Lead-free) 2006-05-10 3/88 TC58FVM7(T/B)5B(TG/XG)65 4. PIN ASSIGNMENT (TOP VIEW) PIN NAME TC58FVM7T5BTG / TC58FVM7B5BTG A0~A22 N.C A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE RESET A21 WP / ACC RY / BY A18 A17 A7 A6 A5 A4 A3 A2 A1 N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 N.C N.C A16 N.C VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 N.C N.C Address Input DQ0~DQ15 Data Input/Output CE Chip Enable Input OE Output Enable Input WE Write Enable Input RY / BY Ready/Busy Output RESET Hardware Reset Input WP / ACC Write Protect/ Program Acceleration Input VDD Power Supply VSS Ground N.C No Connection TC58FVM7T5BXG / TC58FVM7B5BXG 1 2 3 4 5 6 7 8 A NC NC NC NC B NC NC NC NC C NC A3 A7 D NC A4 A17 E NC A2 A6 F NC A1 G NC A0 WE A9 A13 NC WP / ACC RESET A8 A12 A22 A18 A21 A10 A14 NC A5 A20 A19 A11 A15 NC DQ0 DQ2 DQ5 DQ7 A16 NC DQ12 DQ14 NC NC DQ15 NC RY / BY H NC C DQ8 DQ10 J NC OE DQ9 DQ11 VDD DQ13 K NC VSS DQ1 DQ3 DQ4 DQ6 VSS NC L NC NC NC NC M NC NC NC NC 2006-05-10 4/88 TC58FVM7(T/B)5B(TG/XG)65 5. BLOCK DIAGRAM VDD VSS RY / BY DQ0 RY/BY Buffer WP /ACC DQ15 I/O Buffer Control Circuit WE Data Latch RESET CE Command Register Memory Cell Array Memory Cell Array Memory Cell Array Memory Cell Array Bank 0 Bank 1 Bank 14 Bank 15 Address Latch A0 Address Buffer OE A22 2006-05-10 5/88 TC58FVM7(T/B)5B(TG/XG)65 6. MODE SELECTION MODE CE OE WE A9 A6 A1 A0 RESET WP/ACC DQ0~DQ15 Read/Page Read L L H A9 A6 A1 A0 H * DOUT ID Read (Manufacturer Code) L L H VID L L L H * Code ID Read (Device Code) L L H VID L L H H * Code Standby H * * * * * * H * High-Z Output Disable * H H * * * * * * High-Z A9 A6 A1 A0 H * DIN VID L H L H * * (1) Write L H Block Protect 1 L VID Block Protect 2 L H H * L H L VID * * Verify Block Protect L L H VID L H L H * Code Temporary Block Unprotect * * * * * * * VID * * Hardware Reset/Standby * * * * * * * L * High-Z Boot Block Protect * * * * * * * * L * (1) Notes: * = VIH or VIL, L = VIL, H = VIH (1) Pulse input 7. ID CODE TABLE CODE TYPE A22~A12 A6 A1 A0 CODE (HEX) X L L L 0098h TC58FVM7T5B X L L H 001Bh TC58FVM7B5B X L L H 001Dh L H L Data Manufacturer Code Device Code Verify Block Protect (1) BA (2) Notes : X: VIH or VIL L: VIL H: VIH (1) BA: Block Address (2) 0001h-Protected Block 0000h- Unprotected Block 2006-05-10 6/88 TC58FVM7(T/B)5B(TG/XG)65 8. COMMAND SEQUENCES BUS FIRST BUS SECOND BUS THIRD BUS FOURTH BUS FIFTH BUS SIXTH BUS COMMAND WRITE WRITE CYCLE WRITE CYCLE WRITE CYCLE WRITE CYCLE WRITE CYCLE WRITE CYCLE SEQUENCE CYCLES Addr. Data Addr. Data Addr. Data Addr. 2AAh 55h 555h F0h RA 90h IA REQ'D Read/Reset 1 XXXh F0h Read/Reset 3 555h AAh (3) BK + (1) (4) ID Read 3 555h AAh 2AAh 55h Auto Program 4 555h AAh 2AAh 55h 555h A0h PA Auto Page Program 11 555h AAh 2AAh 55h 555h E6h PA Program Suspend 1 BK Program Resume 1 BK Auto Chip Erase 6 555h 2AAh 55h 555h 80h 555h (3) (3) (6) Data Addr. 6 555h 1 BK Block Erase Resume 1 BK 30h Fast Program Set 3 555h AAh (2) RD (5) ID (7) PD (7) PD (6) PA (7) PD (6) PA AAh 2AAh 55h 555h 80h 2AAh 55h 555h 20h 60h XXXh 40h 555h AAh AAh 2AAh 55h 555h 2AAh 55h BA (8) (6) XXXh A0h PA PD Fast Program Reset 2 XXXh 90h XXXh F0h 3 XXXh 60h 3 555h AAh 2AAh 55h 555h 88h 4 555h AAh 2AAh 55h 555h A0h PA 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h BA 5 555h AAh 2AAh 55h 555h 60h XX1Ah 68h XX1Ah 48h RA 4 555h AAh 2AAh 55h 555h 90h XXXh 00h 98h CA Hidden ROM Mode Entry Hidden ROM Program Hidden ROM Erase Hidden ROM Protect Hidden ROM Exit (3) CFI 1 BK 55h + 10h 30h (7) 2 (10) (7) PD B0h Fast Program Block Protect 2 Data 30h AAh Block Erase Suspend (3) (6) Addr. B0h Auto Block Erase (3) 555h Data (11) BPA (13) (9) (6) (12) BPD (7) PD (8) (1) 30h (2) RD (14) CD Notes: The system should generate the following address patterns: (7) 555h or 2AAh on address pins A10~A0. DQ8~DQ15 are ignored. X : VIH or VIL (0h-Fh) (1) RA: Read Address (2) RD: Read Data Output (3) BK: Bank Address = A22~A19 (4) IA: Bank Address and ID Read Address (A6,A1,A0) Bank Address = A22~A19 Manufacturer Code = (0,0,0) Device Code = (0,0,1) (5) ID: ID Code Output (6) PA: Program Address Input Input continuous 8 addresses from (A0, A1, A2) = (0, 0, 0) to (A0, A1, A2) = (1, 1, 1) in Page program. (11) BPA (8) (9) (10) (11) (12) (13) (14) PD: Program Data Input Input continuous 8 address from (A0, A1, A2) = (0, 0, 0) to (A0, A1, A2) = (1, 1, 1) in Page program. BA: Block Address = A22~A12 F0h: 00h is valid too. Input VID to RESET BPA: Block Address and ID Read Address (A6,A1,A0) Block Address = A22~A12 ID Read Address = (0,1,0) BPD: Verify data Output CA: CFI Address CD: CFI Data Output : Read Operations 2006-05-10 7/88 TC58FVM7(T/B)5B(TG/XG)65 8. COMMAND SEQUENCES(continue) BUS FIRST BUS SECOND BUS THIRD BUS FOURTH BUS FIFTH BUS SIXTH BUS SEVENTH BUS COMMAND WRITE WRITE CYCLE WRITE CYCLE WRITE CYCLE WRITE CYCLE WRITE CYCLE WRITE CYCLE WRITE CYCLE SEQUENCE CYCLES Addr. Data Addr. Data Addr. Data Addr. 555h AAh 2AAh 55h 555h 38h XX0h PD0 555h AAh 2AAh 55h 555h 38h XX1h PD1 555h AAh 2AAh 55h 555h 38h XX2h PD2 555h AAh 2AAh 55h 555h 38h XX3h PD3 XX0h PD0 REQ'D Password Program Data 4 Addr. (1) 2AAh 55h 555h 28h Password Verify 3 555h AAh 2AAh 55h 555h C8h 5 555h AAh 2AAh 55h 555h 60h X0Ah 68h X0Ah 5 555h AAh 2AAh 55h 555h 60h X12h 68h X12h 5 555h AAh 2AAh 55h 555h 60h 5 555h AAh 2AAh 55h 555h 60h 3 555h AAh 2AAh 55h (5) ALL PPB Clear Verify Block Protect BA XX02h XX1h (5) (5) BA + 555h 90h BA 3 555h AAh 2AAh 55h 555h 78h PPB Lock Verify 3 555h AAh 2AAh 55h 555h 58h BA DPB Set 4 555h AAh 2AAh 55h 555h 48h BA DPB Clear 4 555h AAh 2AAh 55h 555h 48h BA 3 555h AAh 2AAh 55h 555h 58h + XX02h (5) (5) (5) (5) BA (1) PD1 (1) XX2h PD2 48h XXh PD(0) 48h XXh PD(0) 48h XXh PD(0) 40h XXh PD(0) XX3h (1) PD3 (3) PWD (5) BA 68h BA 60h PD(0) PD(1) + XX02h (5) XX02h PPB Lock Set DPB Verify + Data (1) AAh PPB Set Addr. (1) 555h Password Protection Mode Lock Non-Password Protection Mode Lock Data (1) 7 (2) Addr. (1) Password Unlock PWA Data + XX02h (4) (4) (4) (4) (4) (4) X1h X0h PD(0) (4) Notes: The system should generate the following address patterns: 555h or 2AAh on address pins A10~A0. DQ8~DQ15 are ignored. X : VIH or VIL (0h-Fh) (1) PD0 : 1st Password (Data of 1-16bit) PD1 : 2nd Password (Data of 17-32bit) PD2 : 3rd Password (Data of 33-48bit) PD3 : 4th Password (Data of 49-64bit) (2) PWA: Password Address Input (3) PWD: Password Data Output (4) PD(0): Data (1: Set/ 0: Reset) on DQ0. PD(1): Data (1: Set/ 0: Reset) on DQ1. (5) BA: Block Address = A22~A12 : Read Operations 2006-05-10 8/88 TC58FVM7(T/B)5B(TG/XG)65 9. SIMULTANEOUS READ/WRITE OPERATION The TC58FVM7(T/B)5B features a Simultaneous Read/Write operation. The Simultaneous Read/Write operation enables the device to simultaneously write data to or erase data from a bank while reading data from another bank. The TC58FVM7(T/B)5B has a total of sixteen banks (8Mbits x 16 Banks). Banks can be switched by using the bank addresses (A22~A19). For a description of bank blocks and addresses, please refer to the Block Address Table and Block Size Table. The Simultaneous Read/Write operation cannot perform multiple operations within a single bank. The table below shows the operation modes in which simultaneous operation can be performed. Note that during Auto-Program execution or Auto Block Erase operation, the Simultaneous Read/Write operation cannot read data from addresses in the same bank which have not been selected for operation. Data from these addresses can be read using the Program Suspend or Erase Suspend function, however. In order to perform simultaneous operation during automatic operation execution, when changing a bank, it is necessary to set OE to VIH. SIMULTANEOUS READ/WRITE OPERATION STATUS OF BANK ON WHICH OPERATION IS BEING PERFORMED STATUS OF OTHER BANKS Read Mode (1) ID Read Mode Auto-Program Mode Auto-Page Program Mode (2) Fast Program Mode Program Suspend Mode Read Mode Auto Block Erase Mode Auto Multiple Block Erase Mode (3) Erase Suspend Mode Program during Erase Suspend Program Suspend during Erase Suspend CFI Mode (1) Only Command Mode is valid. (2) Excluding times when Acceleration Mode is in use. (3) If the selected blocks are spread across all sixteen banks, simultaneous operation cannot be carried out. 2006-05-10 9/88 TC58FVM7(T/B)5B(TG/XG)65 10. OPERATION MODES In addition to the Read, Write and Erase Modes, the TC58FVM7(T/B)5B features many functions including block protection and data polling. When incorporating the device into a design, please refer to the timing charts and flowcharts in combination with the descriptions below. 10.1. Read Mode To read data from the memory cell array, set the device to Read Mode. The device is automatically set to Read Mode immediately after power-on or on completion of an automatic operation. The Software Reset Command releases The ID Read Mode, releases the lock state when an automatic operation ends abnormally, and sets the device to Read Mode. Hardware Reset terminates operation of the device and resets it to Read Mode. When reading data without changing the address immediately after power-on, the host should input Hardware Reset or change CE from H to L. 10.2. ID Read Mode ID Read Mode is used to read the device maker code and device code. The mode is useful in that it allows EPROM programmers to identify the device type automatically. Access time in ID Read Mode is the same as that in Read Mode. For a list of the codes, please refer to the ID Code Table. ID read can be executed in two ways, as follows: (1) Applying VID to A9 Mainly EPROM programmers use this method. Applying VID to A9 sets the device to ID Read Mode, outputting the maker code from address 00h and the device code from address 01h. Releasing VID from A9 returns the device to Read Mode. With this method, all banks are set to ID Read Mode; thus, simultaneous operation cannot be performed. (2) Input command sequence With this method simultaneous operation can be performed. Inputting an ID Read command sets the specified bank to ID Read Mode. Banks are specified by inputting the bank address (BK) in the third Bus Write cycle of the Command cycle. To read an ID code, the bank address as well as the ID read address must be specified (with WP/ACC = VIH or VIL). The maker code is output from address BK + 00; the device code is output from address BK + 01. From other banks, data is output from the memory cells. Inputting a Reset command releases ID Read Mode and returns the device to Read Mode. 10.3. Standby Mode TC58FVM7(T/B)5B has two ways to put the device into Standby Mode. In Standby Mode, DQ is put into the High-Impedance state. (1) Control using CE and RESET With the device in Read Mode, input VDD 0.3 V to CE and RESET . The device will enter Standby Mode and the current will be reduced to the standby current (IDDS1). However, if the device is in the process of performing simultaneous operation, the device will not enter Standby Mode but will instead cause the operating current to flow. (2) Control using RESET only With the device in Read Mode, input VSS 0.3 V to RESET . The device will enter Standby Mode and the current will be reduced to the standby current (IDDS1). Even if the device is in the process of performing simultaneous operation, this method will terminate the current operation and set the device to Standby Mode. This is a hardware reset and is described later. 10.4. Auto-Sleep Mode This function suppresses power dissipation during reading. If the address input does not change for 150 ns, the device will automatically enter Sleep Mode and the current will be reduced to the standby current (IDDS2). However, if the device is in the process of performing simultaneous operation, the device will not enter Standby Mode but will instead cause the operating current to flow. Because the output data is latched, data is output in Sleep Mode. When the address is changed, Sleep Mode is automatically released, and data from the new address is output. 10.5. Output Disable Mode Inputting VIH to OE disables output from the device and sets DQ to High-Impedance. 2006-05-10 10/88 TC58FVM7(T/B)5B(TG/XG)65 10.6. Command Write The TC58FVM7(T/B)5B uses the standard JEDEC control commands for a single-power supply E2PROM. A Command of Write is executed by inputting the address and data into the Command Register. The command is written by inputting a pulse to WE with CE = VIL and OE = VIH ( WE control). The command can also be written by inputting a pulse to CE with WE = VIL ( CE control). The address is latched on the falling edge of either WE or CE . The data is latched on the rising edge of either WE or CE . DQ0~DQ7 are valid for data input and DQ8~DQ15 are ignored. To abort input of the command sequence uses the Reset command. The device will reset the Command Register and enter Read Mode. If an undefined command is input, the Command Register will be reset and the device will enter Read Mode. 10.7. Software Reset: Read/Reset Command Initiate the software reset by inputting a Read/Reset command. The software reset returns the device from ID Read Mode or CFI Mode to Read Mode, releases the lock state if automatic operation has ended abnormally, and clears the Command Register. 10.8. Hardware Reset A hardware reset initializes the device and sets it to Read Mode. When a pulse is input to RESET for tRP, the device abandons the operation which is in progress and enters the Read Mode after tREADY. Note that if a hardware reset is applied during data overwriting, such as a Write or Erase operation, data at the address or block being written to at the time of the reset will become undefined. After a hardware reset, the device enters Read Mode if RESET = VIH or Standby Mode if RESET = VIL. The DQ pins are High-Impedance when RESET = VIL. After the device has entered Read Mode, Read operations and input of any command are allowed. 10.9. Comparison between Software Reset and Hardware Reset ACTION SOFTWARE RESET HARDWARE RESET Releases ID Read Mode or CFI Mode. True True Clears the Command Register. True True Releases the lock state if automatic operation has ended abnormally. True True Stops any automatic operation which is in progress. False True Stops any operation other than the above and returns the device to Read Mode. False True 2006-05-10 11/88 TC58FVM7(T/B)5B(TG/XG)65 10.10. Auto-Program Mode The TC58FVM7(T/B)5B can be programmed in word units. Auto-Program Mode is set using the Program command. The program address and program data is latched in the fourth Bus Write cycle. Auto programming starts on the rising edge of the WE signal in the fourth Bus Write cycle. The Program and Program Verify commands are automatically executed by the chip. The device status during programming is indicated by the Hardware Sequence flag. To read the Hardware Sequence flag, specify the address to which the Write is being performed. During Auto Program execution, a command sequence for the bank on which execution is being performed cannot be accepted. To terminate execution, use a hardware reset. Note that if the Auto-Program operation is terminated in this manner, the data written so far is invalid. Any attempt to program a protected block is ignored. In this case, the device enters Read Mode 3 s after a latch of program data in the fourth Bus Write cycle. If an Auto-Program operation fails, the device remains in the programming state and does not automatically return to Read Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or a hardware reset is required to return the device to Read Mode after a failure. If a programming operation fails, the device should not be used. To build a more reliable system, the host processor should take measures to prevent subsequent use of failed blocks. The device allows 0s to be programmed into memory cells which contain a 1. 1s cannot be programmed into cells which contain 0s. If this is attempted, execution of Auto Program will fail. This is a user error, not a device error. A cell containing 0 must be erased in order to set it to 1. 10.11. Auto-Page Program Mode Auto-Page Program is a function which enables simultaneously Programming or 8words of data. In this mode, the Programming time for 128M bit is less than 60% compared with the Auto program mode. In word mode, input the page program command during first bus write cycle to third bus writes cycle. Input program data and address of (A0, A1, A2) = (0, 0, 0) in the forth bus write cycle. Input increment address and program data during the fifth bus write cycle to the eleventh bus write cycle. After input of the eleventh bus write cycle, page program operation starts. 10.12. Fast Program Mode Fast Program is a function which enables execution of the command sequence for the Auto Program to be completed in two cycles. In this mode the first two cycles of the command sequence, which normally requires four cycles, are omitted. Writing is performed in the remaining two cycles. To execute Fast Program, input the Fast Program command. Writes in this mode uses the Fast Program command but operation is the same at that for ordinary Auto-Program. The status of the device is indicated by the Hardware Sequence flag and read operations can be performed as usual. To exit this mode, the Fast Program Reset command must be input. When the command is input, the device will return to Read Mode. 10.13. Acceleration Mode The TC58FVM7(T/B)5B features an Acceleration Mode that allows write time to be reduced. Applying VACC pin to WP/ACC automatically sets the device to Acceleration Mode. In Acceleration Mode, Block Protect Mode changes to Temporary Block Unprotect Mode. Write Mode changes to Fast Program Mode. Modes are switched by the WP/ACC signal; thus, there is no need for a Temporary Block Unprotect operation or to set or reset Fast Program Mode. Operation of Write is the same as in Auto-Program Mode. Removing VACC from WP/ACC terminates Acceleration Mode. This function can perform only Auto Program Mode and Auto Page Program Mode. ID Read or other commands cannot be done. 2006-05-10 12/88 TC58FVM7(T/B)5B(TG/XG)65 10.14. Program Suspend/Resume Mode Program Suspend is used to enable Data Read by suspending the Write operation. The device accepts a Program Suspend command in Write Mode (including Write operations performed during Erase Suspend) but ignores the command in other modes. When the command is input, the address of the bank on which Write is being performed must be specified. In Program Suspend Mode, it is invalid except a Read command, a ID Read command, a CFI command, and a Resume command. After input of the command, the device will enter Program Suspend Read Mode after tSUSP. During Program Suspend, Cell Data Read, ID Read and CFI Data Read can be performed. When Data Write is suspended, the address to which Write was being performed becomes undefined. ID Read and CFI Data Read are the same as usual. After completion of Program Suspend, input a Program Resume command to return to Write Mode. When inputting the command, specify the address of the bank on which Write is being performed. If the ID Read or CFI Data Read function is being used, abort the function before inputting the Resume command. On receiving the Resume command, the device returns to Write Mode and resumes outputting the Hardware Sequence flag for the bank to which data is being written. Program Suspend can be run in Fast Program Mode or Acceleration Mode. However, note that when running Program Suspend in Acceleration Mode, VACC must not be released. 10.15. Auto Chip Erase Mode The Auto Chip Erase Mode is set using the Chip Erase command. An Auto Chip Erase operation starts on the latch of the command in the sixth bus cycle. All memory cells are automatically preprogrammed to 0, erased and verified as erased by the chip. The device status is indicated by the Hardware Sequence flag. Command input is ignored during an Auto Chip Erase. A hardware reset can interrupt an Auto Chip Erase operation. If an Auto Chip Erase operation is interrupted, it cannot be completed correctly. Hence, an additional Erase operation must be performed. Any attempt to erase a protected block is ignored. If all blocks are protected, the Auto Erase operation will not be executed and the device will enter Read mode 400 s after the latch of command in the sixth bus cycle. If an Auto Chip Erase operation fails, the device will remain in the erasing state and will not return to the Read Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or a hardware reset is required to return the device to Read Mode after a failure. In this case, it cannot be ascertained which block the failure occurred in. Either abandon use of the device altogether, or perform a Block Erase on each block, identify the failed blocks, and stop using them. To build a more reliable system, the host processor should take measures to prevent subsequent use of failed blocks 10.16. Auto Block Erase/Auto Multi-Block Erase Modes The Auto Block Erase Mode and Auto Multi-Block Erase Mode are set using the Block Erase command. The block address is latched in the sixth bus cycle. The auto block erase starts as soon as the Erase Hold Time (tBEH) has elapsed after the latch of the command. When multiple blocks are erased, the sixth Bus Write cycle is repeated with each block address and Auto Block Erase command being input within the Erase Hold Time (this constitutes an Auto Multi-Block Erase operation). If a command other than an Auto Block Erase command or Erase Suspend command is input during the Erase Hold Time, the device will reset the Command Register and enter Read Mode. The Erase Hold Time restarts on each successive command latch. Once operation starts, all memory cells in the selected block are automatically preprogrammed to 0, erased and verified as erased by the chip. The device status is indicated by the setting of the Hardware Sequence flag. When the Hardware Sequence flag is read, the addresses of the blocks on which auto-erase operation is being performed must be specified. If the selected blocks are spread across all 16 banks, simultaneous operation cannot be carried out. All commands (except Erase Suspend) are ignored during an Auto Block Erase or Auto Multi-Block Erase operation. Either operation can be aborted using a Hardware Reset. If an auto-erase operation is interrupted, it cannot be completed correctly; therefore, a further erase operation is necessary to complete the erasing. Any attempt to erase a protected block is ignored. If all the selected blocks are protected, the auto-erase operation is not executed and the device returns to Read Mode 400 s after the latch of command in the last bus cycle. If an auto-erase operation fails, the device remains in the Erasing state and does not return to Read Mode. The device status is indicated by the Hardware Sequence flag. After a failure, either a Reset command or a Hardware Reset is required to return the device to Read Mode. If multiple blocks are selected, it will not be possible to ascertain the block in which the failure occurred. In this case either abandon use of the device altogether, or perform a Block Erase on each block, identify the failed blocks, and stop using them. To build a more reliable system, the host processor should take measures to prevent subsequent use of failed blocks. 2006-05-10 13/88 TC58FVM7(T/B)5B(TG/XG)65 10.17. Erase Suspend/Erase Resume Modes Erase Suspend Mode suspends Auto Block Erase and reads data from or writes data to an unselected block. The Erase Suspend command is allowed during an auto block erase operation but is ignored in all other oreration modes. When the command is input, the address of the bank on which Erase is being performed must be specified. In Erase Suspend Mode, it is invalid except a Read command, a ID Read command, a CFI command, a Program command, and a Resume command. If an Erase Suspend command is input during an Auto Block Erase, the device will enter Erase Suspend Read Mode after tSUSE. The device status (Erase Suspend Read Mode) can be verified by checking the Hardware Sequence flag. If data is read consecutively from the block selected for Auto Block Erase, the DQ2 output will toggle and the DQ6 output will stop toggling and RY/ BY will be set to High-Impedance. Inputting a Write command during an Erase Suspend enables a Write to be performed to a block which has not been selected for the Auto Block Erase. Data is written in the usual manner. To resume the Auto Block Erase, input an Erase Resume command. On input of the command, the address of the bank on which the Write was being performed must be specified. On receiving an Erase Resume command, the device returns to the state it was in when the Erase Suspend command was input. If an Erase Suspend command is input during the Erase Hold Time, the device will return to the state it was in at the start of the Erase Hold Time. At this time more blocks can be specified for erasing. If an Erase Resume command is input during an Auto Block Erase, Erase resumes. At this time toggle output of DQ6 resumes and 0 is output on RY/ BY . 2006-05-10 14/88 TC58FVM7(T/B)5B(TG/XG)65 10.18. Block Protection TC58FVM7(T/B)5B has Block Protection that is a function for disabling writing and erasing specific blocks. Block Protection features several level of Block Protection. (1) Write Protect ( WP/ACC pin) [Hardware Protection] The TC58FVM7(T/B)5B has Hardware Block protection feature by WP/ACC =VIL. The TC58FVM7T5B protects BA261 and BA262 with WP/ACC =VIL. TC58FVM7B5B protects BA0 and BA1 with WP/ACC =VIL. This mode is released with WP/ACC =VIH. When the device is programming operation or erasing operation, WP/ACC pin has to fix to VIH or VIL. (2) Block protection 1 Persistent Protection Bit (PPB) [VID Protection] Specify a device block address and make the following signal settings A9= OE =VID, A1 = VIH and CE = A0 = A6 = VIL. Now when a pulse is input to WE for tPPLH, the device will start to write to the block protection circuit. Block protection can be verified using the Verify Block Protect command. Inputting VIL on OE sets the device to Verify Mode. 01h is output if the block is protected and 00h is output if the block is unprotected. If block protection was unsuccessful, the operation must be repeated. Releasing VID from A9 and OE terminates this mode. When the device state is Password Protection Mode, the hosts have to execute the Password Unlock command before performing this protection command. (3) Block protection 2 Persistent Protection Bit (PPB) [VID Protection] Inputting the Block Protect 2 command with RESET =VID also performs block protection. The first cycle of the command sequence is the Set-up command. In the second cycle, the Block Protect command is input, in which a block address and A1 = VIH and A0 = A6 = VIL are input. Now the device writes to the block protection circuit. There is a wait of tPPLH until this write is completed; however, no intervention is necessary during this time. In the third cycle the Verify Block Protect command is input. This command verifies the write to the block protection circuit. Read is performed in the fourth cycle. If the protection operation is complete, 01h is output. If a value other than 01h is output, block protection is not complete and the Block Protect command must be input again. Removing the VID input from RESET , exits this mode. When the device state is Password Protection Mode, the hosts have to execute the Password Unlock command before performing this protection command. (4) Block Protection 3 Persistent Protection Bit(PPB) [Software Protection] This feature is the block protection without VID. By using Persistent Protection Bit, protection can be set to each block. The PPBs retains the state across power cycle. Each PPB can be individually modifiable through the PPB Set command. All PPB can be cleared by the PPB Clear Command at a time. The PPB Verify command to the device can check the PPB status. The 5th and 6th write bus cycle of the PPB Set are PPB Verify cycle. When completely finish the PPB Set, the device outputs `1' on DQ0 at the sixth bus write cycle. When device outputs `0' on DQ0, the PPB Set is not complete, then the hosts must retry from fourth bus write cycle. Similarly, when completely finish the PPB Clear, the device outputs `0' on DQ0 at the sixth bus write cycle. When the device outputs `1' on DQ1, the PPB Clear is not complete, then the hosts must retry from fourth bus write cycle. When PPB is locked by the PPB Lock Set command, PPB is disabled for PPB Set and PPB Clear Operation. The PPB Lock Verify command can check the PPB Lock status on the DQ1 (`1' is Set state and `0' is Clear state). Behaviors of PPB Lock differ between password protection mode and non-password protection mode. At the time of the finishing PPB Set, PPB Clear, PPB Lock Set and PPB Lock Verify, the hosts have to inputting the Hidden ROM Exit command. At the time of shipment, the PPBs and PPB Lock are settled to "0". (5) Block Protection 4 Dynamic Protection Bit (DPB) [Software Protection] This feature is the block protection without VID. By using Dynamic Protection Bit, protection can be set to each block. After power-up or hardware reset cycle, all DPB are settled to "0" as clear. Each DPB can be individually modifiable through the DPB Set command and DPP Clear command. The Writing of the DPB Verify command to the device can check the Set or Clear of the DPB status. When completely finish the DPB Set, device will be outputting `1' on DQ0 at the fourth bus write cycle in the DPB verify. When Device is outputting `0' on DQ0, the DPB Set is not complete, then the hosts must retry from the DPB set command. Similarly, when completely finish the DPB Clear, the device will be outputting `0' on DQ0 at the fourth bus write cycle in the DPB verify. When the device is outputting `1' on DQ0, the DPB Clear is not complete, then the user must retry from the DPB clear command. At the time of the finishing DPB Set, DPB Clear, and DPB Verify, the hosts have to inputting the Hidden ROM Exit command. 2006-05-10 15/88 TC58FVM7(T/B)5B(TG/XG)65 10.18.1 Relationship of the Each Block Protection Block Protection 3 (PPB) (Non-Password Protection mode) Block Protection 1 Block Protection 2 Block Protection 3 (PPB) (Password Protection mode) Power-Up Power-Up Power-Up PPB Lock is a cleared state PPB Lock is a set state (PPB Set/Clear is enabled) (PPB Set/Clear is disabled) Power-up cycle or Hardware Reset Block Protection 4 (DPB) DPB is a cleared state Password Unlock Command PPB Lock is a cleared state Power-up cycle or PPB Lock Set or Hardware Reset (PPB Set/Clear is enabled) PPB Lock is a set state (PPB Set/Clear is disabled) PPB Lock Set Command PPB Set PPB Set DPB Set PPB Clear DPB Clear Device Protect State * A program of one of PPB and the DPB protects an object block. 10.18.2. Block Protection Matrix Hardware Protection WP/ACC L RESET PPB DPB H Clear Set Clear X X X Clear Set Set X Clear X VID H Software Protection H X Set VID X X Notes X: H or L, Set state or Clear state Block Protect Status Two Boot Block Other Block Unprotected Protected Protected Unprotected Unprotected Unprotected Protected Protected Unprotected Unprotected 2006-05-10 16/88 TC58FVM7(T/B)5B(TG/XG)65 10.18.3. Non-Password Protection Mode and Password Protection Mode At Block Protection 3, there are two Protection Mode of Non-Password Protection Mode and Password Protection Mode. Operation of a PPB lock differs in each mode. The hosts need to choose either Non-Password Protection Mode or Password Protection Mode before using of this device. Non-Password Protection Mode Lock Command sets the device to Non-Password Protection Mode. Password Protection Mode Lock Command sets the device to Password Protection Mode. The respective program command can be executed only once, and Mode Lock Erase is impossible. At the shipment, the Non-Password Protection Mode and the Password Protection Mode aren't set state. In the case of using Non-Password Protection Mode, the hosts have to execute a Non-Password Protection Mode Lock in order to prevent the device from being changed to Password Protection Mode. In the case of using Password Protection Mode, the hosts have to execute a Password Protection Mode Lock. Once a Protection Mode is set, it is not eternally changeable. After latching the fourth bus write cycle command of " 68h", the hosts have to wait 100us. The 5th and 6th write bus cycles are Protection Mode Verify command. When the Protection Mode Lock (Set) is completely finished, the device will output `1' on DQ0 at the sixth bus write cycle. When the device is outputting `0' on DQ0, the Protection Mode Lock (Set) is not complete, then the hosts must retry from fourth bus write cycle. When the Protection Mode Lock (Set) is finished, the hosts have to execute the Hidden ROM Exit command. Non-Password Protection Mode Lock Password Protection Mode Lock Device Status 0 Programmed ("1") 0 Programmed ("1") 0 0 Programmed ("1") Programmed ("1") Non-Password Protection Mode (At Shipment) Non-Password Protection Mode Password Protection Mode Inhibit 10.18.4. PPB Lock in Non-Password Protection Mode and Password Protection Mode In the case of Non-Password Protection Mode, the PPB Lock is cleared by power-up cycle and Hardware Reset. When PPB Lock is set, the PPBs are disabled for modification by Block Protection 3. After Power-up cycle and Hardware Reset again, PPB Lock becomes `0' as clear. In Non-Password Protection Mode, Password Unlock command is ignored. In the case of Password Protection Mode, the PPB Lock is set by power-up cycle and Hardware Reset. Once Password Protection Mode is set, PPB is disabled for modification by PPB Set and Clear without the Password Unlock command. The state of PPB Lock doesn't differ before and after Password Protection Mode Lock Command. PPB Lock is set again by power-up cycle, Hardware Reset, or PPB lock Set. In Password Protection Mode, Password Program command and Password Verify command is permanently ignored. Therefore, when the user chooses the Password Protection Mode, it is necessary to program a 64-bit password to this device before performing a password protection mode lock command. After Password program command, the user has to check by Password Verify command whether the desired Password is certainly programmed. Once Password Protection Mode was set, the user cannot check the Password. At modifying PPB, the user has to use the Password Unlock command with a 64-bit password. Please set a Password certainly. PPB Lock Status of the Non-Password Protection Mode and the Password Protection Mode After Power-up cycle and Hardware Reset Non-Password Protection Mode Password Protection Mode PPB Lock is `0' (clear) PPB Lock is `1' (set) PPB Lock Status change method of the each Protection Mode PPB Lock Set PPB Lock Clear Non-Password Protection Mode Password Protection Mode PPB Lock Set PPB Set Command Power-up cycle Hardware Reset Power-up cycle Hardware Reset Password Unlock Command 2006-05-10 17/88 TC58FVM7(T/B)5B(TG/XG)65 10.18.5. Description of Password Protection Command (1) Password Program Command The Password Protect Command permits programming the password that is used as part of the Hardware Protection scheme. The actual Password length is 64-bits. The 64-bits password is split to four of 16-bits Password Program. In Password Protection Mode, Password Program and Password verify are disabled. During programming the Password, Simultaneous Operation is disabled. Read operations to any memory location is available after completion of the password programming. The status of password program operation can be checked by hardware sequence flags. When this mode is finished, the hosts have to execute the Hidden ROM Exit command. Password is set as four words of "FFFFh" at the time of shipment. The Hardware Sequence Flags of the Password Program In Progress Program Complete Program Failed (2) DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 RY/ BY 0 1 0 Toggle 1 Toggle 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 High-Z 0 Password Verify Command The Password Verify Command is verify the Password. Verification of a Password can be performed when the Password Protection Mode Lock is not programmed. In Password Protection Mode, if the user attempts to verify the Password, the device output "FFFFh". The hosts have to execute the Hidden ROM Entry command before Password Verify. During verification the Password, Simultaneous Operation is disabled. At the forth bus write cycle of Password Verify Command, the hosts have to fix the two address bits (A1, A0). When this mode is finished, the hosts have to execute the Hidden ROM Exit command. (3) Password Unlock Command The Password Unlock Command clears the PPB Lock Bit when the user sets the Password Protection Mode. In order to perform Password Unlock command, the exact Password is necessary. It is necessary to input password unlock command at intervals of 2us or more. If the interval is shorter than 2us, the command is ignored. At Password Unlock Command the 64-bits password is input in four step at 4th, 5th, 6th, 7th write bus cycles. The address A1:A0 is 0:0 at 4th write bus cycle, A1:A0 is 0:1 at 5th write bus cycle, A1:A0 is 1;0 at 6th write bus cycle, and finally A1:A0 is 1:1 at 7th write bus cycle. A wrong Password input at the Password Unlock sequence causes mismatch of Password and PPB Lock Bit is not changed. When the Password Unlock Command is entered, the RY/ BY pin is Low, which is indicating the device is busy. The status of password unlock operation can be checked by hardware sequence flags. Then flags are output by specifying the address of Bank0 (Bottom Boot Block) or Bank15 (Top Boot Block). Inputting address of the other Bank then, actual cell array data is output. The hardware sequence flags indicate whether exact password is inputted at 4-6th write bus cycles by intervals of 2us or more. During inputting password at 4-7th write bus cycles, DQ6 is toggling. When the first Password Unlock is successful, RY/ BY pin is LOW and DQ6 stop toggling. Then user can input next password. When the Password Unlock Command operation completes, the user has to perform Hidden ROM Exit command. PPB Lock Bit should be read in order to check whether Password Unlock has completed successfully. 2006-05-10 18/88 TC58FVM7(T/B)5B(TG/XG)65 Status Flags of progressing the Password Unlock Command DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 RY/ BY PWD Unlock in Progress 0 Toggle 0 0 0 1 0 0 0 Finished Input PWD (1) 0(2) 1 0 0 0 1 0 0 0 Finished Input PWD (1) 1(3) 1 0 0 0 1 0 0 High-Z Finished Input PWD (4) Array Data High-Z Notes: () Specified BA within Bank-0 (Bottom Boot Block Device)/ Bank-15 (Top Boot Block Device) () After inputting PWD at the 4th ,5th and 6th bus write cycles, DQ7 is "0" () After inputting PWD at the 7th bus write cycle, DQ7 is "1" () Specified BA without Bank-0 (Bottom Boot Block Device)/ Bank-15 (Top Boot Block Device) 10.18.6. Temporary Block Unprotection The TC58FVM7(T/B)5B has a temporary block unprotection feature which disables block protection for all protected blocks. Unprotection is enabled by applying VID to the RESET pin. Now Write and Erase operations can be performed on all blocks except the boot blocks which have been protected by the Boot Block Protect operation. The device returns to its previous state when VID is removed from the RESET pin. That is, previously protected blocks will be protected again. 10.18.7. Verify Block Protect The Verify Block Protect command is used to ascertain whether a block is protected or unprotected. Verification is performed either by inputting the Verify Block Protect command or by applying VID to the A9 pin. The Verify Block Protect command, which can be performed simultaneously with operations in another bank, is performed by setting the block address with A0 = A6 = VIL and A1 = VIH. If the block is protected, 01h is output. If the block is unprotected, 00h is output. The status depends on PPB, DPB, WP/ACC and RESET state. Inputting the verify block protect command sequence sets the specified bank to the Verify Block Protect mode. Inputting a Reset command releases this mode and returns the device to Read Mode. When verifying block protect across a bank boundary, a Reset command is needed at the time of the change of a bank 2006-05-10 19/88 TC58FVM7(T/B)5B(TG/XG)65 10.19. Hidden ROM Area The TC58FVM7(T/B)5B features a 64-Kbyte hidden ROM area, which is separate from the memory cells. The area consists of one block. Data Read, Write and Protect can be performed on this block. Because Protect cannot be released, once the block is protected, data in the block cannot be overwritten. The hidden ROM area is located in the address space indicated in the HIDDEN ROM AREA ADDRESS TABLE. To access the Hidden ROM area, input a Hidden ROM Mode Entry command. The device now enters Hidden ROM Mode, allowing Read, Write, Erase and Block Protect to be executed. Write and Erase operations are the same as auto operations except that the device is in Hidden ROM Mode. To protect the hidden ROM area, use the Block Protection 1 function or the Block Protection 2 function. The operation of Block Protect 2 here is the same as a normal Block Protect except that VIH rather than VID is input to RESET . When the PPB Lock has been settled, Hidden ROM protect state cannot be changed by the Block Protection 1 function or the Block Protection 2 function. The hosts have to decide the protection state of Hidden ROM Area before the PPB Lock has been settled. Once the block has been protected, protection cannot be released, even using the temporary block unprotection function. Using Block Protection for Hidden ROM Area must be careful. Note that in Hidden ROM Mode, simultaneous operation cannot be performed for BANK15 in top boot type and for BANK0 in bottom boot type. To exit Hidden ROM Mode, use the Hidden ROM Mode Exit command. This will return the device to Read Mode. HIDDEN ROM AREA ADDRESS TABLE TYPE BOOT BLOCK ARCHITECTURE ADDRESS RANGE SIZE TC58FVM7T5B TOP BOOT BLOCK 7F8000h~7FFFFFh 32 Kwords TC58FVM7B5B BOTTOM BOOT BLOCK 000000h~007FFFh 32 Kwords 2006-05-10 20/88 TC58FVM7(T/B)5B(TG/XG)65 10.20. CFI (Common Flash memory Interface) The TC58FVM7(T/B)5B conforms to the CFI specifications. To read information from the device, input the Query command followed by the address. In Word Mode DQ8~DQ15 all output 0s. To exit this mode, input the Reset command. CFI CODE TABLE 1 (Continue) ADDRESS A6~A0 DATA DQ15~DQ0 DESCRIPTION 10h 11h 12h 0051h 0052h 0059h ASCII string "QRY" 13h 14h 0002h 0000h Primary OEM command set 2: AMD/FJ standard type 15h 16h 0040h 0000h Address for primary extended table 17h 18h 0000h 0000h Alternate OEM command set 0: none exists 19h 1Ah 0000h 0000h Address for alternate OEM extended table 1Bh 0023h VDD (min) (Write/Erase) DQ7~DQ4: 1 V DQ3~DQ0: 100 mV 1Ch 0036h VDD (max) (Write/Erase) DQ7~DQ4: 1 V DQ3~DQ0: 100 mV 1Dh 0000h VPP (min) voltage 1Eh 0000h VPP (max) voltage 1Fh 0004h Typical time-out per single word write (2 s) 20h 0000h Typical time-out for minimum size buffer write (2 s) 21h 000Ah Typical time-out per individual block erase (2 ms) 22h 0000h Typical time-out for full chip erase (2 ms) 23h 0005h Maximum time-out for word write (2 times typical) 24h 0006h Maximum time-out for buffer write (2 times typical) 25h 0004h Maximum time-out per individual block erase (2 times typical) 26h 0000h Maximum time-out for full chip erase (2 times typical) 27h 0018h Device Size (2 byte) 18h:128Mbit 28h 29h 0001h 0000h Flash device interface description 1: x 16 2Ah 2Bh 0004h 0000h Maximum number of bytes in multi-byte write (2 ) N N N N N N N N N N 2006-05-10 21/88 TC58FVM7(T/B)5B(TG/XG)65 CFI CODE TABLE 2(Sequel) ADDRESS A6~A0 DATA DQ15~DQ0 DESCRIPTION 2Ch 0002h Number of erase block regions within device 2Dh 2Eh 2Fh 30h 0007h 0000h 0020h 0000h Erase Block Region 1 information Bits 0~15: y = block number Bits 16~31: z = block size (z x 256 bytes) 31h 32h 33h 34h 00FEh 0000h 0000h 0001h Erase Block Region 2 information 40h 41h 42h 0050h 0052h 0049h ASCII string "PRI" 43h 0031h Major version number, ASCII 44h 0031h Minor version number, ASCII 45h 0000h Address-Sensitive Unlock 0: Required 1: Not required 46h 0002h Erase Suspend 0: Not supported 1: For Read-only 2: For Read & Write 47h 0001h Block Protect 0: Not supported X: Number of blocks per group 48h 0001h Block Temporary Unprotect 0: Not supported 1: Supported 49h 0007h Block Protect/Unprotect scheme 4Ah 0001h Simultaneous operation 0: Not supported 1: Supported 4Bh 0000h Burst Mode 0: Not supported 4Ch 0001h Page Mode 0: Not supported 1: Supported 4Dh 0085h VACC (min) voltage DQ7~DQ4: 1 V DQ3~DQ0: 100 mV 4Eh 00C6h VACC (max) voltage DQ7~DQ4: 1 V DQ3~DQ0: 100 mV 4Fh 000xh Top/Bottom Boot Block Flag X = 2: Bottom Boot Block: TC58FVM7B5B X = 3: Top Boot Block: TC58FVM7T5B 50h 0001h Program Suspend 0: Not supported 1: Supported 2006-05-10 22/88 TC58FVM7(T/B)5B(TG/XG)65 CFI CODE TABLE 3(Sequel) ADDRESS A6~A0 DATA DQ15~DQ0 57h 0010h DESCRIPTION Bank Organization 00h: Data at 4Ah is zero X: Number of Banks 58h 00XXh 59h 0010h 5Ah 0010h 5Bh 0010h 5Ch 0010h 5Dh 0010h 5Eh 0010h 5Fh 0010h 60h 0010h 61h 0010h 62h 0010h 63h 0010h 64h 0010h 65h 0010h 66h 0010h 67h 00XXh Bank0 Region information XX: Number of blocks Bank0 TOP : 10h BOTTOM:17h Bank1 Region information n=16 Number of blocks Bank1 Bank2 Region information n=16 Number of blocks Bank2 Bank3 Region information n=16 Number of blocks Bank3 Bank4 Region information Number of blocks Bank4 n=16 Bank5 Region information n=16 Number of blocks Bank5 Bank6 Region information n=16 Number of blocks Bank6 Bank7 Region information n=16 Number of blocks Bank7 Bank8 Region information n=16 Number of blocks Bank8 Bank9 Region information n=16 Number of blocks Bank9 Bank10 Region information Number of blocks Bank10 n=16 Bank11 Region information Number of blocks Bank11 n=16 Bank12 Region information n=16 Number of blocks Bank12 Bank13 Region information n=16 Number of blocks Bank13 Bank14 Region information n=16 Number of blocks Bank14 Bank15 Region information XX: Number of blocks Bank15 TOP : 17h BOTTOM:10h 2006-05-10 23/88 TC58FVM7(T/B)5B(TG/XG)65 10.21. HARDWARE SEQUENCE FLAGS The TC58FVM7(T/B)5B has a Hardware Sequence flag which allows the device status to be determined during an auto mode operation. The output data is read out using the same timing as that used when CE = OE = VIL in Read Mode. The RY/ BY output can be either High or Low. The device re-enters Read Mode automatically after an auto mode operation has been completed successfully. The Hardware Sequence flag is read to determine the device status and the result of the operation is verified by comparing the read-out data with the original data. DQ6 DQ5 DQ3 DQ2 RY/ BY Toggle 0 0 1 0 Data Data Data Data Data High-Z 0 Toggle 0 0 Toggle 0 0 Toggle 0 0 1 0 Selected 0 Toggle 0 1 Toggle 0 Not-selected 0 Toggle 0 1 1 0 Selected 1 1 0 0 Toggle High-Z Not-selected Data Data Data Data Data High-Z Selected DQ 7 Toggle 0 0 Toggle 0 Not-selected DQ 7 Toggle 0 0 1 0 Toggle 1 0 1 0 0 Toggle 1 1 N/A 0 DQ 7 Toggle 1 0 N/A 0 STATUS DQ7 Auto Programming/Auto Page Programming Read in Program Suspend (1) Erase Hold Time Selected Auto Erase Read In Erase Suspend Programming Auto Programming/Auto Page Programming Time Limit Exceeded (2) Not-selected In Auto Erase In Progress DQ 7 Auto Erase Programming in Erase Suspend (3) DQ 7 (4) (4) Notes:DQ outputs cell data and RY/ BY goes High-Impedence when the operation has been completed. DQ0 and DQ1 pins are reserved for future use. 0 is output on DQ0, DQ1 and DQ4. (1) Data output from an address to which Write is being performed is undefined. (2) Output when the block address selected for Auto Block Erase is specified and data is read from there. (3) Output when a block address not selected for Auto Block Erase of same bank as selected block is specified and data is read from there. During Auto Chip Erase, all blocks are selected. (4) In case of Page program operation is program data of (A0, A1, A2) = (1, 1, 1) in eleventh bus write cycle. 10.21.1. DQ7 ( DATA polling) During an Auto-Program or auto-erase operation, the device status can be determined using the data polling function. DATA polling begins on the rising edge of WE in the last bus cycle. In an Auto-Program operation, DQ7 outputs inverted data during the programming operation and outputs actual data after programming has finished. In an auto-erase operation, DQ7 outputs 0 during the Erase operation and outputs 1 when the Erase operation has finished. If an Auto-Program or auto-erase operation fails, DQ7 simply outputs the data. When the operation has finished, the address latch is reset. Data polling is asynchronous with the OE signal. 10.21.2. DQ6 (Toggle bit 1) The device status can be determined by the Toggle Bit function during an Auto-Program or auto-erase operation. The Toggle bit begins toggling on the rising edge of WE in the last bus cycle. DQ6 alternately outputs a 0 or a 1 for each OE access while CE = VIL while the device is busy. When the internal operation has been completed, toggling stops and valid memory cell data can be read by subsequent reading. If the operation fails, the DQ6 output toggles. If an attempt is made to execute an Auto Program operation on a protected block, DQ6 will toggle for around 3 s. It will then stop toggling. If an attempt is made to execute an auto erase operation on a protected block, DQ6 will toggle for around 400 s. It will then stop toggling. After toggling has stopped the device will return to Read Mode. 2006-05-10 24/88 TC58FVM7(T/B)5B(TG/XG)65 10.21.3. DQ5 (internal time-out) If an Auto-Program or auto-erase operates normally, DQ5 outputs a 0. If the internal timer times out during a Program or Erase operation, DQ5 outputs a 1. This indicates that the operation has not been completed within the allotted time. Any attempt to program a 1 into a cell containing a 0 will fail (see Auto-Program Mode). In this case, DQ5 outputs a 1. In this case, DQ5 doesn't indicate defective device but mistaken usage. After an Auto-Program or auto-erase operation ends normally, the device outputs actual cell array data. Therefor only with the data of DQ5 can't specify whether cell array data or hardware sequence flag. The hosts shuold check the state of device whether progrress or not, using DQ7, DQ6, or RY/ BY . In the case of internal time-out, either hardware reset or a software Reset command is required to return the device to Read Mode. 10.21.4. DQ3 (Block Erase timer) The Block Erase operation starts 50 s (the Erase Hold Time) after the rising edge of WE in the last command cycle. DQ3 outputs a 0 for the duration of the Block Erase Hold Time and a 1 when the Block Erase operation starts. Additional Block Erase commands can only be accepted during the Block Erase Hold Time. Each Block Erase command input within the hold time resets the timer, allowing additional blocks to be marked for erasing. DQ3 outputs a 1 if the Program or Erase operation fails. 10.21.5. DQ2 (Toggle bit 2) DQ2 is used to indicate which blocks have been selected for Auto Block Erase or to indicate whether the device is in Erase Suspend Mode. If data is read continuously from the selected block during an Auto Block Erase, the DQ2 output will toggle. Now 1 will be output from non-selected blocks; thus, the selected block can be ascertained. If data is read continuously from the block selected for Auto Block Erase while the device is in Erase Suspend Mode, the DQ2 output will toggle. Because the DQ6 output is not toggling, it can be determined that the device is in Erase Suspend Mode. If data is read from the address to which data is being written during Erase Suspend in Programming Mode, DQ2 will output a 1. 10.21.6. RY/BY (READY/ BUSY ) The TC58FVM7(T/B)5B has a RY/ BY signal to indicate the device status to the host processor. A 0 (Busy state) indicates that an Auto-Program or auto-erase operation is in progress. A 1 (Ready state) indicates that the operation has finished and that the device can now accept a new command. RY/ BY outputs a 0 when an operation has failed. RY/ BY outputs a 0 after the rising edge of WE in the last command cycle. During an Auto Block Erase operation, commands other than Erase Suspend are ignored. RY/ BY outputs a 1 during an Erase Suspend operation. The output buffer for the RY/ BY pin is an open-drain type circuit, allowing a wired-OR connection. A pull-up resistor must be inserted between VDD and the RY/ BY pin. 2006-05-10 25/88 TC58FVM7(T/B)5B(TG/XG)65 11. DATA PROTECTION The TC58FVM7(T/B)5B includes a function which guards against malfunction or data corruption. 11.1. Protection against Program/Erase Caused by Low Supply Voltage To prevent malfunction at power-on or power-down, the device will not accept commands while VDD is below VLKO. In this state, command input is ignored. If VDD drops below VLKO during an Auto Operation, the device will terminate Auto-Program execution. In this case, Auto operation is not executed again when VDD returns to recommended VDD voltage. Therefore, command need to be input to execute Auto operation again. When VDD > VLKO, make up countermeasure to be input accurately command in system side please. 11.2. Protection against Malfunction Caused by Glitches To prevent malfunction write during operation caused by noise from the system, the device will not accept pulses shorter than 3 ns (Typ.) input on WE , CE or OE . However, if a glitch exceeding 3 ns (Typ.) occurs and the glitch is input to the device malfunction write may occur. The device uses standard JEDEC commands. It is conceivable that, in extreme cases, system noise may be misinterpreted as part of a command sequence input and that the device will acknowledge it. Then, even if a proper command is input, the device may not operate. To avoid this possibility, clear the Command Register before command input. In an environment prone to system noise, Toshiba recommends input of a software or hardware reset before command input. 11.3. Protection against Malfunction at Power-on To prevent damage to data caused by sudden noise at power-on, when power is turned on with WE = CE =VIL the device does not latch the command on the first rising edge of WE or CE . Instead, the device automatically Resets the Command Register and enters Read Mode. 2006-05-10 26/88 TC58FVM7(T/B)5B(TG/XG)65 12. ABSOLUTE MAXIMUM RATINGS SYMBOL VDD PARAMETER RANGE -0.6~4.6V VDD Supply Voltage VIN Input Voltage VDQ UNIT Input/Output Voltage VID Maximum Input Voltage for A9, OE and RESET VACC Maximum Input Voltage for WP/ACC PD (2) V -0.5~VDD+0.5V(4.6) (1) -0.5~VDD+0.5V(4.6) (1) V V 13.0 V 13.0 V Power Dissipation 600 mW Tsolder Soldering Temperature (10s) 260 C Tstg Storage Temperature TC58FVM7(T/B)5BTG -55~150 C TC58FVM7(T/B)5BXG -55~125 C Topr Operating Temperature -40~85 C 100 mA IOSHORT (1) (2) (3) (2) (3) Output Short-Circuit Current This level may undershoot to -2.0 V for periods < 20 ns, and may overshoot to +2.0 V for periods < 20 ns. Do not apply VID/VACC when the supply voltage is not within the device's recommended operating voltage range. Outputs should be shorted for no more than one second. No more than one output should be shorted at a time. 13. CAPACITANCE (Ta = 25C, f = 1 MHz) SYMBOL PARAMETER CONDITION MAX UNIT CIN Input Pin Capacitance VIN = 0 V 7 pF COUT Output Pin Capacitance VOUT = 0 V 12 pF CIN2 Control Pin Capacitance VIN = 0 V 7 pF CIN3 WP/ACC Capacitance VIN = 0 V 14 pF MIN MAX UNIT 2.7 3.6 This parameter is periodically sampled and is not tested for every device. 14. RECOMMENDED DC OPERATING CONDITIONS SYMBOL PARAMETER VDD VDD Supply Voltage VIH Input High-Level Voltage 0.7 x VDD VDD + 0.3 VIL Input Low-Level Voltage -0.3 0.2 x VDD VID High-Level Voltage for A9, OE and RESET 11.4 12.6 VACC High-Level Voltage for WP/ACC 8.5 12.6 Ta Operating Ambient Temperature -40 85 V C 2006-05-10 27/88 TC58FVM7(T/B)5B(TG/XG)65 15. DC CHARACTERISTICS SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT ILI Input Leakage Current 0 V VIN VDD 1 ILO Output Leakage Current 0 V VOUT VDD 1 VOH Output High Voltage IOH = -0.1 mA VDD - 0.4 IOH = -2.5 mA 0.85 x VDD VOL Output Low Voltage IOL = 4.0 mA 0.4 IDDO1 VDD Average Random Read Current VIN = VIH/VIL, IOUT = 0 mA tRC =100ns 37 55 IDDO2 VDD Average Program Current VIN = VIH/VIL, IOUT = 0 mA 11 15 IDDO3 VDD Average Erase Current VIN = VIH/VIL, IOUT = 0 mA 9 15 IDDO4 VDD Average Read-While-Program Current VIN = VIH/VIL, IOUT = 0 mA tRC = 100ns 48 70 IDDO5 VDD Average Read-while-Erase Current VIN = VIH/VIL, IOUT = 0 mA tRC = 100ns 46 70 IDDO6 VDD Average Program-whileErase-Suspend Current VIN = VIH/VIL, IOUT = 0 mA 11 15 IDDO7 VDD Average Page Read Current 2 5 IDDO8 VDD Average Address Increment (2) Read Current 5 11 IDDS1 VDD Standby Current 3 10 VIH = VDD VIL = VSS 3 10 11.4 V VID 12.6 V 35 8.5V VACC 12.6 V 20 mA 1.0 2.0 V VIN = VIH/VIL, IOUT = 0 mA tPRC = 25ns VIN = VIH/VIL, IOUT = 0 mA tRC =100ns tPRC = 25ns A V mA WP/ACC = VDD and IDDS2 IID VDD Standby Current (Automatic Sleep Mode CE = RESET = VDD or RESET = VSS (1) ) High-Voltage Input Current for A9, OE and RESET IACC High-Voltage WP/ACC Input Current VLKO Low-VDD Lock-out Voltage for A (1) The device enters Automatic Sleep Mode in which the address remains fixed for during 150 ns. (2) (IDDO1+ IDDO7x7)8words 16. AC TEST CONDITIONS PARAMETER Input Pulse Level Input Pulse Rise and Fall Time (10%~90%) CONDITION VDD, 0.0 V 5 ns Timing Measurement Reference Level (input) VDD/2, VDD/2 Timing Measurement Reference Level (output) VDD/2, VDD/2 Output Load CL (100 pF) + 1 TTL Gate / CL (30 pF) + 1 TTL Gate 2006-05-10 28/88 TC58FVM7(T/B)5B(TG/XG)65 17. AC CHARACTERISTICS AND OPERATING CONDITIONS 17.1. Read Cycle Output load capacitance (CL) Symbol Parameter 30 pF 100 pF MIN MAX MIN MAX UNIT tRC Read Cycle Time 65 70 ns tPRC Page Read Cycle Time 25 30 ns tACC Address Access Time 65 70 ns tCE CE Access Time 65 70 ns tOE OE Access Time 25 30 ns tPACC Page Access Time 25 30 ns tOEH OE High-Level Hold Time (read) 0 0 ns tCEE CE to Output Low-Z 0 0 ns tOEE OE to Output Low-Z 0 0 ns tOH Output Data Hold Time 0 0 ns tAOH Output Data Hold Time (Page Read) 0 0 ns tDF1 CE to Output High-Z 25 25 ns tDF2 OE to Output High-Z 25 25 ns Hardware RESET ( RESET ) Symbol Parameter MIN MAX UNIT tREADY Read Mode Recovery Time from RESET (During Auto Operation) 25 s tREADY Read Mode Recovery Time from RESET During Non Auto Operation 500 ns tRP RESET Low Level Hold Time 500 ns tRH Recovery Time from RESET 50 ns tRPD RESET goes Low to Standby Mode 20 s 2006-05-10 29/88 TC58FVM7(T/B)5B(TG/XG)65 17.2. Block Protect SYMBOL PARAMETER MIN MAX UNIT tVPT VID Transition Time 4 s tVPS VID Set-up Time 4 s tCESP CE Set-up Time 4 s tVPH OE Hold Time 4 s tPPLH WE Low-Level Hold Time 100 s MIN TYP. MAX UNIT 17.3. Program and Erase characteristics SYMBOL PARAMETER tPPW Auto-Program Time (Word Mode) 11 300 s tPPW Accelerated 8 300 s tPPAW Auto-Page program time 58 2400 s tPPAW Accelerated 21 2400 s tPCEW Auto Chip Erase Time 184 1315 s 158 1315 s 0.7 5 tPCEW tPBEW tEW Accelerated Auto-Program Time (Word Mode) Auto-Page program time (1) Auto Chip Erase Time (1) (1) Auto Block Erase Time Erase/Program Cycle 10 5 (2) s Cycle. (1) Auto Chip Erase Time and Auto Block Erase Time include internal pre program time. (2) Minimum interval between resume and the following suspend command is 150 s. If it's shorter than 150 s, auto block erase time is expand more than maximum(5 s). 2006-05-10 30/88 TC58FVM7(T/B)5B(TG/XG)65 17.4. Command Write/Program/Erase cycle SYMBOL PARAMETER MIN MAX UNIT tCMD Command Write Cycle Time 60 ns tAS Address Set-up Time 0 ns tAH Address Hold Time 30 ns tDS Data Set-up Time 30 ns tDH Data Set-up Time 0 ns tWELH WE Low-Level Hold Time ( WE Control) 30 ns tWEHH WE High-Level Hold Time ( WE Control) 20 ns tCES CE Set-up Time to WE Active ( WE Control) 0 ns tCEH CE Hold Time from WE High Level ( WE Control) 0 ns tCELH CE Low-Level Hold Time ( CE Control) 30 ns tCEHH CE High-Level Hold Time ( CE Control) 20 ns tWES WE Set-up time to CE Active ( CE Control) 0 ns tWEH WE Hold Time from CE High Level ( CE Control) 0 ns tOES OE Set-up Time 0 ns tOEHP OE High Level Hold Time (Polling) 10 ns tOEHT OE High Level Hold Time (Toggle Read) 20 ns tCEHT CE High Level Hold Time (Toggle Read) 20 ns tAHT Address Hold Time (Toggle) 0 ns tAST Address Set-up Time (Toggle) 0 ns tBEH Erase Hold Time 50 s tVDS VDD Set-up Time 500 s Program/Erase Valid to RY / BY Delay 90 ns Program/Erase Valid to RY / BY Delay during Suspend Mode 300 ns tRB RY / BY Recovery Time 0 ns tSUSP Program Suspend Command to Suspend Mode 2 s tSUSPA Page Program Suspend Command to Suspend Mode 2.5 s tRESP Program Resume Command to Program Mode 1 s tSUSE Erase Suspend Command to Suspend Mode 25 s tRESE Erase Resume Command to Erase Mode 1 s tBUSY 2006-05-10 31/88 TC58FVM7(T/B)5B(TG/XG)65 18. TIMING DIAGRAMS VIH or VIL Data invalid Read/ID Read Operation tRC Address tACC tOH tCE CE tOE tDF1 tOEE OE tCEE WE tDF2 tOEH DOUT Hi-Z Output data Valid Hi-Z ID Read Operation (apply VID to A9) tRC A0 A1 tACC A6 VID VIH A9 tVPS tCE CE tOE OE WE DOUT Hi-Z Read Mode Manufacture r code ID Read Mode Hi-Z Device code Hi-Z Read Mode 2006-05-10 32/88 TC58FVM7(T/B)5B(TG/XG)65 Page Read Operation Address(A3-22))) tPRC tRC tPRC tPRC Address(0-2) tACC tCE CE tDF1 tOE OE tDF2 WE tOH tPACC DOUT DOUT Hi-Z tPACC DOUT DOUT tPACC DOUT DOUT Hi-Z valid Hi-Z tAOH tAOH Read after command input (Only Hidden Rom/CFI Read) Address Last command address CE OE WE tW EHH+tACC DOUT Command data Hi-Z DOUT 2006-05-10 33/88 TC58FVM7(T/B)5B(TG/XG)65 Command Write Operation This is the timing of the Command Write Operation. The timing which is described in the following pages is essentially the same as the timing shown on this page. * WE Control tCMD Address Command address tAS tAH CE tCES tCEH WE tWELH tWEHH tDS DIN tDH Command data tVDS VDD * CE Control tCMD Address Command address tAS tAH CE tCELH tCEHH tWES tWEH WE tDS tDH Command data DIN tVDS VDD 2006-05-10 34/88 TC58FVM7(T/B)5B(TG/XG)65 ID Read Operation (input command sequence) Address 555h 2AAh BK + 555h tCMD BK + 00h BK + 01h tRC CE OE tOES WE DIN AAh 55h 90h Manufacturer code DOUT Device code Hi-Z Read Mode (input of ID Read command sequence) ID Read Mode (Continued) Address 555h 2AAh 555h tCMD CE OE WE DIN AAh DOUT 55h F0h Hi-Z ID Read Mode (input of Reset command sequence) Read Mode BK: Bank address 2006-05-10 35/88 TC58FVM7(T/B)5B(TG/XG)65 Auto-Program Operation ( WE Control) Address 555h 2AAh 555h PA PA tCMD CE OE tOEHP tOES tPPW WE AAh DIN 55h DOUT A0h Hi-Z PD DQ7 DOUT tVDS VDD Notes: PA: Program address PD: Program data 2006-05-10 36/88 TC58FVM7(T/B)5B(TG/XG)65 Auto Page Program Operation ( WE Control) PA Address(A3-22) PA tCMD 555h Address(A0-2) 2AAh 555h 0h 1h 2h 3h 4h 5h 6h 7h 7h CE tOEHP OE tOES tPPAW WE AAh DIN 55h E6h DOUT PD0 PD1 PD2 Hi-Z PD3 PD4 PD5 PD6 PD7 DQ7 DOUT tVDS VDD Notes: PA: Program address PD: Program Data 2006-05-10 37/88 TC58FVM7(T/B)5B(TG/XG)65 Auto Chip Erase/Auto Block Erase Operation ( WE Control) Address 555h 2AAh 555h 555h 2AAh 555h/BA tCMD CE OE tOES WE DIN AAh 55h 80h AAh 55h 10h/30h tVDS VDD Notes: BA: Block Address 2006-05-10 38/88 TC58FVM7(T/B)5B(TG/XG)65 Auto-Program Operation ( CE Control) Address 555h 2AAh 555h PA PA tCMD CE tPPW OE tOEHP tOES WE DIN AAh DOUT 55h A0h Hi-Z PD DQ7 DOUT tVDS VDD Note: PA: Program address PD: Program data 2006-05-10 39/88 TC58FVM7(T/B)5B(TG/XG)65 Auto Page Program Operation ( CE Control) PA Address(A3-22) PA tCMD 555h Address(A0-2) 2AAh 555h 0h 1h 2h 3h 4h 5h 6h 7h 7h CE tOEHP OE tOES tPPAW WE AAh DIN 55h E6h DOUT PD0 PD1 PD2 Hi-Z PD3 PD4 PD5 PD6 PD7 DQ7 DOUT tVDS VDD Notes: PA: Program address PD: Program data 2006-05-10 40/88 TC58FVM7(T/B)5B(TG/XG)65 Auto Chip Erase/Auto Block Erase Operation ( CE Control) Address 555h 2AAh 555h 555h 2AAh 555h/BA tCMD CE OE tOES WE DIN AAh 55h 80h AAh 55h 10h/30h tVDS VDD Note: BA: Block address for Auto Block Erase operation 2006-05-10 41/88 TC58FVM7(T/B)5B(TG/XG)65 Program/Erase Suspend Operation Address BK RA CE OE WE tOE DIN B0h tCE DOUT Hi-Z DOUT Hi-Z tSUSP/tSUSE RY / BY Program/Erase Mode Suspend Mode RA: Read address 2006-05-10 42/88 TC58FVM7(T/B)5B(TG/XG)65 Program/Erase Resume Operation Address RA BK PA/BA CE OE tOES WE tRESP/tRESE tDF1 tDF2 tOE 30h DIN tCE DOUT DOUT Hi-Z Flag Hi-Z RY / BY Suspend Mode Program/Erase Mode PA: Program address BK: Bank address BA: Block address RA: Read address Flag: Hardware Sequence flag 2006-05-10 43/88 TC58FVM7(T/B)5B(TG/XG)65 RY/BY during Auto Program/Erase Operation CE Command input sequence WE tBUSY During operation RY/ BY Hardware Reset Operation (At the Auto Operation) WE tRB RESET tRP tREADY RY/ BY Read after RESET tRC Address tRH RESET tACC DOUT Hi-Z tOH Output DOUT data valid 2006-05-10 44/88 TC58FVM7(T/B)5B(TG/XG)65 Hardware Sequence Flag ( DATA Polling) Address Last Command Address tCMD PA/BA CE tCE tDF1 tOE OE tOEHP tDF2 WE tPPW/tPCEW/tPBEW tACC tOH Last Command Data DIN DQ7 DQ0~DQ6 DQ7 Valid Valid Invalid Valid Valid tBUSY RY/BY PA: Program address BA: Block address Hardware Sequence Flag (Toggle bit) Address tAST CE tAHT tOEHT tCE tAHT OE tOEH WE tOE DIN Last Command Data Toggle DQ2/6 Toggle Toggl Stop* Toggle Valid tBUSY RY / BY *DQ2/DQ6 stops toggling when auto operation has been completed. 2006-05-10 45/88 TC58FVM7(T/B)5B(TG/XG)65 Block Protect 1 Operation (PPB Set) Block Protect Address Verify Block Protect BA A0 A1 tVPT A6 VID VIH A9 VID VIH OE tVPH tVPS tPPLH tVPH WE tCESP tOE CE DOUT Hi-Z 01h* Hi-Z BA: Block address *: 01h indicates that block is protected. 2006-05-10 46/88 TC58FVM7(T/B)5B(TG/XG)65 Block Protect 2 Operation Address (PPB Set) BA tCMD BA tCMD BA tCMD BA + 1 tRC A0 A1 A6 CE OE tPPLH WE tVPS VID VIH RESET DIN 60h 60h 40h 60h tOE DOUT Hi-Z 01h* BA: Block address BA + 1: Address of next block *: 01h indicates that block is protected. 2006-05-10 47/88 TC58FVM7(T/B)5B(TG/XG)65 19. FLOWCHARTS Auto-Program Start Auto-Program Command Sequence (see below) DATA Polling or Toggle Bit Address = Address + 1 No Last Address? Yes Auto-Program Completed Auto-Program Command Sequence (address/data) 555h/AAh 2AAh/55h 555h/A0h Program Address/ Program Data 2006-05-10 48/88 TC58FVM7(T/B)5B(TG/XG)65 Auto-Page Program START Auto page program command sequence (see below ) DATA Polling or Toggle Bit Address = Address + 1 NO Last address? Yes Auto-Program Completed 555h/AAh 2AAh/55h 555h/E6h Program address (A2=0,A1=0,A0=0) / Program data Program address (A2=1,A1=0,A0=0) / Program data Program address (A2=0,A1=0,A0=1) / Program data Program address (A2=1,A1=0,A0=1) / Program data Program address (A2=0,A1=1,A0=0) / Program data Program address (A2=1,A1=1,A0=0) / Program data Program address (A2=0,A1=1,A0=1) / Program data Program address (A2=1,A1=1,A0=1) / Program data 2006-05-10 49/88 TC58FVM7(T/B)5B(TG/XG)65 Fast Program Start Fast Program Set Command Sequence (see below) Fast Program Command Sequence (see below) DATA Polling or Toggle Bit Address = Address + 1 No Last Address? Yes Program Sequence (see below) Fast Program Completed Fast Program Set Command Sequence (address/data) Fast Program Command Sequence (address/data) Fast Program Reset Command Sequence (address/data) 555h/AAh XXXh/A0h XXXh/90h 2AAh/55h Program Address/ Program Data XXXh/F0h 555h/20h 2006-05-10 50/88 TC58FVM7(T/B)5B(TG/XG)65 Auto Erase Start Auto Erase Command Sequence (see below) DATA Polling or Toggle Bit Auto Erase Completed Auto Chip Erase Command Sequence (address/data) Auto Block/Auto Multi-Block Erase Command Sequence (address/data) 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/80h 555h/80h 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/10h Block Address/30h Block Address/30h Block Address/30h Additional address inputs during Auto Multi-Block Erase 2006-05-10 51/88 TC58FVM7(T/B)5B(TG/XG)65 DQ7 DATA Polling Start Read Byte (DQ0~DQ7) Addr. = VA Yes DQ7 = Data? No No DQ5 = 1? Yes 1) : DQ7 must be rechecked even if DQ5 = 1 because DQ7 may change at the same time as DQ5. 1) Read Byte (DQ0~DQ7) Addr. = VA Yes DQ7 = Data? No Fail Pass DQ6 Toggle Bit Start Read Byte (DQ0~DQ7) Addr. = VA No DQ6 = Toggle? Yes No DQ5 = 1? Yes 1) : DQ6 must be rechecked even if DQ5 = 1 because DQ6 may stop toggling at the same times that DQ5 changes to 1. 1) Read Byte (DQ0~DQ7) Addr. = VA DQ6 = Toggle? No Yes Fail Pass VA: Valid address for programming Any of the addresses within the block being erased during a Block Erase operation "Don't care" during a Chip Erase operation 2006-05-10 52/88 TC58FVM7(T/B)5B(TG/XG)65 Block Protect 1 Start PLSCNT = 1 Set up Block Address Addr. = BPA Wait for 4 s OE = A9 = VID, CE = VIL Wait for 4 s WE = VIL Wait for 100 s WE = VIH PLSCNT = PLSCNT + 1 Wait for 4 s OE = VIH Wait for 4 s OE = VIL Verify Block Protect No Data = 01h? No Yes Yes Protect Another Block? PLSCNT = 25? Yes Device Failed No Remove VID from A9 Block Protect Complete BPA: Block Address and ID Read Address (A6, A1, A0) ID Read Address = (0, 1, 0) 2006-05-10 53/88 TC58FVM7(T/B)5B(TG/XG)65 Block Protect 2 Start RESET = VID Wait for 4 s PLSCNT = 1 Block Protect 2 Command First Bus Write Cycle (XXXh/60h) Set up Address Addr. = BPA Block Protect 2 Command Second Bus Write Cycle (BPA/60h) Wait for 100 s Block Protect 2 Command Third Bus Write Cycle (XXXh/40h) PLSCNT = PLSCNT + 1 Verify Block Protect No Data = 01h? No PLSCNT = 25? Yes Yes Protect Another Block? Remove VID from RESET No Remove VID from RESET Reset Command Reset Command Device Failed Block Protect Complete BPA: Block Address and ID Read Address (A6, A1, A0) ID Read Address = (0, 1, 0) 2006-05-10 54/88 TC58FVM7(T/B)5B(TG/XG)65 Hidden ROM Exit Command Input START 555h/AAh 2AAh/55h 555h/90h 555h/00h FINISH 2006-05-10 55/88 TC58FVM7(T/B)5B(TG/XG)65 Password Protection Mode Locking Set Operation START PLSCNT = 1 555h/AAh 2AAh/55h 555h/60h Password Protection Mode Lock Bit Set Command Sequence 4th Bus Write Cycle (x0A/68h) Wait 100 s Password Protection Mode Lock Bit Set Command Sequence 5th Bus Write Cycle (x0A/48h) PLSCNT = PLSCNT + 1 Verify Lock Bit No Data = x1h? Yes No PLSCNT = 25? Yes HiddenROM Exit Command HiddenROM Exit Command Lock Set Complete Device Failed 2006-05-10 56/88 TC58FVM7(T/B)5B(TG/XG)65 Password Program Operation START PWA = 0 555h/AAh 2AAh/55h 555h/38h PWA = PWA +1 Password Program Command Sequence 4th Bus Write Cycle (PWA/PWD) Read Status No DQ7 = 1? Yes No No DQ5 = 1? Yes HiddenROM Exit Command HiddenROM Exit Command PWA = 3? Device Failed Yes Password Program Complete 2006-05-10 57/88 TC58FVM7(T/B)5B(TG/XG)65 Password Verify Operation START 555h/AAh 2AAh/55h 555h/C8h Read Password 0 1 (x0h/PWD) Read Password 1 (x1h/PWD) Read Password 2 (x2h/PWD) Read Password 3 (x3h/PWD) HiddenROM Exit Command Password Verify Complete 2006-05-10 58/88 TC58FVM7(T/B)5B(TG/XG)65 Password Unlock Command Operation START 555h/AAh 2AAh/55h 555h/28h Read Write Password 0 1 (x0h/PWD0) (x0h/PWD) Wait 2us or DQ6= No Toggle? Write Password 1 (x1h/PWD1) Wait 2us or DQ6= No Toggle? Write Password 2 (x2h/PWD2) Wait 2us or DQ6= No Toggle? Write Password 3 (x3h/PWD3) Wait 2us DQ7=1 or DQ6= No Toggle? HiddenROM Exit Command Password Unlock Complete 2006-05-10 59/88 TC58FVM7(T/B)5B(TG/XG)65 Non-Password Protection Mode Locking Set Operation START PLSCNT = 1 555h/AAh 2AAh/55h 555h/60h Non-Password Protection Mode Lock Bit Set Command Sequence 4th Bus Cycle (x12/68h) Wait 100 s Non-Password Protection Mode Lock Bit Set Command Sequence PLSCNT = PLSCNT + 1 5th Bus Cycle (x12/48h) Verify Lock Bit No Data = x1h? Yes No PLSCNT = 25? Yes HiddenROM Exit Command HiddenROM Exit Command Lock Set Complete Device Failed 2006-05-10 60/88 TC58FVM7(T/B)5B(TG/XG)65 PPB Set Command Sequence START PLSCNT = 1 555h/AAh 2AAh/55h 555h/60h PPB Set Command Sequence 4th Bus Write Cycle (BA+02n/68h) Wait 100 s PPB Set Command PLSCNT = 1 PLSCNT = PLSCNT + 1 Sequence 5th Bus Write Cycle (BA+02h/48h) Verify Block Protect No Data = x1h? Yes Yes Protect Another Block? No PLSCNT = 25? Yes HiddenROM Exit Command No HiddenROM Exit Command Device Failed Block Protect Complete 2006-05-10 61/88 TC58FVM7(T/B)5B(TG/XG)65 PPB Clear Command Sequence START PLSCNT = 1, BA=0 555h/AAh 2AAh/55h 555h/60h PPB Clear Command Sequence 4th Write Cycle (xx02h/60h) Wait 10 ms PPB Clear Command Sequence 5th Write Cycle (BA+02h/40h) PLSCNT = PLSCNT + 1 Verify Block Protect No Data = x0h? Yes BA=BA+1 No Check ALL Blocks? No PLSCNT = 500? Yes HiddenROM Exit Command Device Failed Yes HiddenROM Exit Command Block Protection Complete 2006-05-10 62/88 TC58FVM7(T/B)5B(TG/XG)65 PPB Lock Operation PPB Lock Verify PPB Lock Set START 555h/AAh 2AAh/55h 555h/78h START 555h/AAh 2AAh/55h 555h/58h HiddenROM Exit Command PPB Lock Verify PPB Lock Verify DQ1=1:PPB Lock Set DQ1=0: PPB Lock is cleared HiddenROM Exit Command HiddenROM Exit Command Program Complete Complete PPB Lock Clear START Power On or RESET = VIL Complete 2006-05-10 63/88 TC58FVM7(T/B)5B(TG/XG)65 DPB Command Operation DPB Verify DPB Set START START 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/48h 555h/58h BA/x1h Verify DPB(Add = BA) DQ0=1: DPP set Yes DQ0=0: DPP is cleared Protect Another Block? No Yes Check Another Block? HiddenROM Exit Command No HiddenROM Exit Command Program Complete Verify Complete DPB Clear 1 DPB Clear 2 START START 555h/AAh 2AAh/55h Powe On or RESET = VIL Erase Complete 555h/48h BA/00h Yes Erase Another Block? No HiddenROM Exit Command Erase Complete 2006-05-10 64/88 TC58FVM7(T/B)5B(TG/XG)65 20. BLOCK ADDRESS TABLES * : VIH or VIL 20.1. TC58FVM7T5B (Top Boot Block) 1/9 BLOCK ADDRESS BANK BLOCK # # BK0 BK1 ADDRESS RANGE BANK ADDRESS A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA0 L L L L L L L L * * * 000000h~007FFFh BA1 L L L L L L L H * * * 008000h~00FFFFh BA2 L L L L L L H L * * * 010000h~017FFFh BA3 L L L L L L H H * * * 018000h~01FFFFh BA4 L L L L L H L L * * * 020000h~027FFFh BA5 L L L L L H L H * * * 028000h~02FFFFh BA6 L L L L L H H L * * * 030000h~037FFFh BA7 L L L L L H H H * * * 038000h~03FFFFh BA8 L L L L H L L L * * * 040000h~047FFFh BA9 L L L L H L L H * * * 048000h~04FFFFh BA10 L L L L H L H L * * * 050000h~057FFFh BA11 L L L L H L H H * * * 058000h~05FFFFh BA12 L L L L H H L L * * * 060000h~067FFFh BA13 L L L L H H L H * * * 068000h~06FFFFh BA14 L L L L H H H L * * * 070000h~077FFFh BA15 L L L L H H H H * * * 078000h~07FFFFh BA16 L L L H L L L L * * * 080000h~087FFFh BA17 L L L H L L L H * * * 088000h~08FFFFh BA18 L L L H L L H L * * * 090000h~097FFFh BA19 L L L H L L H H * * * 098000h~09FFFFh BA20 L L L H L H L L * * * 0A0000h~0A7FFFh BA21 L L L H L H L H * * * 0A8000h~0AFFFFh BA22 L L L H L H H L * * * 0B0000h~0B7FFFh BA23 L L L H L H H H * * * 0B8000h~0BFFFFh BA24 L L L H H L L L * * * 0C0000h~0C7FFFh BA25 L L L H H L L H * * * 0C8000h~0CFFFFh BA26 L L L H H L H L * * * 0D0000h~0D7FFFh BA27 L L L H H L H H * * * 0D8000h~0DFFFFh BA28 L L L H H H L L * * * 0E0000h~0E7FFFh BA29 L L L H H H L H * * * 0E8000h~0EFFFFh BA30 L L L H H H H L * * * 0F0000h~0F7FFFh BA31 L L L H H H H H * * * 0F8000h~0FFFFFh 2006-05-10 65/88 TC58FVM7(T/B)5B(TG/XG)65 20.1. TC58FVM7T5B (Top Boot Block) 2/9 BLOCK ADDRESS BANK BLOCK # # BK2 BK3 ADDRESS RANGE BANK ADDRESS A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA32 L L H L L L L L * * * 100000h~107FFFh BA33 L L H L L L L H * * * 108000h~10FFFFh BA34 L L H L L L H L * * * 110000h~117FFFh BA35 L L H L L L H H * * * 118000h~11FFFFh BA36 L L H L L H L L * * * 120000h~127FFFh BA37 L L H L L H L H * * * 128000h~12FFFFh BA38 L L H L L H H L * * * 130000h~137FFFh BA39 L L H L L H H H * * * 138000h~13FFFFh BA40 L L H L H L L L * * * 140000h~147FFFh BA41 L L H L H L L H * * * 148000h~14FFFFh BA42 L L H L H L H L * * * 150000h~157FFFh BA43 L L H L H L H H * * * 158000h~15FFFFh BA44 L L H L H H L L * * * 160000h~167FFFh BA45 L L H L H H L H * * * 168000h~16FFFFh BA46 L L H L H H H L * * * 170000h~177FFFh BA47 L L H L H H H H * * * 178000h~17FFFFh BA48 L L H H L L L L * * * 180000h~187FFFh BA49 L L H H L L L H * * * 188000h~18FFFFh BA50 L L H H L L H L * * * 190000h~197FFFh BA51 L L H H L L H H * * * 198000h~19FFFFh BA52 L L H H L H L L * * * 1A0000h~1A7FFFh BA53 L L H H L H L H * * * 1A8000h~1AFFFFh BA54 L L H H L H H L * * * 1B0000h~1B7FFFh BA55 L L H H L H H H * * * 1B8000h~1BFFFFh BA56 L L H H H L L L * * * 1C0000h~1C7FFFh BA57 L L H H H L L H * * * 1C8000h~1CFFFFh BA58 L L H H H L H L * * * 1D0000h~1D7FFFh BA59 L L H H H L H H * * * 1D8000h~1DFFFFh BA60 L L H H H H L L * * * 1E0000h~1E7FFFh BA61 L L H H H H L H * * * 1E8000h~1EFFFFh BA62 L L H H H H H L * * * 1F0000h~1F7FFFh BA63 L L H H H H H H * * * 1F8000h~1FFFFFh 2006-05-10 66/88 TC58FVM7(T/B)5B(TG/XG)65 20.1. TC58FVM7T5B (Top Boot Block) 3/9 BLOCK ADDRESS BANK BLOCK # # BK4 BK5 ADDRESS RANGE BANK ADDRESS A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA64 L H L L L L L L * * * 200000h~207FFFh BA65 L H L L L L L H * * * 208000h~20FFFFh BA66 L H L L L L H L * * * 210000h~217FFFh BA67 L H L L L L H H * * * 218000h~21FFFFh BA68 L H L L L H L L * * * 220000h~227FFFh BA69 L H L L L H L H * * * 228000h~22FFFFh BA70 L H L L L H H L * * * 230000h~237FFFh BA71 L H L L L H H H * * * 238000h~23FFFFh BA72 L H L L H L L L * * * 240000h~247FFFh BA73 L H L L H L L H * * * 248000h~24FFFFh BA74 L H L L H L H L * * * 250000h~257FFFh BA75 L H L L H L H H * * * 258000h~25FFFFh BA76 L H L L H H L L * * * 260000h~267FFFh BA77 L H L L H H L H * * * 268000h~26FFFFh BA78 L H L L H H H L * * * 270000h~277FFFh BA79 L H L L H H H H * * * 278000h~27FFFFh BA80 L H L H L L L L * * * 280000h~287FFFh BA81 L H L H L L L H * * * 288000h~28FFFFh BA82 L H L H L L H L * * * 290000h~297FFFh BA83 L H L H L L H H * * * 298000h~29FFFFh BA84 L H L H L H L L * * * 2A0000h~2A7FFFh BA85 L H L H L H L H * * * 2A8000h~2AFFFFh BA86 L H L H L H H L * * * 2B0000h~2B7FFFh BA87 L H L H L H H H * * * 2B8000h~2BFFFFh BA88 L H L H H L L L * * * 2C0000h~2C7FFFh BA89 L H L H H L L H * * * 2C8000h~2CFFFFh BA90 L H L H H L H L * * * 2D0000h~2D7FFFh BA91 L H L H H L H H * * * 2D8000h~2DFFFFh BA92 L H L H H H L L * * * 2E0000h~2E7FFFh BA93 L H L H H H L H * * * 2E8000h~2EFFFFh BA94 L H L H H H H L * * * 2F0000h~2F7FFFh BA95 L H L H H H H H * * * 2F8000h~2FFFFFh 2006-05-10 67/88 TC58FVM7(T/B)5B(TG/XG)65 20.1. TC58FVM7T5B (Top Boot Block) 4/9 BLOCK ADDRESS BANK BLOCK # # BK6 BK7 ADDRESS RANGE BANK ADDRESS A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA96 L H H L L L L L * * * 300000h~307FFFh BA97 L H H L L L L H * * * 308000h~30FFFFh BA98 L H H L L L H L * * * 310000h~317FFFh BA99 L H H L L L H H * * * 318000h~31FFFFh BA100 L H H L L H L L * * * 320000h~327FFFh BA101 L H H L L H L H * * * 328000h~32FFFFh BA102 L H H L L H H L * * * 330000h~337FFFh BA103 L H H L L H H H * * * 338000h~33FFFFh BA104 L H H L H L L L * * * 340000h~347FFFh BA105 L H H L H L L H * * * 348000h~34FFFFh BA106 L H H L H L H L * * * 350000h~357FFFh BA107 L H H L H L H H * * * 358000h~35FFFFh BA108 L H H L H H L L * * * 360000h~367FFFh BA109 L H H L H H L H * * * 368000h~36FFFFh BA110 L H H L H H H L * * * 370000h~377FFFh BA111 L H H L H H H H * * * 378000h~37FFFFh BA112 L H H H L L L L * * * 380000h~387FFFh BA113 L H H H L L L H * * * 388000h~38FFFFh BA114 L H H H L L H L * * * 390000h~397FFFh BA115 L H H H L L H H * * * 398000h~39FFFFh BA116 L H H H L H L L * * * 3A0000h~3A7FFFh BA117 L H H H L H L H * * * 3A8000h~3AFFFFh BA118 L H H H L H H L * * * 3B0000h~3B7FFFh BA119 L H H H L H H H * * * 3B8000h~3BFFFFh BA120 L H H H H L L L * * * 3C0000h~3C7FFFh BA121 L H H H H L L H * * * 3C8000h~3CFFFFh BA122 L H H H H L H L * * * 3D0000h~3D7FFFh BA123 L H H H H L H H * * * 3D8000h~3DFFFFh BA124 L H H H H H L L * * * 3E0000h~3E7FFFh BA125 L H H H H H L H * * * 3E8000h~3EFFFFh BA126 L H H H H H H L * * * 3F0000h~3F7FFFh BA127 L H H H H H H H * * * 3F8000h~3FFFFFh 2006-05-10 68/88 TC58FVM7(T/B)5B(TG/XG)65 20.1. TC58FVM7T5B (Top Boot Block) 5/9 BLOCK ADDRESS BANK BLOCK # # BK8 BK9 ADDRESS RANGE BANK ADDRESS A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA128 H L L L L L L L * * * 400000h~407FFFh BA129 H L L L L L L H * * * 408000h~40FFFFh BA130 H L L L L L H L * * * 410000h~417FFFh BA131 H L L L L L H H * * * 418000h~41FFFFh BA132 H L L L L H L L * * * 420000h~427FFFh BA133 H L L L L H L H * * * 428000h~42FFFFh BA134 H L L L L H H L * * * 430000h~437FFFh BA135 H L L L L H H H * * * 438000h~43FFFFh BA136 H L L L H L L L * * * 440000h~447FFFh BA137 H L L L H L L H * * * 448000h~44FFFFh BA138 H L L L H L H L * * * 450000h~457FFFh BA139 H L L L H L H H * * * 458000h~45FFFFh BA140 H L L L H H L L * * * 460000h~467FFFh BA141 H L L L H H L H * * * 468000h~46FFFFh BA142 H L L L H H H L * * * 470000h~477FFFh BA143 H L L L H H H H * * * 478000h~47FFFFh BA144 H L L H L L L L * * * 480000h~487FFFh BA145 H L L H L L L H * * * 488000h~48FFFFh BA146 H L L H L L H L * * * 490000h~497FFFh BA147 H L L H L L H H * * * 498000h~49FFFFh BA148 H L L H L H L L * * * 4A0000h~4A7FFFh BA149 H L L H L H L H * * * 4A8000h~4AFFFFh BA150 H L L H L H H L * * * 4B0000h~4B7FFFh BA151 H L L H L H H H * * * 4B8000h~4BFFFFh BA152 H L L H H L L L * * * 4C0000h~4C7FFFh BA153 H L L H H L L H * * * 4C8000h~4CFFFFh BA154 H L L H H L H L * * * 4D0000h~4D7FFFh BA155 H L L H H L H H * * * 4D8000h~4DFFFFh BA156 H L L H H H L L * * * 4E0000h~4E7FFFh BA157 H L L H H H L H * * * 4E8000h~4EFFFFh BA158 H L L H H H H L * * * 4F0000h~4F7FFFh BA159 H L L H H H H H * * * 4F8000h~4FFFFFh 2006-05-10 69/88 TC58FVM7(T/B)5B(TG/XG)65 20.1. TC58FVM7T5B (Top Boot Block) 6/9 BLOCK ADDRESS BANK BLOCK # # BK10 BK11 ADDRESS RANGE BANK ADDRESS A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA160 H L H L L L L L * * * 500000h~507FFFh BA161 H L H L L L L H * * * 508000h~50FFFFh BA162 H L H L L L H L * * * 510000h~517FFFh BA163 H L H L L L H H * * * 518000h~51FFFFh BA164 H L H L L H L L * * * 520000h~527FFFh BA165 H L H L L H L H * * * 528000h~52FFFFh BA166 H L H L L H H L * * * 530000h~537FFFh BA167 H L H L L H H H * * * 538000h~53FFFFh BA168 H L H L H L L L * * * 540000h~547FFFh BA169 H L H L H L L H * * * 548000h~54FFFFh BA170 H L H L H L H L * * * 550000h~557FFFh BA171 H L H L H L H H * * * 558000h~55FFFFh BA172 H L H L H H L L * * * 560000h~567FFFh BA173 H L H L H H L H * * * 568000h~56FFFFh BA174 H L H L H H H L * * * 570000h~577FFFh BA175 H L H L H H H H * * * 578000h~57FFFFh BA176 H L H H L L L L * * * 580000h~587FFFh BA177 H L H H L L L H * * * 588000h~58FFFFh BA178 H L H H L L H L * * * 590000h~597FFFh BA179 H L H H L L H H * * * 598000h~59FFFFh BA180 H L H H L H L L * * * 5A0000h~5A7FFFh BA181 H L H H L H L H * * * 5A8000h~5AFFFFh BA182 H L H H L H H L * * * 5B0000h~5B7FFFh BA183 H L H H L H H H * * * 5B8000h~5BFFFFh BA184 H L H H H L L L * * * 5C0000h~5C7FFFh BA185 H L H H H L L H * * * 5C8000h~5CFFFFh BA186 H L H H H L H L * * * 5D0000h~5D7FFFh BA187 H L H H H L H H * * * 5D8000h~5DFFFFh BA188 H L H H H H L L * * * 5E0000h~5E7FFFh BA189 H L H H H H L H * * * 5E8000h~5EFFFFh BA190 H L H H H H H L * * * 5F0000h~5F7FFFh BA191 H L H H H H H H * * * 5F8000h~5FFFFFh 2006-05-10 70/88 TC58FVM7(T/B)5B(TG/XG)65 20.1. TC58FVM7T5B (Top Boot Block) 7/9 BLOCK ADDRESS BANK BLOCK # # BK12 BK13 ADDRESS RANGE BANK ADDRESS A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA192 H H L L L L L L * * * 600000h~607FFFh BA193 H H L L L L L H * * * 608000h~60FFFFh BA194 H H L L L L H L * * * 610000h~617FFFh BA195 H H L L L L H H * * * 618000h~61FFFFh BA196 H H L L L H L L * * * 620000h~627FFFh BA197 H H L L L H L H * * * 628000h~62FFFFh BA198 H H L L L H H L * * * 630000h~637FFFh BA199 H H L L L H H H * * * 638000h~63FFFFh BA200 H H L L H L L L * * * 640000h~647FFFh BA201 H H L L H L L H * * * 648000h~64FFFFh BA202 H H L L H L H L * * * 650000h~657FFFh BA203 H H L L H L H H * * * 658000h~65FFFFh BA204 H H L L H H L L * * * 660000h~667FFFh BA205 H H L L H H L H * * * 668000h~66FFFFh BA206 H H L L H H H L * * * 670000h~677FFFh BA207 H H L L H H H H * * * 678000h~67FFFFh BA208 H H L H L L L L * * * 680000h~687FFFh BA209 H H L H L L L H * * * 688000h~68FFFFh BA210 H H L H L L H L * * * 690000h~697FFFh BA211 H H L H L L H H * * * 698000h~69FFFFh BA212 H H L H L H L L * * * 6A0000h~6A7FFFh BA213 H H L H L H L H * * * 6A8000h~6AFFFFh BA214 H H L H L H H L * * * 6B0000h~6B7FFFh BA215 H H L H L H H H * * * 6B8000h~6BFFFFh BA216 H H L H H L L L * * * 6C0000h~6C7FFFh BA217 H H L H H L L H * * * 6C8000h~6CFFFFh BA218 H H L H H L H L * * * 6D0000h~6D7FFFh BA219 H H L H H L H H * * * 6D8000h~6DFFFFh BA220 H H L H H H L L * * * 6E0000h~6E7FFFh BA221 H H L H H H L H * * * 6E8000h~6EFFFFh BA222 H H L H H H H L * * * 6F0000h~6F7FFFh BA223 H H L H H H H H * * * 6F8000h~6FFFFFh 2006-05-10 71/88 TC58FVM7(T/B)5B(TG/XG)65 20.1. TC58FVM7T5B (Top Boot Block) 8/9 BLOCK ADDRESS BANK BLOCK # # BK14 BK15 ADDRESS RANGE BANK ADDRESS A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA224 H H H L L L L L * * * 700000h~707FFFh BA225 H H H L L L L H * * * 708000h~70FFFFh BA226 H H H L L L H L * * * 710000h~717FFFh BA227 H H H L L L H H * * * 718000h~71FFFFh BA228 H H H L L H L L * * * 720000h~727FFFh BA229 H H H L L H L H * * * 728000h~72FFFFh BA230 H H H L L H H L * * * 730000h~737FFFh BA231 H H H L L H H H * * * 738000h~73FFFFh BA232 H H H L H L L L * * * 740000h~747FFFh BA233 H H H L H L L H * * * 748000h~74FFFFh BA234 H H H L H L H L * * * 750000h~757FFFh BA235 H H H L H L H H * * * 758000h~75FFFFh BA236 H H H L H H L L * * * 760000h~767FFFh BA237 H H H L H H L H * * * 768000h~76FFFFh BA238 H H H L H H H L * * * 770000h~777FFFh BA239 H H H L H H H H * * * 778000h~77FFFFh BA240 H H H H L L L L * * * 780000h~787FFFh BA241 H H H H L L L H * * * 788000h~78FFFFh BA242 H H H H L L H L * * * 790000h~797FFFh BA243 H H H H L L H H * * * 798000h~79FFFFh BA244 H H H H L H L L * * * 7A0000h~7A7FFFh BA245 H H H H L H L H * * * 7A8000h~7AFFFFh BA246 H H H H L H H L * * * 7B0000h~7B7FFFh BA247 H H H H L H H H * * * 7B8000h~7BFFFFh BA248 H H H H H L L L * * * 7C0000h~7C7FFFh BA249 H H H H H L L H * * * 7C8000h~7CFFFFh BA250 H H H H H L H L * * * 7D0000h~7D7FFFh BA251 H H H H H L H H * * * 7D8000h~7DFFFFh BA252 H H H H H H L L * * * 7E0000h~7E7FFFh BA253 H H H H H H L H * * * 7E8000h~7EFFFFh BA254 H H H H H H H L * * * 7F0000h~7F7FFFh 2006-05-10 72/88 TC58FVM7(T/B)5B(TG/XG)65 20.1. TC58FVM7T5B (Top Boot Block) 9/9 BLOCK ADDRESS BANK BLOCK # # BK15 ADDRESS RANGE BANK ADDRESS A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA255 H H H H H H H H L L L 7F8000h~7F8FFFh BA256 H H H H H H H H L L H 7F9000h~7F9FFFh BA257 H H H H H H H H L H L 7FA000h~7FAFFFh BA258 H H H H H H H H L H H 7FB000h~7FBFFFh BA259 H H H H H H H H H L L 7FC000h~7FCFFFh BA260 H H H H H H H H H L H 7FD000h~7FDFFFh BA261 H H H H H H H H H H L 7FE000h~7FEFFFh BA262 H H H H H H H H H H H 7FF000h~7FFFFFh 2006-05-10 73/88 TC58FVM7(T/B)5B(TG/XG)65 20.2. TC58FVM7B5B (Bottom Boot Block) 1/9 BLOCK ADDRESS BANK BLOCK # # BK0 ADDRESS RANGE BANK ADDRESS A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA0 L L L L L L L L L L L 000000h~000FFFh BA1 L L L L L L L L L L H 001000h~001FFFh BA2 L L L L L L L L L H L 002000h~002FFFh BA3 L L L L L L L L L H H 003000h~003FFFh BA4 L L L L L L L L H L L 004000h~004FFFh BA5 L L L L L L L L H L H 005000h~005FFFh BA6 L L L L L L L L H H L 006000h~006FFFh BA7 L L L L L L L L H H H 007000h~007FFFh 2006-05-10 74/88 TC58FVM7(T/B)5B(TG/XG)65 20.2. TC58FVM7B5B (Bottom Boot Block) 2/9 BLOCK ADDRESS BANK BLOCK # # BK0 BK1 ADDRESS RANGE BANK ADDRESS A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA8 L L L L L L L H * * * 008000h~00FFFFh BA9 L L L L L L H L * * * 010000h~017FFFh BA10 L L L L L L H H * * * 018000h~01FFFFh BA11 L L L L L H L L * * * 020000h~027FFFh BA12 L L L L L H L H * * * 028000h~02FFFFh BA13 L L L L L H H L * * * 030000h~037FFFh BA14 L L L L L H H H * * * 038000h~03FFFFh BA15 L L L L H L L L * * * 040000h~047FFFh BA16 L L L L H L L H * * * 048000h~04FFFFh BA17 L L L L H L H L * * * 050000h~057FFFh BA18 L L L L H L H H * * * 058000h~05FFFFh BA19 L L L L H H L L * * * 060000h~067FFFh BA20 L L L L H H L H * * * 068000h~06FFFFh BA21 L L L L H H H L * * * 070000h~077FFFh BA22 L L L L H H H H * * * 078000h~07FFFFh BA23 L L L H L L L L * * * 080000h~087FFFh BA24 L L L H L L L H * * * 088000h~08FFFFh BA25 L L L H L L H L * * * 090000h~097FFFh BA26 L L L H L L H H * * * 098000h~09FFFFh BA27 L L L H L H L L * * * 0A0000h~0A7FFFh BA28 L L L H L H L H * * * 0A8000h~0AFFFFh BA29 L L L H L H H L * * * 0B0000h~0B7FFFh BA30 L L L H L H H H * * * 0B8000h~0BFFFFh BA31 L L L H H L L L * * * 0C0000h~0C7FFFh BA32 L L L H H L L H * * * 0C8000h~0CFFFFh BA33 L L L H H L H L * * * 0D0000h~0D7FFFh BA34 L L L H H L H H * * * 0D8000h~0DFFFFh BA35 L L L H H H L L * * * 0E0000h~0E7FFFh BA36 L L L H H H L H * * * 0E8000h~0EFFFFh BA37 L L L H H H H L * * * 0F0000h~0F7FFFh BA38 L L L H H H H H * * * 0F8000h~0FFFFFh 2006-05-10 75/88 TC58FVM7(T/B)5B(TG/XG)65 20.2. TC58FVM7B5B (Bottom Boot Block) 3/9 BLOCK ADDRESS BANK BLOCK # # BK2 BK3 ADDRESS RANGE BANK ADDRESS A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA39 L L H L L L L L * * * 100000h~107FFFh BA40 L L H L L L L H * * * 108000h~10FFFFh BA41 L L H L L L H L * * * 110000h~117FFFh BA42 L L H L L L H H * * * 118000h~11FFFFh BA43 L L H L L H L L * * * 120000h~127FFFh BA44 L L H L L H L H * * * 128000h~12FFFFh BA45 L L H L L H H L * * * 130000h~137FFFh BA46 L L H L L H H H * * * 138000h~13FFFFh BA47 L L H L H L L L * * * 140000h~147FFFh BA48 L L H L H L L H * * * 148000h~14FFFFh BA49 L L H L H L H L * * * 150000h~157FFFh BA50 L L H L H L H H * * * 158000h~15FFFFh BA51 L L H L H H L L * * * 160000h~167FFFh BA52 L L H L H H L H * * * 168000h~16FFFFh BA53 L L H L H H H L * * * 170000h~177FFFh BA54 L L H L H H H H * * * 178000h~17FFFFh BA55 L L H H L L L L * * * 180000h~187FFFh BA56 L L H H L L L H * * * 188000h~18FFFFh BA57 L L H H L L H L * * * 190000h~197FFFh BA58 L L H H L L H H * * * 198000h~19FFFFh BA59 L L H H L H L L * * * 1A0000h~1A7FFFh BA60 L L H H L H L H * * * 1A8000h~1AFFFFh BA61 L L H H L H H L * * * 1B0000h~1B7FFFh BA62 L L H H L H H H * * * 1B8000h~1BFFFFh BA63 L L H H H L L L * * * 1C0000h~1C7FFFh BA64 L L H H H L L H * * * 1C8000h~1CFFFFh BA65 L L H H H L H L * * * 1D0000h~1D7FFFh BA66 L L H H H L H H * * * 1D8000h~1DFFFFh BA67 L L H H H H L L * * * 1E0000h~1E7FFFh BA68 L L H H H H L H * * * 1E8000h~1EFFFFh BA69 L L H H H H H L * * * 1F0000h~1F7FFFh BA70 L L H H H H H H * * * 1F8000h~1FFFFFh 2006-05-10 76/88 TC58FVM7(T/B)5B(TG/XG)65 20.2. TC58FVM7B5B (Bottom Boot Block) 4/9 BLOCK ADDRESS BANK BLOCK # # BK4 BK5 ADDRESS RANGE BANK ADDRESS A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA71 L H L L L L L L * * * 200000h~207FFFh BA72 L H L L L L L H * * * 208000h~20FFFFh BA73 L H L L L L H L * * * 210000h~217FFFh BA74 L H L L L L H H * * * 218000h~21FFFFh BA75 L H L L L H L L * * * 220000h~227FFFh BA76 L H L L L H L H * * * 228000h~22FFFFh BA77 L H L L L H H L * * * 230000h~237FFFh BA78 L H L L L H H H * * * 238000h~23FFFFh BA79 L H L L H L L L * * * 240000h~247FFFh BA80 L H L L H L L H * * * 248000h~24FFFFh BA81 L H L L H L H L * * * 250000h~257FFFh BA82 L H L L H L H H * * * 258000h~25FFFFh BA83 L H L L H H L L * * * 260000h~267FFFh BA84 L H L L H H L H * * * 268000h~26FFFFh BA85 L H L L H H H L * * * 270000h~277FFFh BA86 L H L L H H H H * * * 278000h~27FFFFh BA87 L H L H L L L L * * * 280000h~287FFFh BA88 L H L H L L L H * * * 288000h~28FFFFh BA89 L H L H L L H L * * * 290000h~297FFFh BA90 L H L H L L H H * * * 298000h~29FFFFh BA91 L H L H L H L L * * * 2A0000h~2A7FFFh BA92 L H L H L H L H * * * 2A8000h~2AFFFFh BA93 L H L H L H H L * * * 2B0000h~2B7FFFh BA94 L H L H L H H H * * * 2B8000h~2BFFFFh BA95 L H L H H L L L * * * 2C0000h~2C7FFFh BA96 L H L H H L L H * * * 2C8000h~2CFFFFh BA97 L H L H H L H L * * * 2D0000h~2D7FFFh BA98 L H L H H L H H * * * 2D8000h~2DFFFFh BA99 L H L H H H L L * * * 2E0000h~2E7FFFh BA100 L H L H H H L H * * * 2E8000h~2EFFFFh BA101 L H L H H H H L * * * 2F0000h~2F7FFFh BA102 L H L H H H H H * * * 2F8000h~2FFFFFh 2006-05-10 77/88 TC58FVM7(T/B)5B(TG/XG)65 20.2. TC58FVM7B5B (Bottom Boot Block) 5/9 BLOCK ADDRESS BANK BLOCK # # BK6 BK7 ADDRESS RANGE BANK ADDRESS A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA103 L H H L L L L L * * * 300000h~307FFFh BA104 L H H L L L L H * * * 308000h~30FFFFh BA105 L H H L L L H L * * * 310000h~317FFFh BA106 L H H L L L H H * * * 318000h~31FFFFh BA107 L H H L L H L L * * * 320000h~327FFFh BA108 L H H L L H L H * * * 328000h~32FFFFh BA109 L H H L L H H L * * * 330000h~337FFFh BA110 L H H L L H H H * * * 338000h~33FFFFh BA111 L H H L H L L L * * * 340000h~347FFFh BA112 L H H L H L L H * * * 348000h~34FFFFh BA113 L H H L H L H L * * * 350000h~357FFFh BA114 L H H L H L H H * * * 358000h~35FFFFh BA115 L H H L H H L L * * * 360000h~367FFFh BA116 L H H L H H L H * * * 368000h~36FFFFh BA117 L H H L H H H L * * * 370000h~377FFFh BA118 L H H L H H H H * * * 378000h~37FFFFh BA119 L H H H L L L L * * * 380000h~387FFFh BA120 L H H H L L L H * * * 388000h~38FFFFh BA121 L H H H L L H L * * * 390000h~397FFFh BA122 L H H H L L H H * * * 398000h~39FFFFh BA123 L H H H L H L L * * * 3A0000h~3A7FFFh BA124 L H H H L H L H * * * 3A8000h~3AFFFFh BA125 L H H H L H H L * * * 3B0000h~3B7FFFh BA126 L H H H L H H H * * * 3B8000h~3BFFFFh BA127 L H H H H L L L * * * 3C0000h~3C7FFFh BA128 L H H H H L L H * * * 3C8000h~3CFFFFh BA129 L H H H H L H L * * * 3D0000h~3D7FFFh BA130 L H H H H L H H * * * 3D8000h~3DFFFFh BA131 L H H H H H L L * * * 3E0000h~3E7FFFh BA132 L H H H H H L H * * * 3E8000h~3EFFFFh BA133 L H H H H H H L * * * 3F0000h~3F7FFFh BA134 L H H H H H H H * * * 3F8000h~3FFFFFh 2006-05-10 78/88 TC58FVM7(T/B)5B(TG/XG)65 20.2. TC58FVM7B5B (Bottom Boot Block) 6/9 BLOCK ADDRESS BANK BLOCK # # BK8 BK9 ADDRESS RANGE BANK ADDRESS A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA135 H L L L L L L L * * * 400000h~407FFFh BA136 H L L L L L L H * * * 408000h~40FFFFh BA137 H L L L L L H L * * * 410000h~417FFFh BA138 H L L L L L H H * * * 418000h~41FFFFh BA139 H L L L L H L L * * * 420000h~427FFFh BA140 H L L L L H L H * * * 428000h~42FFFFh BA141 H L L L L H H L * * * 430000h~437FFFh BA142 H L L L L H H H * * * 438000h~43FFFFh BA143 H L L L H L L L * * * 440000h~447FFFh BA144 H L L L H L L H * * * 448000h~44FFFFh BA145 H L L L H L H L * * * 450000h~457FFFh BA146 H L L L H L H H * * * 458000h~45FFFFh BA147 H L L L H H L L * * * 460000h~467FFFh BA148 H L L L H H L H * * * 468000h~46FFFFh BA149 H L L L H H H L * * * 470000h~477FFFh BA150 H L L L H H H H * * * 478000h~47FFFFh BA151 H L L H L L L L * * * 480000h~487FFFh BA152 H L L H L L L H * * * 488000h~48FFFFh BA153 H L L H L L H L * * * 490000h~497FFFh BA154 H L L H L L H H * * * 498000h~49FFFFh BA155 H L L H L H L L * * * 4A0000h~4A7FFFh BA156 H L L H L H L H * * * 4A8000h~4AFFFFh BA157 H L L H L H H L * * * 4B0000h~4B7FFFh BA158 H L L H L H H H * * * 4B8000h~4BFFFFh BA159 H L L H H L L L * * * 4C0000h~4C7FFFh BA160 H L L H H L L H * * * 4C8000h~4CFFFFh BA161 H L L H H L H L * * * 4D0000h~4D7FFFh BA162 H L L H H L H H * * * 4D8000h~4DFFFFh BA163 H L L H H H L L * * * 4E0000h~4E7FFFh BA164 H L L H H H L H * * * 4E8000h~4EFFFFh BA165 H L L H H H H L * * * 4F0000h~4F7FFFh BA166 H L L H H H H H * * * 4F8000h~4FFFFFh 2006-05-10 79/88 TC58FVM7(T/B)5B(TG/XG)65 20.2. TC58FVM7B5B (Bottom Boot Block) 7/9 BLOCK ADDRESS BANK BLOCK # # BK10 BK11 ADDRESS RANGE BANK ADDRESS A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA167 H L H L L L L L * * * 500000h~507FFFh BA168 H L H L L L L H * * * 508000h~50FFFFh BA169 H L H L L L H L * * * 510000h~517FFFh BA170 H L H L L L H H * * * 518000h~51FFFFh BA171 H L H L L H L L * * * 520000h~527FFFh BA172 H L H L L H L H * * * 528000h~52FFFFh BA173 H L H L L H H L * * * 530000h~537FFFh BA174 H L H L L H H H * * * 538000h~53FFFFh BA175 H L H L H L L L * * * 540000h~547FFFh BA176 H L H L H L L H * * * 548000h~54FFFFh BA177 H L H L H L H L * * * 550000h~557FFFh BA178 H L H L H L H H * * * 558000h~55FFFFh BA179 H L H L H H L L * * * 560000h~567FFFh BA180 H L H L H H L H * * * 568000h~56FFFFh BA181 H L H L H H H L * * * 570000h~577FFFh BA182 H L H L H H H H * * * 578000h~57FFFFh BA183 H L H H L L L L * * * 580000h~587FFFh BA184 H L H H L L L H * * * 588000h~58FFFFh BA185 H L H H L L H L * * * 590000h~597FFFh BA186 H L H H L L H H * * * 598000h~59FFFFh BA187 H L H H L H L L * * * 5A0000h~5A7FFFh BA188 H L H H L H L H * * * 5A8000h~5AFFFFh BA189 H L H H L H H L * * * 5B0000h~5B7FFFh BA190 H L H H L H H H * * * 5B8000h~5BFFFFh BA191 H L H H H L L L * * * 5C0000h~5C7FFFh BA192 H L H H H L L H * * * 5C8000h~5CFFFFh BA193 H L H H H L H L * * * 5D0000h~5D7FFFh BA194 H L H H H L H H * * * 5D8000h~5DFFFFh BA195 H L H H H H L L * * * 5E0000h~5E7FFFh BA196 H L H H H H L H * * * 5E8000h~5EFFFFh BA197 H L H H H H H L * * * 5F0000h~5F7FFFh BA198 H L H H H H H H * * * 5F8000h~5FFFFFh 2006-05-10 80/88 TC58FVM7(T/B)5B(TG/XG)65 20.2. TC58FVM7B5B (Bottom Boot Block) 8/9 BLOCK ADDRESS BANK BLOCK # # BK12 BK13 ADDRESS RANGE BANK ADDRESS A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA199 H H L L L L L L * * * 600000h~607FFFh BA200 H H L L L L L H * * * 608000h~60FFFFh BA201 H H L L L L H L * * * 610000h~617FFFh BA202 H H L L L L H H * * * 618000h~61FFFFh BA203 H H L L L H L L * * * 620000h~627FFFh BA204 H H L L L H L H * * * 628000h~62FFFFh BA205 H H L L L H H L * * * 630000h~637FFFh BA206 H H L L L H H H * * * 638000h~63FFFFh BA207 H H L L H L L L * * * 640000h~647FFFh BA208 H H L L H L L H * * * 648000h~64FFFFh BA209 H H L L H L H L * * * 650000h~657FFFh BA210 H H L L H L H H * * * 658000h~65FFFFh BA211 H H L L H H L L * * * 660000h~667FFFh BA212 H H L L H H L H * * * 668000h~66FFFFh BA213 H H L L H H H L * * * 670000h~677FFFh BA214 H H L L H H H H * * * 678000h~67FFFFh BA215 H H L H L L L L * * * 680000h~687FFFh BA216 H H L H L L L H * * * 688000h~68FFFFh BA217 H H L H L L H L * * * 690000h~697FFFh BA218 H H L H L L H H * * * 698000h~69FFFFh BA219 H H L H L H L L * * * 6A0000h~6A7FFFh BA220 H H L H L H L H * * * 6A8000h~6AFFFFh BA221 H H L H L H H L * * * 6B0000h~6B7FFFh BA222 H H L H L H H H * * * 6B8000h~6BFFFFh BA223 H H L H H L L L * * * 6C0000h~6C7FFFh BA224 H H L H H L L H * * * 6C8000h~6CFFFFh BA225 H H L H H L H L * * * 6D0000h~6D7FFFh BA226 H H L H H L H H * * * 6D8000h~6DFFFFh BA227 H H L H H H L L * * * 6E0000h~6E7FFFh BA228 H H L H H H L H * * * 6E8000h~6EFFFFh BA229 H H L H H H H L * * * 6F0000h~6F7FFFh BA230 H H L H H H H H * * * 6F8000h~6FFFFFh 2006-05-10 81/88 TC58FVM7(T/B)5B(TG/XG)65 20.2. TC58FVM7B5B (Bottom Boot Block) 9/9 BLOCK ADDRESS BANK BLOCK # # BK14 BK15 ADDRESS RANGE BANK ADDRESS A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 BA231 H H H L L L L L * * * 700000h~707FFFh BA232 H H H L L L L H * * * 708000h~70FFFFh BA233 H H H L L L H L * * * 710000h~717FFFh BA234 H H H L L L H H * * * 718000h~71FFFFh BA235 H H H L L H L L * * * 720000h~727FFFh BA236 H H H L L H L H * * * 728000h~72FFFFh BA237 H H H L L H H L * * * 730000h~737FFFh BA238 H H H L L H H H * * * 738000h~73FFFFh BA239 H H H L H L L L * * * 740000h~747FFFh BA240 H H H L H L L H * * * 748000h~74FFFFh BA241 H H H L H L H L * * * 750000h~757FFFh BA242 H H H L H L H H * * * 758000h~75FFFFh BA243 H H H L H H L L * * * 760000h~767FFFh BA244 H H H L H H L H * * * 768000h~76FFFFh BA245 H H H L H H H L * * * 770000h~777FFFh BA246 H H H L H H H H * * * 778000h~77FFFFh BA247 H H H H L L L L * * * 780000h~787FFFh BA248 H H H H L L L H * * * 788000h~78FFFFh BA249 H H H H L L H L * * * 790000h~797FFFh BA250 H H H H L L H H * * * 798000h~79FFFFh BA251 H H H H L H L L * * * 7A0000h~7A7FFFh BA252 H H H H L H L H * * * 7A8000h~7AFFFFh BA253 H H H H L H H L * * * 7B0000h~7B7FFFh BA254 H H H H L H H H * * * 7B8000h~7BFFFFh BA255 H H H H H L L L * * * 7C0000h~7C7FFFh BA256 H H H H H L L H * * * 7C8000h~7CFFFFh BA257 H H H H H L H L * * * 7D0000h~7D7FFFh BA258 H H H H H L H H * * * 7D8000h~7DFFFFh BA259 H H H H H H L L * * * 7E0000h~7E7FFFh BA260 H H H H H H L H * * * 7E8000h~7EFFFFh BA261 H H H H H H H L * * * 7F0000h~7F7FFFh BA262 H H H H H H H H * * * 7F8000h~7FFFFFh 2006-05-10 82/88 TC58FVM7(T/B)5B(TG/XG)65 21. BLOCK SIZE TABLE 21.1. TC58FVM7T5B (Top Boot Block) BLOCK # BLOCK SIZE BANK # BANK SIZE BLOCK COUNT BA0~BA15 32 Kwords x 16 BK0 512 Kwords 16 BA16~BA31 32 Kwords x 16 BK1 512 Kwords 16 BA32~BA47 32 Kwords x 16 BK2 512 Kwords 16 BA48~BA63 32 Kwords x 16 BK3 512 Kwords 16 BA64~BA79 32 Kwords x 16 BK4 512 Kwords 16 BA80~BA95 32 Kwords x 16 BK5 512 Kwords 16 BA96~BA111 32 Kwords x 16 BK6 512 Kwords 16 BA112~BA127 32 Kwords x 16 BK7 512 Kwords 16 BA128~BA143 32 Kwords x 16 BK8 512 Kwords 16 BA144~BA159 32 Kwords x 16 BK9 512 Kwords 16 BA160~BA175 32 Kwords x 16 BK10 512 Kwords 16 BA176~BA191 32 Kwords x 16 BK11 512 Kwords 16 BA192~BA207 32 Kwords x 16 BK12 512 Kwords 16 BA208~BA223 32 Kwords x 16 BK13 512 Kwords 16 BA224~BA239 32 Kwords x 16 BK14 512 Kwords 16 BA240~BA262 32 Kwords x 15 + 4 Kwords x 8 BK15 512 Kwords 23 2006-05-10 83/88 TC58FVM7(T/B)5B(TG/XG)65 21.2. TC58FVM7B5B (Bottom Boot Block) BLOCK # BLOCK SIZE BANK # BANK SIZE BLOCK COUNT BA0~BA22 32 Kwords x 15 + 4 Kwords x 8 BK0 512 Kwords 23 BA23~BA38 32 Kwords x 16 BK1 512 Kwords 16 BA39~BA54 32 Kwords x 16 BK2 512 Kwords 16 BA55~BA70 32 Kwords x 16 BK3 512 Kwords 16 BA71~BA86 32 Kwords x 16 BK4 512 Kwords 16 BA87~BA102 32 Kwords x 16 BK5 512 Kwords 16 BA103~BA118 32 Kwords x 16 BK6 512 Kwords 16 BA119~BA134 32 Kwords x 16 BK7 512 Kwords 16 BA135~BA150 32 Kwords x 16 BK8 512 Kwords 16 BA151~BA166 32 Kwords x 16 BK9 512 Kwords 16 BA167~BA182 32 Kwords x 16 BK10 512 Kwords 16 BA183~BA198 32 Kwords x 16 BK11 512 Kwords 16 BA199~BA214 32 Kwords x 16 BK12 512 Kwords 16 BA215~BA230 32 Kwords x 16 BK13 512 Kwords 16 BA231~BA246 32 Kwords x 16 BK14 512 Kwords 16 BA247~BA262 32 Kwords x 16 BK15 512 Kwords 16 2006-05-10 84/88 TC58FVM7(T/B)5B(TG/XG)65 22. PACKAGE DIMENSIONS unit : mm 2006-05-10 85/88 TC58FVM7(T/B)5B(TG/XG)65 Unit: mm 0.145 0.055 20.0 0.2 1.0 0.1 0.1 0.05 1.2max 0~10 0.25 typ 18.4 0.1 0.1 29 14.4max 28 14.0 0.1 56 0.5 1 0.22 0.08 0.08 M TSOPI56-P-1420-0.50 0.5 0.1 PW-M-LD JEDEC EIAJ () IC 2-71 2006-05-10 86/88 TC58FVM7(T/B)5B(TG/XG)65 23. REVISION HISTORY Description Date Rev. 2004-07-22 1.00 Original version 2004-09-06 1.01 Change of the address which makes password unlock possible. 2004-10-04 1.02 The state of the RDY pin in password mode is added. 2004-10-13 1.03 Changed Specification (tSUSP) 2004-11-04 1.04 Changed of the comment. 2004-11-17 1.05 Changed the Hidden Rom Exit Address. 2005-01-11 1.06 Changed Specification (tSUSE/tREADY/tPPAW) 2005-02-28 1.07 2005-06-24 1.08 Changed an explanation of Simultaneous Read/Write Operation (p.9), and Package Dimensions of TFGBA. Changed Specification (VDD) 2005-08-02 1.09 Added Specification of Pin Capacitance. ( WP/ACC ) 2005-08-22 1.10 Added timing diagrams. 2005-08-29 1.11 Changed TSOP package name. (p.1) 2006-02-23 1.12 Comment addition of "Lead-Free". (p.1) 2006-05-10 1.13 Correct PIN ASSIGNMENT of TSOP. (p.4) Correct comment of Program Suspend/Resume and Erase Suspend/Resume. 2006-05-10 87/88 TC58FVM7(T/B)5B(TG/XG)65 RESTRICTIONS ON PRODUCT USE 030619EBA * The information contained herein is subject to change without notice. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. 2006-05-10 88/88