National currently produces seven versions of the INS8250 UART. Functionally, these parts appear to be the same, however, there are differences that the designer and purchaser need to understand. For each version, this document provides a brief overview of their distinct characteristics, a detailed function and timing section, a discussion of software compatibility issues and the AC timing parameters. 1.0 Part Summary The seven versions currently produced are designated INS8250, INS8250-B, INS8250A, NS16450, INS82C50A, NS16C450, and NS16550AF. These devices are grouped below by process type. C1995 National Semiconductor Corporation TL/C/9320 wants this part should order the NS16550AF. Section 5.0 describes the differences between the NS16550 and the NS16550AF in detail. CMOS DEVICES 1. INS82C50A: This is a CMOS version of the INS8250A. It functions identically and for most AC parameters has the same timing specification as the INS8250A (see Section 4.0). It draws approximately 1/10 (10 mA) of the maximum operating current of the INS8250A. 2. NS16C450: This is a CMOS version of the NS16450. It functions identically and for most AC parameters has the same timing specification as the NS16450 (see Section 4.0). It draws approximately 1/12 (10 mA) of the maximum operating current of the NS16450. Note: The XMOS and CMOS UARTs are not plug-in replacements for the INS8250/INS8250-B when used with ICUs that are in the popular edge-triggered configuration. However, there are easily implemented adjustments to the driving software or associated hardware that will allow these parts to be a plug-in replacement (see Section 6.0). TL/C/9320 - 1 FIGURE 1. Connection Diagram 2.0 INS8250 and INS8250-B Functional Considerations Designers using these parts should be aware of the following considerations. 1. When multiple interrupts are pending, the interrupt line (INTR) pulses low after each interrupt instead of remaining high continuously. Recommendation: This will not cause problems in normal operation, however, it is a condition necessary for compatibility in some popular 8086- and 80286-based microcomputers that use an edge-triggered ICU (see Section 6.0). RRD-B30M105/Printed in U. S. A. AN-493 XMOS DEVICES 1. INS8250: This is the original version produced by National. It is the same part as the INS8250-B, but with faster CPU bus timings. 2. INS8250-B: This is the slower speed (CPU bus timing) version of the INS8250. It is used by many popular 8088based microcomputers. 3. INS8250A: This is a revision of the INS8250 using the more advanced XMOS process. The INS8250A is better than the aforementioned parts due to the redesign (compare section 2.0 to 3.0) and the following process characteristicscloser threshold voltage control, more reliably implemented process topography and finer control over the active area critical dimensions. XMOS and CMOS parts should be used for all new designs. This part is used in many popular 8086-based microcomputers. 4. NS16450: This is the faster speed (CPU bus timing) version of the INS8250A. It is used by many popular 80286based microcomputers. 5. NS16550AF: This is the newest member of the UART family. It powers-up in the NS16450 mode and is completely compatible with all software written for the NS16450. It has advanced features such as on-board FIFOs, a DMA interface, faster CPU bus timings and a much higher maximum baud rate than the NS16450. The NS16550AF should be used for all new non-CMOS designs, including those that were originally done with the NS16550. It is used in recent versions of popular 80286based, 80386-based and ROMP-based microcomputers. Software written for the NS16550 is completely compatible with the NS16550AF. Section 5.0 describes how the software can distinguish between the NS16550 and the NS16550AF. 6. NS16550: This part powers-up in the NS16450 mode and is completely compatible with all software written for the NS16450. It has advanced features, such as a DMA interface. The on-board FIFOs are essentially non-functional. This part was issued on a limited basis. Any user that National Semiconductor Application Note 493 Martin S. Michael April 1989 A Comparison of the INS8250, NS16450 and NS16550AF Series of UARTs A Comparison of the INS8250, NS16450 and NS16550AF Series of UARTs items specify differences between XMOS and CMOS parts. They are applicable to the CMOS parts only: 2. Bit No. 6 (TSRE) of the line status register is set as soon as the transmitter shift register empties whether or not the transmitter holding register contains a character. Bit No. 6 is then reset when the transmitter shift register is reloaded. Recommendation: This will not cause problems in normal operation. However, it is a function tested on some popular 8088-based microcomputer systems diagnostic programs. 3. In loopback mode the modem control outputs RTS, DTR, OUT1 and OUT2 remain connected to the associated Modem Control Register bits. 1. Anytime a reset pulse is issued to the INS82C50A or NS16C450 the divisor latches must be rewritten with the appropriate divisors in order to start the baud rate generator. 2. tSI is from 16 to 48 RCLK cycles in length 5.0 NS16550AF and NS16550 Function and Timing Considerations All of the information present in Sections 3.0 and 3.1 is applicable to the NS16550AF and NS16550. The primary difference between these two parts is in the operation of the FIFOs. The NS16550 will sometimes transfer extra characters when the CPU reads the RX FIFO. Due to the asynchronous nature of this failure there is no workaround and the NS16550 should NOT be used in the FIFO mode. The NS16550AF has no problems operating in the FIFO mode and should be used on all new designs. The programmer should note the difference in the function of bit 6 in the Interrupt Identification Register (IIR6). This bit is permanently at logical 0 in the NS16550. In the NS16550AF this bit will be set to a 1 when the FIFOs are enabled. In both parts bit 7 of the IIR is set to a 1 when the FIFOs are enabled. Therefore, the program can distinguish when the FIFOs are enabled and whether the part is an NS16550AF or an NS16550 by checking these two bits. In order to enable the FIFO mode and set IIR6 and IIR7 bit 0 of the FIFO Control Register (FCR0) should be set. Remember unless both bits IIR6 and IIR7 are set, the program should not transfer data via the FIFOs. The following are improvements in the AC timings for the NS16550AF over the NS16450: 1. tAR changes from 60 ns to 30 ns. 3.0 INS8250A and NS16450 Function and Timing Considerations 1. The loopback diagnostic function sets the modem control outputs RTS, DTR, OUT1 and OUT2 to their inactive state (logic ``1''), so they will send no spurious signals. 2. A one byte scratch pad register is included at location 111. This register is not on the INS8250 or -B. 3. When multiple interrupts are pending the interrupt line remains high rather than pulsing low after each interrupt is serviced. The INS8250A and NS16450 have level sensitive interrupts as opposed to edge-triggered interrupts. This requires a change in the UART driver software or associated hardware if the INS8250A, NS16450 is used with some popular microcomputers, and their edge-triggered ICUs (see Section 6.0). 4. Bit 6 of the line status register is set to 1 when both the transmitter holding and shift register are empty. This causes the INS8250A and NS16450 to be incompatible with some INS8250 software utilizing this bit. 3.1 TIMING CONSIDERATIONS 1. A start bit will be sent typically 16 clocks (1 bit time) after the WRTHR signal goes active. 2. The leading edge of WRTHR resets THRE and TEMT. 3. All of the line status errors and the received data flag (DR, data ready) are set during the time of the first stop bit. 4. TEMT is set 2 RCLK clock periods after the stop bit(s) are sent. 5. The modem control register updates the modem outputs on the trailing edge of WRMCR. 2. tCSW changes from 50 ns to 30 ns. 3. tCSR changes from 50 ns to 30 ns. 4. RC changes from 360 ns to 280 ns. 5. tRC changes from 175 ns to 125 ns. 6. tDS changes from 40 ns to 30 ns. 7. tDH changes from 40 ns to 30 ns. 8. tAW changes from 60 ns to 30 ns. 9. tWC changes from 200 ns to 150 ns. 10. WC changes from 360 ns to 280 ns. 11. Timing parameters specified by tSINT will change in some cases when the FIFOs are enabled. Refer to the data sheet for specific changes. 4.0 INS82C50A and NS16C450 Function and Timing Considerations All of the information presented in Sections 3.0 through 3.2 is applicable to the CMOS parts. In addition, the following TL/C/9320 - 2 FIGURE 2. Serial Data Timing 2 6.2 CREATING AN INTERRUPT EDGE VIA SOFTWARE 6.0 Software Compatibility This is done by disabling and then re-enabling UART interrupts via the Interrupt Enable Register (IER) before a specific UART interrupt handling routine (line status errors, received data available, transmitter holding register empty or modem status) is exited. To disable interrupts write H'00 to the IER. To re-enable interrupts write a byte containing ones to the IER bit positions whose interrupts are supposed to be enabled. Two of the conditions present in the INS8250-B are required in many of these personal computers (see Items 1 and 2 in Section 2.0). These two detect multiple pending interrupts from the INS8250-B and test the baud rate. These two conditions were eliminated in the revision part and all parts thereafter. Thus, the more recent UARTs require that one of the following recommendations or a similar change is made to the target system. Changing the software or hardware allows the more recent UARTs to replace the INS8250-B. If the target system services the UART via polling rather than interrupts, then all of the more recent parts will be plug-in replacements for the INS8250-B. 6.3 CREATING AN INTERRUPT EDGE IN HARDWARE This is done externally to the UART. One approach is to connect the INTR pin of the UART to the input of an AND gate. The other input of this AND gate is connected to a signal that will always go low active when the UART is accessed (see Figure 3 ). The output of the AND gate is used as the interrupt to the ICU. Note: The NS16550AF has two pins with new functions (see the data sheet for specifics). 6.1 USING THE INS8250A, NS16450, INS82C50A, NS16C450 AND NS16550AF WITH EDGED-TRIGGERED ICUs Using these UARTs with an edge-triggered ICU as in some of the popular microcomputers requires a signal edge on the INTR pin for each pending UART interrupt. Otherwise, when multiple interrupts are pending the interrupt line will be constantly high active and the edge-triggered ICU will not request additional service for the UART. Note: This simple hardware recommendation will result in one invalid interrupt being generated, so the software routine should be able to handle this. The example shown below was tested using a modified asynchronous card in a few 8088-based microcomputer systems. 7.0 Acknowledgements The editor expresses his gratitude to all of the applications, design and field applications engineers whose laboratory and field research have discovered most of the technical information used in this document. TL/C/9320 - 4 FIGURE 3. Creating an INTR Edge in Hardware 3 4 Address Hold Time RD/RD Delay from Address Address Setup Time WR/WR Delay from Address Chip Select Hold Time Chip Select Setup Time Chip Select Output Delay from Select RD/RD Delay from Chip Select Chip Select Output Delay from Strobe WR/WR Delay from Select Data Hold Time Data Setup Time RD/RD to Floating Data Delay Master Reset Pulse Width Address Hold Time from RD/RD Read Cycle Delay Chip Select Hold Time from RD/RD RD/RD Strobe Width RD/RD Strobe Delay from ADS RD/RD Driver Enable/Disable Delay from RD/RD to Data Address Hold Time from WR/WR Write Cycle Delay tAH tAR tAS tAW tCH tCS tCSC tCSR tCSS tCSW tDH tDS tHZ tMR tRA tRC tRCS tRD tRDA tRDD tRVD tWA tWC (Note 1) (Note 8) (Notes 3, 8) (Note 1) (Note 1) (Notes 3, 8) (Note 1) (Note 1) (Notes 1, 8) (Note 1) (Note 1) Conditions NA e Not Applicable. Note 8: Loading of 100 pF. Note 3: Charge and discharge time is determined by VOL, VOH and the external timing. Note 1: Applicable only when ADS is tied low. Address Strobe Width Parameter tADS Symbol 150 20 NA 125 20 125 20 5 0 30 30 30 30 60 0 30 60 30 0 60 Min 125 60 100 NA NA Max NS16550AF AC Electrical Characteristics TA e 0 C to a 70 C, VCC e 5V g 5% 200 20 NA 125 20 175 20 5 0 40 40 50 50 60 0 60 60 60 0 60 Min 125 60 100 NA 100 Max NS16450 NS16C450 500 20 NA 175 20 500 20 10 0 90 60 80 80 90 0 80 90 80 0 90 Min 175 75 100 NA 125 Max INS8250A INS82C50A 1785 50 0 175 50 1735 50 10 0 175 60 160 0 110 110 0 160 110 110 0 90 Min 250 150 150 150 200 Max INS8250 1785 50 0 350 50 1735 50 10 0 350 100 160 0 110 110 60 160 110 110 60 120 Min 300 250 150 150 200 Max INS8250-B ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units 5 WR/WR Delay from Address WR/WR Strobe Width Duration of Clock High Pulse Duration of Clock Low Pulse Read Cycle e tAR a tDIW a tRC Write Cycle e tDDA a tDOW a tWC tWDA tWR tXH tXL RC WC Baud Output Positive Edge Delay Baud Output Negative Edge Delay Baud Output Up Time Baud Output Down Time tBHD tBLD tHW tLW Delay from Read to RXRDY Inactive Delay from RCLK to Sample Time Delay from Stop to Set Interrupt tRXI tSCD tSINT (Note 8) (Note 6) (Note 5) (Note 8) (Note 8) (Note 4) (Note 4) (Note 1) Conditions 100 75 1 280 280 55 55 100 NA 20 Min 1 RCLK 2000 290 1000 175 175 216b1 Max NS16550AF 425 250 1 360 360 140 140 100 NA 20 Min 1 RCLK 2000 NA 1000 175 175 216b1 Max NS16450 NS16C450 425 250 1 755 755 140 140 175 NA 20 Min 1 RCLK 2000 NA 1000 250 250 216b1 Max INS8250A INS82C50A 425 330 1 2100 2000 140 140 175 50 50 Min 2000 2000 NA 1000 250 250 216b1 Max INS8250 425 330 1 2305 2205 140 140 350 50 50 Min 2000 2000 NA 1000 250 250 216b1 Max INS8250-B ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units NA e Not Applicable. Note 8: Loading of 100 pF. Note 6: The maximum external clock for the NS16550AF is 8 MHz, NS16450 and INS8250A is 2.1 MHz and INS8250 and INS8250-B is 3.1 MHz. 100 pF load. This parameter is tested on the NS16550AF and guaranteed by design on all other parts. Note 5: The maximum external clock for the NS16550AF is 8 MHz, NS16450 and INS8250A is 3.1 MHz and INS8250 and INS8250-B is 3.1 MHz. 100 pF load. This parameter is tested on the NS16550AF and guaranteed by design on all other parts. Note 4: The maximum external clock for the NS16550AF is 8 MHz, NS16450 and INS8250A is 3.1 MHz and INS8250 and INS8250-B is 3.1 MHz. 100 pF load. Note 2: For the NS16550AF in the FIFO Mode (FCR0 e 1) the trigger level and timeout interrupts, the receiver data available indication, the active RXRDY indication and the overrun error indication will be delayed 3 RCLKs. Status indicators (PE, FE, BI) will be delayed 3 RCLKs after the first byte has been received. For subsequently received bytes these indicators will be updated immediately after RDRBR goes inactive. Note 1: Applicable only when ADS is tied low. Delay from RD/RD (RD RBR/RDLSR) to Reset Interrupt tRINT RECEIVER (Note 2) Baud Divisor N BAUD GENERATOR Chip Select Hold Time from WR/WR Parameter tWCS Symbol AC Electrical Characteristics TA e 0 C to a 70 C, VCC e 5V g 5% (Continued) 6 Delay from Initial INTR Reset to Transmit Start Delay from Initial Write to Interrupt Delay from Stop to Next Start Delay from Stop to Interrupt (THRE) Delay from Start to TXRDY Active tIRS tSI tSS tSTI tSXA Delay to Reset Interrupt from RD/RD (RD MSR) Delay to Set Interrupt from MODEM Input tRIM tSIM (Note 8) (Note 8) (Note 8) (Note 8) (Note 8) (Note 7) (Notes 7, 9) (Note 10) (Note 8) (Note 8) Conditions 8 16 8 Min 250 250 200 195 8 8 NA 24 24 250 175 Max NS16550AF 8 16 24 Min 250 250 200 NA NA 8 NA 24 40 250 175 Max NS16450 NS16C450 NA e Not Applicable. Note 9: For both the NS16C450 and INS82C50A the value of tSI will range from 16 to 48 baudout cycles. Note 10: For both the NS16C450 and the INS82C50A the value of tIRS will range from 24 to 40 baudout cycles. Note 8: Loading of 100 pF. Note 7: This delay will be lengthened by 1 character time, minus the last stop bit time if the transmitter interrupt delay circuit is active. Delay from WR/WR (WR MCR) to Output tMDO MODEM CONTROL Delay from Write to TXRDY Inactive Delay from RD/RD (RD IIR) to Reset Interrupt (THRE) tIR tWXI Delay from WR/WR (WR THR) to Reset Interrupt Parameter tHR TRANSMITTER Symbol AC Electrical Characteristics TA e 0 C to a 70 C, VCC e 5V g 5% (Continued) 8 16 24 Min 1000 1000 1000 NA NA 8 NA 24 40 1000 1000 Max INS8250A INS82C50A Min 1000 1000 1000 NA NA 8 1000 50 16 1000 1000 Max INS8250 Min 1000 1000 1000 NA NA 8 1000 50 16 1000 1000 Max INS8250-B ns ns ns ns Baudout Cycles Baudout Cycles ns Baudout Cycles Baudout Cycles ns ns Units 7 A Comparison of the INS8250, NS16450 and NS16550AF Series of UARTs Lit. Y 100493 LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: AN-493 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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