AN-493 - National Semiconductor

TL/C/9320

A Comparison of the INS8250, NS16450 and NS16550AF Series of UARTs AN-493

National Semiconductor

Application Note 493

Martin S. Michael

April 1989

A Comparison of the

INS8250, NS16450 and

NS16550AF Series of

UARTs

National currently produces seven versions of the INS8250

UART. Functionally, these parts appear to be the same,

however, there are differences that the designer and pur-

chaser need to understand. For each version, this docu-

ment provides a brief overview of their distinct characteris-

tics, a detailed function and timing section, a discussion of

software compatibility issues and the AC timing parameters.

1.0 Part Summary

The seven versions currently produced are designated

INS8250, INS8250-B, INS8250A, NS16450, INS82C50A,

NS16C450, and NS16550AF. These devices are grouped

below by process type.

XMOS DEVICES

1. INS8250: This is the original version produced by Nation-

al. It is the same part as the INS8250-B, but with faster

CPU bus timings.

2. INS8250-B: This is the slower speed (CPU bus timing)

version of the INS8250. It is used by many popular 8088-

based microcomputers.

3. INS8250A: This is a revision of the INS8250 using the

more advanced XMOS process. The INS8250A is better

than the aforementioned parts due to the redesign (com-

pare section 2.0 to 3.0) and the following process charac-

teristicsÐcloser threshold voltage control, more reliably

implemented process topography and finer control over

the active area critical dimensions. XMOS and CMOS

parts should be used for all new designs. This part is

used in many popular 8086-based microcomputers.

4. NS16450: This is the faster speed (CPU bus timing) ver-

sion of the INS8250A. It is used by many popular 80286-

based microcomputers.

5. NS16550AF: This is the newest member of the UART

family. It powers-up in the NS16450 mode and is com-

pletely compatible with all software written for the

NS16450. It has advanced features such as on-board

FIFOs, a DMA interface, faster CPU bus timings and a

much higher maximum baud rate than the NS16450. The

NS16550AF should be used for all new non-CMOS de-

signs, including those that were originally done with the

NS16550. It is used in recent versions of popular 80286-

based, 80386-based and ROMP-based microcomputers.

Software written for the NS16550 is completely compati-

ble with the NS16550AF. Section 5.0 describes how the

software can distinguish between the NS16550 and the

NS16550AF.

6. NS16550: This part powers-up in the NS16450 mode and

is completely compatible with all software written for the

NS16450. It has advanced features, such as a DMA inter-

face. The on-board FIFOs are essentially non-functional.

This part was issued on a limited basis. Any user that

wants this part should order the NS16550AF. Section 5.0

describes the differences between the NS16550 and the

NS16550AF in detail.

CMOS DEVICES

1. INS82C50A: This is a CMOS version of the INS8250A. It

functions identically and for most AC parameters has the

same timing specification as the INS8250A (see Section

4.0). It draws approximately 1/10 (10 mA) of the maxi-

mum operating current of the INS8250A.

2. NS16C450: This is a CMOS version of the NS16450. It

functions identically and for most AC parameters has the

same timing specification as the NS16450 (see Section

4.0). It draws approximately 1/12 (10 mA) of the maxi-

mum operating current of the NS16450.

Note: The XMOS and CMOS UARTs are not plug-in replacements for the

INS8250/INS8250-B when used with ICUs that are in the popular

edge-triggered configuration. However, there are easily implement-

ed adjustments to the driving software or associated hardware that

will allow these parts to be a plug-in replacement (see Section

6.0).

TL/C/9320–1

FIGURE 1. Connection Diagram

2.0 INS8250 and INS8250-B

Functional Considerations

Designers using these parts should be aware of the follow-

ing considerations.

1. When multiple interrupts are pending, the interrupt line

(INTR) pulses low after each interrupt instead of remain-

ing high continuously.

Recommendation: This will not cause problems in normal

operation, however, it is a condition necessary for com-

patibility in some popular 8086- and 80286-based micro-

computers that use an edge-triggered ICU (see Section

6.0).

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

2. Bit No. 6 (TSRE) of the line status register is set as soon

as the transmitter shift register empties whether or not

the transmitter holding register contains a character. Bit

No. 6 is then reset when the transmitter shift register is

reloaded.

Recommendation: This will not cause problems in normal

operation. However, it is a function tested on some popu-

lar 8088-based microcomputer systems diagnostic pro-

grams.

3. In loopback mode the modem control outputs RTS, DTR,

OUT1 and OUT2 remain connected to the associated

Modem Control Register bits.

3.0 INS8250A and NS16450

Function and Timing

Considerations

1. The loopback diagnostic function sets the modem control

outputs RTS, DTR, OUT1 and OUT2 to their inactive

state (logic ‘‘1’’), so they will send no spurious signals.

2. A one byte scratch pad register is included at location

111. This register is not on the INS8250 or -B.

3. When multiple interrupts are pending the interrupt line re-

mains high rather than pulsing low after each interrupt is

serviced. The INS8250A and NS16450 have level sensi-

tive interrupts as opposed to edge-triggered interrupts.

This requires a change in the UART driver software or

associated hardware if the INS8250A, NS16450 is used

with some popular microcomputers, and their edge-trig-

gered ICUs (see Section 6.0).

4. Bit 6 of the line status register is set to 1 when both the

transmitter holding and shift register are empty. This

causes the INS8250A and NS16450 to be incompatible

with some INS8250 software utilizing this bit.

3.1 TIMING CONSIDERATIONS

1. A start bit will be sent typically 16 clocks (1 bit time) after

the WRTHR signal goes active.

2. The leading edge of WRTHR resets THRE and TEMT.

3. All of the line status errors and the received data flag

(DR, data ready) are set during the time of the first stop

bit.

4. TEMT is set 2 RCLK clock periods after the stop bit(s) are

sent.

5. The modem control register updates the modem outputs

on the trailing edge of WRMCR.

4.0 INS82C50A and NS16C450

Function and Timing

Considerations

All of the information presented in Sections 3.0 through 3.2

is applicable to the CMOS parts. In addition, the following

items specify differences between XMOS and CMOS parts.

They are applicable to the CMOS parts only:

1. Anytime a reset pulse is issued to the INS82C50A or

NS16C450 the divisor latches must be rewritten with the

appropriate divisors in order to start the baud rate gener-

ator.

2. tSI is from 16 to 48 RCLK cycles in length

5.0 NS16550AF and NS16550 Func-

tion and Timing Considerations

All of the information present in Sections 3.0 and 3.1 is ap-

plicable to the NS16550AF and NS16550.

The primary difference between these two parts is in the

operation of the FIFOs. The NS16550 will sometimes trans-

fer extra characters when the CPU reads the RX FIFO. Due

to the asynchronous nature of this failure there is no work-

around and the NS16550 should NOT be used in the FIFO

mode. The NS16550AF has no problems operating in the

FIFO mode and should be used on all new designs.

The programmer should note the difference in the function

of bit 6 in the Interrupt Identification Register (IIR6). This bit

is permanently at logical 0 in the NS16550. In the

NS16550AF this bit will be set to a 1 when the FIFOs are

enabled. In both parts bit 7 of the IIR is set to a 1 when the

FIFOs are enabled. Therefore, the program can distinguish

when the FIFOs are enabled and whether the part is an

NS16550AF or an NS16550 by checking these two bits. In

order to enable the FIFO mode and set IIR6 and IIR7 bit 0 of

the FIFO Control Register (FCR0) should be set. Remember

unless both bits IIR6 and IIR7 are set, the program should

not transfer data via the FIFOs.

The following are improvements in the AC timings for the

NS16550AF over the NS16450:

1. tAR changes from 60 ns to 30 ns.

2. tCSW changes from 50 ns to 30 ns.

3. tCSR changes from 50 ns to 30 ns.

4. RC changes from 360 ns to 280 ns.

5. tRC changes from 175 ns to 125 ns.

6. tDS changes from 40 ns to 30 ns.

7. tDH changes from 40 ns to 30 ns.

8. tAW changes from 60 ns to 30 ns.

9. tWC changes from 200 ns to 150 ns.

10. WC changes from 360 ns to 280 ns.

11. Timing parameters specified by tSINT will change in

some cases when the FIFOs are enabled. Refer to the

data sheet for specific changes.

TL/C/9320–2

FIGURE 2. Serial Data Timing

6.0 Software Compatibility

Two of the conditions present in the INS8250-B are required

in many of these personal computers (see Items 1 and 2 in

Section 2.0). These two detect multiple pending interrupts

from the INS8250-B and test the baud rate. These two con-

ditions were eliminated in the revision part and all parts

thereafter. Thus, the more recent UARTs require that one of

the following recommendations or a similar change is made

to the target system. Changing the software or hardware

allows the more recent UARTs to replace the INS8250-B. If

the target system services the UART via polling rather than

interrupts, then all of the more recent parts will be plug-in

replacements for the INS8250-B.

Note: The NS16550AF has two pins with new functions (see the data sheet

for specifics).

6.1 USING THE INS8250A, NS16450, INS82C50A,

NS16C450 AND NS16550AF WITH EDGED-TRIGGERED

ICUs

Using these UARTs with an edge-triggered ICU as in some

of the popular microcomputers requires a signal edge on the

INTR pin for each pending UART interrupt. Otherwise, when

multiple interrupts are pending the interrupt line will be con-

stantly high active and the edge-triggered ICU will not re-

quest additional service for the UART.

6.2 CREATING AN INTERRUPT EDGE VIA SOFTWARE

This is done by disabling and then re-enabling UART inter-

rupts via the Interrupt Enable Register (IER) before a specif-

ic UART interrupt handling routine (line status errors, re-

ceived data available, transmitter holding register empty or

modem status) is exited. To disable interrupts write H’00 to

the IER. To re-enable interrupts write a byte containing ones

to the IER bit positions whose interrupts are supposed to be

enabled.

6.3 CREATING AN INTERRUPT EDGE IN HARDWARE

This is done externally to the UART. One approach is to

connect the INTR pin of the UART to the input of an AND

gate. The other input of this AND gate is connected to a

signal that will always go low active when the UART is ac-

cessed (see

Figure 3

). The output of the AND gate is used

as the interrupt to the ICU.

Note: This simple hardware recommendation will result in one invalid inter-

rupt being generated, so the software routine should be able to han-

dle this. The example shown below was tested using a modified asyn-

chronous card in a few 8088-based microcomputer systems.

7.0 Acknowledgements

The editor expresses his gratitude to all of the applications,

design and field applications engineers whose laboratory

and field research have discovered most of the technical

information used in this document.

TL/C/9320–4

FIGURE 3. Creating an INTR Edge in Hardware

AC Electrical Characteristics TAe0§Ctoa

70§C, VCC e5V g5%

NS16550AF NS16450 INS8250A INS8250 INS8250-B

Symbol Parameter Conditions NS16C450 INS82C50A Units

Min Max Min Max Min Max Min Max Min Max

tADS Address Strobe Width 60 60 90 90 120 ns

tAH Address Hold Time 0 0 0 0 60 ns

tAR RD/RD Delay from Address (Note 1) 30 60 80 110 110 ns

tAS Address Setup Time 60 60 90 110 110 ns

tAW WR/WR Delay from Address (Note 1) 30 60 80 160 160 ns

tCH Chip Select Hold Time 0 0 0 0 60 ns

tCS Chip Select Setup Time 60 60 90 110 110 ns

tCSC Chip Select Output Delay from Select (Notes 1, 8) NA 100 125 200 200 ns

tCSR RD/RD Delay from Chip Select (Note 1) 30 50 80 110 110 ns

tCSS Chip Select Output Delay from Strobe NA NA NA 0 150 0 150 ns

tCSW WR/WR Delay from Select (Note 1) 30 50 80 160 160 ns

tDH Data Hold Time 30 40 60 60 100 ns

tDS Data Setup Time 30 40 90 175 350 ns

tHZ RD/RD to Floating Data Delay (Notes 3, 8) 0 100 0 100 0 100 0 150 0 150 ns

tMR Master Reset Pulse Width 5 5 10 10 10 ms

tRA Address Hold Time from RD/RD (Note 1) 20 20 20 50 50 ns

tRC Read Cycle Delay 125 175 500 1735 1735 ns

tRCS Chip Select Hold Time from RD/RD (Note 1) 20 20 20 50 50 ns

tRD RD/RD Strobe Width 125 125 175 175 350 ns

tRDA RD/RD Strobe Delay from ADS NA NA NA 0 0 ns

tRDD RD/RD Driver Enable/Disable (Notes 3, 8) 60 60 75 150 250 ns

tRVD Delay from RD/RD to Data (Note 8) 125 125 175 250 300 ns

tWA Address Hold Time from WR/WR (Note 1) 20 20 20 50 50 ns

tWC Write Cycle Delay 150 200 500 1785 1785 ns

Note 1: Applicable only when ADS is tied low.

Note 3: Charge and discharge time is determined by VOL,V

OH and the external timing.

Note 8: Loading of 100 pF.

NA eNot Applicable.

AC Electrical Characteristics TAe0§Ctoa

70§C, VCC e5V g5% (Continued)

NS16550AF NS16450 INS8250A INS8250 INS8250-B

Symbol Parameter Conditions NS16C450 INS82C50A Units

Min Max Min Max Min Max Min Max Min Max

tWCS Chip Select Hold Time from WR/WR (Note 1) 20 20 20 50 50 ns

tWDA WR/WR Delay from Address NA NA NA 50 50 ns

tWR WR/WR Strobe Width 100 100 175 175 350 ns

tXH Duration of Clock High Pulse (Note 4) 55 140 140 140 140 ns

tXL Duration of Clock Low Pulse (Note 4) 55 140 140 140 140 ns

RC Read Cycle etAR atDIW atRC 280 360 755 2000 2205 ns

WC Write Cycle etDDA atDOW atWC 280 360 755 2100 2305 ns

BAUD GENERATOR

N Baud Divisor 1 216b112

16b112

16b1ns

BHD Baud Output Positive Edge Delay (Note 8) 175 175 250 250 250 ns

tBLD Baud Output Negative Edge Delay (Note 8) 175 175 250 250 250 ns

tHW Baud Output Up Time (Note 5) 75 250 250 330 330 ns

tLW Baud Output Down Time (Note 6) 100 425 425 425 425 ns

RECEIVER (Note 2)

tRINT Delay from RD/RD (RD RBR/RDLSR) (Note 8) 1000 1000 1000 1000 1000 ns

to Reset Interrupt

tRXI Delay from Read to RXRDY Inactive 290 NA NA NA NA ns

tSCD Delay from RCLK to Sample Time 2000 2000 2000 2000 2000 ns

tSINT Delay from Stop to Set Interrupt 1 RCLK 1 RCLK 1 RCLK 2000 2000 ns

Note 1: Applicable only when ADS is tied low.

Note 2: For the NS16550AF in the FIFO Mode (FCR0 e1) the trigger level and timeout interrupts, the receiver data available indication, the active RXRDY indication and the overrun error indication will be delayed 3 RCLKs. Status

indicators (PE, FE, BI) will be delayed 3 RCLKs after the first byte has been received. For subsequently received bytes these indicators will be updated immediately after RDRBR goes inactive.

Note 4: The maximum external clock for the NS16550AF is 8 MHz, NS16450 and INS8250A is 3.1 MHz and INS8250 and INS8250-B is 3.1 MHz. 100 pF load.

Note 5: The maximum external clock for the NS16550AF is 8 MHz, NS16450 and INS8250A is 3.1 MHz and INS8250 and INS8250-B is 3.1 MHz. 100 pF load. This parameter is tested on the NS16550AF and guaranteed by design

on all other parts.

Note 6: The maximum external clock for the NS16550AF is 8 MHz, NS16450 and INS8250A is 2.1 MHz and INS8250 and INS8250-B is 3.1 MHz. 100 pF load. This parameter is tested on the NS16550AF and guaranteed by design

on all other parts.

Note 8: Loading of 100 pF.

NA eNot Applicable.

AC Electrical Characteristics TAe0§Ctoa

70§C, VCC e5V g5% (Continued)

NS16550AF NS16450 INS8250A INS8250 INS8250-B

Symbol Parameter Conditions NS16C450 INS82C50A Units

Min Max Min Max Min Max Min Max Min Max

TRANSMITTER

tHR Delay from WR/WR (WR THR) (Note 8) 175 175 1000 1000 1000 ns

to Reset Interrupt

tIR Delay from RD/RD (RD IIR) to (Note 8) 250 250 1000 1000 1000 ns

Reset Interrupt (THRE)

tIRS Delay from Initial INTR Reset (Note 10) 8 24244024 40 16 16

Baudout

to Transmit Start Cycles

tSI Delay from Initial Write to Interrupt (Notes 7, 9) 16 24 16 24 16 24 50 50 Baudout

Cycles

tSS Delay from Stop to Next Start NA NA NA 1000 1000 ns

tSTI Delay from Stop to Interrupt (THRE) (Note 7) 88888 8 8 8

Baudout

Cycles

tSXA Delay from Start to TXRDY Active (Note 8) 8NANANANA

Baudout

Cycles

tWXI Delay from Write to TXRDY Inactive (Note 8) 195 NA NA NA NA ns

MODEM CONTROL

tMDO Delay from WR/WR (Note 8) 200 200 1000 1000 1000 ns

(WR MCR) to Output

tRIM Delay to Reset Interrupt from (Note 8) 250 250 1000 1000 1000 ns

RD/RD (RD MSR)

tSIM Delay to Set Interrupt from MODEM Input (Note 8) 250 250 1000 1000 1000 ns

Note 7: This delay will be lengthened by 1 character time, minus the last stop bit time if the transmitter interrupt delay circuit is active.

Note 8: Loading of 100 pF.

Note 9: For both the NS16C450 and INS82C50A the value of tSI will range from 16 to 48 baudout cycles.

Note 10: For both the NS16C450 and the INS82C50A the value of tIRS will range from 24 to 40 baudout cycles.

NA eNot Applicable.

AN-493 A Comparison of the INS8250, NS16450 and NS16550AF Series of UARTs

Lit. Ý100493

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