1
Microsemi Corporation
Copyright 2014, Microsemi Corporation All Rights Reserved.
Features
Inputs/Outputs
• Accepts differential or single-ended input
• LVPECL, LVDS, CML, HCSL, LVCMOS
• Eight precision LVDS outputs
• Operating frequency up to 750 MHz
Power
• Option for 2.5 V or 3.3 V power supply
• Current consumption of 106 mA
• On-chip Low Drop Out (LDO) Regulator for superior
power supply noise rejection
Performance
• Ultra low additive jitter of 104 fs RMS
Applications
• General purpose clock distribution
• Low jitter clock trees
• Logic translation
• Clock and data signal restoration
• Wired communications: OTN, SONET/SDH, GE,
10 GE, FC and 10G FC
• PCI Express generation 1/2/3 clock distribution
• Wireless communications
• High performance microprocessor clock
distribution
April 2014
Figure 1 - Functional Block Diagram
clk_p
clk_n
out6_p
out6_n
out5_p
out5_n
out7_p
out7_n
out4_p
out4_n
out3_p
out3_n
out2_p
out2_n
out1_p
out1_n
out0_p
out0_n
Buffer
ZL40218
Precision 1:8 LVDS Fanout Buffer
Data Sheet
Ordering Information
ZL40218LDG1 32 Pin QFN Trays
ZL40218LDF1 32 Pin QFN Tape and Reel
Matte Tin
Package Size: 5 x 5 mm
-40oC to +85oC
ZL40218 Data Sheet
Table of Contents
2
Microsemi Corporation
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.0 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Device Additive Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.1 Sensitivity to power supply noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.2 Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.3 PCB layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.0 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.0 Performance Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.0 Typical Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.0 Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.0 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ZL40218 Data Sheet
List of Figures
3
Microsemi Corporation
Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3 - LVPECL Input DC Coupled Thevenin Equivalent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4 - LVPECL Input DC Coupled Parallel Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5 - LVPECL Input AC Coupled Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6 - LVDS Input DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7 - LVDS Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8 - CML Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9 - HCSL Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10 - CMOS Input DC Coupled Referenced to VDD/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 11 - CMOS Input DC Coupled Referenced to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 12 - Simplified LVDS Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 13 - LVDS DC Coupled Termination (Internal Receiver Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 14 - LVDS DC Coupled Termination (External Receiver Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 15 - LVDS AC Coupled Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 16 - LVDS AC Output Termination for CML Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 17 - Additive Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 18 - Decoupling Connections for Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 19 - Differential Voltage Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 20 - Input To Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ZL40218 Data Sheet
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Microsemi Corporation
Change Summary
Page Item Change
1Applications Added PCI Express clock distribution.
6Pin Description Added exposed pad to Pin Description.
7, 8Figure 3 and Figure 4 Removed 22 Ohm series resistors from Figure 3 and 4. These
resistors are not required; however there is no impact to
performance if the resistors are included.
16 Power supply filtering Corrected typo of 0.3 ohm to 0.15 ohm.
18 Figure 19 Clarification of VID and VOD.
Below are the changes from the February 2013 issue to the April 2014 issue:
Page Item Change
8Figure 4 Changed text to indicate the circuit is not recommended for
VDD_driver=2.5V.
8Figure 5 Changed pull-up and pull-down resistors from 2kOhm to
100 Ohm.
12 Figure 12 Changed gate values to +/+ on the left and -/- on the right.
Below are the changes from the November 2012 issue to the February 2013 issue:
ZL40218 Data Sheet
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Microsemi Corporation
1.0 Package Description
The device is packaged in a 32 pin QFN
26
28
30
32
12
10
8
64
2
out7_n
out6_p
out5_n
out6_n
IC
gnd
clk_p
VDD_core
out2_n
NC
out1_n
out2_p
gnd
out4_n
vdd
gnd
out3_p
14
16
18
2224 20
vdd
out0_p
out1_p
out7_p
clk_n
out3_n
gnd out4_p
vdd
NC
out0_n
VDD_core
out5_p
vdd
vt
gnd (E-pad)
NC
Figure 2 - Pin Connections
ZL40218 Data Sheet
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Microsemi Corporation
2.0 Pin Description
Pin # Name Description
3, 6 clk_p, clk_n, Differential Input (Analog Input). Differential (or single ended) input signals.
For all input configurations see section 3.1, “Clock Inputs“.
30, 29,
28, 27,
26, 25,
24, 23,
18, 17,
16, 15,
14, 13,
12, 11
out0_p, out0_n
out1_p, out1_n
out2_p, out2_n
out3_p, out3_n
out4_p, out4_n
out5_p, out5_n
out6_p, out6_n
out7_p, out7_n
Differential Output (Analog Output). Differential outputs.
9, 19,
22, 32
vdd Positive Supply Voltage. 2.5 VDC or 3.3 VDC nominal.
1, 8 vdd_core Positive Supply Voltage. 2.5 VDC or 3.3 VDC nominal.
2, 7,
20, 21
gnd Ground. 0 V.
4, 5
10, 31
NC No Connection. Leave unconnected.
Exposed Pad Device GND.
ZL40218 Data Sheet
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Microsemi Corporation
3.0 Functional Description
The ZL40218 is an LVDS clock fanout buffer with eight identical output clock drivers capable of operating at
frequencies up to 750MHz.
Inputs to the ZL40218 are externally terminated to allow use of precision termination components and to allow full
flexibility of input termination. The ZL40218 can accept DC coupled LVPECL or LVDS and AC coupled LVPECL,
LVDS, CML or HCSL input signals; single ended input signals can also be accepted. A pin compatible device with
internal termination is also available.
The ZL40218 is designed to fan out low-jitter reference clocks for wired or optical communications applications
while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors
minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its
operation is guaranteed over the industrial temperature range -40°C to +85°C.
The device block diagram is shown in Figure 1; its operation is described in the following sections.
3.1 Clock Inputs
The ZL40218 is adaptable to support different types of differential and singled-ened input signals depending on the
passive components used in the input termination. The application diagrams in the following figures allow the
ZL40218 to accept LVPECL, LVDS, CML, HCSL and single-ended inputs.
50
Ohms
50
Ohms
VDD_driver
VDD
VDD_driver=3.3V:R1=50 ohm
NotrecommendedforVDD_driver=2.5V
ZL40218
clk_p
clk_n
Zo=50Ohms
Zo=50Ohms
R1
LVPECL
Driver
Figure 3 - LVPECL Input DC Coupled Thevenin Equivalent
VDD_driver
R2 R2
R1 R1
VDD_driver
VDD
ForVDD_Rx=3.3V:R1=82Ohms,R2=127Ohms
ForVDD_Rx=2.5V:R1=62.5Ohms,R2=250Ohms
ZL40218
clk_p
clk_n
Zo=50Ohms
Zo=50Ohms
LVPECL
Driver
Figure 4 - LVPECL Input DC Coupled Parallel Termination
RR
VDD_driver
VDD
VDD_driver=3.3V:R=143ohm
VDD_driver=2.5V:R=82ohm
ZL40218
clk_p
clk_n
Zo=50Ohms
Zo=50Ohms
LVPECL
Driver
VDD
100
Ohm
100
Ohm
100
Ohm
100
Ohm
100nF
100nF
Figure 5 - LVPECL Input AC Coupled Termination
ZL40218 Data Sheet
8
Microsemi Corporation
Zo=50Ohms
VDD_driver
VDD
ZL40218
clk_p
clk_n
Zo=50Ohms
100
Ohms
LVDS
Driver
Figure 6 - LVDS Input DC Coupled
VDD
2K
Ohm
VDD_driver
VDD
ZL40218
clk_p
clk_n
Zo=50Ohms
Zo=50Ohms
2K
Ohm
2K
Ohm
2K
Ohm
100Ohm
LVDS
Driver
100nF
100nF
Figure 7 - LVDS Input AC Coupled
ZL40218 Data Sheet
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Microsemi Corporation
VDD
2K
Ohm
VDD_driver
VDD
ZL40218
clk_p
clk_n
Zo=50Ohms
Zo=50Ohms
2K
Ohm
2K
Ohm
2K
Ohm
CML
Driver
100nF
100nF
VDD_driver
50
Ohm
50
Ohm
Figure 8 - CML Input AC Coupled
VDD
2K
Ohm
VDD_driver
VDD
ZL40218
clk_p
clk_n
Zo=50Ohms
Zo=50Ohms
2K
Ohm
2K
Ohm
2K
Ohm
HCSL
Driver
100nF
100nF
50
Ohm
50
Ohm
Figure 9 - HCSL Input AC Coupled
ZL40218 Data Sheet
10
Microsemi Corporation
VDD_driver
VDD_driver VDD
ZL40218
clk_p
clk_n
CMOS
Driver
R
R
C
Vref=VDD_driver/2
R=10kohms,C=100nF
Figure 10 - CMOS Input DC Coupled Referenced to VDD/2
VDD
VDD_driver VDD
ZL40218
clk_p
clk_n
CMOS
Driver
R2
C
RA
R3
R1
Figure 11 - CMOS Input DC Coupled Referenced to Ground
Table 1 - Component Values for Single Ended Input Reference to Ground
VDD_driver R1 (kΩ)R2 (kΩ)R3 (kΩ)RA (kΩ)C (pF)
1.5 1.25 3.075 open 10 10
1.8 13.8 open 10 10
2.5 0.33 4.2 open 10 10
3.3 0.75 open 4.2 10 10
ZL40218 Data Sheet
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Microsemi Corporation
* For frequencies below 100 MHz, increase C to avoid signal integrity issues.
ZL40218 Data Sheet
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Microsemi Corporation
3.2 Clock Outputs
LVDS has lower signal swing than LVPECL which results in a low power consumption. A simplified diagram for the
LVDS output stage is shown in Figure 12.
VDD
3mA
Output
+
+
‐
‐
Figure 12 - Simplified LVDS Output Driver
The methods to terminate the ZL40218 drivers are shown in the following figures.
LVDS
Receiver
VDD
Zo=50Ohms
Zo=50Ohms
ZL40218
clk_p
clk_n
VDD_Rx
Figure 13 - LVDS DC Coupled Termination (Internal Receiver Termination)
LVDS
Receiver
VDD VDD_Rx
Zo=50Ohms
Zo=50Ohms
ZL40218
clk_p
clk_n
100Ohms
Figure 14 - LVDS DC Coupled Termination (External Receiver Termination)
LVDS
Receiver
VDD
VDD_Rx
Zo=50Ohms
Zo=50Ohms
ZL40218
clk_p
clk_n
100Ohms
R2
VDD_Rx
R1 R1
R2
Note:R1andR2valuesandneedforexternaltermination
dependonthespecificationoftheLVDSreceiver
Figure 15 - LVDS AC Coupled Termination
ZL40218 Data Sheet
13
Microsemi Corporation
ZL40218 Data Sheet
14
Microsemi Corporation
Figure 16 - LVDS AC Output Termination for CML Inputs
CML
Receiver
VDD
Zo=50Ohms
Zo=50Ohms
ZL40218
clk_p
clk_n
VDD_Rx
50Ohms
50Ohms
ZL40218 Data Sheet
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Microsemi Corporation
3.3 Device Additive Jitter
The ZL40218 clock fanout buffer is not intended to filter clock jitter. The jitter performance of this type of device is
characterized by its additive jitter. Additive jitter is the jitter the device would add to a hypothetical jitter-free clock as
it passes through the device. The additive jitter of the ZL40218 is random and as such it is not correlated to the jitter
of the input clock signal.
The square of the resultant random RMS jitter at the output of the ZL40218 is equal to the sum of the squares of the
various random RMS jitter sources including: input clock jitter; additive jitter of the buffer; and additive jitter due to
power supply noise. There may be additional deterministic jitter sources, but they are not shown in Figure 17.
+
Jin
2
Jadd
2Jps
2
Jin =Randominputclockjitter(RMS)
Jadd =Additivejitterduetothedevice(RMS)
Jps=Additivejitterduetopowersupplynoise(RMS)
Jout=Resultantrandomoutputclockjitter(RMS)
+Jout
2=Jin
2+Jadd
2+Jps
2
Figure 17 - Additive Jitter
ZL40218 Data Sheet
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Microsemi Corporation
3.4 Power Supply
This device operates employing either a 2.5V supply or 3.3V supply.
3.4.1 Sensitivity to power supply noise
Power supply noise from sources such as switching power supplies and high-power digital components such as
FPGAs can induce additive jitter on clock buffer outputs. The ZL40218 is equipped with an on-chip linear power
regulator and on-chip bulk capacitors to minimize additive jitter due to power supply noise.The on-chip regulation,
recommended power supply filtering, and good PCB layout all work together to minimize the additive jitter from
power supply noise.
3.4.2 Power supply filtering
Jitter levels may increase when noise is present on the power pins. For optimal jitter performance, the device
should be isolated from the power planes connected to its power supply pins as shown in Figure .
• 10 µF capacitors should be size 0603 or size 0805 X5R or X7R ceramic, 6.3 V minimum rating
• 0.1 µF capacitors should be size 0402 X5R ceramic, 6.3 V minimum rating
• Capacitors should be placed next to the connected device power pins
•A 0.15 Ohm resistor is recommended
ZL40218
1
8
9
19
22
32
0.1 µF
0.1 µF
vdd_core
10 µF
0.1 µF
0.15 Ω
vdd
0.1 µF
10 µF
Figure 18 - Decoupling Connections for Power Pins
3.4.3 PCB layout considerations
The power nets in Figure can be implemented either as a plane island or routed power topology without changing
the overall jitter performance of the device.
Absolute Maximum Ratings*
Parameter Sym. Min. Max. Units
1Supply voltage VDD_R -0.5 4.6 V
2Voltage on any digital pin VPIN -0.5 VDD V
3Soldering temperature T260 °C
4Storage temperature TST -55 125 °C
5Junction temperature Tj125 °C
6Voltage on input pin Vinput VDD V
7Input capacitance each pin Cp500 fF
ZL40218 Data Sheet
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Microsemi Corporation
4.0 AC and DC Electrical Characteristics
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
* Voltages are with respect to ground (GND) unless otherwise stated
Recommended Operating Conditions*
Characteristics Sym. Min. Typ. Max. Units
1Supply voltage 2.5 V mode VDD25 2.375 2.5 2.625 V
2Supply voltage 3.3 V mode VDD33 3.135 3.3 3.465 V
3Operating temperature TA-40 25 85 °C
* Voltages are with respect to ground (GND) unless otherwise stated
DC Electrical Characteristics - Current Consumption
Characteristics Sym. Min. Typ. Max. Units Notes
1Supply current LVDS drivers - loaded
(all outputs are active)
Idd_load 106 mA
DC Electrical Characteristics - Inputs and Outputs - for 2.5/3.3 V Supply
Characteristics Sym. Min. Typ. Max. Units Notes
1Differential input common mode
voltage
VICM 1.1 1.6 Vfor 2.5 V
2Differential input common mode
voltage
VICM 1.1 2.0 Vfor 3.3 V
3Differential input voltage difference VID 0.25 1 V
4Differential input resistance VIR 80 100 120 ohm
5LVDS output differential voltage* VOD 0.25 0.30 0.40 V
6LVDS Common Mode voltage VCM 1.1 1.25 1.375 V
* The VOD parameter was measured between 125 and 750 MHz
outx_p
outx_n
VOD
outx_p – outx_n
GND VICM
02*VOD
clk_p – clk_n
02*VID
clk_p
clk_n
VID
GND VCM
AC Electrical Characteristics* - Inputs and Outputs (see Figure 20) - for 2.5/3.3 V supply.
Characteristics Sym. Min. Typ. Max. Units Notes
1Maximum Operating Frequency 1/tp750 MHz
2Input to output clock propagation delay tpd 0 1 2 ns
3Output to output skew tout2out 80 150 ps
4Part to part output skew tpart2part 120 300 ps
5Output clock Duty Cycle degradation tPWH/ tPWL -5 0 5 Percent
6LVDS Output slew rate rSL 0.55 V/ns
ZL40218 Data Sheet
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Microsemi Corporation
Figure 19 - Differential Voltage Parameter
* Supply voltage and operating temperature are as per Recommended Operating Conditions
Input
tP
tPWL
tpd
tPWH
Output
Figure 20 - Input To Output Timing
Additive Jitter at 2.5 V*
Output Frequency (MHz)
Jitter
Measurement
Filter
Typical
RMS (fs) Notes
1125 12 kHz - 20 MHz 148
2212.5 12 kHz - 20 MHz 138
3311.04 12 kHz - 20 MHz 121
4425 12 kHz - 20 MHz 115
5500 12 kHz - 20 MHz 107
6622.08 12 kHz - 20 MHz 107
7750 12 kHz - 20 MHz 105
Additive Jitter at 3.3 V*
Output Frequency (MHz)
Jitter
Measurement
Filter
Typical
RMS (fs) Notes
1125 12 kHz - 20 MHz 150
2212.5 12 kHz - 20 MHz 138
3311.04 12 kHz - 20 MHz 120
4425 12 kHz - 20 MHz 115
5500 12 kHz - 20 MHz 107
6622.08 12 kHz - 20 MHz 106
7750 12 kHz - 20 MHz 104
ZL40218 Data Sheet
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Microsemi Corporation
5.0 Performance Characterization
*The values in this table were taken with a slew rate of approximately 0.8 V/ns.
*The values in this table were taken with a slew rate of approximately 0.8 V/ns.
Additive Jitter from a Power Supply Tone*
Carrier frequency Parameter Typical Units Notes
125MHz 25 mV at 100 kHz 24 fs RMS
750MHz 25 mV at 100 kHz 23 fs RMS
* The values in this table are the additive periodic jitter caused by an interfering tone typically caused by a switching power supply. For this test,
measurements were taken over the full temperature and voltage range for VDD = 3.3 V. The magnitude of the interfering tone is measured at the
DUT.
ZL40218 Data Sheet
20
Microsemi Corporation
6.0 Typical Behavior
Typical Waveform at 155.52 MHz VOD vs Frequency
Power Supply Tone Frequency versus PSRR Power Supply Tone Magnitude versus PSRR
Propagation Delay versus Temperature
Note: This is for a single device. For more details, see the
characterization section.
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0 5 10 15 20
Voltage
Time (ns)
0.3
0.31
0.32
0.33
0.34
0.35
0 100 200 300 400 500 600 700 800
VOD
Frequency (MHz)
-90
-85
-80
-75
-70
-65
-60
100 150 200 250 300 350 400 450 500
PSRR (dBc)
Tone Frequency (kHz)
125 MHz
212.5 MHz
425 MHz
750 MHz
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
20 30 40 50 60 70 80 90 100
PSRR (dBc)
Tone Magnitude (mV)
125 MHz
212.5 MHz
425 MHz
750 MHz
0.6
0.65
0.7
0.75
0.8
0.85
0.9
-40 -20 0 20 40 60 80 100
Delay (ns)
Temperature ( C)
ZL40218 Data Sheet
21
Microsemi Corporation
7.0 Package Characteristics
Thermal Data
Parameter Symbol Test Condition Value Unit
Junction to Ambient Thermal Resistance ΘJA Still Air
1 m/s
2 m/s
37.4
33.1
31.5
oC/W
Junction to Case Thermal Resistance ΘJC 24.4 oC/W
Junction to Board Thermal Resistance ΘJB 19.5 oC/W
Maximum Junction Temperature* Tjmax 125 oC
Maximum Ambient Temperature TA85 oC
ZL40218 Data Sheet
22
Microsemi Corporation
8.0 Mechanical Drawing
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ZL40218
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