Supertex inc.
Supertex inc.
www.supertex.com
TN2640
Doc.# DSFP-TN2640
C071913
Features
Low threshold (2.0V max.)
High input impedance
Low input capacitance
Fast switching speeds
Low on-resistance
Free from secondary breakdown
Low input and output leakage
Applications
Logic level interfaces - ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
General Description
This low threshold enhancement-mode (normally-off)
transistor utilizes a vertical DMOS structure and Supertex’s
well-proven silicon-gate manufacturing process. This
combination produces a device with the power handling
capabilities of bipolar transistors and with the high input
impedance and positive temperature coefcient inherent
in MOS devices. Characteristic of all MOS structures, this
device is free from thermal runaway and thermally induced
secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
N-Channel Enhancement-Mode
Vertical DMOS FETs
Absolute Maximum Ratings
Parameter Value
Drain-to-source voltage BVDSS
Drain-to-gate voltage BVDGS
Gate-to-source voltage ±20V
Operating and storage temperature -55°C to +150°C
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
Pin Conguration
TO-252 (D-PAK)
TO-92
8-Lead SOIC
GATE
SOURCE
DRAIN
GATE
SOURCE
N/C
N/C
DRAIN
DRAIN
DRAIN
DRAIN
GATE
SOURCE
DRAIN
Ordering Information
Part Number Package Option Packing
TN2640K4-G TO-252 (D-PAK) 2000/Reel
TN2640LG-G 8-Lead SOIC 2500/Reel
TN2640N3-G 3-Lead TO-92 1000/Bag
TN2640N3-G P002
3-Lead TO-92 2000/Reel
TN2640N3-G P003
TN2640N3-G P005
TN2640N3-G P013
TN2640N3-G P015
For packaged products, -G indicates package is RoHS compliant (‘Green’).
TO-92 taping specications and winding styles per EIA-468 Standard.
Devices in Wafer / Die form are RoHS compliant (‘Green’).
Refer to Die Specication VF57 for layout and dimensions.
Product Summary
BVDSS/BVDGS
RDS(ON)
(max)
ID(ON)
(min)
VGS(th)
(max)
400V 5.0Ω2.0A 2.0V
Typical Thermal Resistance
Package θja
TO-252 (D-PAK) 81OC/W
8-Lead SOIC 101OC/W
TO-92 132OC/W
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TN2640
Supertex inc.
www.supertex.com
Doc.# DSFP-TN2640
C071913
Thermal Characteristics
Package ID
(continuous)
ID
(pulsed)
Power Dissipation
@TA = 25OCIDR
IDRM
TO-252 (D-PAK) 500mA 3.0A 2.5W500mA 3.0A
8-Lead SOIC 260mA 2.0A 1.3W260mA 2.0A
TO-92 220mA 2.0A 0.74W 220mA 2.0A
Notes:
† ID (continuous) is limited by max rated Tj.
‡ Mounted on FR4 board, 25mm x 25mm x 1.57mm
Electrical Characteristics (TA = 25°C unless otherwise specied)
Sym Parameter Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage 400 - - V VGS = 0V, ID = 1.0mA
VGS(th) Gate threshold voltage 0.8 - 2.0 V VGS = VDS, ID = 2.0mA
ΔVGS(th) Change in VGS(th) with temperature - -2.5 -4.0 mV/OC VGS = VDS, ID = 2.0mA
IGSS Gate body leakage - 100 nA VGS = ±20V, VDS = 0V
IDSS Zero gate voltage drain current
- - 10 µA VGS = 0V, VDS = Max rating
- - 1.0 mA VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
ID(ON) On-state drain current 1.5 3.5 - AVGS = 5.0V, VDS = 25V
2.0 4.0 - VGS = 10V, VDS = 25V
RDS(ON)
Static drain-to-source
on-state resistance
- 3.2 5.0 ΩVGS = 4.5V, ID = 500mA
- 3.0 5.0 VGS = 10V, ID = 500mA
ΔRDS(ON) Change in RDS(ON) with temperature - - 0.75 %/OC VGS = 10V, ID = 500mA
GFS Forward transconductance 200 330 - mmho VDS = 25V, ID = 100mA
CISS Input capacitance - 210 225
pF
VGS = 0V,
VDS = 25V,
f = 1.0MHz
COSS Common source output capacitance - 30 50
CRSS Reverse transfer capacitance - 8.0 15
8-Lead SOIC
Product Marking
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
SiTN
2640
YYWW
TO-252 (D-PAK)
TO-92
YY = Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
Si YYWW
TN2640
LLLLLLL
YY = Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
YYWW
N2640
LLLL
Package may or may not include the following marks: Si or
Package may or may not include the following marks: Si or
Package may or may not include the following marks: Si or
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TN2640
Supertex inc.
www.supertex.com
Doc.# DSFP-TN2640
C071913
90%
10%
90% 90%
10%
10%
Pulse
Generator
VDD
RL
OUTPUT
D.U.T.
t(ON)
td(ON)
t(OFF)
td(OFF)
tr
INPUT
INPUT
OUTPUT
10V
VDD
RGEN
0V
0V
tf
N- Channel Switching Waveforms and Test Circuit
Sym Parameter Min Typ Max Units Conditions
td(ON) Turn-on delay time - 4.0 15
ns
VDD = 25V,
ID = 2.0A,
RGEN = 25Ω
trRise time - 15 20
td(OFF) Turn-off delay time - 20 25
tfFall time - 22 27
VSD Diode forward voltage drop - - 0.9 V VGS = 0V, ISD = 200mA
trr Reverse recovery time - 300 - ns VGS = 0V, ISD = 1.0A
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Electrical Characteristics (TA = 25°C unless otherwise specied)
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TN2640
Supertex inc.
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Doc.# DSFP-TN2640
C071913
Typical Performance Curves
On-Resistance vs. Drain Current
BVDSS Variation with Temperature
253pF
BVDSS (normalized)
1.15
1.10
1.05
1.00
0.95
0.90
-50 0 50 100 150
Tj (OC)
RDS(ON) (ohms)
10
8
6
4
2
0
ID (amperes)
0 1.0 2.0 3.0 4.0 5.0
3.0
2.4
1.8
1.2
0.6
0
ID (amperes)
1.4
1.2
1.0
0.8
0.6
0.4
10
8
6
4
2
0
VGS(th) (normalized)
VGS (volts)
C (picofarads)
400
300
200
100
0
VGS = 5.0V
VGS = 10V
0 2 4 6 8 10
VGS (volts)
-50 0 50 100 150
Tj (OC)
VDS = -25V
TA = -55OC
25OC
125OC
2.2
1.8
1.4
-1.0
0.6
0.2
RDS(ON) (normalized)
RDS(ON) @ 10V, 0.5A
V(th) @ 2.0mA
V(th) and RDS Variation with Temperature
Transfer Characteristics
VDS (volts)
0 10 20 30 40 0 1 2 3 4 5
QG (nanocoulombs)
f = 1MHz
CISS
COSS
CRSS
VDS = 10V
VDS = 40V
653pF
Capacitance vs. Drain-to-Source Voltage Gate Drive Dynamic Characteristics
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TN2640
Supertex inc.
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Doc.# DSFP-TN2640
C071913
Typical Performance Curves (cont.)
Output CharacteristicsSaturation Characteristics
Maximum Rated Safe Operating Area Thermal Response Characteristics
Transconductance vs. Drain Current Power Dissipation vs. Temperature
SO-8
TO-92
TA = -55OC
4V
8V
VGS = 10V
TO-92 (pulsed)
TO-92 (DC)
SO-8 (DC)
2V
4V
3V
6V
8V
2V
3V
6V
SO-8 (pulsed)
DPAK
DPAK (DC)
VGS = 10V
VDS = 25V
25OC
125OC
T
C
= 25
O
C
ID (amperes)
0 10 20 30 40 50
5.0
4.0
3.0
2.0
1.0
0
VDS (volts)
2.5
2.0
1.5
1.0
0.5
0 0 2 4 6 8 10
ID (amperes)
VDS (volts)
0 1.0 2.0 3.0 4.0 5.0
ID (amperes)
GFS (siemens)
2.0
1.6
1.2
0.8
0.4
0
3.0
2.4
1.8
1.2
0.6
0
PD (watts)
0 25 50 75 100 125 150
TC (OC)
ID (amperes)
0 1.0 100 1000
VDS (volts)
10
1.0
0.1
0.01
0.001
0.001 0.01 0.1 1.0 10
1.0
0.8
0.6
0.4
0.2
0
TO-92
PD = 1W
TC = 25OC
tP (seconds)
Thermal Resistance (normalized)
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TN2640
Supertex inc.
www.supertex.com
Doc.# DSFP-TN2640
C071913
3-Lead TO-252 D-PAK Package Outline (K4)
Note:
1. Although 4 terminal locations are shown, only 3 are functional. Lead number 2 was removed.
1 2 3
4
L4 L5
b
b2
e
D1
E1
L1
L
Seating
Plane
A1
Gauge
Plane
θ
D
E
View B
Front View Side View
Rear View
View B
θ1
H
c2
A
L3
L2
b3
Note 1
Symbol A A1 b b2 b3 c2 D D1 E E1 e H L L1 L2 L3 L4 L5 θθ1
Dimen-
sion
(inches)
MIN .086 .000* .025 .030 .195 .018 .235 .205 .250 .170
.090
BSC
.370 .055
.108
REF
.020
BSC
.035 .025* .045 0O0O
NOM - - - - - - .240 - - - - .060 - - - - -
MAX .094 .005 .035 .045 .215 .035 .245 .217* .265 .182* .410 .070 .050 .040 .060 10O15O
JEDEC Registration TO-252, Variation AA, Issue E, June 2004.
* This dimension is not specied in the JEDEC drawing.
Drawings not to scale.
Supertex Doc. #: DSPD-3TO252K4, Version E041309.
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TN2640
Supertex inc.
www.supertex.com
Doc.# DSFP-TN2640
C071913
8-Lead SOIC (Narrow Body) Package Outline (LG)
4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch
1
8
Seating
Plane
Gauge
Plane
L
L1
L2
EE1
D
eb
AA2
A1
Seating
Plane
A
A
Top View
Side View
View B View B
θ1
θ
Note 1
(Index Area
D/2 x E1/2)
View A-A
h
h
Note 1
Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1
Dimension
(mm)
MIN 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80*
1.27
BSC
0.25 0.40
1.04
REF
0.25
BSC
0O5O
NOM - - - - 4.90 6.00 3.90 - - - -
MAX 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00* 0.50 1.27 8O15O
JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.
* This dimension is not specied in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-8SOLGTG, Version I041309.
Note:
1. This chamfer feature is optional. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier;
an embedded metal marker; or a printed indicator.
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
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TN2640
(The package drawing(s) in this data sheet may not reect the most current specications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-TN2640
C071913
3-Lead TO-92 Package Outline (N3)
Symbol A b c D E E1 e e1 L
Dimensions
(inches)
MIN .170 .014.014.175 .125 .080 .095 .045 .500
NOM - - - - - - - - -
MAX .210 .022.022.205 .165 .105 .105 .055 .610*
JEDEC Registration TO-92.
* This dimension is not specied in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc.#: DSPD-3TO92N3, Version E041009.
Seating
Plane
1
2
3
Front View Side View
Bottom View
E1 E
D
e1
L
e
c
1 2 3
b
A