0 High-Speed CMOS QS54/74FCT841T 4 Bus Interface QS54/74FCT2841T QUALITY "Bi SEMICONDUCTOR, INC. 10-Bit Latch FEATURES/BENEFITS DESCRIPTION Pin and function compatible to the Am29841 74FCT841 and 74FCT841T Industrial temperature -40C to 85C * CMOS power levels: <7.5mW static * Available in DIP, SOIC, QSOP, ZIP Undershoot Clamp diodes on all inputs TTL-compatible input and output levels Ground bounce controlled outputs * Reduced output swing of 0-3.5V * Military product compliant to MIL-STD-883, Class B FCT-T 841T JEDEC-FCT spec compatible * A,B, and C speed grades with 5.5ns tpp for C * Io. = 48mA Ind., 32mA Mil. FCT-T 2841T * Built-in 25Q series resistor outputs reduce reflection and other system noise * A,B, and C speed grades with 5.5ns tpp for C * Io, = 12mA Ind. The QSFCT841T is a 10-bit high-speed CMOS TTL- compatible buffered latch with three-state outputs that are ideal for driving high capacitance loads such as memory and address buses. The device comes in A, B, and C speed grades with 5.5ns (Max.) tp, 4/tp, 4 for the C grade. The 2841 devices is a 25Q resistor output version useful for driving transmission lines and reducing system noise. The 2841 eliminates the need for external series resistor in high speed sys- tems and can replace the 841 series to reduce noise in an existing design. Allinputs have clamp diodes for undershoot noise suppression. All outputs have ground bounce suppression (see QSI Application Note AN-001 ), and outputs will not load an active bus when Voc is removed from the device. Figure 1. Functional Block Diagram bi j D Q Yi 250, LE (FCT2841 Only) OE MDSL-00029-05 QUALITY SEMICONDUCTOR, INC. 1 DECEMBER 28, 1998QS54/74FCT841T, 2841T Figure 2. Pin Configurations (All Pins Top View) PDIP, SOIC, QSOP ZIP OED: ~ 240 Voc CEqt 5b do Do 2 231] Yo D1d3 4b 2 bi 3 207] V4 D3q5 gh pa b2 14 211] Y2 DS q7 8p D6 b3 115 20f Y3 D749 sob pe b4 6 191] Y4 Do qi 12D GND ps 7 181] YS G'S sab ya pe O18 171 Ye Y8q 15 seh y7 b7 09 16[] Y7 Yoq 17 18D Y5 bs Lf 10 151] Y8 Y4q19 sob v3 bo O11 1410 Yo Yo 921 sob v1 GND [12 PLE YO 23 ob Voc Figure 2. Logic Symbol 10 10 Di44 D Q Yi LE LE | OE Table 1. Pin Description Name VO | Description Di | Data Inputs Yi | Data Outputs - Three State LE | Latch Enable OE | | Output Enable Table 2. Function Tables Inputs Internal Outputs OE LE Di Qi Yi Function H X X X Z Hi-Z L X x H H Output Enabled L X x L L Output Enabled x H H H Xx Transparent x H L L Xx Transparent x L x NC x Latched QUALITY SEMICONDUCTOR, INC. MDSL-00029-05 DECEMBER 28, 1998QS54/74FCT84T, 2841T Table 3. Absolute Maximum Ratings Supply Voltage to Ground DC Output Voltage Voy DC Input Voltage Vix, AC Input Voltage (for a pulse width < 20ns) DC Input Diode Current with Vy < 0 DC Output Diode Current with Voy7 < 0 DC Output Current Max. Sink Current/Pin Maximum Power Dissipation Tstg Storage Temperature 0.5V to 7.0V 0.5V to 7.0V 0.5V to 7.0V beeueeeueceuueeeaueueueeuaeuueeeeaeeuaeeeeneavanees 0.5 watts 65 to 150C Table 4. Capacitance Ta = 25C, f = 1MHz, Vin = OV, Vout = OV Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to QSI devices that result in func- tional or reliability type failures. Pins SOIC QSOP PDIP ZIP Unit 1-11, 13, 14, 23 4 4 5 7 pF 15-22 6 6 7 9 pF Notes: 1. Capacitance is characterized but not tested. 2. Pin reference for 24-pin package Table 5. Power Supply Characteristics Symbol | Parameter Test Conditions Min | Max | Unit loc Quiescent Power Voc = Max., freq = 0 1.5 | mA Alec Supply Current per Veco = Max., Vin = 3.4V, freq = 0 2.0 | mA Input @ TTL HIGH Qeep Supply Current per Veco = Max., Outputs open and enabled _ 0.25 | mA/ Input per MHz One bit toggling @ 50% duty cycle MHz Other inputs at GND or Voc8) Notes: 1. For conditions shown as Min. or Max., use the appropriate values specified under DC specifications. 2. Per TTL driven input (V\ = 3.4V). 3. For flip-flops, Qap is measured by switching one of the data input pins so that the output changes every clock cycle. This is ameasurementof device power consumption only and does notinclude power to drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested. 4. |, can be computed using the above parameters as explained in the Technical Overview section. MDSL-00029-05 DECEMBER 28, 1998 QUALITY SEMICONDUCTOR, INC.QS54/74FCT841T, 2841T Table 6. DC Electrical Characteristics Over Operating Range Industrial T, = 40C to 85C, Vog = 5.0V +5% Military T, =55C to 125C, Vog = 5.0V +10% Symbol | Parameter Test Conditions Min | Typ| Max | Unit Vin Input HIGH Voltage Logic HIGH for All Inputs 2.0 Vv Vie Input LOW Voltage Logic LOW for All Inputs 0.8 Vv AV Input Hysteresis Vain Vr for All Inputs 0.2 Vv | tin | Input Current Voc = Max., O< Vin < Veo 5 HA Ite | Input HIGH or LOW | loz | Off-State Output Voc = Max., 0 < Vin < Voc 5 HA Current (Hi-Z) los Short Circuit Current Voc = Max., Voyr = GND@?) 60 mA (FCT841) lor Current Drive Voc = Min., VoyT = 2.0V 50 mA (FCT2841 25Q) Vic Input Clamp Voltage Voc = Min., In = 18MA, Ty = 25C) -0.7 | -1.2 Vv Vou Output HIGH Voltage Veco =Min. Io4 =-12mA (MIL) 2.4 Vv lon = 15mA (IND) 2.4 _ _ Vor Output LOW Voltage Voc = Min. Io, = 32mA (MIL) 0.50 Vv (FCT841) lo. = 48mA (IND) 0.50 Vo. Output LOW Voltage Voc =Min. Ig, = 12mA (MIL) 0.50 Vv (FCT2841 25Q) lo, = 12mA (IND) 0.50 Rout Output Resistance Veco =Min. Io, = 12mA (MIL) _ 25 a (FCT2841 25Q) lo, = 12mA (IND) 20 28 40 Notes: 1. Typical values indicate V., = 5.0V and T, = 25C. 2. Not more than one output should be shorted and the duration is <1 second. 3. These parameters are guaranteed by design but not tested. QUALITY SEMICONDUCTOR, INC. MDSL-00029-05 DECEMBER 28, 1998QS54/74FCT84T, 2841T Table 7. Switching Characteristics Over Operating Range Industrial T, = 40C to 85C, Veg = 5.0V +5% Croap = DOPF, Rioap = 5000 unless otherwise noted. Military T, = 55C to 125C, Vog = 5.0V 10% 841A 841B 841C 2841A 2841B 2841C Symbol | Description Min Max Min Max Min Max | Unit tp Data to Y Delay IND 9.0 6.5 5.5 ns tp_y | OE =LOW, 841 MIL | 10 7.5 6.3 toy Data to Y Delay3) IND 13 13 13 ns tp_y | OE =LOW, 841 MIL | 15 15 15 tp Data to Y Delay IND 9.5 6.5 5.5 ns tpy | OE =LOW, 2841 MIL | 11 7.5 6.3 teHL Data to Y Delay@) IND 20 13 13 ns tp_y | OE =LOW, 2841 MIL | 20 15 15 ts Data to LE Setup IND 2.5 2.5 2.5 ns MIL | 2.5 2.5 2.5 ty Data to LE Hold Time IND | 2.5 2.5 2.5 ns MIL | 3.0 2.5 2.5 tley LE to Y Delay IND 12 8.0 6.4 | ns OE = LOW, 841 MIL 13 | 105 | 6.8 tley LE to Y Delay23) IND 16 | 155 | 15 ns OE = LOW, 841 MIL 20 18 16 tley LE to Y Delay IND 12 8 8 ns OE = LOW, 2841 MIL 13 | 105 | | 10.5 tley LE to Y Delay2) IND 16 | 155 | 15 ns OE = LOW, 2841 MIL 20 18 16 Notes: 1. See Test Circuit and Waveforms. 2. This parameter is guaranteed by design but not tested. 3. Croan = 300pF. MDSL-00029-05 QUALITY SEMICONDUCTOR, INC. 5 DECEMBER 28, 1998QS54/74FCT841T, 2841T Table 8. Switching Characteristics Over Operating Range Industrial T, = 40C to 85C, Veg = 5.0V +5% Croap = DOPF, Rioap = 5000 unless otherwise noted. Military T, = 55C to 125C, Vog = 5.0V 10% 841A 841B 841C 2841A 2841B 2841C Symbol | Description Min Max Min Max Min Max | Unit tlen LE Pulse Width HIGH) IND 6 _ 4 _ 4 _ ns MIL 6 4 4 _ tpzy Output Enable Time IND 11.5 8 6.5 ns toz, OE to Yi, 841 MIL _ 13 _ 8.5 _ 8.5 tezy Output Enable Time@*) IND 23 14 12 ns tpz, | OEto Yi, 841 MIL 25 15 13 tpzy Output Enable Time IND 11.5 8 6.5 ns toz. OE to Yi, 2841 MIL _ 13 _ 8.5 _ 8.5 tezy Output Enable Time@*) IND 23 14 12 ns tpz, | OEto Yi, 2841 MIL | 25 15 13 tpyz Output Disable Time?) IND 7 6 5.7 ns tp_z | OEto Yi MIL | 6.5 tpyz Output Disable Time IND 8 7 6 ns tp_z | OE to Yi MIL | 10 7.5 6.3 Notes: 1. See Test Circuit and Waveforms. 2. This parameter is guaranteed by design but not tested. 3. Cioap = 300pF. 4. Cigap = SPF. QUALITY SEMICONDUCTOR, INC. MDSL-00029-05 DECEMBER 28, 1998