I2C Bus Interface - Hitachi Semiconductor

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Hitachi Single-Chip Microcomputer

I2C Bus Interface

Application Note

ADE-502-054A

Rev. 2.0

11/27/01

Hitachi, Ltd.

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s

patent, copyright, trademark, or other intellectual property rights for information contained in

this document. Hitachi bears no responsibility for problems that may arise with third party’s

rights, including intellectual property rights, in connection with use of the information

contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you

have received the latest product standards or specifications before final design, purchase or

use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.

However, contact Hitachi’s sales office before using the product in an application that

demand s esp ecially high qua lity and reliability or where its failure or malfunction may directly

threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear

power, combustion control, transportation, traffic, safety equipment or medical equipment for

life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi

particularly for maximum rating, operating supply voltage range, heat radiation characteristics,

installation conditions and other characteristics. Hitachi bears no responsibility for failure or

damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,

consider normally foreseeable failure rates or failure modes in semiconductor devices and

employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi

product does not cause bodily injury, fire or other consequential damage due to operation of

the Hitachi pro duc t.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document

without written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi

semiconductor pro duct s .

Rev. 2.0, 11/01, page i of vi

Contents

Section 1 Overview of the I2C Bus.................................................................. 1

1.1 Overview of the I2C Bus.................................................................................................... 1

1.1.1 Features of the I2C Bus......................................................................................... 1

1.1.2 Differences with the Serial Communications Interface (SCI).............................. 1

1.1.3 Connection Type of the I 2C bus Interface ............................................................ 2

1.2 Method of Data Transfer over an I2C Bus......................................................................... 3

1.2.1 Basic Concepts and Elements of Data Transfer over an I2C Bus ......................... 3

1.2.2 Procedure for Data Transfer (Example: master transmission, slave reception).... 6

1.3 The Single-Master and Multi-Master Configurations ....................................................... 8

1.3.1 Single-Master....................................................................................................... 8

1.3.2 Multi-Master ........................................................................................................ 8

1.4 Procedure for Adjusting Communications........................................................................ 9

Section 2 Explanation of the Interface Functions of the I2C Bus.................... 11

2.1 Lineup of Products that Incorporate the I2C Bus Interface................................................ 11

2.2 Specifications of the I2C Bus Interfaces Incorporated in H8/300 Series and

H8/300L Series Products [H8 Series]................................................................................ 13

2.2.1 Specifications of the I2C Bus Interfaces Incorporated in H8/300 Series

and H8/300L Series Products............................................................................... 13

2.2.2 Configuration of the I2C Bus Interfaces Incorporated in H8 /300 Series

and H8/300L Series Products............................................................................... 14

2.2.3 Data Transfer Format of the I2C Bus Interfaces Incorporated in H8/300 Series

and H8/300L Series Products............................................................................... 15

2.2.4 Explanation of Functions of the Registers of the I2C Bus Interfaces

Incorporated in H8/300 Series and H8/300L Series Products.............................. 17

2.3 Specifications of the I2C Bus Interfaces Incorporated in H8S Series Products ................. 19

2.3.1 Features of the I2C Bus Interfaces In corporated in H8S Series Products............. 19

2.3.2 Internal Block Configuration of the H8S Series I2C Bus Interface ...................... 21

2.3.3 Data Format for the H8S Series I2C Bus .............................................................. 22

2.3.4 Description of Functions of the H8S Series I2C Bus Interface Incorporated

Registers............................................................................................................... 24

2.3.5 Relationship between Flags of On-chip I2C Bus Interface and Transfer State in

H8S Series (H8S/2138 Series) ............................................................................. 42

2.4 Description of I2C Bus Interface Usage............................................................................. 43

2.5 Synchronization of the I2C Bus Communication............................................................... 54

2.6 Description of Data Transfer in H8/300 and H8/300L Series [H8 Series]........................ 56

2.6.1 Master transmission.............................................................................................. 56

2.6.2 Master Reception.................................................................................................. 58

2.6.3 Slave Reception.................................................................................................... 60

Rev. 2.0, 11/01, page ii of vi

2.6.4 Slave Transmission .............................................................................................. 63

2.7 Description of Data Transfer in H8S Series (H8/2138 Series) [H8S Series]..................... 65

2.7.1 Master Transmission............................................................................................ 65

2.7.2 Master Reception.................................................................................................. 70

2.7.3 Slave Reception.................................................................................................... 75

2.7.4 Slave Transmission .............................................................................................. 78

Section 3 Examples of Application to the H8/300 and H8/300L Series......... 83

3.1 System Specifications........................................................................................................83

3.2 Circuit for Multi-Master Evaluation System..................................................................... 87

3.3 Design of Software............................................................................................................ 88

3.3.1 Description of Modules........................................................................................ 88

3.3.2 Master................................................................................................................... 88

3.3.3 Slave..................................................................................................................... 90

3.4 Flowcharts......................................................................................................................... 92

3.4.1 Master Program.................................................................................................... 92

3.4.2 Slave Program...................................................................................................... 95

3.5 Program Listings............................................................................................................ ... 98

3.5.1 Master Program.................................................................................................... 98

3.5.2 Slave Program...................................................................................................... 105

Section 4 Example Applications for the H8S Series.........................................113

4.1 Usage Guide to the Example Applications for the H8S Series.......................................... 113

4.1.1 The Structure of the Example Applications for the H8S Series........................... 113

4.1.2 Description of the Definition File for th e Vector Table....................................... 114

4.1.3 Description of the Definition File for th e Registers ............................................. 118

4.1.4 Description of the Inclusion of Assembler Files in C Language Programs.......... 148

4.1.5 Description of the Linkage of Files...................................................................... 149

4.2 Single-Master Transmission.............................................................................................. 150

4.2.1 Specification......................................................................................................... 150

4.2.2 Description of the Operation................................................................................ 152

4.2.3 Description of the Software.................................................................................. 153

4.2.4 Flowchart.............................................................................................................. 157

4.2.5 Program List......................................................................................................... 162

4.3 Single-Master Reception................................................................................................... 167

4.3.1 Specifications....................................................................................................... 167

4.3.2 Operation Descriptions ......................................................................................... 169

4.3.3 Software Descriptions.......................................................................................... 172

4.3.4 Flowchart.............................................................................................................. 175

4.3.5 Program List......................................................................................................... 183

4.4 One-Byte Data Transmission by Single-Master Transmission.......................................... 189

4.4.1 Specifications....................................................................................................... 189

4.4.2 Operation Descriptions ......................................................................................... 191

Rev. 2.0, 11/01, page iii of vi

4.4.3 Software Descriptions.......................................................................................... 192

4.4.4 Flowchart.............................................................................................................. 195

4.4.5 Program List......................................................................................................... 200

4.5 One-Byte Data Reception by Single-Master Reception.................................................... 204

4.5.1 Specifications....................................................................................................... 204

4.5.2 Operation Description.......................................................................................... 205

4.5.3 Software Description............................................................................................ 207

4.5.4 Flowchart.............................................................................................................. 210

4.5.5 Program List......................................................................................................... 217

4.6 Single-Master Transmission by DTC................................................................................ 222

4.6.1 Specifications....................................................................................................... 222

4.6.2 Operation Description.......................................................................................... 229

4.6.3 Software Description............................................................................................ 229

4.6.4 Flowchart.............................................................................................................. 235

4.6.5 Program List......................................................................................................... 240

4.7 Single-Master Reception by DTC..................................................................................... 245

4.7.1 Specifications....................................................................................................... 245

4.7.2 Description of Operation...................................................................................... 252

4.7.3 Description of Software ....................................................................................... 253

4.7.4 Flowchart.............................................................................................................. 258

4.7.5 Program List......................................................................................................... 266

4.8 Slave Transmission........................................................................................................... 272

4.8.1 Specifications....................................................................................................... 272

4.8.2 Description of Operation...................................................................................... 273

4.8.3 Description of Software ....................................................................................... 275

4.8.4 Flowcharts............................................................................................................ 279

4.8.5 Program List......................................................................................................... 282

4.9 Slave Reception................................................................................................................. 286

4.9.1 Specifications....................................................................................................... 286

4.9.2 Description of Operation...................................................................................... 288

4.9.3 Description of Software ....................................................................................... 289

4.9.4 Flowcharts............................................................................................................ 293

4.9.5 Program List......................................................................................................... 297

4.10 Example of Processing Bus Disconnection....................................................................... 301

4.10.1 Specification......................................................................................................... 301

4.10.2 Description of Operation...................................................................................... 303

4.10.3 Description of Software ....................................................................................... 304

4.10.4 Flowcharts............................................................................................................ 308

4.10.5 Program List......................................................................................................... 317

4.11 Bus Conflict....................................................................................................................... 324

4.11.1 Specifications....................................................................................................... 324

4.11.2 Operation Description.......................................................................................... 330

4.11.3 Description of Software ....................................................................................... 331

Rev. 2.0, 11/01, page iv of vi

4.11.4 Flowchart.............................................................................................................. 335

4.11.5 Master-1 program List.......................................................................................... 344

4.11.6 Master-2 program List.......................................................................................... 351

Rev. 2.0, 11/01, page v of vi

Introduction

In recent times, the peripheral interfaces fo r all fields of application have been being unified and

standardized b ecause of th e need for lower costs and greater utility. The I2C bus* interface covered

by this application note is one such standardized interface. It is for use as an interface with the

control ICs of home appliances, and in controlling the battery packs of notebook-sized PCs, PC

monitors, etc.

The I2C bus is the standardized form of a bi-directional serial bus system which was developed by

Philips in the Netherlands. In products based on this standard, two wires (a clock line and data

line) are used to carry mutual data communications among multiple peripheral ICs.

The I2C bus interfaces incorporated in Hitachi’s 8- b it/16-bit H8/300-series, H8/300L-series, and

H8S-series single-chip microcomputers are an implementation of a sub-set of the standard

functions and conform to the I2C bus interface method proposed by Philips, Ltd. (that is, note that

some specifications of the I2C bus interface are not completely implemented depending on the

condition us ed).

In sections 1 and 2 of this application note, an outline of the I2C bus is given and the specifications

and functions of our I2C bus-interface module are described. Examples of systems in multi-master

configurations are introduced in section 3 and examples of the application of the I2C bus interface

with H8S-series products are given in section 4.

The operation of the examples of hardware and software described in this application note has

been confirmed. However, when they are actually used, be sure to base this usage on a

confirmation of their operation.

Note: * I2C Bus: Inter-IC Bus

Rev. 2.0, 11/01, page vi of vi

Rev. 2.0, 11/01, page 1 of 358

Section 1 Overview of the I2C Bus

1.1 Overview of the I2C Bus

1.1.1 Features of the I2C Bus

Features of the I2C bus are shown below.

• An I2C bus is made up of two bus lines; a serial data line (SDA) and a serial clock line (SCL).

It is easy to extend an I2C bus so that it serves more devices.

• In the I2C bus, the master-slave relationships among devices is always set up and each device

has a particular address. Specifying the particular address of the object of the communication

forms a path along which data communications is enabled.

• Any device is able to act as a m aster (i.e., construction of a multi-master system is possible). A

system to avoid competition for bus rights and thus pr even t the loss of data has th us been

defined for the I2C bus interface.

• The maximum data transfer rates are 100 kbps in normal mode and 400 kbps in high-speed

mode (up to 3.4 Mbps is defined in version 2.0 of the I2C bus specification).

• The limit on the attachment of devices to an I2C bus system is defined as 400 pF, which is the

upper limit of the bus-load capacity of the system.

• Examples of the standard's application are the SMBus*1 and Access.bus*2.

Notes: *1 SMBus is a form of serial bus devised by Duracell and Intel.

*2 ACCESS.bus is a form of serial bus devised by Digital Equipment.

1.1.2 Differences with the Serial Communications Interface (SCI)

Hitachi's serial interface is referred to as the serial communications interface (SCI). The

differences between this interface and the standard I2C interface are listed in the table below.

As listed in table 1.1, an SCI is connected to two data lines, one fo r transmission and one for

reception. Data communications is generally on a one-to-one basis.

On the other hand, communications on an I2C bus are bi-directional over a single data line by the

equipment to a master. An object is selected for a communication by specifying that object's

particular address. This allows the transmission and reception of data between any pair among

multiple connected devices. The mechanism for avoiding conflicts over bus access that has been

defined for the I2C bus means that the bus supports the operation of multi-master systems, in

which any device is able to act as the master. The maximum transfer rates are 100 kbps in normal

mode and 400 kbps in high-speed mode.

Rev. 2.0, 11/01, page 2 of 358

Table 1.1 Differences from SCI

SCI I2C bus

Clock synchronous Asynchronous

Used pins Three-line method Two-line method Two-line method

Transmiss ion data outp ut T ransmission data output Transmi ss ion/r eception

data (input/output)

Reception dat a input Reception data input

Serial clock Serial cloc k (when an

external clock is used) Serial clock

Transfer rate 100 bps to 4 Mbps 110 bps to 38.4 kpbs 100 kbps (normal mode)

400 kbps (high-speed

mode)*

Transmission/rec

eption with

multiple ICs

Impossible Impossible Possible;

slave devices have

individual addresses

Note: *Hs mode (maximum transfer speed: 3.4 Mbps) which is defined in the I2C Bus

Specifications Ver. 2.0 is not supported.

1.1.3 Connection Ty pe of the I2C bus Interfac e

Figure 1.1 shows the form of a connection between I2C bus interfaces. As shown in the drawing,

the I2C bus is made up of clock line SCL and data line SDA, and they are connected to the power

source of the bus, VBB, via pull-up resistors. The SCL and SDA pins of devices 1 and 2 have

wired-AND connections with the SCL and SDA lines, respectively.

In the figure, device 2 has been monitoring the state of the SCL line and thus confirms that another

device is using the bus when device 1 drives the SCL line low. Furthermore, even while device 1

is using the bus and thus driving the SCL line, device 2 is able to drive SCL low and place the

device 1 in its wait state, in term s of communications ope ration s (fo r details, see the I2C bus

specification).

Rev. 2.0, 11/01, page 3 of 358

Pull-up resistors

Clock input 1 Data input 1 Data input 2Clock input 2

VBB

SDA

SCL

Device 2Device 1

drives the bus low

Monitors the state of SCL

device 1 has driven SCL

low, so device 2 waits.

Figure 1.1 Form of a Connection between I2C Bus Interfaces

(when device 1 initia tes the connection by driving SCL low)

1.2 Method of Data Transfer over an I2C Bus

1.2.1 Basic Concepts and Elements of Data Transfer over an I2C Bus

To start with, the basic concepts and elements of data transfer over an I2C bus are given below.

(1) Master device

The master device generates the clock signals that synchronize data communications and sets the

start and stop conditions that indicate the beginning and end of each data communication.

(2) Slave device

The slave device is a device other than a master device which is on the I2C bus.

(3) Transmission device

The transmission device is a device which is transmitting data. It may be a master device or a

slave device.

(4) Reception device

Rev. 2.0, 11/01, page 4 of 358

The reception device is a device which is receiving data. It may be a master device or a slave

device.

(5) Start condition

The start condition is set by changing the level on the SDA line fro m hig h to low while the SCL

line is high. This is shown in figure 1.2. A data communicatio n is initiated by this operation. The

start condition is set by the master device.

Start condition

SCL

SDA

Figure 1.2 Start Condition

(6) Stop condition

The stop condition is set by changing the level on th e SDA line from low to high while the SCL

line is high. This is shown in figure 1.3. A data communication is stopped by this operation. The

stop condition is set by the master device.

SCL

SDA

Stop condition

Figure 1.3 Stop Condition

(7) Output timing of the data

Figure 1.4 shows the timing of data output. The data on the SDA line is updated while the SCL

line is low and the data on the SDA line is settled for placement on the SDA line while the SCL

line is high. The signal on the SDA line only changes while the SCL line is high, that is, only from

the setting of the start condition to the setting of the stop condition.

Rev. 2.0, 11/01, page 5 of 358

SCL

SDA

Setting of data for placement

Updating of data

Figure 1.4 Timing of Data Output

(8) Ma ster transmissio n

Master transmission is the activity when a master device is a transmission device. This is the

activity when a slave address is transmitted after the start condition has been issued or a command

is transmitted to the slave device, etc.

(9) Master reception

Master reception is the activity when a master device is a reception device.

(10) Slave transmission

Slave transmission is the activity when a slave device is a transmission device.

(11) Slave reception

Slave reception is the activity when a slave device is a reception device. A master device transmits

a slave address after the start co nditio n is in place to initiate slave-reception activity in the selected

slave device.

(12) Bus-released state

This is the state in which no I2C bus devices are in communication. While this state applies, both

the SCL and SDA lines stay at the logic-high level.

(13) Bus-occupied state

This is the state in which somethin g is communicated ov er the I2C bus device. The system returns

to the bus-released state after the transmission master device has set a stop condition.

(14) Format for data transfer

Figure 1.5 shows the format for the transfer of data over the I2C bus. The start and stop condition

signals and the SCL clock are generated by the master device. The first data after the start

Rev. 2.0, 11/01, page 6 of 358

condition carry the slave address. The eighth bit indicates the direction of communication. A zero

value for this bit ind icates th at the subsequent data is transmitted from a master device while a one

indicates that the communication after the second byte is for reception by a master device. The

slave address is defined by 7 bits*1, and is set between B'0000000 and H'1111111 by the user.

However, address B'0000000 (referred to as the general call address) and certain other addresses

are reserved.

Data is transferred in 1-byte (8-bit) units. The ninth bit is an acknowledge bit from the reception

device. For example, when a slave addr ess is transmitted from the master dev ice, th e

corresponding slave device drives SDA low on the ninth clock cycle to return an

acknowledgement to the master.

There is no limit on the number of bytes of data that can be transferred between the setting of a

start condition and of the corresponding stop cond ition. A communication is completed when the

stop con dition is set.

Notes: *1 The I2C bus specification describes 10-bit addresses. Hitachi's I2C bus interface module

does not support this 10-bit address specification.

*2 The general call address, B'0000000, is used to specify all slave addresses that are

connected to the bus.

S : Start bit (start condition)

R/ : Data-direction bit

ACK : Acknowledge bit

P : Stop bit (stop condition)

Legend:

First byte Second byte

11 8 1 11

R/ ACK ACK ACK P

Data

Slave address

Figure 1.5 Format for Data Transfer

1.2.2 Procedure for Data Transfer (Example: master transmission, slave reception)

Figure 1.6 shows an example when the master device transmits 1 byte of data to the slave device.

In the first place, the master device sets the start conditio n by ch angin g the level on the SDA line

from high to low while the SCL line is high. Next, the master outputs a clock signal on the SCL

line and outputs, on the SDA line, the address of th e slave that will be the target of this

communication. The address of the slave is defined by 7 bits. A bit to indicate the direction of the

communication is added as an eighth bit.

Rev. 2.0, 11/01, page 7 of 358

The master device releases the SDA line in the ninth clock cycle so that it is able to receive an

acknowledgement of selection from the slave device. The selected slave device drives the SDA

line low during this clock cy cle to return the acknowledg ement.

The master device receives the acknowledgement from the slave at the specified address and keeps

the SCL line low until the first byte of data is ready for transmission. When the first byte is ready,

the master device outputs the data on the SDA line while outputting a clock signal on the SCL

line. In the same way as for the slave address, the selected slave device returns an

acknowledgement to the master device in the ninth clock cycle. This signal acknowledges that the

slave device has received the data without problems.

The master device keeps the SCL line low while receiving this acknowledgement from the slave

device. To set the stop condition, the level on the SDA line is then changed from lo w to high while

the SCL line is high.

During the transmission of data, the slave device may become unable to receive the data because it

is busy with some other processing. In this case, the slave device keeps the SCL line at its low

level so that th e m a ster device stays in its wait state. Th e tim ing with which the slave device is

able to driv e SCL low is at th e same time as the master d evice is driving SCL lo w.

Start condition

123

··· ···

789 123 789

During this period, the SDA line is kept high by the

master while it waits for the arrival of the ACK bit.

Legend:

ACK : Acknowledgement bit

R/ : Bit to indicate the direction of transmission/reception

“0”

SCL

SDA ACK ACKSlave address

Master

Slave

Direction of data

transfer

Transmission data

Stop condition

Master

Slave

Master

Slave

Master

Slave

Figure 1.6 Format for Data Transfer (Master Transmission, Slave Reception)

Rev. 2.0, 11/01, page 8 of 358

1.3 The Single-Master and Multi-Master Configurations

1.3.1 Single-Master

The master device sets start and stop conditions to control data communications. It also outputs

the synch r onizing clock sign a l on the SCL line and slave addresses so that data can be transmitted

and received. The system configuration shown in figure 1.7, in which a set device is always the

master, is a single-master configuration.

Slave

Master

Slave

2Slave

C bus SCL

SDA

Figure 1.7 A Single-Master Configuration

1.3.2 Multi-Master

A configuration in which two or more devices are included as masters in one system is called a

multi-master configuration .

The master device is only able to start the transfer of data after the bus has been released.

However, in th e multi-master configuration, multiple master devices may simultan eou sly attempt

to start to transfer data. There is then a conflict over bus rights. The specifications of the I2C bus

thus include a procedure for adjusting communications when there is a conflict over bus rights.

For details, see 1.4, Procedure for Adjusting Communications.

Rev. 2.0, 11/01, page 9 of 358

Slave

1Slave

2Slave

C bus SCL

SDA

Master 1

(slave 5) Slave 4

(master 2)

Figure 1.8 A Multi-Master Configuration

1.4 Procedure for Adjusting Communications

The specification of the I2C bus interface includes a procedure for adjusting communications to

prevent conflicts over bus rights. This supports systems in multi-task configurations.

Master devices monito r the bus line to confirm that the bus has been released b e fore they set the

start condition. When the bus is released , multiple master devices ma y attempt to set the start

condition. A single valid master device is thus defined by the procedure shown in figure 1.9.

In the I2C bus, the data is settled for placement on the SDA lin e while the SCL line is at its high

level. Therefore, each device monitors for the rising edge of the SCL line after the start condition

has been set and compares the state of the SDA line with the bit of data that each device is

attempting to send (this initial data will be the slave address). If device 1 is driving SDA high

while device 2 is dr iv ing SDA low, the actual SDA line will be low because o f the wired-AND

connection, so device 1 confirms that this differs from the bit which is attemp ting to output.

Device 1 then switches the data output stage off. In this example, device 2 continues its operation

as a master device (see figure 1.9). When all masters are trying to specify the address of the same

slave device, the operation will proceed to the next step and the first bit of data will be compared,

and so on.

For example, when the data to be transferred transfer data are H'01 and H'02 as shown in

figure1.10, the datum H'01 is low over a longer period, and its transmission thus continues to be

enabled. In the same way, the general call address (H'00) has the highest priority.

Rev. 2.0, 11/01, page 10 of 358

SCL1

SDA1

SCL2

SDA2

SCL

SDA

The bus signals output

by each master The output stage is switched off

because the desired output differs

from the state of the bus line.

Start condition

Gets the bus right

The SCL output is suspended.

Master 1Master 2Bus line

Figure 1.9 Procedure for Adjusting Communications

(Detection of the Loss of Bus Arbitration)

SCL

H' 01

0001

27···

···

SDA

SCL 1

0010

27···

···

SDA

H' 02

Figure 1.10 A Specific Exa mple of the Adjustment of Communicatio ns

Rev. 2.0, 11/01, page 11 of 358

Section 2 Explanation of the Interface Functions of the

I2C Bus

2.1 Lineup of Products that Incorporate the I2C Bus Interface

Our I2C bus interface modules may be roughly classified into two groups.

(1) H8 family: The models wh ich feature the first I2C bus interface module to have been

manufactured by Hitachi.

(2) H8S family: An enhanced version of the H8 family.

Table 2.1 lists Hitachi's products that incorporate the I2C bus interface and the types of the I2C bus

interface modules.

Table 2.1 Products that Incorporate the I2C Bus Interface

Series Product

name Number

of pins ChannelMASK*1F-ZTATTM ZTAT®I2C

module

H8/3217 2ch —

H8/3216 2ch ——

H8/3214 2ch —

H8/3212 2ch ——

H8/3217

series

H8/3202

64, 80

1ch ——

H8/3337Y 1ch —

H8/3337YF 1ch — —

H8/3337SF 1ch — —

H8/3336Y 1ch ——

H8/3334Y 1ch —

H8/3337

series

H8/3334YF

80, 84

1ch — —

H8/3437 1ch —

H8/3437YF 1ch — —

H8/3437SF 1ch — —

H8/3436 1ch ——

H8/3434 1ch —

H8/300

series

H8/3437

series

H8/3434F

100

1ch — —

H8 series

Rev. 2.0, 11/01, page 12 of 358

Table 2.1 Products that Incorporate the I2C Bus Interface (continued)

Series Product

name Number

of pins ChannelMASK*1F-ZTATTM ZTAT®I2C

module

H8/3567 2ch —

H8/3564 2ch ——

H8/3561 2ch ——

H8/3567U 2ch —

H8/3567

series

H8/3564U

42, 44

2ch ——

H8/3577 2ch —

H8/300

series

H8/3577

series H8/3574

2ch —

H8S

series

H8/3947 2ch —

H8/3946 2ch ——

H8/300L

series H8/3947

series

H8/3945

100

2ch ——

H8 series

H8/300H

Tiny series *2

H8/3664

series H8/3664 42, 64 1ch —H8S

series

H8S/2127 2ch ——

H8S/2126 2ch ——

H8S/2128F

64, 80

2ch — —

H8S/2138 2ch ——

H8S/2137 2ch ——

H8S/2138F

2ch — —

H8S/2148 2ch ——

H8S/2147 2ch ——

H8S/2148F 2ch — —

H8S/2147NF 2ch — —

H8S/2149YV

100

2ch — —

H8S/2169YV

F144 2ch — —

H8S/2194 1ch ——

H8S/2193 1ch ——

H8S/2192 1ch ——

H8S/2191 1ch ——

H8S series H8S/2100

series

H8S/2194F

112

1ch — —

H8S

series

Rev. 2.0, 11/01, page 13 of 358

Table 2.1 Products that Incorporate the I2C Bus Interface (continued)

Series Product

name Number

of pins ChannelMASK*1F-ZTATTM ZTAT®I2C

module

H8S/2199 2ch ——

H8S/2198 2ch ——

H8S/2197 2ch ——

H8S/2196 2ch ——

H8S/2199F 2ch — —

H8S/2238 2ch *2*2—

H8S/2236 2ch *2——

H8S/2258 2ch *2*2—

H8S/2200

series

H8S/2256

100

2ch *2——

H8S/2633 120,128 2ch — —

H8S series

H8S/2600

series H8S/2643*2144 2ch — —

H8S

series

Notes: *1 MASK versions are available.

*2 For details on the specification/usage of the I2C bus interface which is included in the

H8/300H Tiny series, see the additional volume.

2.2 Specifications of the I2C Bus Interfaces Incorporated in H8/300 Series

and H8/300L Series Products [H8 Series]

2.2.1 Specifications of the I2C Bus Interfaces Incorporated in H8/300 Series and H8/300L

Series Products

The main specifications of the I2C bus interfaces incorporated in Hitachi's H8/300 series and

H8/300L series 8-bit microcomputers are shown below. For the groups of products that

incorporate this module, see table 2.1.

• Units for data transfer

number of bits on each transfer:1 to 8 bits

number of frames to be transferred: unlimited

• Automatic setting of start/stop co nditions

• Automatic loading of acknowledge bits

• Wait function

• Internal clock signals can be selected from among eight types.

• Acknowledgement and serial modes are available.

• Selectable order of ou tput for the data to b e transmitted (selection of MSB/LSB first)

Rev. 2.0, 11/01, page 14 of 358

• The on-chip filter (noise canceller) keeps the data reliable.

2.2.2 Configuration of the I2C Bus Interfaces Incorporated in H8/300 Series and

H8/300L Series Products

Figure 2.1 is an internal block diagram of the I2C bus interface. It consists of a prescaler (PS),

clock controller, data control circuit, bus-state decision circuit, bus-arbitration decision circuit,

address comparator, interrupt controller, and a group of registers that store the bus information and

data.

Noise

canceller

Noise

canceller

Legend:

ICCR

ICMR

ICSR

ICDR

SAR

øP

SCL

SDA

ICCR : I

C control register

ICMR : I

C mode register

ICSR : I

C status register

ICDR : I

C data register

SAR : Slave address register

PS : Prescaler

Clock

controller

Bus-state

decision circuit

Arbitration

decision circuit

Output data

control circuit

Address

comparator

Interrupt

generator Interrupt request

Internal data bus

Figure 2.1 Block Diagram of I2C Bus Interface

Rev. 2.0, 11/01, page 15 of 358

Table 2.2 is a list of the registers.

Table 2.2 Internal Registers of the I2C Bus Interface

Name Abbrev. Function

I2C bus control register ICCR Register for setting transfer mode

I2C bus status register ICSR The various state flags are set here

I2C bus data register ICDR Stores data for transmission/reception

I2C bus mode register ICMR Register to set the transfer format

Slave address register SAR Register to set the slave address

2.2.3 Data Transfer Format of the I2C Bus Interfaces Incorporated in H8/300 Series and

H8/300L Series Products

The I2C bus interface handles the following three formats for the transfer of data. There is no limit

on the number of frames transferred.

(1) Addressing format

1711 1 11

Number of transmission bits:

n = 1 to 8

Number of transmission frames:

m = 1 or more

SLA A A PDATAR/ A/

(2) Addressing format (with resending of the start condition signal)

Number of transmission bits: n1 and n2 = 1 to 8

Number of transmission frames: m1 and m2 = 1 or more

A/ A/S

1711 11 11 1n2 17n1

1m1 1m2

SLA A SDATA R/R/ SLA A PDATA

The addressing format with resending of the start condition is used in cases where the direction of the

transfer must be changed during the transfer (structuring of the data transfer). After the resending start

condition is sent, the slave address is made the same as that when the first start condition was set.

Rev. 2.0, 11/01, page 16 of 358

(3) Non-addressing format

181 111Number of transmission bits:

n = 1 to 8

Number of transmission frames:

m = 1 or more

Legend:

S : Start condition

SLA : Slave address

R/ : Indicates the direction of transmission/reception

A : Acknowledge (the reception device drives SDA low)

DATA : Transmission/reception data

P : Stop condition

The slave address and R/W bit are not recognized in this format.

DATA A A PDATA A/

Rev. 2.0, 11/01, page 17 of 358

2.2.4 Explanation of Functions of the Registers of the I2C Bus Interfaces Incorporated in

H8/300 Series and H8/300L Series Products

Table 2.3 lists the function of each bit of the registers of this I2C bus interface.

Table 2.3 Functions of the Incorporated Registers of the I2C Bus Interface

name Bit

name Function Master Slave Site and Properties of

this Setting

WSCR*1CKDBL Selects whether or not the

frequency of the input clock to the

peripheral module is divided by

two.

IICE Enables access to the registers of

the I2C bus interfac e.

STCR*1

IICX Selects the transfer clock's

frequency according to the

settings of CSK2 to 0 in ICCR.

FS Selects whether or not

the slave address of this

interface is recognized

SAR

SLV6 to

When

ICE = 0

Hold the slave address.

Only enabled when FS

=0.

A: Set in the initial setting

routine. The values are

retained. Confirm the

completion of processing

by the I2C bus interface

when changing the

settings in this register.

MLS Selects MSB or LSB

first.

WAIT Selects whether a wait is

inserted between the

data and

acknowledgement by the

transmissi on equi pm ent.

ICMR

BC2 to 0

When

ICE = 1

Specify the transfer bit.

Set immediately before

transfers other than 8

bits.

B: Set while the SCL clock

has stopped (when the

bus is released, and the

transmission/reception of

data is complete). The

values are retained.

Rev. 2.0, 11/01, page 18 of 358

name Bit

name Function Master Slave Site and Properties of

this Setting

ICE*21 is set after SAR is set. The I2C

bus interface enters the transfer-

enabled stat e.

IEIC Disables/enables the interrupt.

MST

TRS

Sets master/slave and

transmission/reception. The

communications mode

(transmission/reception) of the

sl ave is automatically set

according to the TRS bit setting in

the master's interface.

ACK Specifies whether the

acknowle dge bit is or is not

inserted after 8-bit serial data has

been transmitted.

ICCR

CKS2

to 0 Specify the transfer rate.

BBSY

SCP

BBSY monitors the bus state.

Sets the start/stop condition.

⋅The start condit ion is set by

setting BBSY = 1 and SCP = 0.

⋅The stop condition is set by

setting BBSY = 0 and SCP = 0.

IRIC Set to 1 when this interface is an

interrupt sour ce.

AL Set to 1 when losing in bus

arbitration.

AAS Set to 1 when the slave address

transmitted by the master

matches the value in SAR.

ADZ Set to 0 when the general call

address (H'00) is recognized.

C: Flags that are

automatically set during

the process of data

communication. Clear

them in order according to

the communications

protocol (BBSY and SCP

are also used to set the

start/stop conditions).

ICSR

ACKB Sets/recognizes the acknowledge

bit. As described under B

above.

ICDR ICDR7

to 0 Data register for

transmission/reception. Accessed in the

transmissi on and

receptio n of data.

Rev. 2.0, 11/01, page 19 of 358

Notes: *1 Only applies to H8/3337 series, H8/3437 series, and H8/3217 series products.

*2 The ICE bit is used to control the switching of the I/O port between operation as an I2C

bus module and as a general-purpose I/O port. When the ICE bit is switched, a clock

signal or start/stop condition may be generated as a pseudo-state according to the state

of the setting of the general-purpose I/O port. As a result, there is the possibility that a

defect will be caused in some other device. When this bit is manipulated, the

corresponding port is recommended to be set in the input state or to output a high level.

2.3 Specifications of the I2C Bus Interfaces Incorporated in H8S Series

Products

2.3.1 Features of the I2C Bus Interfaces Incorporated in H8S Series Products

The main features of the I2C bus interface incorpor ated in H8S series produ c ts are illustrated with

Hitachi's 16-bit single chip H8S/2138 series microprocessor as an example.

• Selection of format as addressing or non-addressing

 I2C bus format: addressing format with acknowledge bit, for master/slave operation.

 Serial format: non-addressing format without acknowledgement bit, for master operation

only

• The I2C bus format conforms to the specification of th e Philips I2C bus interface.

• There are two ways of setting the slave address in the I2C bus format.

• Start and stop conditions are generated automatically in master mode in the I2C bus format.

• Selection of acknowledge output levels when receiving in the I2C bus format.

• Automatic loading of acknowledge bit when transmitting in the I2C bus format

• Wait function in master mode in th e I2C bus format

 A wait can be inserted by driving the SCL pin low after transfers of data other than

acknowledgement bits. The wait request is cleared when the next transfer becomes

possible.

• Wait function in slave mode in th e I2C bus format

 A wait request can be generated by driving the SCL after the transfers of data other than

acknowledgement bits. The wait request is cleared when the next transfer becomes

possible.

• Five interrupt sources

 Detection of start condition (in master mode)

 End of data transfer : at the rising edge of the ninth clock of the SCL, including

transmission m ode transition s with I2C bus format and address reception after loss of the

master arbitration.

Rev. 2.0, 11/01, page 20 of 358

 Address match: when any slave address matches the address of this unit or the general call

address is received while the unit is in the I2C bus fo rmat's slave reception mode.

 Detection of stop condition (in slave mode)

 When the internal flag TDRE or RDRF is set to 1 (when data is transferred from ICDRT to

ICDRS or from ICDRS to ICDRR)

• Selection from among 16 internal clocks while in master mode

• Direct bus drive (SCL/SDA pins)

 Two pins, P52/SCL0 and P97/SDA0, normally function as NMOS push-pull outputs and

function as NMOS open-drain outputs when the bus-drive function is selected.

 Two pins, P86/SCL1 and P42/SDA1, normally function as CMOS pins and only function

as NMOS outputs when the bus-drive function is selected.

• An on-chip-filter (noise canceller) is provid ed to m a in tain the reliability of data.

• The control function is supported in the standard DDC (display data channel) for PC monitors.

 Automatic switching fro m format-less to I2C bus format is possible (only on channel 0).

 Format-less operation (i.e., without start/stop condition, non-addressing) in slave mode

 Operation in the pin configuration of common data pin (SDA) and independent clock pins

(VSYNCI and SCL).

 Automatic switching fro m format-less mod e to I2C bus mode on the falling edge of SCL.

Rev. 2.0, 11/01, page 21 of 358

2.3.2 Interna l Block Configuration of the H8 S Series I2C Bus Int erface

Figure 2.2 shows the internal block diagram of the I2C bus interface for H8S/2138 series products.

Noise

canceller

Noise

canceller

Legend:

PS ICCR

ICMR

ICSR

ICDRT

ICDRS

ICDRR

SAR, SARX

SCL

SDA

ICCR : I

C control register

ICMR : I

C mode register

ICSR : I

C status register

ICDR : I

C data register

SAR : Slave address register

SARX : Slave address register X

PS : Prescaler

Clock

control

Clock for format-less transfer only

(only on channel 0)

Bus-state

decision circuit

Arbitration

decision circuit

Output data

control circuit

Address

comparator

Interrupt

generator Interrupt

request

Internal data bus

Figure 2.2 Block Diagram of the H8S/2138 Series I2C Bus Interface

Rev. 2.0, 11/01, page 22 of 358

The registers are described in table 2.4.

Table 2.4 The Registers of the H8S/2138 Series I2C Bus Interfac e

Name Abbrev. Function

I2C bus control register ICCR Register for setting transfer mode

I2C bus status register ICSR Each state flag is set.

I2C bus data register ICDR Stores received data and data for transmission

I2C bus mode register ICMR Register to set the transfer format

Slave address register SAR Register to set the slave address

Slave address register SARX Register to set the second slave addres s

2.3.3 Data Format for the H8S Series I2C Bus

Figures 2.3 shows the format for the I2C bus of H8S series products. The I2C bus format is made

up of the start condition, the slave address field (7-bit addressing) that specifies the slave device's

address, the R/W-bit field that indicates the direction of communications, the acknowledge-bit

field, data field, and stop condition (for a description of the symbols, see table 2.5).

This I2C bus interface module allows the use of format-less and serial formats, as well as the I2C

bus format itself (this is so for IIC channel 0 in H8S/2138 series products; for other products,

confirm th e details o n this point in the respective hardware manuals). The additional modes are

shown in figure 2.3, (c) and (d).

Rev. 2.0, 11/01, page 23 of 358

1111 11n7 1m

(a) I

C bus format (FS = 0 or FSX = 0)

(b) I

C bus format, when the start condition is resent (FS = 0 or FSX = 0)

Number of transmission bits: n = 1 to 8

Number of transmission frames:

m = 1 or more

SLA AAP

DATAR

S SLA ADATAR/ S SLA AP

DATAR/

A/ A/

1 7 1 1 n1 1 1 7 1 1 n2 1 1

1m1 1m2

Upper: Number of transmission bits:

n1 and n2 = 1 to 8

Lower: Number of transmission frames:

m1 and m2 = 1 or more

Figure 2.3 The I2C Bus Data Format

(d) Serial format (FS = 1 and FSX = 1)

Number of transmission bits: n = 1 to 8

Format-less transfer applies to the standard DDC (display-data channel)

of the PC-monitor system.

The serial format is a clock-synchronous format with neither slave address

nor acknowledge-bit field.

Number of transmission frames: m = 1 or more

Number of transmission bits: n = 1 to 8

Number of transmission frames:

m = 1 or more

DATA DATAA

DATA DATASP

n1 1

Figure 2.3 Other Data Formats

Table 2.5 lists the description of symbols in the I2C bus data format and I2C bus timing.

Rev. 2.0, 11/01, page 24 of 358

Table 2.5 Symbols

Symbol Function

S Start condition. The master device drives SDA from high to low while SCL is high.

SLA Slave address, by which the master device selects a slave device.

R/:Indicates the direction of transmission/reception: from the slave device to the master

device when the R/: bit is 1, or from the master device to the slave device when the

R/: bit is 0.

A Acknowledge. The reception device (the slave in master-transmit mode or the

master in master-receive mode) drives SDA to its low level to acknowledge a

transfer.

DATA The data being transferred. The number of bits of data to be transmitted and

received is set by bits BC2 to BC0 in ICMR. Either the MSB-first or LSB-first format

is selected by the MLS bit in ICMR.

P Stop condition. The master device drives SDA from low to high level while SCL is

high.

Figure 2.4 shows the timing of the I2C bus.

Start condition (S): Operation in which SDA is changed from high to low while SCL is

high.

Stop condition (P): Operation in which SDA is chang ed from low to high while SCL is

in its high state

Data (SLA/R/:/DATA): Settled for placement on SDA while SCL is hig h .

For the ac characteristics of the bus, see the hardware manuals for the individual products.

SDA

SCL 1-7 8 9 8 91-7 8 91-7

SA ADATA DATA PSLA A/

Figure 2.4 I2C Bus Timing

2.3.4 Description of Functions of the H8S Series I2C Bus Interface Incorporated

Registers

Table 2.6 lists the functions of the H8S series I2C bus interface incorporated registers of H8S

series (H8S/2138 series).

Rev. 2.0, 11/01, page 25 of 358

Table 2.6 Description of functions of built-in registers

name Bit

name Functions R/W Initial

value

ICDR ICDR7

to 0 ICDR is an 8-bit readable/writable register that is used as a

transmit data register when transmission and reception data

(ICDRT). ICDRS cannot be read or written to by the CPU,

ICDRR is read-only, and ICDRT is write-only. Data transfer

among the three registers is performed automatically in

coordination with changes in the bus state, and affect the status

of internal flags such as TDRE and RDRF.

If IIC is in transmit mode and the next data is in ICDRT (the

TDRE flag is 0) following transmission/reception of one frame of

data using ICDRS, data is transferred automatically from ICDRT

to ICDRS. If IIC is in receive mode and no previous data remains

in ICDRR (the RDRF flag is 0) following reception of one frame

of data using ICDRS, data is transferred automatically from

ICDRS to ICDRR.

ICDR is assigned to the same address as SARX, and can be

written and read only when the ICE bit is set to 1 in ICCR.

R/W —

— TDRE TDRE is a one bit internal flag that cannot be read/written.

• TDRE = 0 indicates that transmission cannot be started or

the next transmit data is in ICDR (ICDRT).

[Clear conditi ons ]

(1) When transmit data is written in ICDR (ICDRT) in

transmit mode (TRS = 1)

(2) When a stop condition establishment is detected in the

bus line state after a stop condition is set with the I2C

bus format or serial format selected

(3) When a stop condition is detected wi th the I2C bus

format selected

(4) In receive mode (TRS = 0)

(A0 write to TRS during transfer is valid after reception

of a frame containing an acknowledge bit.)

• TDRE = 1 indicates that the next transmit data can be written

in ICDR (ICDRT).

[Set conditions]

(1) In transmit mode (TRS = 1), when a start condition is

detected in the bus line state after a start condition is

set in master mode with the I2C bus format or serial

format selected

—0

Rev. 2.0, 11/01, page 26 of 358

name Bit

name Functions R/W Initial

value

(2) When using formatless mode in transmit mode (TRS =

(3) When data is transferred from ICDRT to ICDRS (Data

transfer from ICDRT to ICDRS when TRS = 1 and

TDRE = 0, and ICDRS is empty)

(4) When a switch is made from receive mode (TRS = 0) to

transmit mode (TRS = 1) after detection of a start

condition

— RDRF RDRF is a one bit internal flag that cannot be read/written.

• RDRF = 0 indicates that the data in ICDR (ICDRR) is invalid.

• RDRF = 1 indicates that the receive data in ICDR (ICDRR)

can be read.

[Clearing cond iti ons ]

When ICDR (ICDRR) receive data is read in receive mode

[Setting conditions]

When data is transferred from ICDRS to ICDRR (Data

transfer from ICDRS to ICDRR in case of normal

transmission termination with TRS = 0 and RDRF = 0)

—0

SAR SAR is an 8-bit readable/writable register that selects the format

and stores the slave address. When the chip is in slave mode

(and the addres sing mode is selected), if the upper 7 bits of SAR

match the upper 7 bits of the first frame received after a start

condition, the chip operates as the slave device specified by the

master device. SAR is assigned to the same address as ICMR,

and can be written and read only when the ICE bit is cleared to 0

in ICCR.

R/W H'00

SVA6

to 0 A unique address is set in bits SVA6 to SVA0, differing from the

addresses of other slave devices connected to the I2C bus. R/W 0

Rev. 2.0, 11/01, page 27 of 358

name Bit

name Functions R/W Initial

value

FS Used together with the FSX bit in SARX and the SW bi t in

DDCSWR to select the transfer format.

• SW = 0, FS = 0, FSX = 0

I2C bus format (SAR and SARX slave address are

recognizes)

• SW = 0, FS = 0, FSX = 1

I2C bus format (SAR slave address is recognized and SARX

slave address is ignored)

• SW = 0, FS = 1, FSX = 0

I2C bus format (SAR slave address is ignored and SARX

slave address is recognized)

• SW = 0, FS = 1, FSX = 1

Clock synchronous serial format (SAR and SARX slave

addresses ignor ed)

• SW = 1, FS = 0, FSX = 0

• SW = 1, FS = 0, FSX = 1

• SW = 1, FS = 1, FSX = 0

Formatless (start condition/stop condition is not detected,

with acknowledge bit)

• SW = 1, FS = 1, FSX = 1

Formatless (start condition/stop condition is not detected,

without acknowledge bit)

R/W 0

SARX SARX is an 8-bit readable/writable register that selects the

format and stores the second sl ave address. When the chip is in

slave mode (and the addressing format is selected), if the upper

7 bits of the first frame received after a start condition and the

upper 7 bits of SARX match, the chip operates as the slave

device specified by the master device. SARX is assigned to the

same address as ICDR, and can be written and read only when

the ICE bit is cleared to 0 in ICCR.

R/W H'01

SVAX6

to 0 A unique address differing from the addresses of other slave

devices connected to the I2C bus is set in bits SVAX6 to SVAX0. R/W 0

FSX The FSX bit selects whether or not SARX slave address is

recognized in slave mode. For details, see the description of the

FS bit in SAR.

R/W 1

Rev. 2.0, 11/01, page 28 of 358

name Bit

name Functions R/W Initial

value

ICMR ICMR is an 8-bit readable/writable register that selects whether

the MSB or LSB is transferred first, performs master mode wait

control, and sel ect s the mast er mode tran sfer clo ck frequen cy,

and the transfer bit count. ICMR is assigned to the same

address as SAR. ICMR can be written and read only when the

ICE bit is set to 1 in ICCR.

R/W H'00

MLS MLS selects whether data is transferred MSB-first or LSB-first (if

the number of bits in a frame, excluding the acknowledge bit, is

less than 8, transmit data and receive data are stored differently.

Transmit data should be written justified toward the MSB side

when MLS = 0, and toward the LSB side when MLS = 1.

Receive data bits read from the LSB side should be treated as

valid when MLS = 0, and bits read from the MSB side when MLS

= 1). MLS should not be set to 1 when they are used in the I2C

bus format.

• MLS = 0

MSB-first

• MLS = 1

LSB-first

R/W 0

WAIT WAIT selects whether to insert a wait between the transfer of

data and the ac knowledge bit, in master mode with the I2C bus

format. When WAIT is set to 1, after the fall of the clock for the

final data bit, the IRIC flag is set to 1 in ICCR, and a wait state

begins (with SCL at the low level). When the IRIC flag is cleared

to 0 in ICCR, the wait ends and the acknowledge bit is

transferred. If WAIT is cleared to 0, data and acknowledge bits

are transf erred consecutiv ely with no wait inserted.

The IRIC flag in ICCR is set to 1 on compl etion of the

acknowledge bit transfer, regardless of the WAIT setting.

• WAIT = 0

Data and acknowledge bits transferred consecutively

• WAIT = 1

Wait inserted between data and acknowledge bits

R/W 0

Rev. 2.0, 11/01, page 29 of 358

name Bit

name Functions R/W Initial

value

CKS2

CKS0

Bits CKS2 to CKS0, together with the IICX1 (channel 1) or IICX0

(channel 0) bit in the STCR register, select the transfer clock

frequency in master mode. They should be set according to the

required transfer rate.

• IICX = 0, CKS2 = 0, CKS1 = 0, CKS0 = 0

The transfer clock is set to φ/28.

• IICX = 0, CKS2 = 0, CKS1 = 0, CKS0 = 1

The transfer clock is set to φ/40.

• IICX = 0, CKS2 = 0, CKS1 = 1, CKS0 = 0

The transfer clock is set to φ/48.

• IICX = 0, CKS2 = 0, CKS1 = 1, CKS0 = 1

The transfer clock is set to φ/64.

• IICX = 0, CKS2 = 1, CKS1 = 1, CKS0 = 0

The transfer clock is set to φ/80.

• IICX = 0, CKS2 = 1, CKS1 = 0, CKS0 = 1

The transfer clock is set to φ/100.

• IICX = 0, CKS2 = 1, CKS1 = 1, CKS0 = 0

The transfer clock is set to φ/112.

• IICX = 0, CKS2 = 1, CKS1 = 1, CKS0 = 1

The transfer clock is set to φ/128.

• IICX = 1, CKS2 = 0, CKS1 = 0, CKS0 = 0

The transfer clock is set to φ/56.

• IICX = 1, CKS2 = 0, CKS1 = 0, CKS0 = 1

The transfer clock is set to φ/80.

• IICX = 1, CKS2 = 0, CKS1 = 1, CKS0 = 0

The transfer clock is set to φ/96.

• IICX = 1, CKS2 = 0, CKS1 = 1, CKS0 = 1

The transfer clock is set to φ/128.

• IICX = 1, CKS2 = 1, CKS1 = 0, CKS0 = 0

The transfer clock is set to φ/160.

• IICX = 1, CKS2 = 1, CKS1 = 0, CKS0 = 1

The transfer clock is set to φ/200.

• IICX = 1, CKS2 = 1, CKS1 = 1, CKS0 = 0

The transfer clock is set to φ/224.

• IICX = 1, CKS2 = 1, CKS1 = 1, CKS0 = 1

The transfer clock is set to φ/256.

R/W 0

Rev. 2.0, 11/01, page 30 of 358

name Bit

name Functions R/W Initial

value

BC2

BC0

Bits BC2 to BC0 specify the number of bits to be transferred next

time. With the I2C bus format (when the FS bi t in SAR or the FSX

bit in SARX is 0), the data is transferred with one additional

acknowledge bit. Bit BC2 to BC0 settings should be made during

an interval between transfer frames. If bits BC2 to BC0 are set to

a value other than 000, the setting should be made while the

SCL line is low.

Bits BC2 to BC0 are initialized to 000 by a reset and when a

start condition is detected. The value returns to 000 at the end of

a data transfer, including the acknowledge bit.

• BC2 = 0, BC1 = 0, BC0 = 0

Clock synchronous serial = 8 bits/frame

I2C bus = 9 bits/frame

• BC2 = 0, BC1 = 0, BC0 = 1

Clock synchronous serial = 1 bit/frame

I2C bus = 2 bits/frame

• BC2 = 0, BC1 = 1, BC0 = 0

Clock synchronous serial = 2 bits/frame

I2C bus = 3 bits/frame

• BC2 = 0, BC1 = 1, BC0 = 1

Clock synchronous serial = 3 bits/frame

I2C bus = 4 bits/frame

• BC2 = 1, BC1 = 0, BC0 = 0

Clock synchronous serial = 4 bits/frame

I2C bus = 5 bits/frame

• BC2 = 1, BC1 = 0, BC0 = 1

Clock synchronous serial = 5 bits/frame

I2C bus = 6 bits/frame

• BC2 = 1, BC1 = 1, BC0 = 0

Clock synchronous serial = 6 bits/frame

I2C bus = 7 bits/frame

• BC2 = 1, BC1 = 1, BC0 = 1

Clock synchronous serial = 7 bits/frame

I2C bus = 8 bits/frame

R/W 0

Rev. 2.0, 11/01, page 31 of 358

name Bit

name Functions R/W Initial

value

AAS In I2C bus format slave receive mode, AAS is set to 1 if the first

frame following a start condition ma tches bits SVA6 to SVA0 in

SAR, or if the general call address (H'00) is detected.

AAS is cleared by reading AAS after it has been set to 1, then

writing 0 in AAS. In addition, AAS is reset automatically by write

access to ICDR in transmit mode, or read access to ICDR in

receive mode.

• AAS = 0

Slave addres s or general ca ll addre ss is not reco gnized.

[Clear conditi ons ]

(1) When ICDR data is written (transmit mode) or read

(receive mode)

(2) When 0 is written in AAS after reading AAS = 1

(3) In master mode

• AAS = 1

Slave address or general call address is recognized.

[Setting condition]

When the slave address or general call address is detected

in slave receive mode and FS = 0

R/(W)*10

ADZ In I2C bus format slave receive mode, ADZ is set to 1 if the first

frame following a start condition is the general call address

(H'00).

ADZ is cleared by reading ADZ after it has been set to 1, then

writing 0 in ADZ. In addition, ADZ is reset automatically by write

access to ICDR in transmit mode, or read access to ICDR in

receive mode.

• ADZ = 0

General call address is not reco gni zed .

[Clearing cond iti ons ]

(1) When ICDR data is written (transmit mode) or read

(receive mode)

(2) When 0 is written in ADZ after reading ADZ =1

(3) In master mode

• ADZ = 1

General call address is reco gni ze d.

[Setting condition]

When the general call address is detected in slave receive

mode and (FS = 0 or FSX = 0)

R/(W)*10

Rev. 2.0, 11/01, page 32 of 358

name Bit

name Functions R/W Initial

value

ACKB ACKB stores acknowledge data. In transmit mode, after the

reception device receives data, it returns acknowledge data, and

this data is loaded into ACKB. In receive mode, after data has

been received, the acknowledge data set in this bit is sent to the

transmission device.

When this bit is read, in transmission (when TRS = 1), the value

loaded from the bus line (returns by the reception device) is

read. In reception (when TRS = 0), the value set is read.

• ACKB = 0

• In receive mode, 0 is output at acknowledge output timing

• In transmit mode, indicates that the reception device has

acknowledged the data (signal is 0).

• ACKB = 1

• In receive mode, 1 is output at acknowledge output

timing.

• In transmit mode, indicates that the reception device has

not acknowledge the data (signal is 1).

R/W 0

ICCR ICCR is an 8-bit readable/writable register that enables or

disables the I2C bus interface operation, enables or disables

interrupts, selects master or sl ave mode and transmission or

reception, enables or disables acknowledgement, confirms the

I2C bus interface bus status, sets start/stop conditions, and

performs interrupt flag confirmation.

R/W H'01

ICE ICE selects whether or not the I2C bus interface is t o be used .

When ICE is set to 1, port pins function as SCL and SDA

input/output pins and transfer operations are enabled in the I2C

bus interface module. When ICE is cleared to 0, the I2C bus

interface module is halted and its internal states are cleared.

The SAR and SARX registers can be accessed when ICE is 0.

The ICMR and ICDR registers can be accessed when ICE is 1.

• ICE = 0

I2C bus interface module is disabled (SCL and SDA signal

pins set to port function).

I2C bus interface module internal states are initialized.

SAR and SARX can be accessed.

• ICE = 1

I2C bus interface module is enabled for transfer operation

(pins SCL and SCA are driving the bus).

ICMR and ICDR can be accessed.

R/W 0

Rev. 2.0, 11/01, page 33 of 358

name Bit

name Functions R/W Initial

value

IEIC IEIC enables or disables interrupts from the I2C bus interface to

the CPU.

• IEIC = 0

I2C bus interface interrupts are disabled.

• IEIC = 1

I2C bus interface interrupts are enabled.

R/W 0

MST MST selects whether the I2C bus interface operates in master

mode or slave mode.

• MST = 0

Slave mode

[Clearing cond iti ons ]

(1) When 0 is written by software

(2) When bus arbitrati on is lost after transm is sio n is starte d

in I2C bus format master mode

• MST = 1

Master mode

[Setting conditions]

(1) When 1 is written by software (in cases other than

clearing condition 2)

(2) When 1 is written in MST after reading MST = 0

R/W 0

TRS TRS selects whether the I2C bus interface operates in transmit

mode or receive mode.

• TRS = 0

Reception mode

[Clearing cond iti ons ]

(1) When 0 is written by software (in cases other than

setting condition 3)

(2) When 0 is written in TRS after reading TRS = 1 (in case

of setting condition 3)

(3) When bus arbitration is lost after transmis sio n is starte d

in I2C bus format master mode

(4) When the SW bit in DDCSWR changes from 1 to 0

• TRS = 1

Transmit mode

[Setting conditions]

(1) When 1 is written by software (in cases other than

clearing conditions 3 and 4)

R/W 0

Rev. 2.0, 11/01, page 34 of 358

name Bit

name Functions R/W Initial

value

(2) When 1 is written in TRS after reading TRS = 0 (in case

of clearing conditions 3 and 4)

(3) When 1 is received as the R/: bit of the first frame in

I2C bus format slave mode

ACKE ACKE specifies whether the value of the acknowledge bit

returned from the reception device when using the I2C bus

format is to be ignored and continuous transfer is performed, or

transfer is to be aborted and error handling will be performed if

the acknowledge bit is 1. When the ACKE bit is 0, the value of

the received acknowledge bit is not indicated by the ACKB bit,

which is alwa ys 0.

• ACKE = 0

The value of the acknowledge bit is ignored, and continuous

transfer is performed.

• ACKE = 1

If the acknowledge bit is 1, continuous transfer is aborted.

R/W 0

BBSY The BBSY flag can be read to check whether the I2C bus (SCL,

SDA) is busy or free. In master mode, this bit is also used to set

start and stop conditions.

A high-to-low transition of SDA while SCL is high is recognized

as a start condition, setting BBSY to 1. A low-to-high transition of

SDA while SCL is high is recognized as a stop condition,

clearing BBSY to 0.

To set a start condition, write 1 in BBSY and 0 in SCP. A

retransmit start condition is set in the same way. To set a stop

condition, write 0 in BBSY and 0 in SCP. It is not possible to

write to BBSY in slave mode: the I2C bus interface must be set to

master transmit mode before issuing a start condition. MST and

TRS should both be set to 1 before writing 1 in BBSY and 0 in

SCP.

• BBSY = 0

Bus is free.

[Clearing cond iti on]

When a stop condition is detected

• BBSY = 1

Bus is bu sy.

[Setting condition]

When a start condition is detected

R/W 0

Rev. 2.0, 11/01, page 35 of 358

name Bit

name Functions R/W Initial

value

IRIC IRIC indicates that the I2C bus interface ha s issued an interrupt

request to the CPU. IRIC is set to 1 at the end of a data transfer,

when a slave addres s or general cal l addre ss is detected in

slave receive mode, when bus arbitration is lost in master

transmit mode, and when a stop condition is detected. IRIC is

set at different times depending on the FS bit in SAR and the

WAIT bit in ICMR. The conditions under which IRIC is set also

differ depending on the setting of the ACKE bit in ICCR.

IRIC is cleared by reading IRIC after it has been set to 1, then

writing 0 in IRIC.

When the DTC is used, IRIC is cleared automatically and

transfer can be performed continuously without CPU

intervention.

• IRIC = 0

Waiting for transfer, or transfer in progress

[Clear conditi ons ]

(1) When 0 is written in IRIC after reading IRIC = 1

(2) When ICDR is written or read by the DTC (when the

TDRE or RDFR flag is cleared to 0)

• IRIC = 1

Interrupt requested.

[Setting conditions]

1. I2C bus format master mode

(1) When a start condition is detected in the bus line state

after a start condition is set (when the TDRE flag is set

to 1 because of first frame transmission)

(2) When a wait is inserted between the data and

acknowledge bit when WAIT = 1

(3) At the end of data transfer (at the rise of the 9th

transmit/receive clock pulse, or at the fall of the 8th

transmit/receive clock pulse when using wait insertion)

(4) When a slave address is received after bus arbitration

is lost (when the AL flag is set to 1)

(5) When 1 is received as the acknowledge bit when the

ACKE bit is 1 (when the ACKE bit is set to 1)

R/(W)*10

Rev. 2.0, 11/01, page 36 of 358

name Bit

name Functions R/W Initial

value

2. I2C bus format slave mode

(1) When the slave address (SVA, SVAX) matches (when

the AAS and AASX flags are set to 1) and at the end of

data transfer up to the subsequent retransmission start

condition or stop condition detection (when the TDRE

or RDRF flag is set to 1)

(2) When the general call address is detected (when FS =

0 and the ADZ flag is set to 1) and at the end of data

transfer up to the subsequent retransmission start

condition or stop condition detection (when the TDRE

or RDRF flag is set to 1)

(3) When 1 is received as the acknowledge bit when the

ACKE bit is 1 (when the ACKB bit is set to 1)

(4) When a stop condition is detected (when the STOP or

ESTP flag is set to 1)

3. Synchronous serial format and formatless

(1) At the end of data transfer (when the TDRE or RDRF

flag is set to 1)

(2) When a start condition is detected with serial format

selected

(3) When the SW bit of DDCSWR is set to 1

(4) When any other condition arises in which the TDRE or

RDRF flag is set to 1

SCP The SCP bit controls the issuing of start and stop conditions in

master mode. To set a start condition, write 1 in BBSY and 0 in

SCP. A retransmit start condition is set in the same way. To set

a stop condition, write 0 in BBSY and 0 in SCP. This SCP bit is

always read as 1. If 1 is written, the data is not stored.

• SCP = 0

Writing 0 sets a start or stop condit ion, in combi nati on wit h

the BBSY flag.

• SCP = 1

Reading always returns a value of 1.

Writing is ignored.

Rev. 2.0, 11/01, page 37 of 358

name Bit

name Functions R/W Initial

value

ICSR ICSR is an 8-bit readable/writable register that performs flag

confirmation and acknowledge confirmation and control. R/W H'00

ESTP The ESTP flag indicates that a stop condition has been detected

during frame transfer in I2C bus format slave mode.

• ESTP = 0

No error stop condition

[Clearing cond iti ons ]

(1) When 0 is written in ESTP after reading ESTP = 1

(2) When the IRIC flag is cleared to 0

• ESTP = 1

In I2C bus format slave mode, error stop condition is

detected.

[Setting condition]

When a stop condition is detected during frame transfer

• In I2C bus format slave mode

No meaning

R/(W)*10

STOP The STOP flag indicates that a stop condition has been detected

after completion of frame transfer in I2C bus format slave mode.

• STOP = 0

No normal stop condition

[Clearing cond iti ons ]

(1) When 0 is written in STOP after reading STOP = 1

(2) When the IRIC flag is cleared to 0

• STOP = 1

• In I2C bus format slave mode

Normal stop condition is detected.

[Setting condition]

When a stop condition is detected after completion of frame

transfer

• In mode other than slave mode in I2C bus format

No meaning

R/(W)*0

Rev. 2.0, 11/01, page 38 of 358

name Bit

name Functions R/W Initial

value

IRTR The IRTR flag indicates that the I2C bus interface has issued an

interrupt request to the CPU, and the source is completion of

reception/transmission of one frame in continuous

transmission/reception operation for which DTC activation is

possible. When the IRTR flag is set to 1, the IRIC flag is also set

to 1 at the same time.

IRTR flag setting is performed when the TDRE or RDRF flag is

set to 1. IRTR is cleared by reading IRTR after it has been set to

1, then writing 0 in IRTR. IRTR is also cleared automatically

when the IRIC flag is cleared to 0.

• IRTR = 0

Waiting for transfer, or transfer in progress

[Clearing cond iti ons ]

(1) When 0 is written in IRTR after reading IRTR = 1

(2) When the IRIC flag is cleared to 0

• IRTR = 1

Continuous transfer state

[Setting condition]

• In I2C bus format slave mode

When the TDRE or RDRF flag is set to 1 when AASX = 1

• In modes other than slave mode in I2C bus format

When the TDRE or RDRF flag is set to 1

R/(W)*10

AASX In I2C bus format slave receive mode , the AASX flag is set to 1 if

the first frame following a start condition matches bits SVAX6 to

SVAX0 in SARX.

AASX is cleared by reading AASX after it has been set to1, then

writing 0 in AASX. AASX is also cleared automatically when a

start condit ion is dete cte d.

• AASX = 0

The second slave address is not recognized.

[Clearing cond iti ons ]

(1) When 0 is written in AASX after reading AASX = 1

(2) When a start condition is detected

(3) In master mode

• AASX = 1

The second slave address is recognized.

R/(W)*0

Rev. 2.0, 11/01, page 39 of 358

name Bit

name Functions R/W Initial

value

[Setting condition]

When the second slave address is detected in slave receive

mode and FSX = 0

AL The AL flag indicates that arbitration was lost in master mode.

The I2C bus interface monitors the bus. When two or more

master devices attempt to seize the bus at nearly the same time,

if the I2C bus interface detects data differing from the data it sent,

it sets AL to 1 to indicate that the bus has been taken by another

master.

AL is cleared by reading AL after it has been set to 1, then

writing 0 in AL. In addition, AL is reset automatically by write

access to ICDR (transmit mode), or read access to ICDR

(receive mode).

• AL = 0

Bus arbitration won

[Clearing cond iti on]

(1) When ICDR data is written (transmit mode) or read

(receive mode)

(2) When 0 is written in AL after reading AL= 1

• AL = 1

Arbitration lost

[Set flag conditions]

(1) If the internal SDA and SDA pin disagree at the rise of

SCL in master tran smit mode

(2) If the internal SCL line is high at the fall of SCL in

master transmit mode

R/(W)*10

STCR STCR is an 8-bit readable/writable register that controls register

access, the I2C interface operating mode (when the on-chip IIC

option is included), and on-chip flash memory control (F-ZTAT

version), and selects the input clock of TCNT. Details other than

the I2C bus interface are omitted. If a module controlled by STCR

is not used, do not write 1 to the corresponding bit.

R/W H'00

IICX1 The IICX1 bit, together with bits CKS2 to CKS0 in ICMR, selects

the transfer rate in master mode of IIC channel 1. For details,

see CSK2 to CSK0 in ICMR.

R/W 0

IICX0 The IICX0 bit, together with bits CKS2 to CKS0 in ICMR, selects

the transfer rate in master mode of IIC channel 0. For details,

see CSK2 to CSK0 in ICMR.

R/W 0

Rev. 2.0, 11/01, page 40 of 358

name Bit

name Functions R/W Initial

value

IICE The IICE bit controls CPU access to the I2C bus interface data

and control registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR).

• IICE = 0

CPU access to I2C bus interface data and co ntrol regi sters is

disabled.

• IICE = 1

CPU access to I2C bus interface data and co ntrol regis ters is

enabled.

R/W 0

DDCSWR DDCSWR is an 8-bit readable/writable register that is used to

control the format automatic switching of IIC channel 0 and

controls the internal latch clear of IIC.

R/W H'0F

SWE The SWE bit selects the automatic switching function from

formatless to I2C bus format.

• SWE = 0

Disables automatic switching of IIC channel 0 from

formatless to I2C bus format.

• SWE = 1

Enables automatic switching of IIC channel 0 from formatless

to I2C bus format.

R/W 0

SW The SW bit selects formatless and I2C bus format in IIC channel

• SW = 0

IIC channel 0 is used in I2C bus format.

[Clearing cond iti ons ]

(1) When 0 is written by software

(2) When a falling edge is detected in SCL when SWE = 1

• SW = 1

IIC channel 0 is used by formatless.

[Setting conditions]

When 1 is written after read in SW = 0

R/W 0

Rev. 2.0, 11/01, page 41 of 358

name Bit

name Functions R/W Initial

value

IE The IE bit enables/disables the interrupt request from CPU when

the format's automatic switching is performed in IIC channel 0.

• IE = 0

Interrupt when the format is automatically switched is

disabled.

• IE = 1

Interrupt when the format is automatically switched is

enabled.

R/W 0

IF The IF bit is an interrupt request flag when the format is

automatically switched in IIC channel 0.

• IF = 0

Interrupt is not requested when format's automatic switching

is carried out.

[Clearing cond iti on]

When 0 is written after reading the sate of IF = 1

• IF = 1

Interrupt is requested when the format is automatically

switched.

[Setting condition]

When a falling edge is detected in SCL when SWE = 1

R/W 0

CLR3

to 0 Bits CLR3 to CLR0 control initialization of the internal state of

IIC0 and IIC1.

These bits can only be written to; if read, they will always return

to a value of 1.

When a write operation is performed on these bits, a clear signal

is generated for the internal latch circuit of the corresponding

module, and the internal state of the IIC module is initialized.

The write data for these bits is not retained . To perform IIC

clearance, bits CLR3 to CLR0 must be written to simultaneously

using an MOV instruction. Do not use a bit manipulation

instruction such as BCLR.

When clearing is required again, all the bits must be written to in

accordance with the setting.

• CLR3 = 0, CLR2 = 0, CLR1 = *, CLR0 = *,

setting is prohibited.

• CLR3 = 0, CLR2 = 1, CLR1 = 0, CLR0 = 1,

IIC0 internal latch is cleared.

W*11

Rev. 2.0, 11/01, page 42 of 358

name Bit

name Functions R/W Initial

value

• CLR3 = 0, CLR2 = 1, CLR1 = 1, CLR0 = 0,

IIC1 internal latch is cleared.

• CLR3 = 0, CLR2 = 1, CLR1 = 1, CLR0 = 1,

IIC0 and IIC1 internal latch is cleared

• CLR3 = 1, CLR2 = *, CLR1 = *, CLR0 = *,

setting is invali d.

Note *: 0 or 1

MSTPCR

LMSTP4 The MSTP4 bit specifies the module of IIC channel 0.

• MSTP4 = 0

IIC channel 0 module stop mode is cleared.

• MSTP4 = 1

IIC channel 0 module stop mode is set.

R/W 1

MSTP3 The MSTP3 bit specifies IIC channel 1 module.

• MSTP3 = 0

IIC channel 1 module stop mode is cleared.

• MSTP3 = 1

IIC channel 1 module stop mode is set.

R/W 1

Note: *1 Always read as 1.

2.3.5 Relationship betw een Flags o f On-chip I2C Bus Interface and Transfer State in H8S

Series (H8S/2138 Series)

When an interr up tion occurs after the IRIC flag in ICCR has been set to 1 with the I2C bus format,

it is necessary to check other flags to determine the cause of the IRIC flag being set to 1. Although

each cause has its corresponding flag, special care must be taken at the end of a data transfer.

When the internal flags TDRE or RDRF are set, the readable IRTR flag can be either set or not

set. Between the moment that the slave address (SVA) or general call address is matched and the

moment that the restart condition or stop condition is detected in the slave mode of the I2C bus

format, the IRTR flag, which is a DTC start requ est flag, is not set at the end of data transfer.

Even if the IRIC or IRTR flags are set, the internal flags TDRE or RDRF cannot be set. In the case

of a continuous transfer using the DTC, the IRIC or IRTR flags are not cleared when the specified

number of transfers has been completed. On the other hand, the flags TDRE or RDRF are cleared

because the specified number of read/write actions of ICDR have been completed.

Table 2.7 shows the relationship between transfer states and flags.

Rev. 2.0, 11/01, page 43 of 358

Table 2.7 Relationship between Tra nsf er States and Fla gs

MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB State

1/01/0000000000Idle state (flags

must be cleared)

11000000000Setting the start

condition

11100100000Start condition is

satisfied

11/0100000000/1Master mode wait

11/0100100000/1Master mode

transmit/receive

end

0010001/011/01/00Arbitration lost

00100000100Coincident with

SAR in slave mode

frame

00100000110Coincident with

general cal l

address

00100010000Coincident with

SARX

01/0100000000/1End of slave mode

transmission/recept

ion (except fo r after

SARX coincidence)

01/0

1End of slave mode

transmission/recept

ion (after SARX

coincidence)

01/001/01/0000000/1Stop condition

detected

2.4 Description of I2C Bus Interface Usage

(1) How to confirm the bus state [H8 Series, H8S Series]

In the I2C bus, the master device must confirm whether or not the bus is in the open state (both

SCL and SDA lines are constantly high) before starting to transfer data. This confirmation of the

bus state can be performed by reading the BBSY bit in the ICSR register in the H8 series or in the

ICCR register in the H8 S series. When the BBSY bit is 0, which means that the bus is in the o pen

state, the master device can start the data transfer.

Rev. 2.0, 11/01, page 44 of 358

(2) How to issue the start or stop co nditions [H8 Series, H8S Series]

The start condition is the change from high to low in SDA when SCL is high. The stop condition

is the change from low to high in SDA when SCL is high. The start con dition can be generated by

simultane ously writing BBSY=1 and SCP=0 into the register (ICSR in H8 serie s, ICCR in H8S

series). Simultaneous writing BBSY=0 and SCP=0 allows the stop condition to be generated.

Therefore, use the MOV instruction to issue the start/stop conditions.

Refer to section 2.4 (6), (7) “Continuous issuing of instructions”, and (8) “Notes on re-sending the

start condition”.

(3) How to transmit data [H8 Series, H8S Series]

Master operation

Data transmission is started by writing data in to the ICDR register. After the completion of the

transmission (or after the start condition h a s been generated), the SCL lin e must be held low to

generate the communication waiting state.

Slave operation

The low drive of the SCL line can b e released by writing data into the ICDR register to pr ep are

data transmission. Data must be transmitted to the master de vice by synchronizing the SCL

clock that is sent from the master device. After the co mpletion of the transmission, the SCL

line must be he ld low to in d icate th e waiting state to the master device. After the completion of

the last data transmission, release the SCL line by writing H'FF into the ICDR. This lets the

master device issue the stop condition.

(4) How to receive data (H8 Series I2C module) [H8 Series]

Master operation

Reading the ICDR register enables the SCL clock to be output and the data reception can be

started. The first data reading is a dummy run. The actual data reception starts after the

confirmation of the completion of the dummy data reception. After the completion of the data

reception, the SCL line must b e held low until the next read operation of ICDR to generate the

communication waiting state. The last data must be read by settin g TRS to 1 to enter transm it

mode after confirming the end of the last data reception.

Slave operation

In the I2C bus system, devices other than the master device start operation from slave reception

mode. Since the first byte is a slave address + R/W bit, the SCL is made to be in high-

impedance state and the slave address data is loaded in the data register (ICDR). When the

eighth bit is loaded, the slave address register (SAR) is compared to the data register (ICDR).

When addresses match, an acknowledge is returned to the master device at the ninth clock. At

this time, if the IRIC flag is set and an I2C bus interrupt is enabled (IEIC = 1), an interrupt

occurs. When addresses do not match, the IRIC flag is not set and this I2C module enters a wait

state in slave mode.

Rev. 2.0, 11/01, page 45 of 358

The eighth bit in the slave address phase means an R/W bit. When this bit is 1, subsequent

operations seen from the slave side are in transmit mode. When this bit is 0, subsequent

operations are in receive mode. The eighth bit is automatically reflected to the TRS bit.

When the TRS bit is 0, slave reception mode is still entered. The SCL is driven to low until the

CPU reads ICDR to indicate the waiting state to the master device (When the TRS bit is 1,

slave transmission mode is entered. The SCL is driven to low until the CPU sets data in ICDR

to indicate the waiting state to the master device).

(5) How to receive data (H8S Series I2C module) [H8S Series]

For the H8S ser ies I2C module, a data reception buffer is composed of ICDRR (register which can

be read by CPU, ICDR) and ICDRS (shift register). 2-byte-long data can be received after the data

reception trigger (dummy reading of ICDR register) has been issued. The load on the CPU is thus

reduced in application programs that read multiple data continuously.

Master operation

Reading the ICDR register enables the SCL clock to be output and the data reception can be

started. The first data reading is a dummy run. The actual data reception starts after the

confirmation of the completion of the dummy data reception. As the data buffer structure is

doubled, the next data reception takes place when the ICDRR (ICDR) register is empty or

when the CPU is reading the ICDRR (ICDR) register. When the data is stored in ICDRR

(ICDR) and ICDRS, the SCL line is held low un til the next read ope ration of ICDR to generate

the communication waiting state. The last data must be received in the way shown below.

(a) For reception of multiple data (3 bytes or more)

• Store 2-byte data before receiving the last data in ICDRR (ICDR) and ICDRS.

• After setting the WAIT bit to 1, continuously read the 2-byte data mentioned above to

make the buffer empty.

• Set the TRS bit to 1 (set th e transmission mode) after IRIC interruption occurred at the

falling edge of th e eighth clock in the SCL for the last da ta reception. Set the ACKB bit to

1. Then clear the IRIC flag to output the ninth clock.

• After an IRIC interruption occurred for the last data reception, read the last data.

• Clear the WAIT bit, then the ACKB b it, and finally the IRIC flag to issu e th e stop

condition.

(b) For reception of a datum (2 bytes or less)

• Set the WAIT bit to 1 before starting the data reception.

• Read the ICDRR (ICDR) register for the dummy run to start the data reception.

• Clear the IRIC flag after IRIC interruption occurred at the falling edge of the eighth clock

in the SCL to output the ninth clock of the SCL.

• The data reception completes at the rising edge of the ninth clock.

• Read the ICDRR (ICDR) register to receive the data.

Rev. 2.0, 11/01, page 46 of 358

• Set the TRS bit to 1 (set th e transmission mode) after IRIC interruption occurred at the

falling edge of the eighth clock in the SCL for the second byte data reception. Set the

ACKB bit to 1. Then clear the IRIC flag to output the ninth clock.

• After an IRIC interruption occurred for the last data reception, read the last data.

• Clear the WAIT bit, then the ACKB b it, and finally the IRIC flag to issu e th e stop

condition.

For an example for the master reception, refer to section 4 “Example Applications for the H8S

series”.

Slave operation:

In this I2C module, the data register is a double-buffer configuration (ICDRS and

ICDRR/ICDR). Therefore after a slave address which is the first data, the second data can be

continuously received. First, a slave address after the start condition by th e master device is

input to the buffer (ICDRS), and the buffer is compared to the value of the slave address

device at the ninth clock and the address data is loaded in the data register (ICDRR/ICDR). At

this time, if the IRIC flag is set and an I2C bus interrupt is enabled (IEIC = 1) , an in terru pt

occurs. When addresses do not match, the address data is not loaded in ICDRR/ICDR and a

wait state is entered in slave mode.

The eighth bit in the slave address phase means an R/W bit. When this bit is 1, subsequent

operations seen from the slave side are in transmit mode. When this bit is 0, subsequent

operations are in receive mode. The eighth bit is automatically reflected to the TRS bit.

When the TRS bit is 0, slave reception mode is still entered. ICDRS is now empty, therefore

the next data is received continuously by outputting the SCL clock of the master device. When

an acknowledge is returned to th e master device at the ninth clock and the CPU reads slave

address data from ICDR, data is shifted fro m ICDRS to ICDR R/ICDR. At this tim e, if the

IRIC flag is set to 1 and an I2C bus interrupt is enabled (IEIC = 1), an interrupt occurs. Th en

ICDRS is empty again and the next data is received continuously.

In the operation described above, if the I2C bus interrupt processing is delayed since another

interrupt processing is executed, and the CPU does not read the previously received data from

ICDR (internal RDRF flag = 1), the next data is held by ICDRS at the end of the reception, the

SCL is driven low, and the communication enters a waiting state for the master device.

Therefore the received data is protected. The receive end interrupt of the first data is erased by

the receive end interrupt of the second data. After the CPU reads the first data in

ICDRR/ICDR, the second data in ICDRS is immediately shifted to ICDRR/ICDRS. Then IRIC

is set again. When the I2C bus interrupt is enabled (IEIC = 1), an interrupt occurs. A procedure

for interrupts in slave reception is described below.

Example of procedure for interrupts in slave reception (H8S series)

(a) Confirms the contents of the status register (ICSR).

Rev. 2.0, 11/01, page 47 of 358

 Confirms the slave address matching (AAS or AASX = 1).

 Detects the stop condition (STOP = 1).

 Detects the error stop condition (ESTOP = 1).

 Detects the arbitration lost (AL = 1).

 Detects the general call address (b’0000000) (ADZ = 1).

(b) Clears the IRIC flag.

(d) Judges the TRS bit in ICCR and confirms the subsequent operation mode

(receive/transmit mode) after the slave address is received (When TRS = 1, the

subsequent operations are in slave transm ission mode. The SCL is d riven to low until th e

CPU sets data in ICDR to indicate the waiting state to the master d evice).

(6) Continuous issuing of instructions (H8 Series I2C module) [H8 Series]

A progr am that continuously issues in structions for start con dition issuing, data

transmission/reception, and stop co ndition issuing often does not work well. This is becau se

internal competition often occurs among the data transmission instructions and an instru ction is

ignored, when the generation for the start condition by setting the start condition in struction is

delayed due to the instruction timing and the load on the bus line. Some programming notes are

shown below.

(a) Timing for issuing the data tran smission instruction after the start con dition has been

issued:

after the instruction for setting the start condition has been issued, in sert a wait tim e of

one clock for the data transfer rate if any before executing the data transmit instru ctio n .

(b) To issue the stop condition after the start condition has b een issued:

confirm that BBSY = 1 and that bus authority has been ob tained.

(d) To set the start condition after the stop condition has been issued:

confirm that BBSY = 0 and that the bus has been released.

(e) To change the communication mode after the stop condition has been issued:

confirm that BBSY = 0 and that the bus has been released.

(f) To start the next data transmission/reception after the completion of the current data

transmission/reception:

For data transmission: confirm the completion of data transfer (IRIC = 1) and clear the

IRIC to 0; then write the n ext data to ICDR.

For data reception: confirm the completion of data transfer (IRIC = 1) and read the

ICDR; then clear the IRIC to 0. When TRS = 0, reading the ICDR acts as a trigger for the

next data reception. To read the last data, set the TRS to 1 and read the ICDR to receive

the reception data.

Rev. 2.0, 11/01, page 48 of 358

(g) To set the start condition again after the completion of data transmission/reception (to

issue start condition for re-transmission):

this operatio n is applied when the master transmission is ex changed with the ma ster

reception. Confirm first that the data transmission has been ended (IRIC = 1), th en clear

the IRIC to 0, an d finally execute the instruction for setting the start condition.

(h) To issue the stop condition after the completion of data transmission/reception:

For master transmission: confirm the comp letion of data transmission (IRIC = 1) and

clear the IRIC to 0; then issue the stop con dition.

For master reception: confirm the comp letion of data reception (IRIC = 1) and set the

TRS to 1 (master transmissio n mode); then read the fina l data. After th at, clear the IRIC

to 0 and issue the stop condition.

(7) Continuous issuing of instructions (H8S Series I2C module) [H8S Series]

(a) Timing for issuing data transmission instruction after the start condition has been issued:

after the instruction for setting the start condition has been executed, co nfirm that the

start condition has been generated, by checking the IRIC flag; then execute the data

transmission instruction.

(b) To issue the stop condition after the start condition has b een issued:

after the instruction for setting the start condition has been executed, co nfirm that the

start condition has been generated by checking the IRIC flag. After confirming that

BBSY = 1, issu e the stop condition.

after the instruction for setting the start condition has been executed, co nfirm that the

start condition has been generated by checking the IRIC flag. After confirming that

BBSY = 1 and that the bus right is acquired, change the communication mode.

(d) To issue the start condition after the stop condition has been issued:

confirm that BBSY = 0 and that the bus has been released.

(e) To change the communication mode after the stop condition has been issued:

confirm that BBSY = 0 and that the bus has been released.

(f) To start the next data transmission/reception after the completion of data

transmission/reception:

For data transmission: confirm the completion of data transfer (IRIC = 1) and write the

next datum to ICDR. To confirm that the next data transfer is completed, clear th e IRIC

flag to 0.

For data reception: confirm the completion of data transfer (IRIC = 1) and read the

ICDR; then clear the IRIC to 0. As the buffer for data reception has a two-stage structure

in the H8S series I2C module, 2-byte-long data is continuously received after reading the

ICDRR (ICDR). To terminate the data reception, you must change the TRS bit to 1

(transmitting mode) during the last data reception (during the time period between the

rising edge of the SCL first clock and the rising edge of the ninth clock). How to set this

TRS bit is described in section 2.4 (13).

Rev. 2.0, 11/01, page 49 of 358

(g) To issue the start condition again after the completion of data transmission/reception (to

issue the start condition for re-transmission):

this operatio n is applied when the master transmission is ex changed with the ma ster

reception. First, confirm that the data transmission has been ended (IRIC = 1), then clear

the IRIC to 0, an d finally execute the instruction for issuing the start condition.

(h) To issue the stop condition after the completion of data transmission/reception:

For master transmission: confirm the comp letion of data transmission (IRIC = 1) and

clear the IRIC to 0; then issue the stop con dition.

For master reception: confirm the comp letion of data reception (IRIC = 1) and set the

TRS to 1 (master transmissio n mode); then read the fina l data. After that, clear the IRIC

to 0 and issue the stop condition.

(8) Notes on re-sending the start condition [H8 Series, H8S Series]

When data is going to be transferred af ter the restart condition has been issued, the transfer

instruction for the next byte should be executed by confirming that the SCL rose (point (A) in

figure 2.5 after issuing the restart condition.

SCL 9 (A) 1

SDA ACK Bit 7

Restart condition

Period for generating

the restart condition

Period for transferring

the next byte

Bit 6

IRIC

Standard

clock

Execution of the instruction

for issuing restart condition

Execution of a transfer

instruction for the next byte

Figure 2.5 Execution Timing for Transfer Instruction for the Next Byte

in the case of Resending t he St art condition

The execution takes place as follows:

In the I2C bus, the waiting state of a transfer operation in the case of the bus-occupied

state is shown by SCL = low and SDA = high. Therefore, the instruction for issuing

Rev. 2.0, 11/01, page 50 of 358

the restart condition should be executed after confirming that SCL = low. Then

confirm that the SCL = high (because the SCL is changed from low to high by the

generation of the restart cond ition ) and execute a transfer instruction for the next by te.

In the H8S series, when the restart condition is satisfied, an interrupt is generated.

Then the transfer instruction for the next byte must be executed.

(9) Confirmation of the coincidence of slave addresses [H8 Series, H8S Series]

Each bit of a slave address that was transmitted from the master device is compared with the

corresponding bit of the SAR (in the H8S series I2C module, two slave addresses, SAR and

SARX, are available). If the slave address matches the SAR, the AAS bit (in the H8S series I2C

module: AAS or AASX bit) is set, and you can thus know that this device is the slave device that

was specified by the master device in the IRIC interruption at the rising edge of the ninth SCL

clock.

(10) Recognition of general call address [H8 Series, H8S Series]

The master device uses the general call address H'00 to specify all the I2C devices as slave devices.

The I2C module sets the ADZ flag to 1 after recognizing the general call address. This flag is

confirmed during the IRIC interruption at the rising edge of the ninth SCL clock.

(11) Recognition and setting of the acknowledge bit [H8 Series, H8S Series]

A data transmitting d evice receives the acknowledge bit from the data receiving device at the ninth

SCL clock. This value is loaded in the ACKB bit and can be confirmed during the IRIC

interruption at the rising edge of the ninth SCL clock. Th e data receiving device (TRS = “0”)

outputs th e value set in the ACKB bit to th e SDA line at the ninth SCL clo c k. Note that when the

TRS bit is set to 1, the value set in the ACKB bit in transmit mode is output. There are two

internal ACKB bits according to whether the TRS bit is set to 1 or cleared to 0.

(12) Setting the transmit/receive mode in slave operation [H8 Series, H8S Series]

The R/: bit is automatically reflected to the TRS bit. If the R/: bit is 1 (read operation from the

viewpoint of the master device) after the slave address sent out from the master device, the TRS

bit is automatically set to 1 and slave transmit mode is entered.

(13) Wait operation [H8 Series, H8S Series]

A wait can be inserted between the eighth and ninth SCL clocks by setting the WAIT bit to 1 in

master mode. An I2C module holds the SCL line low after outputting the eighth clock. The ninth

clock is sent out by clearing the IRIC flag to 0. In an I2C bus and SMBus, a protocol that does not

return an acknowledgment to slave devices upon receiving the last data in master operation is also

available. Changing the ACKB bit from 0 to 1 by stopping the SCL clock at the eighth clock using

this wait operatio n makes it easy to con tro l the acknowledge bit.

This wait operation can be applied to the master receiving operation in a byte-wise manner in the

Rev. 2.0, 11/01, page 51 of 358

I2C module for the H8S series. The SCL clock can be stopped because the transmit mode becomes

valid at the output timing of the SCL ninth clock after the IRIC flag was cleared by setting the

transmit mode (TRS = 1) during this wait operation. Refer to (f) in section 2.4 (5) and 2.4 (7).

(14) How to confirm the number of transferred bits [H8 Series, H8 S Series]

The bits BC2 to BC0 in the ICMR register are the bit counter that controls the number of SCL

clocks. This counter decrements by 1 with each output of a clock. Reading the counter bits enables

you to know how many bits were sent out. Writing back a value to the counter bits, however,

needs special care. For example, wh en the sam e value as before is written back to the bits BC2 to

BC0 immediately after the SCL clock has been output by the I2C module, an excess SCL clock is

output. This generates a discrepancy among the bits for the slave device.

(15) Clearing the bits AL, AAS (AASX), and ADZ [H8 Series, H8S Series]

The bits AL (arbitration lost flag), AAS (AASX) (slave address recogn ition flag), and ADZ

(general call address recog nition flag) can be cleared by writing 0 to the respective b it after

reading it. Reading from or writing to the ICDR automatically clears bits AAS and ADZ.

Detecting the start condition automatically clears the AASX bit.

(16) Bus arbitration [H8 Series, H8S Series]

The I2C bus corresponds to m ultiple masters and has the structure for bus arbitration (refer to

figure 1.9 for details). When multip le master devices simultaneously issu e a start condition, each

device compares the data of the SDA line and the intern al SDA data at the rising edge of the SCL

line clock. If these data are different from each other, the device stops the driving of the bus. In

other words, the device that continues to output the low level to th e SDA line until the final time

can become the master device.

This I2C module sets the AL flag to 1 and turns the bus output off when the bus right is lost (bus

arbitration lost). Also this I2C module automatically changes the operation mode from master

transmission to slave reception, because the master device that got the bus right may specify the

H8 as a slave device. When the slave addresses match (AAS or AASX = 1), an interrupt occurs at

the rising edge of the ninth clock of the SCL. Therefore the AL flag can be confirmed to be 1.

When the slave addresses do not match, an interrupt occurs by detecting the stop condition. Then

the AL flag can be confirmed to be 1. Figure 2.6 shows an example of this bus arbitration

processing flow.

Rev. 2.0, 11/01, page 52 of 358

Start of I

C master operation

BBSY = 1 ?

IRIC = 1 ?

Set the master transmission mode

and execute the start condition

Set the slave address in ICDR

and clear the IRIC flag

The next master

operation

Slave reception

Yes

IRIC = 1 ?

AL = 1 ?

AAS(AASX)

= 1 ?

Confirm that the bus is available

Confirm that the start condition

has been satisfied

(in the case of H8S/2138)

Confirm the rising edge of the ninth

SCL clock

Confirm the coincidence of the

slave addresses

Read the ICDR register to receive the data

Confirm the bus arbitration loss

Figure 2.6 Bus Arbitration Processing

(17) The controllable ranges of the ICE bit [H8 Series, H8S Series]

The ICE bit controls:

(a) assignment of I/O addresses (changing the SAR or ICMR registers), and

(b) changing the pin functions of the SCL and SDA ports to general purpose I/O ports (in

H8/3947 series: changing to the Hi-Z state).

Clearing the ICE bit can initialize the internal state of an H8S series I2C module. This can be used

to return the state to normal when the bus line of the microprocessor is stuck at low as a result of,

for example, a communication malfunction.

Rev. 2.0, 11/01, page 53 of 358

(18) Using the serial communication interface together with the I2C bus [H8 Series]

(H8/3337 Series and H8/3437 Series)

H8/3337 series and H8/3437 series have two serial communication interfaces (SCI0 and SCI1).

SCI0 shares part of the register addresses with the I2C bus interface. The SCK1 pin (clock pin) of

the SCI1 is also used as the SCL pin*1. When SCI (serial communication interface) is used as two

channels and the I2C bus is used as one channel, care shou ld be taken about the following points.

(a) As SCK1 shares pins with the SCL, use the SCI1 in the asynchronous mode (UART).

(b) When SCI0 and the I2C bus are used, set SCI0 to the state in which IICE = 0. The

registers SMR and BBR share the addresses with the I2C bus interface register. These

registers are used for the initial setting, so there is no need to set them again once they

have been set unless the communication mode is changed. Then set the IICE to 1 and

change to the accessing for I2C bus interface register to set the I2C bus.

Note: In the case of the H8/3217 series, two SCIs (one SCI in H8/3212) and two I2C bus

interface (one I2C bus interface in H8/3202) are independently available.

(19) Using the serial communication interface together with the I2C bus [H8S Series]

(H8S/2138 Series and H8S/2148 Series)

The H8S/2138 series and H8S/2148 series have three serial communication interfaces (SCI0,

SCI1, and SCI2) and two I2C bus interfaces (IIC0 and IIC1). (SCI0 and SCI1 share part of the

as three channels and I2C bus is used as two channels, care should be taken about the following

points.

(a) As SCK (pins SCK0, SCK1, and SCK2) of the SCI shares pins with the I2C bus, use the

SCI in the asynchronous mode (UART).

(b) When SCI and the I2C bus are used, set SCI0, SCI1, and SCI2 to the state in which IICE

= 0. The registers SCMR and BRR are shared with the I2C bus interface register. These

registers are used for initial setting. Th erefore on ce these registers are set, resetting is not

necessary unless the communication mode is changed. Then set IICE to 1 and change to

the accessing for the I2C bus interface register to set the I2C bus.

Rev. 2.0, 11/01, page 54 of 358

2.5 Synchronization of the I2C Bus Communication

The format of the output port of the I2C bus is an open-drain. Therefore, the time taken to change

from low to high depends on the load on a bus line. In the I2C bus specification, the rise time of

the SCL line is decided to 1000 ns in normal mode (maximum data transfer rate is 100 kbps) and

300 ns in high-speed mode (maximum data transfer rate is 100 kbps). In the I2C bus, data must be

fixed during the time period when the SCL line (clock line) is high. The actual data transfer rate is

changed (synchronized communication) for the purpose of performing normal data transfer if the

bus line load capacity and the value of the pull-up resistance connected between the bus line and

power supply are inadequate.

Figure 2.7 shows an example of synchronized communication. This I2C module outputs the SCL

clock on the SCL line in its master operation according to the internal standard clock that has the

prescribed data transfer rate. Monitor th e SCL line at the prescribed timing (refer to table 2.8) after

the SCL line has risen from low to high to con f irm that each bit of the SCL line h as become high.

If the rising edge of the SCL line is delayed or another device drives the SCL line to the low level,

then the voltage level may not reach VIH (threshold voltage for recognizing the high level of I/O).

In this case, delay the timing that drives the SCL line to the low level so that normal data

communication takes place. After confirming that the SCL line has become high, drive the SCL

line to the low level. As a result, the period of high level in the SCL line is p r olonged and the da ta

transfer rate becomes lower.

In other words, to get th e prescribed data tran sfer rate, the pull-u p resistance or b u s line load

capacity should be adjusted to adequate values.

SCL

VIH

tSr tSr

[1] Drive the SCL line to high

[5] Drive the SCL line to low at this timing

As a result, the data transfer rate becomes half the prescribed rate in this example

[4] Recognize the high level of the SCL line at this timing

[2] Monitor the SCL line to check

that it has became low at this timing

(voltage level is lower than VIH)

Internal standard

clock

[3] Do not drive the SCL line to low

Figure 2.7 When the Rising Edge of the SCL Line is Delayed

Rev. 2.0, 11/01, page 55 of 358

Table 2.8 Monitoring Timing for Rising Edge of the SCL Line (H8S/2138 Series)

tSr Time expression

IICX bit

Monitoring

timing for rising

edge of the SCL

Line tSr (tcyc

expression)

Modes Specificatio

n of I2C bus

(max) φ

φφ

φ=5MHz 8MHz 10MHz 6MHz 20MHz

Normal

mode 1000 ←937 750 468 37507.5×tcyc*

High-speed

mode 300 ←←←←←

Normal

mode 1000 ←←←←8751 17.5×tcyc*

High-speed

mode 300 ←←←←←

Note: *The tcyc is the system clock period of this microprocessor.

(For reference only)

An example of the calculation for the pull-up resistance on the I2C bus (H8S/2138 Series)

This is an example of the calculation for the pull-up resistance that connects the I2C b us to the

power supply.

• load capacity of the SCL line CB = 100 pF

• rise time of the SCL line tSr = 300 ns

• power supply voltage Vcc = 5.0 V

• voltage level for judging the high level of I/O VIH = Vcc x 0.7 = 3.5 V

using the calculation formula, Vcc x (1- exp(-t/(CB x R)) = VIH, gives the value of R as follows:

∴ R ≅ 2.5 kΩ.

Rev. 2.0, 11/01, page 56 of 358

2.6 Description of Data Transfer in H8/300 and H8/300L Series [H8 Series]

Data transfer should be done in the following conditions:

• Operation mode: addressing mode (a mode to recognize the slave address: FS = 0)

• Data transmission: MSB first (MLS = 0), no wait (WAIT = 0), and acknowledgement

mode (a mode to recognize the acknowledgement: ACK = 0)

2.6.1 Master transmission

In the master transmission mode, the master device outputs the transmission clock (SCL line) and

transmission data (SDA line), and slave devices return ackno wledgments. Figure 2.8 describes the

setting procedures and operation of th e master transmission mode.

76543210 76···

···

2 3 4 5 6 7 8 9 1 2 ···

SDA

(Master output)

SDA

(Slave output)

IRIC

SCL

[1] to [7] [8] [9] [10] [11] [12] [14]

Interrupt request occurs

Figure 2.8 Operation Timing of the Master Transmission Mode

(for MLS=WAIT=ACK=0)

Example of set t ing procedures of mast er t r ansmission mode

[1] *

Software processing: Sets CKDBL.

Objective: Selects the system clock (φ) or clock of ½ division ratio (φ/2) for the

peripheral clock.

[2] *

Software processing : Sets th e IICE b it to 1.

Objective: Enables access to the I2C bus interface registers.

Note: * This setting is only for the H8/3337, H8/3437, and H8/3217 series.

Rev. 2.0, 11/01, page 57 of 358

[3]

Software processing: Sets the SAR register. The uppermost 7 bits of the SAR are a slave

address and the lowermost 1 bit (FS bit) are 0. This setting should be

done in the case of a single master operation.

Objective: Sets the SAR register, because a slave mode may be set even in master

mode when the system is in multi master mode .

[4]

Software processin g: Sets the ICE bit to 1.

Objective: The SAR shares the address with the ICMR. An access to the SAR can

thus be changed to an access to the ICMR by sharing the address. This

change enables data transfer.

[5]

Software processing: Sets the ACKB bit.

Objective: Be sure to set the ACKB bit, because the mode automatically is shifted to

slave reception by the bus arbitration even if the device is used in master

mode.

[6]

Software processin g: Clears the bits MLS, WAIT, and ACK to 0. Sets the b its CKS2 to 0,

IICX, and IEIC so as to suit the operation mode.

Objective: Be sure to set the ACKB bit, because the mode automatically is shifted to

slave reception by the bus arbitration even if the device is used in master

mode.

[7]

Software processing: Reads the BBSY bit.

Objective: Confirms whether the bus has been released or is in use. If it has been

released, BBSY equals 0. Th en proceed to the next setting step.

[8]

Software processing: Sets the bits MSB and TRS to 1, writes 1 to the BBSY bit, and writes 0

to the SCP bit. The MOV instruction must be used to set these bits,

because they must be simultaneously set.

Objective: Switches to the master transmissio n mode and sets the start condition.

Hardware processing: The SDA changes from high to low, when the SCL is high.

[9]

Software processing: Writes data to the ICDR register. The first data is a slave address and the

R/W bit (= 0 ).

Objective: Starts the data tran sfer.

Hardware processing: The master device sequentially sends the transmission clock and the data

written in the ICDR with the timing shown in figure 2.8.

Rev. 2.0, 11/01, page 58 of 358

[10]

Software processing: Sets the IRIC bit to 1 at the ninth clock when one byte of data has been

transmitted. The master device receives an ackno wledgment from the

slave device, and sets the ACKB bit to 0. Fixes the SCL to low by

synchronizing with the internal clock after transferring one frame of data.

Objective: The state in which the IRIC bit equals 1 means the end of a data transfer

or bus arbitration. An interrupt request is issu ed to the CPU when the

IEIC bit has been set to 1. The ACKB bit is used to confirm whether the

acknowledge from the slave device has been received or not.

[11]

Software processing: Clears the IRIC bit.

Objective: Clears the IRIC b it for the subsequ e nt data transmission.

[12]

Software processing: Writes data to the ICDR register.

Objective: Starts the data tran sfer.

[13]

Software processing: Repeats procedures [10] to [12].

Objective: Con tinues to transmit data.

[14]

Software processin g: Writes 0 to the bits BBSY and SCP in the ICSR register. The MOV

instruction must be used to set these bits, because they must be

simultaneously set.

Objective: Issues the stop condition to terminate the transmission.

Hardware processing: The SDA changes from low to high, when the SCL is high.

2.6.2 Master Reception

In the master reception mode, the master device outputs the reception clock (SCL line) and

receives data from slave devices. The master device retu rns acknowledgments to slave devices.

In addressing mode, a slave address is firstly output with master transmission mode. The operation

is the same as shown in “2.6.1 Master transmission mode” when the data transmission

subsequently takes place. When data is going to be received, the mode should be switched to

master reception after the first frame (one byte of data including the slave address) has been

transferred. Figu re 2.9 describes the setting procedures and operation of the master reception

mode.

Rev. 2.0, 11/01, page 59 of 358

19 2 1 2 ···3456789

7A 6543210 76···

SDA

(Master

output)

SDA

(Slave

output)

IRIC

SCL

[9][7][6][5][4][3][2][1]

Interrupt request occurs

···

Figure 2.9 Operation Timing of the Master Reception Mode (for MLS=WAIT=ACKB=0)

Example of setting procedures of master reception mode

[1]

Hardware processing: Th e master device sets the start co ndition in the master transmission

mode, and sends out the first byte including the slave address. The IRIC

bit is set to 1 at the ninth clock. The master device receives an

acknowledge from the slave device, and sets the ACCB bit to 0.

Objective: The state in which IRIC = 1 means the matching of the slave address.

[2]

Software processing: Clears the IRIC bit by the software.

Objective: Prepares for the subsequent data reception.

[3]

Software processin g: Sets the TRS bit to 0.

Objective: Switches to the master reception mode.

[4]

Software processing: Reads the ICDR register (dummy reading).

Objective: This reading starts the reception of data.

Hardware processing: The master device outputs the reception clock by synchronizing with the

internal clock and receives data.

Rev. 2.0, 11/01, page 60 of 358

[5]

Hardware processing: Sets the IRIC bit to 1 at the ninth clock, when one-byte data reception

has ended. The master device simultaneously makes the SDA low and

returns an acknowledgment. After transferring the one-frame data, the

SCL is automatically fixe d to low by synchronizing with th e internal

clock.

Objective: The state in which the IRIC bit equals 1 means the end of a data transfer.

An interrupt request is issued to the CPU when the IEIC bit has b een set

to 1.

[6]

Software processing: Clears the IRIC bit to 0 by the software

Objective: Prepares the subsequent data reception

[7]

Software processing: Reads the ICDR register

Objective: The subsequent data reception is started by synchronizing with the

internal clock. Set the ACKB bit to 1 before starting data reception, when

an acknowledgment is not returned after the reception of the last byte.

[8]

Software processing: Repeats procedures [5] to [7 ]

Objective: Continues to receive data

[9]

Software processing: To stop the data reception, set the TRS bit to 1 and write 0 to bits BBSY

and SCP after reading the ICDR register.

Objective: Switches th e communication mode to the transmission mod e so th at the

data is not received again. Issues the stop condition after releasing the

SCL and SDA lines by reading the ICDR register.

Hardware processing: The SDA changes from low to high, when the SCL is high.

2.6.3 Slave Reception

In the slave reception mode, the master device outputs the transmission clock and transmission

data, and slave devices receive the data and return acknowledgments.

Figure 2.10 describes the setting procedures and operation of the slave reception mode.

Rev. 2.0, 11/01, page 61 of 358

76543210 76···

···

2 3 4 5 6 7 8 9 1 2 ···

SDA

(Master output)

SDA

(Slave output)

SCL

(Slave output)

IRIC

SCL

(Master output)

[14][11][10][9][8][1] to [7]

Interrupt request occurs

Figure 2.10 Operation Timing of the Slave Reception Mode (for MLS=WAIT=ACKB=0)

Example of setting procedures of slave reception mode

[1]

Software processing: Sets CKDBL.

Objective: Selects the system clock (φ) or clock of ½ division ratio (φ/2) for the

peripheral clock.

[2]

Software processing : Sets th e IICE b it to 1.

Objective: Enables access to the I2C bus interface registers.

[3]

Software processing: Sets the SAR register. Writes the slave address to the uppermost 7 bits of

the SAR, and 0 to the lowermost 1 bit (FS bit) (in addressing format).

Objective: Assigns an address to the slave device because the mode is an addressing

mode.

[4]

Software processin g: Sets the ICE bit to 1.

Objective: The SAR shares the address with the ICMR. An access to the SAR can

thus be changed to an access to the ICMR by sharing the address. This

change enables data transfer.

Rev. 2.0, 11/01, page 62 of 358

[5]

Software processin g: Clears the bits MLS, WAIT, and ACK to 0. Sets the b its CKS2 to CKS0,

IICX, and IEIC.

Objective: Sets the MSB first mode with the MLS bit, the no-wait mode with the

WAIT bit, and the acknowledgement mode with the ACK bit. Defines

the transfer clock frequency by the combination of the bits CKS2 to

CKS0, and IICX. The IEIC bit defines the interrupt request of the I2C bus

interface as being enabled or disabled.

[6]

Software processing: Sets the bits MST and TRS to 0.

Objective: Sets the slave reception mode.

[7]

Software processin g: Sets the ACKB bit to 0.

Objective: Sets the ACKB bit to 0 so that the master dev ice will return an

acknowledgment after receiving the data.

[8]

Hardware processing: After th e start condition th at was issued by the m a ster dev ice h a s been

detected, the BBSY b it is set to 1.

Objective: Shows that the bus is in use (The master device outputs the first byte).

[9]

Hardware processing: The slave device confirms the matching of the slave address by reading

the first byte after the start cond ition, and sets the IRIC bit to 1 at the

ninth clock. It simultaneously makes the SDA low and returns an

acknowledgment. It fixes the SCL to low from the falling edge of the

ninth reception clock to the moment of reading data into the ICDR.

Objective: The state in which the IRIC bit equals 1 means the matching of the slave

address. An in terrupt request is issued to the CPU when the IEIC bit has

been set to 1.

[10]

Software processing: Clears the IRIC bit by software.

Objective: Prepares for the subsequent data reception.

[11]

Software processing: Reads the ICDR register.

Objective: The slave device releases the SCL line, and the subsequent data reception

starts.

[12]

Software processing: Repeats procedures [9] to [11].

Objective: Continues to receive data.

Rev. 2.0, 11/01, page 63 of 358

[13]

Software processing: The SDA changes from low to high when the SCL is high in response to

the stop condition issued from the master device, and the BBSY bit is

automatically cleared to 0 after the stop condition has been detected.

Objective: Terminates the data reception.

2.6.4 Slave Transmission

In slave transmission mode, a slave device outputs the reception data. The master device outputs

the reception clock and returns an acknowledgment to the slave device.

In addressing mode, a slave address is first transferred from the master device to the slave device.

At that time, the operation mode of the slave device is thus set to slave reception. The operation is

the same as shown in “2.6.3 Slave reception” when the data reception subsequently takes place.

When the slave device is going to transmit data to the master device, the mode should be switched

to slave tran smission mo de.

Figure 2.11 describes the setting procedures and operation of slave transmission mode.

198

[7][6][5][4][3][2][1]

6543210 76

···

2 3 4 5 6 7 8 9 1 2 ···

SCL

(Slave

output)

SDA

(Slave

output)

IRIC

SCL

(Master

output)

Slave reception mode Slave transmission mode

SCL

(Master

output)

Interrupt request

occurs

Interrupt request occurs

Figure 2.11 Operation Timing of Slave Transmission Mode (for MLS=WAIT=ACK=0)

Rev. 2.0, 11/01, page 64 of 358

Example of setting procedures of slave transmission mode

[1]

Hardware processing: The slave device confirms that the slave address matches by reading the

first byte after detecting the start condition , and sets the IRIC bit to 1 at

the ninth clock. The slave device simultaneously sets the SDA line to low

and returns an acknowledgment. Wh en the R/: bit (the eighth bit of the

received data) is 1, the TRS bit is set to 1 and the operation mode

automatically switches to slave transmission mode. The slave device

fixes the SCL line to low from the falling edge of th e ninth transmission

clock to th e start of writing data to the ICDR.

Objective: When IRIC bit equals 1, it means the slave address matches.

[2]

Software processing: Clears the IRIC bit to 0.

Objective: Prepares the subsequent data transmission.

[3]

Software processin g: Writes the data in the ICDR register.

Objective: Starts the d ata transmission.

Hardware processing The slave device releases the SCL line by changing it to high and

sequentially sen d s th e d a ta written in the ICDR according to the clock

that is output by the master device with the timing shown in figure 2.8.

[4]

Hardware processing: After o ne byte of data has been transmitted, sets th e IRIC bit to 1 at the

rising edge of the ninth clock. The slave device receives an

acknowledgment from the master device, and sets the ACKB bit to 0.

The slave device automatically fixes the SCL line to low during the

period from th e falling edge of the ninth transmission clock to the start of

writing data to the ICDR.

Objective: The state in which the IRIC bit equals 1 means the end of a data transfer.

An interrupt request is issued to the CPU when the IEIC bit has b een set

to 1. The ACKB bit indicates whether or not the acknowledgment has

been received from the master device.

[5]

Software processing: Clears the IRIC bit by software.

Objective: Prepares the subsequent data transmission.

[6]

Software processing: Writes the subsequent transmission data to the ICDR register.

Objective: The slave device releases the SCL line by changing it to high and starts

the data transmission.

Rev. 2.0, 11/01, page 65 of 358

[7]

Software processing: Repeats procedures [4] to [6 ].

Objective: Con tinues the data tran smission.

[8]

Software processing: Writes H'FF in the ICDR register.

Objective: Releases the SCL line so that the master device can issue the stop

condition.

Hardware processing: The SCL line is released and allowed to go high. The SDA line changes

from low to high when the SCL line is high by the issuing of the stop

condition from the master device, and the BBSY bit is automatically

cleared to 0 after the stop cond ition is detected.

2.7 Description of Data Transfer in H8S Series (H8/2138 Series) [H8S

Series]

2.7.1 Master Transmission

In the master transmission mode using the I2C bus format, the master device outputs the

transmission clock and transmissio n data, and slav e devices return acknowledgm ents. The setting

procedures and operation of the master transmission mode are described below.

Rev. 2.0, 11/01, page 66 of 358

[15]

[19]

[17]

[18] [23]

[24]

[16]

[1] to [14] [25] to [28]

bit7 bit6 bit5 bit4 bit3 bit2

R/W

bit1 bit0 bit7 bit6

[21]

[22]

[20]

Address + R/W

23456789

SDA

(Master output)

SDA

(Slave output)

IRIC

TDRE

ICDRT

ICDRS

SCL

(Master output)

Slave address Data 1

Data 1

Figure 2.12 Operation Timing of Master Transmission Mode

(for MLS=WAIT=0)

Example of set t ing procedures of mast er t r ansmission mode

[1] Initial setting 1

Software setting: Clears the MSTP4 or MSTP3 bit in the MSTPCRL to 0.

Objective: Cancels the module stop mode of IIC channel 0 or IIC channel 1.

[2] Initial setting 2

Software setting: Sets the IICE bit in the STCR to 1.

Objective: Enables the CPU to access the data register and control register of the I2C

bus interface.

[3] Initial setting 3

Software setting: Sets the DDCSWR.

Objective: Selects enable/d isab le fo r th e automatic switching function b e tween

format-less and I2C bus format in IIC channel 0.

Selects format-less or I2C bus format in IIC channel 0.

Selects enable/disable for interrupt requests to the CPU when automatic

switching of the format takes place in IIC channel 0.

Rev. 2.0, 11/01, page 67 of 358

[4] Initial setting 4

Software setting: Clears th e ICE bit in th e ICCR to 0.

Objective: Enables access to the SAR and SARX.

[5] Initial setting 5

Software settin g: Sets the SAR and SARX.

Objective: Sets the SW bit in th e DDCSWR, the transfer format, and the slave

address.

Note: Sets the slave address, because slave mode may be set even in master

mode when the system is in multi-master mode.

[6] Initial setting 6

Software setting: Sets the I CE bit in the I CCR to 1.

Objective: Enables access to the ICMR and ICDR.

Puts the I2C module in the transfer-enabled state.

[7] Initial setting 7

Software setting: Sets the ACKB bit in the ICSR.

Objective: Sets the acknowledgment data that is output during data reception.

Note: Be sure to set the ACKB bit, because the mode automatically shifts to

slave reception if bus arbitration is lost even if the device was being used

in master mode.

[8] Initial setting 8

Software setting: Sets the bits IICX1 or IICX0 in the STCR, and the bits CKS2 to

CKS0 in the ICMR.

Objective: Selects the transfer clock frequency to be used.

[9] Initial setting 9

Software setting: Sets th e b its MLS and WAIT in the ICMR to 0.

Objective: Sets the MSB-first mode and the no-wait m o d e in data tran sfer.

[10] Initial setting 10

Software setting: Sets the ACKE bit in the ICCR.

Objective: Selects on e of the following two actions:

Transfer data continuously by ignoring the contents of the

acknowledgment bit returned from the reception device in the I2C bus

format.

Perform the error processing by discontinuing the transfer operation

when the acknowledgment bit equ a ls 1.

[11] Initial setting 11

Software setting: Sets the IEIC bit in the IICR.

Objective: Selects enable/d isab le fo r in terrupt request to the CPU from th e I2C bus

interface.

Rev. 2.0, 11/01, page 68 of 358

[12] Confirmation of the bus state

Software setting: Reads the BBSY b it.

Objective: Confirms whether the bus is released or in use.

Hardware behavior: If the bus is released, the BBSY bit is equal to 0 .

[13] Setting the master transmission mode

Software setting: Sets the bits MST and TRS in ICCR to 1.

Objective: Sets the op eratio n m ode of th e I2C bus interface to master transmission

mode.

[14] Clearing the IRIC

Software setting: Clears th e IRIC bit in th e ICCR to 0.

Objective: Judges whether the start condition was detected.

[15] Setting the start condition

Software setting: Sets the BBSY bit to 1, a nd clears the SCP bit to 0 in ICCR.

Objective: Sets the start co ndition.

Note: The MOV instructio n m ust be used to set the BBSY bit to 1 and clear

the SCP bit to 0, because these two bits must be simultaneously set.

Hardware behavior: The SDA changes from high to low, when the SCL is high.

[16] Confirmation that start condition has been satisfied

Software setting: Reads the IRIC bit.

Objective: Con f irms that the start cond ition is detected from the bus lin e state.

Hardware behavior: If the start condition is detected, the bits IRIC and TDRE are equal to 1.

[17] Setting the slave address + R/W data

Software setting: Writes the slave addr ess + R/W data to the ICDR.

Objective: Starts the data tran sfer.

Hardware behavior: If th e d ata to be transmitted is written to the ICDR in transmission

mode, the TDRE flag is cleared to 0.

[18] Data transfer from the ICDRT to the ICDRS

Hardware behavior: Clears the TDRE flag to 0.

Objective: Transfers data to be transmitted from the ICDRT to the ICDRS.

[19] Clearing the IRIC

Software setting: Clears th e IRIC bit in th e ICCR to 0.

Objective: Judges the termination of the data transmission.

Rev. 2.0, 11/01, page 69 of 358

[20] Termination of one-byte data transmission

Hardware behavior: Sets the IRIC bit in the ICCR to 1 at the rising edge of the ninth

transmission clock.

Objective: The state in which the IRIC bit equals 1 means the end of data

transmission or that bus arbitration has been lost. An interrupt request

is issued to the CPU when the IEIC bit in the I CCR has been set to 1.

[21] Confirmation of the acknowledgment

Software setting: Reads the ACKB b it in the ICSR.

Objective: Confirms the acknowledgment from the slave device.

Hardware behavior: Loads the acknowledgment, returned from the slave device, to the

ACKB bit.

[22] Setting the transmit data

Software setting: Writes the transmit data to the ICDR.

Objective: Starts data tran smission.

Hardware behavior: If th e tran sm it d a ta is written to th e ICDR in transm issio n mode, the

TDRE flag is cleared to 0.

[23] Data transfer from the ICDRT to the ICDRS

Hardware behavior: Clears the TDRE flag to 0.

Objective: Transfers transmit data from the ICDRT to the ICDRS.

[24] Clearing the IRIC

Software setting: Clears th e IRIC bit in th e ICCR to 0.

Objective: Judges the termination of the data transfer.

[25] Termination of one-byte data transfer

Hardware behavior: Sets the IRIC bit in the ICCR to 1 at the rising edge of the ninth

transmission clock.

Objective: The state in which the IRIC bit equals 1 means the end of data

transmission or that bus arbitration has been lost. An interrupt request

is issued to the CPU when the IEIC bit in the I CCR has been set to 1.

[26] Confirmation of the acknowledgment

Software setting: Reads the ACKB b it in the ICSR.

Objective: Confirms the acknowledgment from the slave device.

Hardware behavior: Loads the acknowledgment, returned from the slave device, to the

ACKB bit.

[27] Continuation of the data transmission

Software setting: Repeats procedures [22] to [26].

Objective: Con tinues to transmit data.

Rev. 2.0, 11/01, page 70 of 358

[28] Issuing the stop condition

Software setting: Clears th e bits BBSY and SCP to 0 in ICCR.

Objective: Issues the stop condition.

Note: The MOV instruction must be used to clear the bits BBSY and SCP to

0, because these two bits must be simultaneously set.

Hardware behavior: If the stop cond ition is detected from th e bus line state, the TDRE flag

is cleared to 0. If the bus is released, the BBSY bit is cleared to 0.

2.7.2 Master Reception

In master reception mode using th e I2C bus format, the master device outputs the reception clock,

receives data, and returns an acknowledg m ent. The slave device transmits data. The setting

procedures and operation of the master reception mode are described belo w.

SDA

(Slave output)

SDA

(Master output)

IRIC

RDRF

ICDRS

ICDRR

SCL

(Master output) 19

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6

23456789 12

Data 2

[1] to [21] [22]

[23], [24]

[25] [26]

Data 1

Master transmission mode Master reception mode

Data 1

[27] [29]

to [32]

[28]

Data 1

Figure 2.13 Operation Timing of Master Reception Mode

(for MLS=WAIT=ACKB=0)

Rev. 2.0, 11/01, page 71 of 358

Example of set t ing procedures of mast er t r ansmission mode

[1] Initial setting 1

Software setting: Clears the MSTP4 or MSTP3 bit in the MSTPCRL to 0.

Objective: Cancels the module stop mode of IIC channel 0 or IIC channel 1.

[2] Initial setting 2

Software setting: Sets the IICE bit in the STCR to 1.

Objective: Enables the CPU to access the data register and control register of the I2C

bus interface.

[3] Initial setting 3

Software setting: Sets the DDCSWR.

Objective: Selects enable/d isab le fo r th e automatic switching function b e tween

format-less and I2C bus format in IIC channel 0.

Selects format-less or I2C bus format in IIC channel 0.

Selects enable/disable for interrupt request to the CPU when automatic

switching of the format takes place in IIC channel 0.

[4] Initial setting 4

Software setting: Clears th e ICE bit in th e ICCR to 0.

Objective: Enables access to the SAR and SARX.

[5] Initial setting 5

Software settin g: Sets the SAR and SARX.

Objective: Sets the SW bit in th e DDCSWR, the transfer format, and the slave

address.

Note: Sets the slave address, because slave mode may be set even in master

mode when the system is in multi-master mode.

[6] Initial setting 6

Software setting: Sets the I CE bit in the I CCR to 1.

Objective: Enables access to the ICMR and ICDR.

Puts the I2C module in the transfer-enabled state.

[7] Initial setting 7

Software setting: Sets the ACKB bit in the ICSR.

Objective: Sets the acknowledgment data that is output during data reception.

Note: Be sure to set the ACKB bit, because the mode automatically shifts to

slave reception if bus arbitration is lost even if the device was being used

in master mode.

Rev. 2.0, 11/01, page 72 of 358

[8] Initial setting 8

Software setting: Sets the bits IICX1 or IICX0 in the STCR, and the bits CKS2 to 0 in the

ICMR.

Objective: Selects the transfer clock frequency to be used.

[9] Initial setting 9

Software setting: Sets th e b its MLS and WAIT in the ICMR to 0.

Objective: Sets the MSB-first mode and the no-wait m o d e in data tran sfer.

[10] Initial setting 10

Software setting: Sets the ACKE bit in the ICCR.

Objective: Selects on e of the following two actions:

Transfer data continuously by ignoring the contents of the

acknowledgment bit returned from the reception device in the I2C bus

format.

Perform the error processing by discontinuing the transfer operation

when the acknowledgment bit equ a ls 1.

[11] Initial setting 11

Software setting: Sets the IEIC bit in the IICR.

Objective: Selects enable/d isab le fo r in terrupt request to the CPU from th e I2C bus

interface.

[12] Confirmation of the bus state

Software setting: Reads the BBSY b it.

Objective: Confirms whether the bus is released or in use.

Hardware behavior: If the bus is released, the BBSY bit is equal to 0 .

[13] Setting the master transmission mode

Software setting: Sets the bits MST and TRS in ICCR to 1.

Objective: Sets the op eratio n m ode of th e I2C bus interface to master transmission

mode.

[14] Clearing the IRIC

Software setting: Clears th e IRIC bit in th e ICCR to 0.

Objective: Judges the detection for the start condition.

[15] Setting the start condition

Software setting: Sets the BBSY bit to 1, a nd clears the SCP bit to 0 in ICCR.

Objective: Sets the start co ndition.

Note: The MOV instruction must be used to set the BBSY bit to 1 and clear

the SCP bit to 0, because these two bits must be simultaneously set.

Hardware behavior: The SDA changes from high to low, when the SCL is high.

Rev. 2.0, 11/01, page 73 of 358

[16] Confirmation that the start condition has been satisfied

Software setting: Reads the IRIC bit.

Objective: Con f irms that the start cond ition is detected from the bus lin e state.

Hardware behavior: If the start condition is detected, the bits IRIC and TDRE are equal to 1.

[17] Setting the slave address + R/W data

Software setting: Writes the slave addr ess + R/W data to the ICDR.

Objective: Starts the data tran sfer.

Hardware behavior: If th e tran sm it d a ta is written to th e ICDR in transm issio n mode, the

TDRE flag is cleared to 0.

[18] Data transfer from the ICDRT to the ICDRS

Hardware behavior: Clears the TDRE flag to 0.

Objective: Transfers transmit data from the ICDRT to the ICDRS.

[19] Clearing the IRIC

Software setting: Clears th e IRIC bit in th e ICCR to 0.

Objective: Judges the termination of the data transmission.

[20] Termination of one-byte data transmission

Hardware behavior: Sets the IRIC bit in the ICCR to 1 at the rising edge of the ninth

transmission clock.

Objective: The state in which the IRIC bit equals 1 means the end of data

transmission or that bus arbitration has been lost. An interrupt request

is issued to the CPU when the IEIC bit in the I CCR has been set to 1.

[21] Confirmation of the acknowledgment

Software setting: Reads the ACKB b it in the ICSR.

Objective: Confirms the acknowledgment from the slave device.

Hardware behavior: Loads the acknowledgment, returned from the slave device, to the

ACKB bit.

[22] Setting the master reception mode

Software setting: Clears the TRS bit in the ICCR to 0.

Objective: Switches from master transmission mode to master reception mode

[23] ACKB=0

Software setting: Clears the ACKB bit in the ICSR to 0.

Objective: Outputs 0 at the acknowledgment output timing.

[24] Dummy reading

Software setting: Reads the ICDR.

Objective: Starts the data reception.

Rev. 2.0, 11/01, page 74 of 358

[25] Clearing the IRIC

Software setting: Clears th e IRIC bit in th e ICCR to 0.

Objective: Judges the termination of the data reception.

[26] Termination of one-byte data reception

Hardware behavior: Sets the IRIC bit in the ICCR and the RDRF flag to 1 at the rising edge

of the ninth reception clock.

Objective: The state in which the IRIC bit equals 1 means the end of data transfer.

An interrupt request is issued and sent to the CPU when the IEIC bit

has been set to 1 . Data reception will continue after setting the internal

RDRF flag to 1, when the flag has been cleared to 0.

[27] Reading the received data

Software setting: Reads the ICDR.

Objective: Starts data reception.

Hardware behavior: Clears the RDRF flag to 0.

Note: Sets the ACKB bit to 1 before reading the ICDR when an

acknowledgment is not returned after reception of the last byte.

[28] Clearing the IRIC

Software setting: Clears th e IRIC bit in th e ICCR to 0.

Objective: Judges the termination of the data reception.

[29] Continuation of data reception

Software setting: Repeats procedures [26] to [28].

Objective: Continues to receive data.

[30] Termination of reception

Software setting: Sets the TRS bit in the ICCR to 1.

Objective: To terminate the data reception, sets the TRS b it in the ICCR to 1

before the rise up of the reception clock for the subsequent frame.

Hardware behavior: Sets the TDRE flag to 1.

[31] Reading the last data

Software setting: Reads the ICDR.

Objective: Reads the last byte of the reception data.

[32] Issuing the stop condition

Software setting: Clears th e bits BBSY and SCP to 0 in ICCR.

Objective: Issues the stop condition.

Note: The MOV instruction must be used to clear the bits BBSY and SCP to

0, because these two bits must be simultaneously set.

Hardware behavior: If the stop cond ition is detected from th e bus line state, the TDRE flag

is cleared to 0. If the bus is released, the BBSY bit is cleared to 0.

Rev. 2.0, 11/01, page 75 of 358

2.7.3 Slave Reception

In slave reception mode using the I2C bus format, the master device outputs the transmission clock

and transmission data, and slave devices return acknowledgments.

The setting procedures and operation of the slave reception mode are described below.

SDA

(Slave output)

SDA

(Master output)

IRIC

RDRF

ICDRS

ICDRR

SCL

(Master output)

SCL

(Slave output)

123456789 12

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6

Slave address

[13]

[14]

R/W

[15]

Slave address

+ R/W

Slave address

+ R/W

[17]

[16] [18] to [22]

[1] to [12]

Data 1

Figure 2.14 Operation Timing of Slave Reception Mode (for MLS=ACKB=0)

Example of setting procedures of the slave reception mode

[1] Initial setting 1

Software setting: Clears the MSTP4 or MSTP3 bit in the MSTPCRL to 0.

Objective: Cancels the module stop mode of IIC channel 0 or IIC channel 1.

[2] Initial setting 2

Software setting: Sets the IICE bit in the STCR to 1.

Objective: Enables the CPU to access the data register and control register of the I2C

bus interface.

Rev. 2.0, 11/01, page 76 of 358

[3] Initial setting 3

Software setting: Sets the DDCSWR.

Objective: Selects enable/d isab le fo r th e automatic switching function b e tween

format-less and I2C bus format in IIC channel 0.

Selects format-less or I2C bus format in IIC channel 0.

Selects enable/disable for interrupt request to the CPU when automatic

switching of the format takes place in IIC channel 0.

[4] Initial setting 4

Software setting: Clears th e ICE bit in th e ICCR to 0.

Objective: Enables access to the SAR and SARX.

[5] Initial setting 5

Software settin g: Sets the SAR and SARX.

Objective: Sets the SW bit in th e DDCSWR, the transfer format, and the slave

address.

[6] Initial setting 6

Software setting: Sets the I CE bit in the I CCR to 1.

Objective: Enables access to the ICMR and ICDR.

Puts the I2C module in the transfer-enabled state.

[7] Initial setting 7

Software setting: Sets the ACKB bit in the ICSR.

Objective: Sets the acknowledgment data that is output during data reception.

Note: Be sure to set the ACKB bit, because the mode automatically shifts to

slave reception if bus arbitration is lost even if the device was being used

in master mode.

[8] Initial setting 8

Software setting: Sets the bits IICX1 or IICX0 in the STCR, and the bits CKS2 to 0 in the

ICMR.

Objective: Selects the transfer clock frequency to be used.

[9] Initial setting 9

Software setting: Sets th e b its MLS and WAIT in the ICMR to 0.

Objective: Sets the MSB-first mode and the no-wait m o d e in data tran sfer.

[10] Initial setting 10

Software setting: Sets the ACKE bit in the ICCR.

Objective: Selects on e of the following two actions:

Transfer data continuously by ignoring the contents of the

acknowledgment bit returned from the reception device in the I2C bus

format.

Perform the error processing by discontinuing the transfer operation

when the acknowledgment bit equ a ls 1.

Rev. 2.0, 11/01, page 77 of 358

[11] Initial setting 11

Software setting: Sets the IEIC bit in the IICR.

Objective: Selects enable/d isab le fo r in terrupt request to the CPU from th e I2C bus

interface.

[12] Initial setting 12

Software setting: Sets the bits MST and TRS to 0.

Objective: Sets the slave reception mode.

[13] Detecting the start condition

Hardware behavior: Sets the BBSY bit in the ICCR to 1.

Objective: Detects the start condition issued by the master device.

[14] Reception of the slave address

Hardware behavior: Clears the TRS bit in the ICCR to 0.

Objective: Acts as the slave device that is specified by the master device when the

slave address has been matched at the first frame after the starting

condition. When the eigh th da ta (R/W) is equal to 0, the TRS bit in the

ICCR remains 0 (unchanged), and slave reception operation takes

place.

[15] Matching the slave address

Hardware behavior: The slave device sets the SDA to low and returns an acknowledgment

at the ninth clock of the reception frame. The slave device

simultan e ously sets the IRIC bit in the ICCR and the RDRF flag to 1.

Objective: The state in which the IRIC bit equals 1 means the ma tching of the

slave address. An interrupt request is issued to the CPU when the IEIC

bit in the ICCR has be e n set to 1.

[16] Dummy reading

Software setting: Reads the ICDR (dummy reading).

Objective: Starts the data reception.

[17] Clearing the IRIC

Software setting: Clears th e IRIC bit in th e ICCR to 0.

Objective: Judges the termination of the data reception.

[18] Termination of data reception

Hardware behavior: The slave device sets the SDA to low and returns an acknowledgment

at the ninth clock of the reception frame. The slave device

simultan e ously sets the IRIC bit in the ICCR and the RDRF flag to 1.

Objective: The state in which the IRIC bit equals 1 means the termination of the

data transfer. An interrupt request is issued and sen t to th e CPU when

the IEIC bit in the ICCR has been se t to 1.

Rev. 2.0, 11/01, page 78 of 358

[19] Reading the received data

Software setting: Reads the ICDR.

Objective: Reads the received data.

Hardware behavior: Clears the RDRF flag to 0 by reading the received data in the ICDR

(ICDRR).

[20] Clearing the IRIC

Software setting: Clears th e IRIC bit in th e ICCR to 0.

Objective: Judges the termination of the data reception.

[21] Continuation of the data reception

Software setting: Repeats procedures [18] to [20].

Objective: Continues to receive data.

[22] Termination of reception

Hardware behavior: The SDA changes from low to high when the SCL is high. Clears the

BBSY bit in the ICCR to 0 .

Objective: Detects the stop condition issued by the master device.

2.7.4 Slave Transmission

In slave transmission mode using the I2C bus format, a slave device outputs the transmission data.

The master device outputs the reception clock and returns acknowledgment. The setting

procedures and operation of the slave transmission mode are described below.

Rev. 2.0, 11/01, page 79 of 358

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6

Data 2

Slave reception mode Slave transmission mode

Data 2Data 1

Data 1

[14]

[1] to [13] [24]

to [26]

[15]

[16] [18]

[17]

[19]

[20]

[21] [22]

[23]

Data 1

SDA

(Slave output)

SDA

(Master output)

IRIC

TDRE

ICDRT

ICDRS

SCL

(Master output)

SCL

(Slave output)

19 23456789 12

Data 2

Figure 2.15 Operation Timing of Slave Transmission Mode (for MLS=0)

Example of setting procedures of the slave transmission mode

[1] Initial setting 1

Software setting: Clears the MSTP4 or MSTP3 bit in the MSTPCRL to 0.

Objective: Cancels the module stop mode of IIC channel 0 or IIC channel 1.

[2] Initial setting 2

Software setting: Sets the IICE bit in the STCR to 1.

Objective: Enables the CPU to access the data register and control register of the I2C

bus interface.

[3] Initial setting 3

Software setting: Sets the DDCSWR.

Objective: Selects enable/d isab le fo r th e automatic switching function b e tween

format-less and I2C bus format in IIC channel 0.

Selects format-less or I2C bus format in IIC channel 0.

Selects enable/disable for interrupt request to the CPU when the

automatic switching of the format takes place in IIC channel 0.

Rev. 2.0, 11/01, page 80 of 358

[4] Initial setting 4

Software setting: Clears th e ICE bit in th e ICCR to 0.

Objective: Enables access to the SAR and SARX.

[5] Initial setting 5

Software settin g: Sets the SAR and SARX.

Objective: Sets the SW bit in th e DDCSWR, the transfer format, and the slave

address.

[6] Initial setting 6

Software setting: Sets the I CE bit in the I CCR to 1.

Objective: Enables access to the ICMR and ICDR.

Puts the I2C module in the transfer-enabled state.

[7] Initial setting 7

Software setting: Sets the ACKB bit in the ICSR.

Objective: Sets the acknowledgment data that is output during data reception.

Note: Be sure to set the ACKB bit, because the mode automatically shifts to

slave reception if bus arbitration is lost even if the device was being used

in master mode.

[8] Initial setting 8

Software setting: Sets the bits IICX1 or IICX0 in the STCR, and the bits CKS2 to 0 in the

ICMR.

Objective: Selects the transfer clock frequency to be used.

[9] Initial setting 9

Software setting: Sets th e b its MLS and WAIT in the ICMR to 0.

Objective: Sets the MSB-first mode and the no-wait m o d e in data tran sfer.

[10] Initial setting 10

Software setting: Sets the ACKE bit in the ICCR.

Objective: Selects on e of the following two actions:

Transfer data continuously by ignoring the contents of the

acknowledgment bit returned from the reception device in the I2C bus

format.

Perform the error processing by discontinuing the transfer operation

when the acknowledgment bit equ a ls 1.

[11] Initial setting 11

Software setting: Sets the IEIC bit in the IICR.

Objective: Selects enable/d isab le fo r in terrupt request to the CPU from th e I2C bus

interface.

Rev. 2.0, 11/01, page 81 of 358

[12] Initial setting 12

Software setting: Sets the bits MST and TRS to 0.

Objective: Sets the slave reception mode.

[13] Detecting the start condition

Hardware behavior: Sets the BBSY bit in the ICCR to 1.

Objective: Detects the start condition issued by the master device.

[14] Reception of the slave address

Hardware behavior: Clears the TRS bit in the ICCR to 0, and sets the TDRE flag to 1.

Objective: Acts as the slave device that is specified by the master device when the

slave address has been matched at the first frame after the starting

condition. When the eigh th da ta (R/W) equals 1, sets the TRS b it in the

ICCR to 1, and automatically change s to slave transmission mode.

[15] Matching the slave address

Hardware behavior: The slave device sets the SDA to low and returns an acknowledgment

at the ninth clock of the reception frame. The slave device

simultan e ously sets the IRIC bit in the ICCR to 1. The sla ve dev ic e

fixes the SCL to low during the period from the falling edge of the

transmission clock to the start o f writing data to the ICDR.

Objective: The state in which the IRIC bit equals 1 means the ma tching of the

slave address. An interrupt request is issued and sent to the CPU when

the IEIC bit in the ICCR has been se t to 1.

[16] Clearing the IRIC

Software setting: Clears th e IRIC bit in th e ICCR to 0.

Objective: Judges the data transfer from the ICDRT to the ICDRS.

[17] Writing the first byte of the transmission data

Software setting: Writes the first byte of the transmission data to the ICDR.

Objective: Starts the d ata transmission.

Hardware behavior: Clears the TDRE flag to 0.

[18] Data transfer from the ICDRT to the ICDRS

Hardware behavior: Sets the TDRE fla g, the IRIC b it in the ICCR, and the IRTR in the

ICSR to 1.

Objective: Transfers th e data written in the ICDRT to th e ICDRS.

[19] Clearing the IRIC

Software setting: Clears th e IRIC bit in th e ICCR to 0.

Objective: Judges the termination of the data transmission.

Rev. 2.0, 11/01, page 82 of 358

[20] Writing the transmission data

Software setting: Writes the transmis sion data to th e ICDR.

Objective: Starts the d ata transmission.

Hardware behavior: Clears the TDRE flag to 0.

[21] Termination of transmission

Hardware behavior: After one-frame data transmission ended, sets the IRIC bit in the ICCR

to 1 at the rising edge of the ninth transmission clock. The slave device

receives an acknowledgment from the master device, and stores it in

the ACKB bit. The slave device automa tically fixes the SCL to lo w

during the period from the falling edge of the ninth transmission clock

to the start of writin g data to the ICDR.

Objective: The state in which the IRIC bit equals 1 means the end of a data

transfer. An interrupt request is issued an d sent to the CPU when the

IEIC bit in the ICCR h as been se t to 1. Th e acknowledgment from the

master device can be confirmed by reading the ACKB bit.

[22] Clearing the IRIC

Software setting: Clears th e IRIC bit in th e ICCR to 0.

Objective: Judges the termination of the data transmission.

[23] Writing the transmission data

Software setting: Writes the transmis sion data to th e ICDR.

Objective: The slave device releases the SCL and allows it to go high, and starts

the data transmission.

[24] Continuation of the data transmission

Software setting: Repeats procedures [21] to [23].

Objective: Con tinues to transmit data.

[25] Termination of transmission

Software setting: Clears the TRS bit in the ICCR to 0, and reads the ICDR (dummy

reading).

Objective: Sets the slave reception mode by clearing the TRS bit to 0. Releases the

SCL line by the dummy reading of the ICDR.

[26] Detecting the stop condition

Hardware behavior: The SDA changes from low to high when the SCL is high. Clears the

BBSY bit in the ICCR to 0 .

Objective: Detects the stop condition issued by the master device.

Rev. 2.0, 11/01, page 83 of 358

Section 3 Examples of Application to the H8/300 and

H8/300L Series

3.1 System Specifications

The system specifications are described belo w. Figure 3.1 illustrates the system configuration.

• The system has a m ulti-master configu r ation comprising two masters and one slav e. The

H8/3434F, which has an on-chip flash memory, is used as a device.

• The 8-segment LED displays on its screen: ‘CPU1’ when switch-1 (SW1: master-1 side) is

pressed and ‘CPU2’ when switch-2 (SW2: master-2 side) is pressed.

(1) Master-1 sends H'01 to the slave when switch-1 is pressed, and the master-2 sends H'02

when the switch-2 is pressed.

(2) The slave distinguishes the received data and displays on the screen of the 8-segment

LED: ‘CPU1’ when the data is H'01 and ‘CPU2’ when the data is H'02.

• The transfer rate of the I2C bus is 200 kbps.

Rev. 2.0, 11/01, page 84 of 358

SW1 Master-1

H8/3434F

SW2 Master-2

Slave

LED display

SCL

SDA

C bus

H8/3434F

Figure 3.1 System for Evaluating the Multi-Master configuration

• In the on-chip I2C bus interf ace of the H8/300 and H8/300L series, the adjustment procedures

shown in figure 3.2 are performed as well as the communication adjustment procedures

described in “1.4 Procedure for Communication Adjustment”. Each master device monitors the

bus line at the fallin g edge of the SCL line, and switch e s off its output gates if the monitored

level does not coincide with its own level.

Rev. 2.0, 11/01, page 85 of 358

The bus signals that each

master is going to output Start condition

SDA1

SCL1

SDA2

SCL2

SDA

SCL

Obtains the bus authority.

Switches off its output gates

because the SCL line is high.

Master-1Master-2Bus line

Figure 3.2 How to detect the bus arbitration

• When master-1 and master-2 start data transmissio n simultaneo usly (multi-master op eration)

(1) When a collision is detected, master-1 obtains the bus au thority, because the period when

the SDA line (data line) is low is longer for master-1 (transmitted data is H'01) than for

master-2 (transmitted da ta is H'0 2). Refer to figure 3.3.

Rev. 2.0, 11/01, page 86 of 358

SCL 1

H'01

(a) Master-1

H'02

(b) Master-2

··· 0010

···

789··· 1 2 7 8 9···

SDA

SCL

SDA

Figure 3.3 Why master-1 obtains the bus authority

(2) Master-2 loses the bus arbitration and automatically transits to slave reception mode. To

use master-2 in master transm ission mode again, the sy stem must perform a reset. The

data that was no t tran smitted must be written to the ICDR again. This sy stem, therefore,

calls the data transmission routine again regardless of the switch input, after confirming

the bus arbitration loss of master-2.

Rev. 2.0, 11/01, page 87 of 358

3.2 Circuit for Multi-Master Evaluation System

Figure 3.4 illustrates the circuit diagram for evaluating a multi-master system that has the mu lti-

master configuration.

Circuit for reset

Master-2 Master-1 Vcc

Vcc

P60

Vss

SCL

SDA SW1

Vcc Vcc Vcc Vcc Vcc

H8/3434F

Slave 8-segment LED

H8/3434F

Vcc

P60

Vss

SCL

SDA

H8/3434F

SW2

Vcc

P20

Vss

P27

P10

P11

P12

P13

SCL

SDA

Figure 3.4 Circuit diagram of the system for performing a simple evaluation of the I2C bus

Rev. 2.0, 11/01, page 88 of 358

3.3 Design of Software

3.3.1 Description of Modules

This section presen ts an example of the software of the system that h as the multi-master

configuration. The divided program modules and their functions are listed in table 3.1.

Table 3.1 Description of modules

Module name Label name Functions

Master main program Main (1) Initial setting (stack pointer, I2C bus interface, and 8-

bit timer)

(2) Enables interruption

(3) Watches the switch and calls the master subroutine

Key scanning program

(interruption program) Compare Reads the bit of I/O port 6 every 8 ms using the

compare-match interruption for the 8-bit timer.

Data transmitting program Master Watches the bus and transmits the data

Slave main program _Main (1) Initial setting (stack pointer, I2C bus interface, and 8-

bit timer)

(2) Enables interruption

(3) Calls the slave subroutine

Program to display data on

the 8-segment LED _Display Displays data on the 8-segment LED.

Data receiving program

(interruption program) _Receive Receives data to make a decision.

3.3.2 Master

(1) Description of internal registers used by the master

Table 3.2 Description of internal registers use d by the master

Registers Functions Names of modules

using the registers

STCR Selects the input clock for the 8-bit timer.

ICCR Enables the I2C bus interfa ce.

Sets for interruptions.

Selects the communication mode.

Selects the acknowledgment mode.

Selects the frequency of the input clock.

Data transmitting

program

Rev. 2.0, 11/01, page 89 of 358

Registers Functions Names of modules

using the registers

ICSR Issu es starting/stopping con diti on s.

Recogniz es and con trol s the ackn ow led gm ent.

ICDR Stores the transmission/reception data.

ICMR Selects MSB-first or LSB-first.

SAR Stores the slave addres s and sele cts the form at.

TCR Selects the clock input.

Selects the condition for clearing the counter.

Enables compare-m at ch interru pt ion A.

TCSR Clears the flag for the compare-match.

TCORA Sets the time for the compare-match.

P6DR Switches input port.

P6DDR Sets the port mode.

Main program

(2) Description of the general-purpose registers used by the master

Table 3.3 Description of the general-purpose registers used by the master

Registers Functions Names of module

using the registers

R1L,R2L Working registers Main program

R3L Stores the transmission data temporarily. Data transmitting

program

R5L Counts the bytes of transmitted data. Data transmitting

program

CCR Checks the interruption flags. Main program

(3) Description of the RAM used by the master

Table 3.4 Description of the RAM used by the master

Registers Functions Data length Names of modules using the

registers

Switch Counts the jitter. 1 byte Key scanning program

(interruption program)

Rev. 2.0, 11/01, page 90 of 358

(4) Description of the ROM used by the master

Table 3.5 Description of the ROM used by the master

Label

names Functions Data length Names of modules using the

registers

Table Stores the transmission data. 2 bytes Data transmitting program

3.3.3 Slave

(1) Description of internal registers used by the slave

Table 3.6 Description of internal registers use d by the slave

Registers Functions Names of module

using the registers

STCR Selects the input clock for the 8-bit timer.

ICCR Enables the I2C bus interfa ce.

Sets for interruptions.

Selects the communication mode.

Selects the acknowledgment mode.

Selects the frequency of the input clock.

Main program

ICSR Watch es the data transmission/recept ion and che ck s

whether or not an interruption occurred.

ICDR Stores the transmission/reception data.

ICMR Selects MSB-first or LSB-first.

SAR Stores the slave addres s and sele cts the form at.

Data receiving

program (interruption

program)

TCR Selects the clock input.

Selects the clearing condition for the counter (clears the

counter by compare-match interruption A).

TCSR Checks the state of the flag for the compare-match.

TCORA Sets the time for compare-match A.

TCORB Sets the time for compare-match B.

P1DDR Sets the mode for port 1.

Main program

P1DR Digit data of the 8-segment LED Program for displaying

data on the 8-segment

LED

P2DDR Sets the mode for port 2. Main program

P2DR Segment data of the 8-segment LED Program for displaying

data on the 8-segment

LED

Rev. 2.0, 11/01, page 91 of 358

(2) Description of the general-purpose registers used by the slave

Table 3.7 Description of the general-purpose registers used by the slave

Registers Functions Names of module

using the registers

R1L Working register Main program

R1L Working register

R6 Temporary area for exchanging the data

Program for displaying

data on the 8-segment

LED

R1L Working register

R4 Sets the data table.

Data receiving

program (interruption

program)

CCR Checks the interruption flags. Main program

(3) Description of the RAM used by the slave

Table 3.8 Description of the RAM used by the slave

Label

names Functions Data length Names of module using the

registers

_TABLE Stores the start ing address of the

data table. 1 word Data receiving program

(interruption program)

_Count Manages the display time for the

LED. 1 byte

_Count2 Manages the display time for the

LED. 1 byte

_D_DATA Initial value of the digit data 1 byte

Program for displaying data on

the 8-segment LED

_First Stores the first byte of the reception

data. 1 byte

_Second Stores the second byte of the

reception data. 1 byte

Data receiving program

(interruption program)

(4) Description of the ROM used by the slave

Table 3.9 Description of the ROM used by the slave

Label

names Functions Data length Names of module using the

registers

_Table1 Stores the data for 8-segment. 1 byte

_Table2 Stores the data for 8-segment. 1 byte

_Table3 Stores the data for 8-segment. 1 byte

_Table4 Stores the data for 8-segment. 1 byte

Data receiving program

(interruption program)

Rev. 2.0, 11/01, page 92 of 358

3.4 Flowcharts

3.4.1 Master Program

(1) Main Program

Main

Initial setting

Set the TCNT to 0 and start the

8-bit timer

Check the switch flag

Disable the compare-match interruption

Data transmitting program (master)

Enable the compare-match interruption

Clear the switch flag

Switch 3 ?

Yes

Initial setting

Set the interruption vector

Reserve the variable region

Set the stack pointer

Initialize the I

C bus interface

Initialize the 8-bit timer

Initialize the I/O ports

Enable the interruptions

Rev. 2.0, 11/01, page 93 of 358

(2) Ke y scanning program (interruption program)

Compare

RTE

Store the contents of the working registers

Clear the CMFA

Read the I/O port P6o

Increment the switch counter (Switch)

Recover the contents of the working registers

Yes

P6o = 0 ?

Read the state of the key switch.

Clear the switch counter (Switch)

Rev. 2.0, 11/01, page 94 of 358

(3) Data transmitting program

Master

Read the BBSY bit in the ICSR

Set the bits MST and TRS in the ICCR to 1

Write 1 to the BBSY bit, and 0

to the SCP bit in the ICSR

Write the transmission data to the ICDR

Read the IRIC bit in the ICSR

Clear the IRIC bit in the ICSR

Read the AL bit in the ICSR

Read the ACKB bit in the ICSR

Write 0 to the bits BBSY and SCP

in the ICSR

IRIC = 1 ?

AL = 0 ?

ACKB = 0 ?

RTS

BBSY = 0 ?

Yes

Is the bus free?

Set the master transmission mode.

Set the start condition.

Wait for the termination of the

master transmission.

Bus arbitration lost?

Did an acknowledgment return?

Issue the stop condition.

Yes

Rev. 2.0, 11/01, page 95 of 358

3.4.2 Slave Program

(1) Main Program

_Main

Initial setting

Program for displaying data on the 8-segment LED

Initial setting

Set the interruption vector

Reserve the variable region

Set the stack pointer

Initialize the I

C bus interface

Initialize the 8-bit timer

Initialize the I/O ports

Enable the interruptions

Set the data table (_Table) for the 8-segment LED to 000

Rev. 2.0, 11/01, page 96 of 358

(2) Program for displaying data on the 8-segment LED

_Display

RTS

CMFB = 1 ?

CMFA = 1 ?

Is the digit data

H'00?

COUNT = 500 ?

Yes

Set the data table for the 8-segment LED

Clear the COUNT to 0

Set the first digit (H'01)

Clear the CMFB

Clear the CMFA

Increment the COUNT

Output the digit data to the I/O port

Output the segment data to the I/O port

Shift the digit data and

set the next segment data

Set the digit data to 0 and

output it to the I/O port

Adjust the display time.

Is compare-match A?

Is compare-match B?

Rev. 2.0, 11/01, page 97 of 358

(3) Data receiving program

_Receive

RTS

IRIC = 1 ?

_Second = H'01 ?

_Second = H'02 ?

Yes

Store the contents of the working registers

Set the bits MST and TRS in the ICCR to 0

Read the ICDR

Clear the IRIC bit in the ICSR

Set the ACKB bit in the ICSR to 1

Read the IRIC bit in the ICSR

Clear the IRIC bit in the ICSR

Set the data table to "E---" (_Table3)

Recover the contents of the working registers

Read the ICDR

_Second = ICDR

Read the second byte.

Wait for reception of the second byte.

Set the ACKB bit so that

an acknowledgment will not return.

Read the first byte.

(dummy reading)

Set the slave reception mode.

Set the data table to

"CPU1" (_Table1)

Set the data table to

"CPU2" (_Table2)

Rev. 2.0, 11/01, page 98 of 358

3.5 Program Listings

3.5.1 Master Program

.cpu 300

.output dbg

;********************************************************************************************

; Master program of the evaluation system for the I2C bus

; Key scanning

; Data transmission

;********************************************************************************************

;******************************************************************

; Vector addresses

;******************************************************************

.section VECT,CODE,LOCATE=H'0000

Res .DATA.W Main

.ORG H'0006

NMI .DATA.W Main

IRQ0 .DATA.W Main

IRQ1 .DATA.W Main

IRQ2 .DATA.W Main

IRQ3 .DATA.W Main

IRQ4 .DATA.W Main

IRQ5 .DATA.W Main

IRQ6 .DATA.W Main

IRQ7 .DATA.W Main

ICIA .DATA.W Main

ICIB .DATA.W Main

ICIC .DATA.W Main

ICID .DATA.W Main

OCIA .DATA.W Main

OCIB .DATA.W Main

FOVI .DATA.W Main

Rev. 2.0, 11/01, page 99 of 358

CMI0A .DATA.W Compare

CMI0B .DATA.W Main

OVI0 .DATA.W Main

CMI1A .DATA.W Main

CMI1B .DATA.W Main

OVI1 .DATA.W Main

MREI .DATA.W Main

MWEI .DATA.W Main

ERI .DATA.W Main

RXI .DATA.W Main

TXI .DATA.W Main

RDI .DATA.W Main

;

;******************************************************************

; Definitions of the various interfaces

;******************************************************************

;-------------------------------------------------

; Definition of the I2C bus regi sters

;-------------------------------------------------

_STCR .EQU H'FFC3 ; Serial timer control register

_ICCR .EQU H'FFD8 ; I2C bus contro l regist er

_ICSR .EQU H'FFD9 ; I2C bus state re gister

_ICDR .EQU H'FFDE ; I2C bus data register

_ICMR .EQU H'FFDF ; I2C bus mode register

_SAR .EQU H' FFDF ; Sl av e-addr ess regi ster

;-------------------------------------------------

; Definition of the I/O registers

;-------------------------------------------------

_KMPCR .EQU H'FFF2 ; Port 6 input pull-u p MOS control

; register

_P6DDR .EQU H'FFB9 ; Data-direction register

_P6DR .EQU H'FFBB ; Data register (connects the switch)

;-------------------------------------------------

; Definition of the 8-bit timer register

;-------------------------------------------------

Rev. 2.0, 11/01, page 100 of 358

_TCR .EQU H'FFC8

_TCSR .EQU H'FFC9

_TCORA .EQU H'FFCA

_TCORB .EQU H' FF CB ; Unused

_TCNT .EQU H'FFCC

;-------------------------------------------------

; Definition of the variables in RAM variables

;-------------------------------------------------

.section RAM,DATA,LOCATE=H'FB80

_Switch .R ES 1 ; Variable to de signat e the swit ch's state

;******************************************************************

; Start of the main program

;******************************************************************

.section program,data,locate=H'1000

Main MOV.W #H'FEF E, SP ; Set the stack po inter.

;-------------------------------------------------

; Initialization of the I2C bu s regist ers

;-------------------------------------------------

MOV.B #H'10,R1L

MOV.B R1L,@_STCR ; IICE = 1

MOV.B #H'B4,R1L

MOV.B R1L,@_ICCR ; ICE = 1,MS T = 1, TRS = 1

; Set the transfer clock to 200 bps.

;-------------------------------------------------

; Initialization of the I/O registers

;-------------------------------------------------

MOV.B #H'00,R1L

MOV.B R1L,@_P6DDR

MOV.B #H'00,R1L

MOV.B R1L,@_KMPCR

Rev. 2.0, 11/01, page 101 of 358

;-------------------------------------------------

; Initialization of the 8-bit timer register

;-------------------------------------------------

MOV.B #H'4B,R1L

MOV.B R1L,@_TCR

MOV.B #H'7D,R1L

MOV.B R1L,@_TCORAe

;-------------------------------------------------

; Initialization of the switch counter

;-------------------------------------------------

MOV.B #H'00,R1L

MOV.B R1L,@_Switch ; Initialize the switch counter to 0.

MOV.B #H'00,R1L ; Reset the internal 8-bit counter to 0.

MOV.B R1L,@_TCNT ; Start co un ting.

ANDC #H'7F,CCR ; Clea r th e interr upt flag .

;-------------------------------------------------

; Judgement of the switch's state, ON or OFF

;-------------------------------------------------

MOV.B #H'03,R2L

SwOn MOV.B @_Switch,R1L

CMP.B R2L,R1L

BLT SwOn

MOV.B #H'00,R1L

MOV.B R1L,@_ Switch ; Clear th e switch cou nter.

;-------------------------------------------------

; Data transmission

;-------------------------------------------------

MOV.B #H'0B,R1L

MOV.B R1L,@_TCR ; Disable the CMPA interrupt.

JSR @Master ; Jump to the data-transmission program.

Rev. 2.0, 11/01, page 102 of 358

MOV.B #H'4B,R1L

MOV.B R1L,@_TCR ; Enable the CMFA interrupt.

BRA SwOn

;-------------------------------------------------

; Key-scanning routine (interrupt routine)

;-------------------------------------------------

Compare .EQU $

PUSH R1

BCLR #6,@_TCSR ; Clear the CMFA bit.

BTST #0,@_P6DR ; Check the switch flag.

BNE Off ; Clear the switch counter.

MOV.B @_Switch,R1L ; When the switch is off

INC R1L ; Increment the switch counter.

MOV.B R1L,@_Switch

BRA Clear

Off MOV.B #H'00,R1L ; When the switch is off

MOV.B R1L,@_ Switch ; Clear th e switch cou nter.

Clear POP R1

RTE ; Return from the key-scanning routine.

.include "maste r. asm" ; Combin e th e files.

;-------------------------------------------------

; Set the initial value to the ROM

;-------------------------------------------------

_Table .DATA.B H'EE ; The slave addr ess (=H' 77 ) and the R/ W bit

; (=H'0) > B'111011 10

.DATA.B H'01 ; The data to distinguish this master (master

; 2 is H'02)

Rev. 2.0, 11/01, page 103 of 358

.END

;********************************************************************************************

; Data-trans missio n pr ogram fo r the mast er

; The first byte is the slave's address.

; The second byte is the data that distinguishes this master.

;********************************************************************************************

Master BTST #7,@_ICSR ; Is the I2C bus free ?

BNE Master

BSET #5,@_ICCR ; Set th e ma ster-t ransmi ssion mo de.

BSET #4,@_ICCR ;(MS T = 0, TRS = 0)

MOV.B #H'90, R1L ; Issue th e st art cond ition fo r

; transmissi on.

MOV.B R1L,@_ICSR ; ICSR : 1001 0000

MOV.B #H'00,R5L

Transmit MOV.B @(_Table,R5),R3L ; Write the first byte (the sla ve address)

; and the second byte (the data that

; distinguis hes the ma st er).

MOV.B R3L,@_ICDR

INC R5L

ChkIRIC1 BTST #6,@_ICSR

BEQ ChkIRIC1 ; IRIC = 1? (transmission completed?)

BCLR #6,@_ICSR ; Clear the IRIC bit for the subsequent

; transmissi on.

BTST #3,@_ICSR ; AL = 0?

BNE Master

BTST #0,@_ICSR ; ACKB = 0?

BEQ Transmit

Rev. 2.0, 11/01, page 104 of 358

MOV.B #H'10,R1L ; Issue the stop condition for transmission

MOV.B R 1L,@_ICS ; ICSR : 0001 000 0

RTS ; Return subroutine

Rev. 2.0, 11/01, page 105 of 358

3.5.2 Slave Program

.cpu 300

.output dbg

;********************************************************************************************

; Slave program of the evaluation system for the I2C bus

; (1) LED displa y

; (2) Data reception

;********************************************************************************************

;******************************************************************

; Definition of the on-chip registers

;******************************************************************

_STCR .EQU H'FFC3 ; Serial timer control register

_ICCR .EQU H'FFD8 ; I2C bus contro l regist er

_ICSR .EQU H'FFD9 ; I2C bus state re gister

_ICDR .EQU H'FFDE ; I2C bus data register

_ICMR .EQU H'FFDF ; I2C mode register

_SAR .EQU H' FFDF ; Sl av e-addr ess regi ster

_TCR .EQU H' FFC8 ; Ti me r contro l regist er

_TCSR .EQU H'FFC9 ; Ti me r contro l/stat e regist er

_TCORA .EQU H'FFCA ; Time constant register

_TCORB .EQU H'FFCB ; Time constant register

_P1DDR .EQU H'FFB0 ; Port 1 data-direction register

_P2DDR .EQU H'FFB1 ; Port 2 data-direction register

_P1DR .EQU H'FFB2 ; Port 1 data register

_P2DR .EQU H'FFB3 ; Port 2 data register

.section VECT,CODE,LOCATE=H'0000

;********************************************************************************************

; Vector Address

;********************************************************************************************

Res .DATA.W _Main

.ORG H'0006

NMI .DATA.W _Main

IRQ0 .DATA.W _Main

IRQ1 .DATA.W _Main

IRQ2 .DATA.W _Main

Rev. 2.0, 11/01, page 106 of 358

IRQ3 .DATA.W _Main

IRQ4 .DATA.W _Main

IRQ5 .DATA.W _Main

IRQ6 .DATA.W _Main

IRQ7 .DATA.W _Main

ICIA .DATA.W _Main

ICIB .DATA.W _Main

ICIC .DATA.W _Main

ICID .DATA.W _Main

OCIA .DATA.W _Main

OCIB .DATA.W _Main

FOVI .DATA.W _Main

CMI0A .DATA.W _Main

CMI0B .DATA.W _Main

OVI0 .DATA.W _Main

CMI1A .DATA.W _Main

CMI1B .DATA.W _Main

OVI1 .DATA.W _Main

IBF1 .DATA.W _Main

IBF2 .DATA.W _Main

ERI0 .DATA.W _Main

RXI0 .DATA.W _Main

TXI0 .DATA.W _Main

TEI0 .DATA.W _Main

ERI1 .DATA.W _Main

RXI1 .DATA.W _Main

TXI1 .DATA.W _Main

TEI1 .DATA.W _Main

ADI .DATA.W _Main

WOVF .DATA.W _Main

IICI .DATA.W _Receive

.SECTION RAM,DATA,LOCATE=H'FB80

;-------------------------------------------------

; Initialization of the RAM area

;-------------------------------------------------

_TABLE .RES.W 1 ; H'FB80<- The place to store the received

Rev. 2.0, 11/01, page 107 of 358

; data

_Count .RES.B 1 ; H'FB82<- The time period for illuminating

; the LED

_Count2 .RES.B 1 ; H'FB83<- The time period for illuminating

; the LED

_D_DATA .RES.B 1 ; H'FB84<- Keep the digit data here.

_First .RES.B 1 ; H'FB85<- Data for transmission 1

_Second .RES.B 1 ; H'FB86<- Data for transmission 2

.SECTION PROGRAM,CODE,LOCATE=H'1000

;******************************************************************

; Start of the main program

;******************************************************************

_Main MOV.W #H'FEFE, SP ; Set the st ack poin ter.

; Settings for the program to use in

;-------------------------------------------------------------------

; Settings for the program to use in displaying data on the LED

;-------------------------------------------------------------------

MOV.B #H'0A,R1L ; Set the condition for clearing the counter.

MOV.B R1L,@_TCR

MOV.B #H'F0, R1L ; Compar e- match B

MOV.B R1L,@_TCORB

MOV.B #H'FF, R1L ; Compar e- match A

MOV.B R1L,@_TCORA

MOV.B #H'FF,R1L

MOV.B R1L,@_P1DDR ; All pins are outputs.

MOV.B R1L,@_P2DDR ; All pins are outputs.

;-------------------------------------------------------------------

; Initialization of the I2C bu s interf ace regi sters

;-------------------------------------------------------------------

MOV.B #H'11,R1L ; IICE = 1

MOV.B R1L,@_STCR ; 0001 0001

Rev. 2.0, 11/01, page 108 of 358

MOV.B #H'EE,R1L

MOV.B R1L,@_ SAR ; Set the sl av e addres s.

MOV.B #H'C4,R1L ; ICE = 1,IEIC = 1, Transfer clock : 400 MHz

MOV.B R1L,@_ICCR ; B'1100 0100

;-------------------------------------------------------------------

; Cancellation of the interruption mask

;-------------------------------------------------------------------

ANDC #H'7F,CCR

;-------------------------------------------------------------------

; Swapping the data tables

;-------------------------------------------------------------------

MOV.W #_Table4,R0

MOV.W R0,@_TABLE

LOOP JSR @_Display ; Jump to the routine for displaying data on

; the LED.

BRA LOOP

;******************************************************************

; Subroutine for displaying data on the LED

;******************************************************************

_Display MOV.W @_TABLE,R6 ; Exchanging the data tables.

MOV.B R1L,@_Count2 ; Count2 = 0

MORE2 MOV.B #H'00,R1L

MOV.B R1L,@_ Count ; Count = 0

MORE1 MOV.W @_TABLE,R6 ; Set the starting address of the data table.

MOV.B #H'08,R1L

MOV.B R1L,@_ D_DATA ; Set the di git data , H' 01.

NEXT1 MOV.B @_D_DATA,R1L

NOT R1L

MOV.B R1L,@_P1DR ; Output the digit data.

MOV.B @R6,R1L

MOV.B R1L,@_P2DR ; Output the segment data.

Rev. 2.0, 11/01, page 109 of 358

CMFB1 BTST #7,@_TCSR ; CMFB = 1?

BEQ CMFB1

BCLR #7,@_TCSR

MOV.B #H'FF,R1L

MOV.B R1L,@_P1DR ; Output the digit data, H'FF.

CMFA1 BTST #6,@_TCSR ; CMFA = 1?

BEQ CMFA1

BCLR #6,@_TCSR

MOV.B @_D_DATA, R1L ; Shift the digit data.

SHLR R1L

MOV.B R1L,@_D_DATA

ADDS #1,R6 ; Prepare the next data for the LED.

CMP.B #H'00,R1L

BNE NEXT1

MOV.B @_Count,R1L

INC R1L

MOV.B R1L,@_Count

MOV.B @_Count,R1L

CMP.B #H'FF,R1L

BNE MORE1

MOV.B @_Count2,R1L

INC R1L

MOV.B R1L,@_Count2

MOV.B @_Count2,R1L

CMP.B #H'02,R1L

BNE MORE2

RTS

Rev. 2.0, 11/01, page 110 of 358

;********************************************************************************************

; The interrupt handler for the I2C bus interf ace

; Data reception and judgemen t

; Exchanging the data tables

;********************************************************************************************

_Receive PUSH R1

PUSH R4 ; Store the contents of the registers.

BCLR #6,@_ICSR ; Clea r th e IRIC.

MOV.B @_ICDR,R1L ; Read the data (a dummy read).

MOV.B R1L,@_First ; Store the data in memory.

BSET #0,@_ICSR ; ACKB = 1

LOOP1 BTST #6,@_ICSR ; Has reception of the second byte (the data

; to distinguish the master) finished?

BEQ LOOP1 ;

BCLR #6,@_ICSR ; Clea r th e IRIC.

MOV.B @_ICDR,R1L

MOV.B R1L,@_Second ; Store the received data in memory.

BCLR #0,@_ICSR ; ACKB = 0

; Set the conditions for the subsequent

; reception of data.

MOV.B #H'00,R1L

MOV.B R1L,@_ICMR ; Set the condition that specifies 9 bits per

; 1 frame.

;-------------------------------------------------------------------

; Judgement

;-------------------------------------------------------------------

MOV.B @_Second,R1L ; Read the data that distinguishes the master.

_Judge CMP.B #H'01,R1L ; Judgement of the reception data

BEQ EXIT1

Rev. 2.0, 11/01, page 111 of 358

CMP.B #H'02,R1L

BEQ EXIT2

EXIT3 MOV.W #_Table3,R4

MOV.W R4,@_TABLE

BRA Clear

EXIT1 MOV.W #_Table1,R4

MOV.W R4,@_TABLE

BRA Clear

EXIT2 MOV.W #_Table2,R4

MOV.W R4,@_TABLE

BRA Clear

Clear POP R1

POP R2

POP R4 ; Recover the contents of the registers.

RTE

;-------------------------------------------------------------------

; The data table for the 8-segment LED

;-------------------------------------------------------------------

_Table1 .DATA.B H'9C ;H'004B LED DATA of "C"

.DATA.B H'CE ;H'004C LED DATA of "P"

.DATA.B H'7C ;H'004D LED DATA of "U"

.DATA.B H'60 ;H'004E LED DATA of "1"

_Table2 .DATA.B H'9C ;H'004F LED DATA of "C"

.DATA.B H'CE ;H'0050 LED DATA of "P"

.DATA.B H'7C ;H'0051 LED DATA of "U"

.DATA.B H'DA ;H'0052 LED DATA of "2"

_Table3 .DATA.B H'9F ;H'0053 LED DATA of "E"

.DATA.B H'02 ;H'0054 LED DATA of "-"

.DATA.B H'02 ;H'0055 LED DATA of "-"

.DATA.B H'02 ;H'0056 LED DATA of "-"

_Table4 .DATA.B H'FC ;H'0053 LED DATA of "0"

.DATA.B H'FC ;H'0054 LED DATA of "0"

.DATA.B H'FC ;H'0055 LED DATA of "0"

Rev. 2.0, 11/01, page 112 of 358

.DATA.B H'FC ;H'0056 LED DATA of "0"

.END

Rev. 2.0, 11/01, page 113 of 358

Section 4 Example Applications for the H8S Series

4.1 Usage Guide to the Example Applications for the H8S Series

4.1.1 The Structure of the Example Applications for the H8S Series

The chapter, ‘Example Applications for the H8S series’, has the structure shown in the figure 4.1.

The example applications for the H8S series product’s I2C bus interface are described in this

chapter.

The H8S/2138 is used as the device.

Example applications Specification

Description of behavior

Description of the

software Description of the modules

Description of the on-chip register usage

Description of variables

Description of the RAM usage

Flowchart

Programming lists

Figure 4.1 The structure of the example applications for the H8S Series

(1) Specification

Describes the system specification for these example tasks.

(2) Description of behavior

Uses timing charts to describe the behavior of these example tasks.

(3) Description of the software

(1) Description of the modules

Describes the modules of the software of this example task.

(2) Description of the on-chip register usage

Describes the settings of the I2C bus interface in the modules and of the on-chip registers

(3) Description of the variables

Describes the variables of the software that are used in the task examples.

(4) Description of the RAM usage

Describes the label names and functions of RAM locations that are used by the modules.

Rev. 2.0, 11/01, page 114 of 358

(4) Flowchart

Uses flowcharts to describe the software that carries out the task examples.

(5) Program listings

Gives the program listings of the software that carries out th e task examples.

4.1.2 Description of the Definition File for the Vector Table

The definition file for the vector table, in the C language, is described below. The file that defines

the starting addresses of the interrupt handling routines is shown in figure 4.2. To use an interrupt

handlin g routine, a label that gives the startin g address of that routine should be written to the

corresponding position in the vector table. Figure 4.2 gives an example that uses the IIC’s

channel-0 interrupt. The starting address (IIC0INT) is referred to by ‘external reference’ (refer to

figure 4.2-A). The label that shows the position of the IICI0 handler should be named IIC0INT

(refer to figure 4.2-B).

The label name ‘IIC0INT’ is referred to by ‘external reference’.

/********************************************************

* H8S/2138 Series vector table

* for mode3(normal,single-chip mode)

*********************************************************/

extern void main(void);

extern void IIC0INT (void);

const void (*vect_tbl[])(void) =

{

main, /* H’0000 Reset */

main, /* H’0002 Reserve */

main, /* H’0004 Reserve */

main, /* H’0006 Reserve */

main, /* H’0008 Reserve */

main, /* H’000A Reserve */

main, /* H’000C Direct transfer */

main, /* H’000E NMI */

main, /* H’0010 Trap */

main, /* H’0012 Trap */

main, /* H’0014 Trap */

Figure 4.2 Definition file for the vector table

The labe l name ‘IIC0INT’ is referred to by ‘external reference’.

Rev. 2.0, 11/01, page 115 of 358

main, /* H’0016 Trap */

main, /* H’0018 Reserve */

main, /* H’001A Reserve */

main, /* H’001C Reserve */

main, /* H’001E Reserve */

main, /* H’0020 IRQ0 */

main, /* H’0022 IRQ1 */

main, /* H’0024 IRQ2 */

main, /* H’0026 IRQ3 */

main, /* H’0028 IRQ4 */

main, /* H’002A IRQ5 */

main, /* H’002C IRQ6,KIN7-KIN0 */

main, /* H’002E IRQ7 */

main, /* H’0030 SWDTEND */

main, /* H’0032 WOVI0 */

main, /* H’0034 WOVI1 */

main, /* H’0036 PC break */

main, /* H’0038 ADI */

main, /* H’003A Reserve */

main, /* H’003C Reserve */

main, /* H’003E Reserve */

main, /* H’0040 Reserve */

main, /* H’0042 Reserve */

main, /* H’0044 Reserve */

main, /* H’0046 Reserve */

main, /* H’0048 Reserve */

main, /* H’004A Reserve */

main, /* H’004C Reserve */

main, /* H’004E Reserve */

main, /* H’0050 Reserve */

main, /* H’0052 Reserve */

main, /* H’0054 Reserve */

main, /* H’0056 Reserve */

main, /* H’0058 Reserve */

main, /* H’005A Reserve */

main, /* H’005C Reserve */

Figure 4.2 Definition file for the vector table (cont)

Rev. 2.0, 11/01, page 116 of 358

main, /* H’005E Reserve */

main, /* H’0060 ICIA */

main, /* H’0062 ICIB */

main, /* H’0064 ICIC */

main, /* H’0066 ICID */

main, /* H’0068 OCIA */

main, /* H’006A OCIB */

main, /* H’006C FOVI */

main, /* H’006E Reserve */

main, /* H’0070 Reserve */

main, /* H’0072 Reserve */

main, /* H’0074 Reserve */

main, /* H’0076 Reserve */

main, /* H’0078 Reserve */

main, /* H’007A Reserve */

main, /* H’007C Reserve */

main, /* H’007E Reserve */

main, /* H’0080 CMIA0 */

main, /* H’0082 CMIB0 */

main, /* H’0084 OVI0 */

main, /* H’0086 Reserve */

main, /* H’0088 CMIA1 */

main, /* H’008A CMIB1 */

main, /* H’008C OVI1 */

main, /* H’008E Reserve */

main, /* H’0090 CMIAY */

main, /* H’0092 CMIBY */

main, /* H’0094 OVIY */

main, /* H’0096 ICIX */

main, /* H’0098 IBF1 */

main, /* H’009A IBF2 */

main, /* H’009C Reserve */

main, /* H’009E Reserve */

main, /* H’00A0 ERI0 */

main, /* H’00A6 TEI0 */

main, /* H’00A8 ERI1 */

Figure 4.2 Definition file for the vector table (cont)

Rev. 2.0, 11/01, page 117 of 358

main, /* H’00AA RXI1 */

main, /* H’00AC TXI1 */

main, /* H’00AE TEI1 */

main, /* H’00B0 ERI2 */

main, /* H’00B2 RXI2 */

main, /* H’00B4 TXI2 */

IIC0INT, /* H’00B6 TEI2 */

main, /* H’00B8 IICI0 */

main, /* H’00BA DDCSWI */

main, /* H’00BC IICI1 */

main, /* H’00BE Reserve */

main, /* H’00C0 Reserve */

main, /* H’00C2 Reserve */

main, /* H’00C4 Reserve */

main, /* H’00C6 Reserve */

main, /* H’00C8 Reserve */

main, /* H’00CA Reserve */

main, /* H’00CC Reserve */

main, /* H’00CE Reserve */

};

Figure 4.2 Definition file for the vector table (cont)

Describes the label

name ‘IIC0INT’.

Rev. 2.0, 11/01, page 118 of 358

4.1.3 Description of the Definition File for the Registers

The definitio n file for the registers of H8S/2138 series products is given below.

The definition file for the registers of H8S/2138 Series products (1) <2138s.h>

/******************************************************************************************/

/* H8S/2138 Series Include File */

/******************************************************************************************/

union un_kbcomp {/* union KBCOMP */

unsigned char BYTE; /* */

struct { /* Bit Access */

unsigned char IrE :1; /* IrE */

unsigned char IrCKS:3; /* IrCKS */

unsigned char KBADE:1; /* KBADE */

unsigned char KBCH :3; /* KBCH */

} BIT; /* */

}; /* */

struct st_iic { /* struct IIC */

union { /* ICCR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char ICE :1; /* ICE */

unsigned char IEIC:1; /* IEIC */

unsigned char MST :1; /* MST */

unsigned char TRS :1; /* TRS */

nsigned char ACKE:1; /* ACKE */

unsigned char BBSY:1; /* BBSY */

unsigned char IRIC:1; /* IRIC */

unsigned char SCP :1; /* SCP */

} BIT; /* */

} ICCR; /* */

union { /* ICSR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char ESTP:1; /* ESTP */

unsigned char STOP:1; /* STOP */

unsigned char IRTR:1; /* IRTR */

Rev. 2.0, 11/01, page 119 of 358

unsigned char AASX:1; /* AASX */

unsigned char AL :1; /* AL */

unsigned char AAS :1; /* AAS */

unsigned char ADZ :1; /* ADZ */

unsigned char ACKB:1; /* ACKB */

} BIT; /* */

} ICSR; /* */

char wk[4]; /* */

union { /* */

struct { /* */

union { /* SARX */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char SVAX:7; /* SVAX */

unsigned char FSX :1; /* FSX */

} BIT; /* */

} UN_SARX; /* */

union { /* SAR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char SVA:7; /* SVA */

unsigned char FS :1; /* FS */

} BIT; /* */

} UN_SAR; /* */

} ICE0; /* */

struct { /* */

unsigned char UN_ICDR; /* ICDR */

union { /* ICMR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char MLS :1; /* MLS */

unsigned char WAIT:1; /* WAIT */

unsigned char CKS :3; /* CKS */

unsigned char BC :3; /* BC */

} BIT; /* */

} UN_ICMR; /* */

} ICE1; /* */

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} EQU; /* */

}; /* */

union un_ddcswr { /* union DDCSWR */

unsigned char BYTE; /* */

struct { /* Bit Access */

unsigned char SWE:1; /* SWE */

unsigned char SW :1; /* SW */

unsigned char IE :1; /* IE */

unsigned char IF :1; /* IF */

} BIT; /* */

}; /* */

struct st_intc { /* struct INTC */

union { /* ICRA */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char B7:1; /* IRQ0 */

unsigned char B6:1; /* IRQ1 */

unsigned char B5:1; /* IRQ2,IRQ3 */

unsigned char B4:1; /* IRQ4,IRQ5 */

unsigned char B3:1; /* IRQ6,IRQ7 */

unsigned char B2:1; /* DTC */

unsigned char B1:1; /* WDT0 */

unsigned char B0:1; /* WDT1 */

} BIT; /* */

} ICRA; /* */

union { /* ICRB */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char B7:1; /* A/D */

unsigned char B6:1; /* FRT */

unsigned char :2; /* */

unsigned char B3:1; /* TMR0 */

unsigned char B2:1; /* TMR1 */

unsigned char B1:1; /* TMRX,Y */

unsigned char B0:1; /* HIF */

} BIT; /* */

} ICRB; /* */

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union { /* ICRC */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char B7:1; /* SCI0 */

unsigned char B6:1; /* SCI1 */

unsigned char B5:1; /* SCI2 */

unsigned char B4:1; /* IIC0 */

unsigned char B3:1; /* IIC1 */

} BIT; /* */

} ICRC; /* */

union { /* ISR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char IRQ7F:1; /* IRQ7F */

unsigned char IRQ6F:1; /* IRQ6F */

unsigned char IRQ5F:1; /* IRQ5F */

unsigned char IRQ4F:1; /* IRQ4F */

unsigned char IRQ3F:1; /* IRQ3F */

unsigned char IRQ2F:1; /* IRQ2F */

unsigned char IRQ1F:1; /* IRQ1F */

unsigned char IRQ0F:1; /* IRQ0F */

} BIT; /* */

} ISR; /* */

union { /* ISCR */

unsigned int WORD; /* Word Access */

struct { /* Byte Access */

unsigned char H; /* ISCRH */

unsigned char L; /* ISCRL */

} BYTE; /* */

struct { /* Bit Access */

unsigned char IRQ7SC:2; /* IRQ7SC */

unsigned char IRQ6SC:2; /* IRQ6SC */

unsigned char IRQ5SC:2; /* IRQ5SC */

unsigned char IRQ4SC:2; /* IRQ4SC */

unsigned char IRQ3SC:2; /* IRQ3SC */

unsigned char IRQ2SC:2; /* IRQ2SC */

unsigned char IRQ1SC:2; /* IRQ1SC */

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unsigned char IRQ0SC:2; /* IRQ0SC */

} BIT; /* */

} ISCR; /* */

char wk1[6]; /* */

union { /* ABRKCR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char CMF:1; /* CMF */

unsigned char :6; /* */

unsigned char BIE:1; /* BIE */

} BIT; /* */

} ABRKCR; /* */

unsigned char BARA; /* BARA */

unsigned char BARB; /* BARB */

unsigned char BARC; /* BARC */

char wk2[202]; /* */

union { /* IER */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char IRQ7E:1; /* IRQ7E */

unsigned char IRQ6E:1; /* IRQ6E */

unsigned char IRQ5E:1; /* IRQ5E */

unsigned char IRQ4E:1; /* IRQ4E */

unsigned char IRQ3E:1; /* IRQ3E */

unsigned char IRQ2E:1; /* IRQ2E */

unsigned char IRQ1E:1; /* IRQ1E */

unsigned char IRQ0E:1; /* IRQ0E */

} BIT; /* */

} IER; /* */

char wk3[46]; /* */

union { /* KMIMR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char B7:1; /* Bit 7 */

unsigned char B6:1; /* Bit 6 */

unsigned char B5:1; /* Bit 5 */

unsigned char B4:1; /* Bit 4 */

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unsigned char B3:1; /* Bit 3 */

unsigned char B2:1; /* Bit 2 */

unsigned char B1:1; /* Bit 1 */

unsigned char B0:1; /* Bit 0 */

} BIT; /* */

} KMIMR; /* */

char wk4; /* */

union { /* KMIMRA */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char B15:1; /* Bit 7 */

unsigned char B14:1; /* Bit 6 */

unsigned char B13:1; /* Bit 5 */

unsigned char B12:1; /* Bit 4 */

unsigned char B11:1; /* Bit 3 */

unsigned char B10:1; /* Bit 2 */

unsigned char B9 :1; /* Bit 1 */

unsigned char B8 :1; /* Bit 0 */

} BIT; /* */

} KMIMRA; /* */

}; /* */

struct st_dtc { /* struct DTC */

union { /* EA */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char B7:1; /* IRQ0 */

unsigned char B6:1; /* IRQ1 */

unsigned char B5:1; /* IRQ2 */

unsigned char B4:1; /* IRQ3 */

unsigned char B3:1; /* A/D */

unsigned char B2:1; /* FRT ICIA */

unsigned char B1:1; /* FRT ICIB */

unsigned char B0:1; /* FRT OCIA */

} BIT; /* */

} EA; /* */

union { /* EB */

unsigned char BYTE; /* Byte Access */

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struct { /* Bit Access */

unsigned char B7:1; /* FRT OCIB */

unsigned char :4; /* */

unsigned char B2:1; /* TMR0 CMIA */

unsigned char B1:1; /* TMR0 CMIB */

unsigned char B0:1; /* TMR1 CMIA */

} BIT; /* */

} EB; /* */

union { /* EC */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char B7:1; /* TMR1 CMIB */

unsigned char B6:1; /* TMRY CMIA */

unsigned char B5:1; /* TMRY CMIB */

unsigned char B4:1; /* HIF1 */

unsigned char B3:1; /* HIF2 */

unsigned char B2:1; /* SCIO RXI */

unsigned char B1:1; /* SCIO TXI */

unsigned char B0:1; /* SCI1 RXI */

} BIT; /* */

} EC; /* */

union { /* ED */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char B7:1; /* SCI1 TXI */

unsigned char B6:1; /* SCI2 RXI */

unsigned char B5:1; /* SCI2 TXI */

unsigned char B4:1; /* IIC0 */

unsigned char B3:1; /* IIC1 */

} BIT; /* */

} ED; /* */

char wk; /* */

union { /* VECR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char SWDTE:1; /* SWDTE */

unsigned char DTVEC:7; /* DTVEC */

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} BIT; /* */

} VECR; /* */

}; /* */

struct st_flash { /* struct FLASH */

union { /* FLMCR1 */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char FWE:1; /* FWE */

unsigned char SWE:1; /* SWE */

unsigned char :2; /* */

unsigned char EV :1; /* EV */

unsigned char PV :1; /* PV */

unsigned char E :1; /* E */

unsigned char P :1; /* P */

} BIT; /* */

} FLMCR1; /* */

union { /* FLMCR2 */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char FLER:1; /* FLER */

unsigned char :5; /* */

unsigned char ESU :1; /* ESU */

unsigned char PSU :1; /* PSU */

} BIT; /* */

} FLMCR2; /* */

union { /* EBR1 */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char wk :6; /* */

unsigned char EB9:1; /* EB9 */

unsigned char EB8:1; /* EB8 */

} BIT; /* */

} EBR1; /* */

union { /* EBR2 */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char EB7:1; /* EB7 */

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unsigned char EB6:1; /* EB6 */

unsigned char EB5:1; /* EB5 */

unsigned char EB4:1; /* EB4 */

unsigned char EB3:1; /* EB3 */

unsigned char EB2:1; /* EB2 */

unsigned char EB1:1; /* EB1 */

unsigned char EB0:1; /* EB0 */

} BIT; /* */

} EBR2; /* */

}; /* */

struct st_pwm { /* struct PWM */

union { /* PCSR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char wk :5; /* */

unsigned char PWCKB:1; /* PWCKB */

unsigned char PWCKA:1; /* PWCKA */

} BIT; /* */

} PCSR; /* */

char wk[79]; /* */

union { /* PWOER */

unsigned int WORD; /* Word Access */

struct { /* Byte Access */

unsigned char B; /* PWOERB */

unsigned char A; /* PWOERA */

} BYTE; /* */

struct { /* Bit Access */

unsigned char OE15:1; /* OE15 */

unsigned char OE14:1; /* OE14 */

unsigned char OE13:1; /* OE13 */

unsigned char OE12:1; /* OE12 */

unsigned char OE11:1; /* OE11 */

unsigned char OE10:1; /* OE10 */

unsigned char OE9 :1; /* OE9 */

unsigned char OE8 :1; /* OE8 */

unsigned char OE7 :1; /* OE7 */

unsigned char OE6 :1; /* OE6 */

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unsigned char OE5 :1; /* OE5 */

unsigned char OE4 :1; /* OE4 */

unsigned char OE3 :1; /* OE3 */

unsigned char OE2 :1; /* OE2 */

unsigned char OE1 :1; /* OE1 */

unsigned char OE0 :1; /* OE0 */

} BIT; /* */

} OER; /* */

union { /* PWDPR */

unsigned int WORD; /* Word Access */

struct { /* Byte Access */

unsigned char B; /* PWDPRB */

unsigned char A; /* PWDPRA */

} BYTE; /* */

struct { /* Bit Access */

unsigned char OS15:1; /* OS15 */

unsigned char OS14:1; /* OS14 */

unsigned char OS13:1; /* OS13 */

unsigned char OS12:1; /* OS12 */

unsigned char OS11:1; /* OS11 */

unsigned char OS10:1; /* OS10 */

unsigned char OS9 :1; /* OS9 */

unsigned char OS8 :1; /* OS8 */

unsigned char OS7 :1; /* OS7 */

unsigned char OS6 :1; /* OS6 */

unsigned char OS5 :1; /* OS5 */

unsigned char OS4 :1; /* OS4 */

unsigned char OS3 :1; /* OS3 */

unsigned char OS2 :1; /* OS2 */

unsigned char OS1 :1; /* OS1 */

unsigned char OS0 :1; /* OS0 */

} BIT; /* */

} DPR; /* */

union { /* PWSL */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char PWCKE:1; /* PWCKE */

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unsigned char PWCKS:1; /* PWCKE */

unsigned char :2; /* */

unsigned char RS :4; /* RS */

} BIT; /* */

} SL; /* */

unsigned char DR; /* PWDR0-PWDR15 */

}; /* */

struct st_hif { /* struct HIF */

union { /* SYSCR2 */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char wk :7; /* */

unsigned char HI12E:1; /* HI12E */

} BIT; /* */

} SYSCR2; /* */

char wk[108]; /* */

union { /* HICR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char wk :5; /* */

unsigned char IBFIE2:1; /* IBFIE2 */

unsigned char IBFIE1:1; /* IBFIE1 */

unsigned char FGA2OE:1; /* FGA2OE */

} BIT; /* */

} HICR; /* */

}; /* */

struct st_hif1 { /* struct HIF1 */

unsigned char IDR; /* IDR */

unsigned char ODR; /* ODR */

union { /* STR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char DBU7:1; /* DBU */

unsigned char DBU6:1; /* DBU */

unsigned char DBU5:1; /* DBU */

unsigned char DBU4:1; /* DBU */

unsigned char CD :1; /* C/D */

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unsigned char DBU2:1; /* DBU */

unsigned char IBF :1; /* IBF */

unsigned char OBF :1; /* OBF */

} BIT; /* */

char wk2[5]; /* */

}; /* */

union un_sbycr { /* union SBYCR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char SSBY :1; /* SSBY */

unsigned char STS :3; /* STS */

unsigned char :1; /* */

unsigned char SCK :3; /* SCK */

} BIT; /* */

}; /* */

union un_lpwrcr { /* union LPWRCR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char DTON :1; /* DTON */

unsigned char LSON :1; /* LSON */

unsigned char NESEL:1; /* NESEL */

unsigned char EXCLE:1; /* EXCLE */

} BIT; /* */

}; /* */

union un_mstpcr { /* union MSTPCR */

unsigned int WORD; /* Word Access */

struct { /* Byte Access */

unsigned char H; /* MSTPCRH */

unsigned char L; /* MSTPCRL */

} BYTE; /* */

struct { /* Bit Access */

unsigned char wk :1; /* */

unsigned char B14:1; /* DTC */

unsigned char B13:1; /* FRT */

unsigned char B12:1; /* TMR0,TMR1 */

unsigned char B11:1; /* PWM,PWMX */

unsigned char B10:1; /* D/A */

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unsigned char B9 :1; /* A/D */

unsigned char B8 :1; /* TMRX,TMRY */

unsigned char B7 :1; /* SCI0 */

unsigned char B6 :1; /* SCI1 */

unsigned char B5 :1; /* SCI2 */

unsigned char B4 :1; /* IIC0 */

unsigned char B3 :1; /* IIC1 */

unsigned char B2 :1; /* HIF */

} BIT; /* */

}; /* */

union un_stcr { /* union STCR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char IICS :1; /* IICS */

unsigned char IICX1:1; /* IICX1 */

unsigned char IICX0:1; /* IICX0 */

unsigned char IICE :1; /* IICE */

unsigned char FLSHE:1; /* FLSHE */

unsigned char :1; /* */

unsigned char ICKS1:1; /* ICKS1 */

unsigned char ICKS0:1; /* ICKS0 */

} BIT; /* */

}; /* */

union un_syscr { /* union SYSCR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char CS2E :1; /* CS2E */

unsigned char IOSE :1; /* IOSE */

unsigned char INTM :2; /* INTM */

unsigned char XRST :1; /* XRST */

unsigned char NMIEG:1; /* NMIEG */

unsigned char HIE :1; /* HIE */

unsigned char RAME :1; /* RAME */

} BIT; /* */

}; /* */

union un_mdcr { /* union MDCR */

unsigned char BYTE; /* Byte Access */

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struct { /* Bit Access */

unsigned char EXPE:1; /* EXPE */

unsigned char :5; /* */

unsigned char MDS :2; /* MDS */

} BIT; /* */

}; /* */

union st_sci { /* struct SCI */

union { /* SMR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char CA :1; /* C/A */

unsigned char CHR :1; /* CHR */

unsigned char PE :1; /* PE */

unsigned char OE :1; /* O/E */

unsigned char STOP:1; /* STOP */

unsigned char MP :1; /* MP */

unsigned char CKS :2; /* CKS */

} BIT; /* */

} SMR; /* */

unsigned char BRR; /* BRR */

union { /* SCR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char TIE :1; /* TIE */

unsigned char RIE :1; /* RIE */

unsigned char TE :1; /* TE */

unsigned char RE :1; /* RE */

unsigned char MPIE:1; /* MPIE */

unsigned char TEIE:1; /* TEIE */

unsigned char CKE :2; /* CKE */

} BIT; /* */

} SCR; /* */

unsigned char TDR; /* TDR */

union { /* SSR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char TDRE:1; /* TDRE */

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unsigned char RDRF:1; /* RDRF */

unsigned char ORER:1; /* ORER */

unsigned char FER :1; /* FER */

unsigned char PER :1; /* PER */

unsigned char TEND:1; /* TEND */

unsigned char MPB :1; /* MPB */

unsigned char MPBT:1; /* MPBT */

} BIT; /* */

} SSR; /* */

unsigned char RDR; /* RDR */

union { /* SCMR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char wk :4; /* */

unsigned char SDIR:1; /* SDIR */

unsigned char SINV:1; /* SINV */

unsigned char :1; /* */

unsigned char SMIF:1; /* SMIF */

} BIT; /* */

} SCMR; /* */

}; /* */

union st_frt { /* struct FRT */

union { /* TIER */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char ICIAE:1; /* ICIAE */

unsigned char ICIBE:1; /* ICIBE */

unsigned char ICICE:1; /* ICICE */

unsigned char ICIDE:1 /* ICIDE */

unsigned char OCIAE:1; /* OCIAE */

unsigned char OCIBE:1; /* OCIBE */

unsigned char OVIE :1; /* OVIE */

} BIT; /* */

} TIER; /* */

union { /* TCSR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

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unsigned char ICFA :1; /* ICFA */

unsigned char ICFB :1; /* ICFB */

unsigned char ICFC :2; /* ICFC */

unsigned char ICFD :1; /* ICFD */

unsigned char OCFA :1; /* OCFA */

unsigned char OCFB :1; /* OCFB */

unsigned char OVF :1; /* OVF */

unsigned char CCLRA:1; /* CCLRA */

} BIT; /* */

} TCSR; /* */

unsigned int FRC; /* FRC */

unsigned int OCRA; /* OCRA or OCRB */

union { /* TCR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char IEDGA:1; /* IEDGA */

unsigned char IEDGB:1; /* IEDGB */

unsigned char IEDGC:1; /* IEDGC */

unsigned char IEDGD:1; /* IEDGD */

unsigned char BUFEA:1; /* BUFEA */

unsigned char BUFEB:1; /* BUFEB */

unsigned char CKS :2; /* CKS */

} BIT; /* */

} TCR; /* */

union { /* TOCR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char ICRDMS:1; /* ICRDMS */

unsigned char OCRAMS:1; /* OCRAMS */

unsigned char ICRS :1; /* ICRS */

unsigned char OCRS :1; /* OCRS */

unsigned char OEA :1; /* OEA */

unsigned char OEB :1; /* OEB */

unsigned char OLVLA :1; /* OLVLA */

unsigned char OLVLB :1; /* OLVLB */

} BIT; /* */

} TOCR; /* */

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unsigned int ICRA; /*ICRA or OCRAR */

unsigned int ICRB; /*ICRB or OCRAF */

unsigned int ICRC; /*ICRC or OCRDM */

unsigned int ICRD; /* ICRD */

}; /* */

union un_pwmx { /* struct PWMX */

struct { /* */

union { /* DACR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char TEST :1; /* TEST */

unsigned char PWME :1; /* PWME */

unsigned char char :2; /* */

unsigned char char OEB :1; /* OEB */

unsigned char char OEA :1; /* OEA */

unsigned char char OS :1; /* OS */

unsigned char char CKS :1; /* CKS */

} BIT; /* */

} ST_DACR; /* */

char wk[5]; /* */

union { /* DACNT */

unsigned int WORD; /* Word Access */

struct { /* Bit Access */

unsigned int wk :15; /* */

unsigned int REGS: 1; /* REGS */

} BIT; /* */

} ST_DACNT; /* */

} REGS1; /* */

struct { /* */

union { /* DADRA */

unsigned int WORD; /* Word Access */

struct { /* Bit Access */

unsigned int wk :14; /* */

unsigned int CFS: 1; /* CFS */

} BIT; /* */

} ST_DADRA; /* */

char wk[4]; /* */

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union { /* DADRB */

unsigned int WORD; /* Word Access */

struct { /* Bit Access */

unsigned int wk :14; /* */

unsigned int CFS : 1; /* CFS */

unsigned int REGS: 1; /* REGS */

} BIT; /* */

} ST_DADRB; /* */

} REGSO; /* */

}; /* */

struct st_p1 { /* struct P1 */

union { /* P1PCR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char B7:1; /* Bit 7 */

unsigned char B6:1; /* Bit 6 */

unsigned char B5:1; /* Bit 5 */

unsigned char B4:1; /* Bit 4 */

unsigned char B3:1; /* Bit 3 */

unsigned char B2:1; /* Bit 2 */

unsigned char B1:1; /* Bit 1 */

unsigned char B0:1; /* Bit 0 */

} BIT; /* */

} PCR; /* */

char wk1[3]; /* */

unsigned char DDR; /* P1DDR */

char wk2; /* */

union { /* P1DR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char B7:1; /* Bit 7 */

unsigned char B6:1; /* Bit 6 */

unsigned char B5:1; /* Bit 5 */

unsigned char B4:1; /* Bit 4 */

unsigned char B3:1; /* Bit 3 */

unsigned char B2:1; /* Bit 2 */

unsigned char B1:1; /* Bit 1 */

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unsigned char B0:1; /* Bit 0 */

} BIT; /* */

} DR; /* */

}; /* */

struct st_p3 { /* struct P3 */

union { /* P3PCR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char B7:1; /* Bit 7 */

unsigned char B6:1; /* Bit 6 */

unsigned char B5:1; /* Bit 5 */

unsigned char B4:1; /* Bit 4 */

unsigned char B3:1; /* Bit 3 */

unsigned char B2:1; /* Bit 2 */

unsigned char B1:1; /* Bit 1 */

unsigned char B0:1; /* Bit 0 */

} BIT; /* */

} PCR; /* */

char wk1[5]; /* */

unsigned char DDR; /* P3DDR */

char wk2; /* */

union { /* P3DR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char B7:1; /* Bit 7 */

unsigned char B6:1; /* Bit 6 */

unsigned char B5:1; /* Bit 5 */

unsigned char B4:1; /* Bit 4 */

unsigned char B3:1; /* Bit 3 */

unsigned char B2:1; /* Bit 2 */

unsigned char B1:1; /* Bit 1 */

unsigned char B0:1; /* Bit 0 */

} BIT; /* */

} DR; /* */

}; /* */

struct st_p4 { /* struct P4 */

unsigned char DDR; /* P4DDR */

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char wk; /* */

union { /* P4DR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char B7:1; /* Bit 7 */

unsigned char B6:1; /* Bit 6 */

unsigned char B5:1; /* Bit 5 */

unsigned char B4:1; /* Bit 4 */

unsigned char B3:1; /* Bit 3 */

unsigned char B2:1; /* Bit 2 */

unsigned char B1:1; /* Bit 1 */

unsigned char B0:1; /* Bit 0 */

} BIT; /* */

} DR; /* */

}; /* */

struct st_p5 { /* struct P5 */

unsigned char DDR; /* P5DDR */

char wk; /* */

union { /* P5DR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char wk:5; /* Bit 7-3 */

unsigned char B2:1; /* Bit 2 */

unsigned char B1:1; /* Bit 1 */

unsigned char B0:1; /* Bit 0 */

} BIT; /* */

} DR; /* */

}; /* */

struct st_p6 { /* struct P6 */

unsigned char DDR; /* P6DDR */

char wk1; /* */

union { /* P6DR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char B7:1; /* Bit 7 */

unsigned char B6:1; /* Bit 6 */

unsigned char B5:1; /* Bit 5 */

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unsigned char B4:1; /* Bit 4 */

unsigned char B3:1; /* Bit 3 */

unsigned char B2:1; /* Bit 2 */

unsigned char B1:1; /* Bit 1 */

unsigned char B0:1; /* Bit 0 */

} BIT; /* */

} DR; /* */

char wk2[54]; /* */

union { /* P6PCR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char B7:1; /* Bit 7 */

unsigned char B6:1; /* Bit 6 */

unsigned char B5:1; /* Bit 5 */

unsigned char B4:1; /* Bit 4 */

unsigned char B3:1; /* Bit 3 */

unsigned char B2:1; /* Bit 2 */

unsigned char B1:1; /* Bit 1 */

unsigned char B0:1; /* Bit 0 */

} BIT; /* */

} PCR; /* */

}; /* */

struct st_p7 { /* struct P7 */

union { /* P7PIN */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char B7:1; /* Bit 7 */

unsigned char B6:1; /* Bit 6 */

unsigned char B5:1; /* Bit 5 */

unsigned char B4:1; /* Bit 4 */

unsigned char B3:1; /* Bit 3 */

unsigned char B2:1; /* Bit 2 */

unsigned char B1:1; /* Bit 1 */

unsigned char B0:1; /* Bit 0 */

} BIT; /* */

} PIN; /* */

}; /* */

Rev. 2.0, 11/01, page 139 of 358

struct st_p8 { /* struct P8 */

unsigned char DDR; /* P8DDR */

char wk; /* */

union { /* P8DR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char wk:1; /* Bit 7 */

unsigned char B6:1; /* Bit 6 */

unsigned char B5:1; /* Bit 5 */

unsigned char B4:1; /* Bit 4 */

unsigned char B3:1; /* Bit 3 */

unsigned char B2:1; /* Bit 2 */

unsigned char B1:1; /* Bit 1 */

unsigned char B0:1; /* Bit 0 */

} BIT; /* */

} DR; /* */

}; /* */

struct st_p9 { /* struct P9 */

unsigned char DDR; /* P9DDR */

union { /* P9DR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char B7:1; /* Bit 7 */

unsigned char B6:1; /* Bit 6 */

unsigned char B5:1; /* Bit 5 */

unsigned char B4:1; /* Bit 4 */

unsigned char B3:1; /* Bit 3 */

unsigned char B2:1; /* Bit 2 */

unsigned char B1:1; /* Bit 1 */

unsigned char B0:1; /* Bit 0 */

} BIT; /* */

} DR; /* */

}; /* */

struct st_bsc { /* struct BSC */

union { /* BCR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

Rev. 2.0, 11/01, page 140 of 358

unsigned char ICIS1 :1; /* ICIS1 */

unsigned char ICIS0 :1; /* ICIS0 */

unsigned char BRSTRM:1; /* BRSTRM */

unsigned char BRSTS1:1; /* BRSTS1 */

unsigned char BRSTS0:1; /* BRSTS0 */

unsigned char :1; /* */

unsigned char IOS :2; /* IOS */

} BIT; /* */

} BCR; /* */

union { /* WSCR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char RAMS:1; /* RAMS */

unsigned char RAM0:1; /* RAM0 */

unsigned char ABW :1; /* ABW */

unsigned char AST :1; /* AST */

unsigned char WMS :2; /* WMS */

unsigned char WC :2; /* WC */

} BIT; /* */

} WSCR; /* */

}; /* */

struct st_tmr { /* struct TMR */

union { /* TCR0 */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char CMIEB:1; /* CMIEB */

unsigned char CMIEA:1; /* CMIEA */

unsigned char OVIE :1; /* OVIE */

unsigned char CCLR :2; /* CCLR */

unsigned char CKS :3; /* CKS */

} BIT; /* */

} TCR0; /* */

union { /* TCR1 */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char CMIEB:1; /* CMIEB */

unsigned char CMIEA:1; /* CMIEA */

Rev. 2.0, 11/01, page 141 of 358

unsigned char OVIE :1; /* OVIE */

unsigned char CCLR :2; /* CCLR */

unsigned char CKS :3; /* CKS */

} BIT; /* */

} TCR1; /* */

union { /* TCSR0 */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char CMFB:1; /* CMFB */

unsigned char CMFA:1; /* CMFA */

unsigned char OVF :1; /* OVF */

unsigned char ADTE:1; /* ADTE */

unsigned char OS :4; /* OS */

} BIT; /* */

} TCSR0; /* */

union { /* TCSR1 */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char CMFB:1; /* CMFB */

unsigned char CMFA:1; /* CMFA */

unsigned char OVF :1; /* OVF */

unsigned char :1; /* */

unsigned char OS :4; /* OS */

} BIT; /* */

} TCSR1; /* */

unsigned int TCORA; /* TCORA */

unsigned int TCORB; /* TCORB */

unsigned int TCNT; /* TCNT */

}; /* */

struct st_tmr0 { /* struct TMR0 */

union { /* TCR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char CMIEB:1; /* CMIEB */

unsigned char CMIEA:1; /* CMIEA */

unsigned char OVIE :1; /* OVIE */

unsigned char CCLR :2; /* CCLR */

Rev. 2.0, 11/01, page 142 of 358

unsigned char CKS :3; /* CKS */

} BIT; /* */

} TCR; /* */

char wk; /* */

union { /* TCSR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char CMFB:1; /* CMFB */

unsigned char CMFA:1; /* CMFA */

unsigned char OVF :1; /* OVF */

unsigned char ADTE:1; /* ADTE */

unsigned char OS :4; /* OS */

} BIT; /* */

} TCSR; /* */

char wk2; /* */

unsigned char TCORA; /* TCORA */

char wk3; /* */

unsigned char TCORB; /* TCORB */

char wk4; /* */

unsigned char TCNT; /* TCNT */

}; /* */

struct st_tmr1 { /* struct TMR1 */

union { /* TCR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char CMIEB:1; /* CMIEB */

unsigned char CMIEA:1; /* CMIEA */

unsigned char OVIE :1; /* OVIE */

unsigned char CCLR :2; /* CCLR */

unsigned char CKS :3; /* CKS */

} BIT; /* */

} TCR; /* */

char wk1; /* */

union { /* TCSR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char CMFB:1; /* CMFB */

Rev. 2.0, 11/01, page 143 of 358

unsigned char CMFA:1; /* CMFA */

unsigned char OVF :1; /* OVF */

unsigned char :1; /* */

unsigned char OS :4; /* OS */

} BIT; /* */

} TCSR; /* */

char wk2; /* */

unsigned char TCORA; /* TCORA */

char wk3; /* */

unsigned char TCORB; /* TCORB */

char wk4; /* */

unsigned char TCNT; /* TCNT */

}; /* */

struct st_tmrx { /* struct TMRX */

union { /* TCR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char CMIEB:1; /* CMIEB */

unsigned char CMIEA:1; /* CMIEA */

unsigned char OVIE :1; /* OVIE */

unsigned char CCLR :2; /* CCLR */

unsigned char CKS :3; /* CKS */

} BIT; /* */

} TCR; /* */

union { /* TCSR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char CMFB:1; /* CMFB */

unsigned char CMFA:1; /* CMFA */

unsigned char OVF :1; /* OVF */

unsigned char ICF :1; /* ICF */

unsigned char OS :4; /* OS */

} BIT; /* */

} TCSR; /* */

unsigned char TICRR; /* TICRR */

unsigned char TICRF; /* TICRF */

unsigned char TCNT; /* TCNT */

Rev. 2.0, 11/01, page 144 of 358

unsigned char TCORC; /* TCORC */

unsigned char TCORA; /* TCORA */

unsigned char TCORB; /* TCORB */

}; /* */

struct st_tmry { /* struct TMRY */

union { /* TCR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char CMIEB:1; /* CMIEB */

unsigned char CMIEA:1; /* CMIEA */

unsigned char OVIE :1; /* OVIE */

unsigned char CCLR :2; /* CCLR */

unsigned char CKS :3; /* CKS */

} BIT; /* */

} TCR; /* */

union { /* TCSR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char CMFB:1; /* CMFB */

unsigned char CMFA:1; /* CMFA */

unsigned char OVF :1; /* OVF */

unsigned char ICIE:1; /* ICIE */

unsigned char OS :4; /* OS */

} BIT; /* */

} TCSR; /* */

unsigned char TCORA; /* TCORA */

unsigned char TCORB; /* TCORB */

unsigned char TCNT; /* TCNT */

union { /* TISR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char wk:7; /* */

unsigned char IS:1; /* IS */

} BIT; /* */

} TISR; /* */

}; /* */

struct st_ad { /* struct A/D */

Rev. 2.0, 11/01, page 145 of 358

unsigned int DRA; /* ADDRA */

unsigned int DRB; /* ADDRB */

unsigned int DRC; /* ADDRC */

unsigned int DRD; /* ADDRD */

union { /* ADCSR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char ADF :1; /* ADF */

unsigned char ADIE:1; /* ADIE */

unsigned char ADST:1; /* ADST */

unsigned char SCAN:1; /* SCAN */

unsigned char CKS :1; /* CKS */

unsigned char CH :3; /* CH */

} BIT; /* */

} CSR; /* */

union { /* ADCR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char TRGS:2; /* TRGS */

} BIT; /* */

} CR; /* */

}; /* */

struct st_da { /* struct D/A */

unsigned char DR0; /* DADR0 */

unsigned char DR1; /* DADR1 */

union { /* DACR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char DA0E1:1; /* DA0E1 */

unsigned char DA0E0:1; /* DA0E0 */

unsigned char DAE :1; /* DAE */

} BIT; /* */

} CR; /* */

}; /* */

struct st_tc { /* struct TC */

union { /* TCONRI */

unsigned char BYTE; /* Byte Access */

Rev. 2.0, 11/01, page 146 of 358

struct { /* Bit Access */

unsigned char SIMOD:2; /* SIMOD */

unsigned char SCONE:1; /* SCONE */

unsigned char ICST :1; /* ICST */

unsigned char HFINV:1; /* HFINV */

unsigned char VFINV:1; /* VFINV */

unsigned char HIINV:1; /* HIINV */

unsigned char VIINV:1; /* VIINV */

} BIT; /* */

} TCONRI; /* */

union { /* TCONR0 */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char HOE :1; /* HOE */

unsigned char VOE :1; /* VOE */

unsigned char CLOE :1; /* CLOE */

unsigned char CBOE :1; /* CBOE */

unsigned char HOINV :1; /* HOINV */

unsigned char VOINV :1; /* VOINV */

unsigned char CLOINV:1; /* CLOINV */

unsigned char CBOINV:1; /* CBOINV */

} BIT; /* */

} TCONR0; /* */

union { /* TCONRS */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char TMRXY :1; /* TMRXY */

unsigned char ISGENE:1; /* ISGENE */

unsigned char HOMOD :2; /* HOMOD */

unsigned char VOMOD :2; /* VOMOD */

unsigned char CLMOD :2; /* CLMOD */

} BIT; /* */

} TCONRS; /* */

union { /* SEDGR */

unsigned char BYTE; /* Byte Access */

struct { /* Bit Access */

unsigned char VEDG :1; /* VEDG */

Rev. 2.0, 11/01, page 147 of 358

unsigned char HEDG :1; /* HEDG */

unsigned char CEDG :1; /* CEDG */

unsigned char HFEDG:1; /* HFEDG */

unsigned char VFEDG:1; /* VFEDG */

unsigned char PREQF:1; /* PREQF */

unsigned char IHI :1; /* IHI */

unsigned char IVI :1; /* IVI */

} BIT; /* */

} SEDGR; /* */

}; /* */

#define KBCOMP (*(volatile union un_kbcomp*)0xFFFEE4) /* KBCOMP Address */

#define IIC0 (*(volatile struct st_iic0 *)0xFFFFD8) /* IIC0 Address */

#define IIC1 (*(volatile struct st_iic1 *)0XFFFF88) /* IIC1 Address */

#define ICDR EQU.ICE1.UN_ICDR /* ICDR Change */

#define ICMR EQU.ICE1.UN_ICMR /* ICDR Change */

#define SAR EQU.ICE0.UN_SAR /* SAR Ch a n g e */

#define SARX EQU.ICE0.UN_SARX /* S A R X Ch a n g e */

#define DDCSWR (*(volatile union un_ddcswr*)0xFFFEE6) /* DDCSWR Address */

#define INTC (*(volatile struct st_intc *)0xFFFEE8) /* INTC Address */

#define DTC (*(volatile struct st_dtc *)0xFFFEEE) /* DTC Address */

#define FLASH (*(volatile struct st_flash *)0xFFFF80) /* FLASH Address */

#define PWM (*(volatile struct st_pwm *)0xFFFF82) /* PWM Address */

#define HIF (*(volatile struct st_hif *)0xFFFF83) /* HIF Ad dress * /

#define HIF1 (*(volatile struct st_hif1 *)0xFFFFF4) /* HIF1 Address */

#define HIF2 (*(volatile struct st_hif2 *)0xFFFFFC) /* HIF1 Address */

#define SBYCR (*(volatile union un_sbycr *)0xFFFF84) /* SBYCR Address */

#define LPWRCR (*(volatile union un_lpwrcr*)0xFFFF85) /* LPWRCR Address */

#define MSTPCR (*(volatile union un_mstpcr*)0xFFFF86) /* MSTPCR Address */

#define STCR (*(volatile union un_stcr *)0xFFFFC3) /* STCR Address */

#define SYSCR (*(volatile union un_syscr *)0xFFFFC4) /* SYSCR Address */

#define MDCR (*(volatile union un_mdcr *)0xFFFFC5) /* MDCR Address */

#define SCI0 (*(volatile struct st_sci0 *)0xFFFFD8) /* SCI0 Address */

#define SCI1 (*(volatile struct st_sci1 *)0xFFFF88) /* SCI1 Address */

#define SCI2 (*(volatile struct st_sci2 *)0xFFFFA0) /* SCI2 Address */

#define FRT (*(volatile struct st_frt *)0xFFFF90) /* FRT Address */

#define OCRB OCRA /* OCRB Change */

#define OCRAR ICRA /* OCRAR Change */

Rev. 2.0, 11/01, page 148 of 358

#define OCRAF ICRB /* OCRAF Change */

#define OCRDM ICRC /* OCRDM Change */

#define PWMX (*(volatile union un_pwmx *)0xFFFFA0) /* PWMX Address */

#define DACR REGS1.ST_DACR /* DACR Change */

#define DACNT REGS1.ST_DACNT /* DACNT Change */

#define DADRA REGS0.ST_DADRA /* DADRA Change */

#define DADRB REGS0.ST_DADRB /* DADRB Change */

#define P1 (*(volatile struct st_p1 *)0xFFFFAC) /* P1 Address */

#define P2 (*(volatile struct st_p2 *)0xFFFFAD) /* P2 Address */

#define P3 (*(volatile struct st_p3 *)0xFFFFAE) /* P3 Address */

#define P4 (*(volatile struct st_p4 *)0xFFFFB5) /* P4 Address */

#define P5 (*(volatile struct st_p5 *)0xFFFFB8) /* P5 Address */

#define P6 (*(volatile struct st_p6 *)0xFFFFB9) /* P6 Address */

#define P7 (*(volatile struct st_p7 *)0xFFFFBE) /* P7 Address */

#define P8 (*(volatile struct st_p8 *)0xFFFFBD) /* P8 Address */

#define P9 (*(volatile struct st_p9 *)0xFFFFC0) /* P9 Address */

#define BSC (*(volatile struct st_bsc *)0xFFFFC6) /* BSC Address */

#define TMR (*(volatile struct st_tmr *)0xFFFFC8) /* TMR Address */

#define TMR0 (*(volatile struct st_tmr0 *)0xFFFFC8) /* TMR0 Address */

#define TMR1 (*(volatile struct st_tmr1 *)0xFFFFC9) /* TMR1 Address */

#define TMRX (*(volatile struct st_tmrx *)0xFFFFF0) /* TMRX Address */

#define TMRY (*(volatile struct st_tmry *)0xFFFFF0) /* TMRY Address */

#define AD (*(volatile struct st_ad *)0xFFFFE0) /* A/D Address */

#define DA (*(volatile struct st_da *)0xFFFFF8) /* D/A Address */

#define TC (*(volatile struct st_tc *)0xFFFFFC) /* TC Address */

#define st_hif2 st_hif1 /*Change Struct HIF2 */

#define st_p2 st_p1 /*Change Struct P2->P1 */

4.1.4 Description of the Inclusion of Assembler Files in C Language Programs

The technique of including assembler files in C language programs enables us, within a C-

language program, to carry out such processes as initializing the contents of the stack by using

assembly language. This technique is used in the program listings of the example applications.

The C-compiler (CH38.EXE) is unable to directly generate object files from assembly language.

Assembling an assembly-language file, therefore, must generate the object file. The assembly-

language file is generated by using the assembler (ASM38.EXE) with the correct code option.

The file’s name is “sub -file name.src”.

Rev. 2.0, 11/01, page 149 of 358

The code option must be specified as “-c=a” to generate the object file for the CH38.EXE. Refer

to the manua l of the comp iler for more details.

4.1.5 Description of the Linkage of Files

Figure 4.3 shows the submit-file used in the linkage process. The definition file for the vector

table, definition file for the registers, and each task file is linked according to the information in

the submit-file. Figure 4.3 shows an example of a submit-file.

····················································

·············································

·································································

····································································

···········

input SMRxd, 2138vec [1]

Iib c : ¥ch38¥Iib¥c8s26n.Iib [2]

output SMRxd [3]

print SMRxd [4]

start VECT(00000), P(01000), Bramerea(0E100) [5]

exit

[1]: The object file versions of the definition file for the vector table (2138vec.obj) and task files

(SMRxd.obj) are selected as the objects of the linkage.

[2]: Specifies the library (c8s26n.lib) for the H8S/2600 in its normal mode.

[3]: Specifies the object file's name (the output file is called SMRxd.abs).

[4]: Specifies the map file's name (the output file is called SMRxd.map).

[5]: Specifies the starting addresses (in this example, the vector (VECT) is allocated from H'0000,

program (P) from H'1000, and data region that has not been initialized (Bramerea) from H'E100,

respectively in this example).

Figure 4.3 A submit-file

Rev. 2.0, 11/01, page 150 of 358

4.2 Single-Master Transmission

4.2.1 Specification

• Writes 10 bytes of data to the EEPROM (HN58X2408), using channel 0 of the I2C bus

interface for the H8S/2138.

• The data is written to the memory area in the address range from H'00 to H'09 in the connected

EEPROM that has a slave address of [1010000].

• The data written is [H'01, H'02, H'03 , H'04, H'05, H'06, H'07, H'08, H'0 9, and H'0A].

• The device that is connected to the I2C bus of this system has a single-master configuration.

Along with the one master device (H8S/2138), there is one slave device (EEPROM).

• The frequency of the transfer clock is 100 kHz.

• Figure 4.4 illustrates the connection of the H8S/2138 with the EEPROM.

SCL0 SCL

SDA

SDA0

H8S/2138

Master

SCL

SDA

EEPROM

Slave

Figure 4.4 Example of the connection of the H8S/2138 with the EEPROM

• Figure 4.5 shows the I2C bus format used in the task example.

Rev. 2.0, 11/01, page 151 of 358

S SLA A MEA A DATA A

71 11 1

1 1

A P

111

Number of

transmission bits

Number of

transmission frames

Legend:

SLA

MEA

DATA

: Start condition

: Slave address of the EEPROM

: Direction of transmission/reception

: Acknowledge

: Memory address of the EEPROM

: Data being transmitted

: Stop condition

Figure 4.5 Transfer format used in the task example

Rev. 2.0, 11/01, page 152 of 358

4.2.2 Description of the Operation

Figure 4.6 illustrates the principle of operation of single-m a ster transmission.

10µs Transmission clock frequency

100 kHz.

···

Start condition Ack Ack Ack Ack Ack Ack Stop

condition

10th transmission

data = H'0A

Second

transmission

data = H'02

First transmission

data = H'01

Memory address

= H'00

Slave address

+ R/ = H'A0

SCL

SDA

TDRE

IRIC

[4]

[5]

[4] [4]

[3]

[4] [4]

[6]

TDRE=0 (writes data to ICDRT with TRS=1)

TDRE=1 (transmits data from ICDRT to ICDRS)

IRIC=1 (ends data transmission (at rising of ninth clock

of transmission clocks))

No action

IRIC=1 and TDRE=1 (detects start conditions from

the bus line state)

TDRE=0 (detects the stop conditions from the bus line

state)

Software processing Hardware processing

[1]

Writes data for transmission to ICDR0

[2] No action

[3] No action

[4] Clears IRIC to 0 to judge transmission

end

[5] Sets start conditions (BBSY=1, SCP=0)

[6] Issues stop conditions

(BBSY=0, SCP=0)

[2] [2]

[3]

[1]

[2]

[3]

[1]

[2]

[3]

[1]

[2]

[3]

[1]

[2]

[3]

[1] [1]

Figure 4.6 Single-Master Transmission Operation Principle

Rev. 2.0, 11/01, page 153 of 358

4.2.3 Description of the Software

(1) Description of the Module

Table 4.1 describes the modules of this example task.

Table 4.1 Description of the modules

Module name Label name Functions

Main routine main Sets the stack pointer, and the MCU mode. Enables

interrupts.

Initial setting Intialize Initial setting for the IIC0.

Single-master

transmission mst_trs Uses single-master transmission to transmit 10-bytes of

data to the EEPROM.

Setting the start

condition set_start Sets the start condition.

Issuing the stop

condition set_stop Issues the stop condition.

Transmission of the

slave address + W trs_slvadr_a0 Transmits the slave address of the EEPROM + W data

(H'A0).

Transmission of the

memory address of

the EEPROM

trs_memadr Transmits the memory address data of the EEPROM

(H'00).

Rev. 2.0, 11/01, page 154 of 358

(2) Description of the on-chip registers to be used

Table 4.2 describes the on-chip registers that are used in this example task.

Table 4.2 Description of the on-chip registers

Registers Functions Addresses Settings

ICDR0 Stores the data for transmission. H'FFDE —

SAR0 FS Sets the FSX bit in the SARX0, the SW bit in the

DDCSWR, and the transfer format. H'FFDF bit00

SARX0 FSX Sets the FS bit in the SAR0, the SW bit in the

DDCSWR, and the transfer format. H'FFDE bit01

MLS Sets the data transfer as in the MSB-first mode. H'FFDF bit70

WAIT Sets the continuous transfer of the data and

acknowledge. H'FFDF bit60

CKS2

CKS0

Set the frequency of the transfer clock to 100 kHz

by the combination of the values in bits CKS2 to

CKS0 and the IICX0 bit in the STCR.

H'FFDF

bit5 to

bit3

CKS2=1

CKS1=0

CKS0=1

ICMR0

BC2

BC0

Set the number of bits per frame for the subsequent

transfer of data in the I2C bus format to nine. H'FFDF

bit2 to

bit0

BC2=0

BC1=0

BC0=0

ICE Selects the access control for the registers ICMR0,

ICDR0/SAR and SARX. Selects the activation

(SCL0/SDA0 have port functions) or non-activation

of the I2C bus in terface (the SCL/SDA pins are in

the bus-driven state).

H'FFD8 bit70/1

IEIC Disables the generation of interrupt requests by the

I2C bus interface. H'FFD8 bit60

ICCR0

MST Uses the I2C bus interface in the master mode. H'FFD8 bit51

TRS Uses the I2C bus interface in the transmission

mode. H'FFD8 bit41

ACKE Ceases the continuous transfer if the acknowledge

bit equals 1. H'FFD8 bit31

BBSY Determines whether or not the I2C bus is occupied.

Uses the combination of the bits BBSY and SCP to

issue the start or stop condition.

H'FFD8 bit20/1

IRIC Detects the start cond iti on. Jud ges the end of data

transmission. Detects the condition that

acknowle dge = 1.

H'FFD8 bit10/1

ICCR0

SCP Uses the combination of the bits SCP and BBSY to

issue the start or stop condition. H'FFD8 bit00

Rev. 2.0, 11/01, page 155 of 358

Table 4.2 Descriptions of Registers (cont)

Registers Functions Addresses Settings

ICSR0 ACKB Stores the acknowledge data transmitted from the

EEPROM. H'FFD9 bit0—

IICX0 Sets the combination of values in the IICX0 bit and

the bits CKS2 to CKS0 of the ICMR0 to make the

frequency of the tran sfer clo ck 100 kHz.

H'FFC3 bit51

IICE Enables access to the data register and control

registers of the I2C bus interface by the CPU. H'FFC3 bit41

STCR

FLSHE Sets the control registers for the flash memory to

their non-sel ect ed state . H'FFC3 bit3 0

SWE Inhibits automatic switching from format-less to I2C

bus format for IIC channel 0. H'FEE6 bit7 0

SW Uses IIC channel 0 in the I2C bus format. H'FEE6 bit60

IE Inhibits an interrupt in automatic format switching. H'FEE6 bit50

DDCSWR

CLR3

CLR0

Control initialization of the internal state of IIC0. H'FEE6

bit3 to

bit0

CLR3=1

CLR2=1

CLR1=1

CLR0=1

MSTP7 Cancels module stop mode of SCI channel 0. H'FF87 bit7 0MSTPCRL

MSTP4 Cancels module stop mode of IIC channel 0. H'FF87 bit4 0

SCR0 CKE1, 0 Set the P52/SCK0/SCL0 pi n to an I/O port. H'FFDA

bit1, 0 CKE1=0

CKE0=0

SMR0 C/$Sets SCI0 operating mode to asynchronous mode. H'FFD8 bit7 0

SYSCR INTM1, 0 Set interrupt control mode of the interrupt controller

to control by bit 1. H'FFC4

bit5, 4 INTM1=0

INTM0=0

MDCR MDS1, 0 Set MCU operating mode to mode 3 by latching the

input level of pins MD1 and MD0. H'FFC5

bit1, 0 MDS1=1

MDS0=1

Rev. 2.0, 11/01, page 156 of 358

(3) Descriptions of variables

Table 4.3 shows the descriptions of variables in this task example.

Table 4.3 Descriptions of Variables

Variable Function Data

Length Initial

Value Used Module

Name

dt_trs[0] First-byte transmission data 1 byte H'01 mst_trs

dt_trs[1] Second-byte transmission data 1 byte H'02 mst_trs

dt_trs[2] Third-byte transmission data 1 byte H'03 mst_trs

dt_trs[3] Fourth-byte transmission data 1 byte H'04 mst_trs

dt_trs[4] Fifth-byte transmission data 1 byte H'05 mst_trs

dt_trs[5] Sixth-byte transmission data 1 byte H'06 mst_trs

dt_trs[6] Seventh-byte transmission data 1 byte H'07 mst_trs

dt_trs[7] Eighth-byte transmission data 1 byte H'08 mst_trs

dt_trs[8] Ninth-byte transmission data 1 byte H'09 mst_trs

dt_trs[9] Tenth-byte transmission data 1 byte H'0A mst_trs

i Transmission-data counter 1 byte H'00 mst_trs

dummy MDCR read value 1 byte — main

(4) Used RAM descr ipt ions

RAM for other than variables is not u sed in th is task example.

Rev. 2.0, 11/01, page 157 of 358

4.2.4 Flowchart

(1) Main routine

main

SP H'F000 Set stack pointer (SP) to H'F000.

Call initial-setting subroutine.

Clear bit 1 to 0 to enable an interrupt.

Call single master transmission subroutine.

Latch the input level of pins MD1 and MD0

in bits MDS1 and MDS0 by reading MDCR.

Set interrupt control mode of the interrupt

controller to interrupt control by bit 1.

SYSCR H'09

Initialize

CCR 1bit 0

mst_trs

dummy MDCR

············

Rev. 2.0, 11/01, page 158 of 358

(2) Initial-setting subroutine

STCR H'00

MSTPCRL H'7F

DDCSWR H'0F

MSTPCRL H'EF

ICMR0 H'28

ICCR0 H'01

SAR0 H'00

ICSR0 H'00

STCR H'30

ICCR0 H'89

SARX0 H'01

ICCR0 H'81

SMR0 H'00

SCR0 H'00

STCR H'10

Set bit FLSHE of STCR to 0 to set the control register of

flash memory to non-select state.

Set bit MSTP7 of MSTPCRL to 0 to cancel module stop

mode of SCI0.

Set ICE of ICCR0 to 0 to enable access to SAR0 and SARX0.

Set ICE of ICCR0 to 1 to enable access to ICMR0 and ICDR0.

Set ACKB of ICSR0 to 0.

Set SWE, SW, and IE of DDCSWR to 0. Inhibit automatic switch

from format-less of IIC0 to I

C bus format, use IIC0 in I

C bus format,

and inhibit an interrupt in automatic format switching.

Set bit MSTP7 of MSTPCRL to 1 and bit MSTP4 to 0 to set

module stop mode of SCI0 and cancel module stop mode of IIC0.

Set bit C/ of SMR to 0 to set SCI0 operating mode

to asynchronous mode.

Set bit IICE of STCR to 1 to enable CPU access to the data register

and control register of the I

C bus interface.

Set bits CKE1 and CKE of SMR to 0 to set pin SCK0 to an I/O port.

Set FS of SAR0 and FSX of SARX0 to 0 to select I

C bus format

for IIC0 transmission format (recognize SAR slave address and

ignore SARX slave address).

Set IICX0 of STCR and CKS2 and CKS0 of ICMR0 to 1 and CKS1 to 0.

Set IIC0 transmission clock frequency to 100 kHz, set WAI to 0, and

continuously transfer data and acknowledge.

Set IEIC ICCR0 to 0 to inhibit IIC0 interrupt request.

Set ACKE to 1 to halt continuous transmission when the acknowledge

bit is 1.

initialize

rts

············

·······

············

·······

Rev. 2.0, 11/01, page 159 of 358

(3) Single-master transmission subroutine

setstart

mst_trs

MST 1

TRS 1

trs_slvadr_a0

trs_memadr

i 0

ICDR0 A[i]

IRIC 0

set_start

ACKB = 0 ?

Yes

BBSY = 0 ?

Yes

IRIC = 1 ?

i = 0 ?

i++

···············

·········

···············

·········

···············

·········

············

······

Call the slave address + W transmission subroutine.

·········

···············

Bus release state?

Set MST and TRS of ICCR0 to 1 to set IIC0 mode

to master transmission mode.

Call the subroutine that sets the start condition.

Are there acknowledge from EEPROM?

Call the EEPROM memory address transmission subroutine.

Are there acknowledge from EEPROM?

Initially set the transmission data counter.

10-byte transmission end?

Write ith-byte transmission data in ICDR0.

Clear IRIC to 0 to decide data-transmission end

(at rising of ninth clock of transmission clocks).

Data transmission end?

Are there acknowledge from EEPROM?

Increment the transmission data counter.

ACKB = 0 ? 1

ACKB = 0 ? No 1

Rev. 2.0, 11/01, page 160 of 358

rts

·····················

·········

BBSY = 0 ? No

Yes

Bus release state?

Call the subroutine that sets the start condition.

set_stop

(4) Subroutine that sets the start condition

set_start

rts

IRIC 0

ICCR0 H'BC

··················

······

IRIC = 1 ? No

Yes

Clear IRIC to decide start condition detection.

Set BBSY of ICCR0 to 1 and SCP to 0 to issue the start condition.

Is the start condition detected from the bus line state?

(5) Subroutine that sets the stop condition

set_stop

rts

ICCR0 H'B8 ··················

······

BBSY = 0 ? No

Yes

Set BBSY and SCP of ICCR0 to 0 to issue the stop condition.

Bus release state?

Rev. 2.0, 11/01, page 161 of 358

(6) Slave address + W transmission subroutine

trs_slvadr_a0

rts

ICCR0 H'A0

IRIC 0

··················

·······

IRIC = 1 ? No

Yes

Transmit the EEPROM slave address + W data (H'A0).

Clear IRIC to 0 to decide data-transmission end

(at rising of ninth clock of transmission clocks).

EEPROM slave address + W data transmission end?

(7) EEPROM memory address transmissio n subroutine

trs_memadr

rts

ICCR0 H'00

IRIC 0

··················

······

IRIC = 1 ? No

Yes

Transmit EEPROM memory address data (H'00).

Clear IRIC to 0 to decide data-transmission end

(at rising of ninth clock of transmission clocks).

EEPROM memory address data transmission end?

Rev. 2.0, 11/01, page 162 of 358

4.2.5 Program List

/*****************************************************

* H8S/2138 IIC bus application note *

* 1.Single master transmit to EEPROM *

* File name : SMTxd.c *

* Fai : 20MHz *

* Mode : 3 *

******************************************************/

#include <stdio.h>

#include <machine.h>

#include "2138s.h"

/*****************************************************

* Prototype *

******************************************************/

void main(void); /* Main routine */

void initialize(void); /* IIC0 initialize */

void mst_trs(void); /* Master transmit to EEPROM */

void set_start(void); /* Start condition set */

void set_stop(void); /* Stop condition set */

void trs_slvadr_a0(void); /* Slave address + W data transmit */

void trs_memadr(void); /* EEPROM memory address data transmit */

/*****************************************************

* Data table *

******************************************************/

const unsigned char dt_trs[10] = /* Transmit data (10 byte) */

{

0x01, /* 1st transmit data */

0x02, /* 2nd transmit data */

0x03, /* 3rd tranmist data */

0x04, /* 4th tranmist data */

0x05, /* 5th tranmist data */

0x06, /* 6th tranmist data */

0x07, /* 7th tranmist data */

0x08, /* 8th tranmist data */

Rev. 2.0, 11/01, page 163 of 358

0x09, /* 9th tranmist data */

0x0a /* 10th tranmist data */

};

/*****************************************************

* main : Main routine *

******************************************************/

void main(void)

#pragma asm

mov.l #h'f000,sp ;Stack pointer initialize

#pragma enda sm

{

unsigned char dummy;

dummy = MDCR.BYTE; /* MCU mode set */

SYSCR.BYTE = 0x09; /* Interrupt control mode set */

initialize(); /* Initialize */

set_imask_ccr(0); /* Interrupt enable */

mst_trs(); /* Master transmit to EPROM */

while(1); /* End */

}

/*****************************************************

* initialize : IIC0 Initialize *

******************************************************/

void initialize(void)

{

STCR.BYTE = 0x00; /* FLSHE = 0 */

MSTPCR.BYTE.L = 0x7f; /* SCI0 module stop mode reset */

SCI0.SMR.BYTE = 0x00; /* SCL0 pin function set */

SCI0.SCR.B YTE = 0x00 ;

MSTPCR.BYTE.L = 0xef; /* IIC0 module stop mode reset */

STCR.BYTE = 0x10; /* IICE = 1 */

DDCSWR.BYTE = 0x0f; /* IIC bus format initialize */

IIC0.ICCR.BYTE = 0x01; / * ICE = 0 */

IIC0.SAR.BYTE = 0x00; /* FS = 0 */

IIC0.SARX.BYTE = 0x01; / * FSX = 1 */

Rev. 2.0, 11/01, page 164 of 358

IIC0.ICCR.BYTE = 0x81; / * ICE = 1 */

IIC0.ICSR.BYTE = 0x00; /* ACKB = 0 */

STCR.BYTE = 0x30; /* IICX0 = 1 */

IIC0.ICMR.BYTE = 0x28; /* Transfer rate = 100kHz */

IIC0.ICCR.BYTE = 0x89; /* IEIC = 0, ACKE = 1 */

}

/*****************************************************

* mst_trs : Master transmit to EEPROM *

******************************************************/

void mst_trs(void)

{

unsigned char i; /* Tranmit data counter */

while(IIC0.ICCR.BIT.BBSY == 1); /* Bus empty (BBSY=0) ? */

IIC0.ICCR.BIT.MST = 1; /* Master transmit mode set */

IIC0.ICCR.BIT.TRS = 1; /* MST = 1, TRS = 1 */

set_start(); /* Start condition set */

trs_slvadr_a0(); /* Slave address + W data transmit */

if(IIC0.ICSR.BIT.ACKB == 0)

{

trs_memadr(); /* EEPROM memory address data transmit */

if(IIC0.ICSR.BIT.ACKB == 0)

{

for(i=0; i<10; i++)

{

IIC0.ICDR = dt_trs[i]; /* Transmit data write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

if(IIC0.ICSR.BIT.ACKB == 1) /* ACKB = 0 ? */

{

break; /* ACKB = 1 */

}

Rev. 2.0, 11/01, page 165 of 358

}

set_stop(); /* Stop condition set */

}

/*****************************************************

* set_start : Start condition set *

******************************************************/

void set_start(void)

{

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

IIC0.ICCR.BYTE = 0xbc; /* Start condition set (BBSY=1,SCP=0) */

while(IIC0.ICCR.BIT.IRIC == 0); /* Start condition set (IRIC=1) ? */

}

/*****************************************************

* set_stop : Stop condition set *

******************************************************/

void set_stop(void)

{

IIC0.ICCR.BYTE = 0xb8; /* Stop condition set (BBSY=0,SCP=0) */

while(IIC0.ICCR.BIT.BBSY == 1); /* Bus empty (BBSY=0) ? */

}

/*****************************************************

* trs_slvadr_a0 : Slave addres + W data transmit *

******************************************************/

void trs_slvadr_a0(void)

{

IIC0.ICDR = 0xa0; /* Slave address + W data(H'A0) write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

Rev. 2.0, 11/01, page 166 of 358

/*****************************************************

* trs_memadr : EEPROM memory address data transmit *

******************************************************/

void trs_memadr(void)

{

IIC0.ICDR = 0x00; /* EEPROM memory address data(H'00) write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

Rev. 2.0, 11/01, page 167 of 358

4.3 Single-Master Reception

4.3.1 Specifications

• The I2C bus interface of channel 0 in H8S/2138 is used to read 10-byte data from EEPROM

(HN58X2408).

• The slave address of EEPROM to be connected is “1010000”, and data is read from H'00 to

H'09 of EEPROM memory addresses.

• Read data is stored in H'E100 to H'E1009 of RAM.

• Devices connected to the I2C bus of this system consist of a master device (H8S/2138) and a

slave device (EEPROM) (single-master configuration).

• The frequency of a transmission clock is 100 kHz.

• Figure 4.7 shows the connection example of H8S/2138 and EEPROM.

VCC

VSS

SCL0 SCL

SDA

SDA0

VCC

H8S/2138

Master

VCC

VSS

SCL

SDA

EEPROM

Slave

VCC VCC

VCC

Figure 4.7 Connection Example of H8S/2138 and EEPROM

• Figure 4.8 shows the I2C bus format used in this task example.

Rev. 2.0, 11/01, page 168 of 358

S SLA A MEA A DATA A

71 11 SLAS

1 1

711

8A P

111

R/ A

R/ Number of

transmission

bits

Number of

transmission

frames

Legend:

SLA

MEA

DATA

: Start condition

: EEPROM slave address

: Transmission/reception direction

: Acknowledge

: EEPROM memory address

: Reception data

: Stop condition

Figure 4.8 Transmission Format Used in this Task Example

Rev. 2.0, 11/01, page 169 of 358

4.3.2 Operation Descriptions

Figures 4.9 and 4.10 show the operation principle.

Rev. 2.0, 11/01, page 170 of 358

10µs Transmission/reception clock frequency = 100 kHz

Start condition

Software Processing Hardware Processing

IRIC = 1, TDRE = 1 (detects start conditions from the bus line state)

TDRE = 0 (writes data to ICDRT when TRS = 1)

TDRE = 1 (transmits data to ICDRS from ICDRT)

IRIC = 1 (ends data transmission

(at rising of 9th transmission clock))

No processing

TDRE = 0 (when TRS = 0)

IRIC = 1 (ends data reception (at rising of 9th reception

clock))

RDRF = 0 (reads reception data of ICDRR in reception mode)

No processing

Start

condition

Ack Ack Ack Ack Ack

2nd

reception

data

3rd

reception

data

1st

reception

data

Memory address

=H'00

Slave address

+ R/ =H'A0 Slave address

+ R/ =H'A1

SCL

SDA

TDRE

IRIC

RDRF

[1] [5] [5] [5][1]

[2] [6][2]

[3][3] [3]

[4] [4]

[7] [10] [10] [10]

[9] [9]

[8] [8]

[4]

···

[2]

Issues start conditions (BBSY = 1, SCP = 0)

Writes transmission data to ICDR0

No processing

Clears IRIC to 0 to judge transmission end

Clears IRIC to 0 to judge start condition detection

Sets master reception mode (MST = 1, TRS = 0)

No processing

Reads reception data from ICDR0

Clears IRIC to 0 to judge reception end

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

Figure 4.9 Single-Master Reception Operation Principle (1)

Rev. 2.0, 11/01, page 171 of 358

10µs Transmission/reception clock frequency = 100 kHz

Software Processing Hardware Processing

Stop condition

Ack Ack Ack Ack Ack

6th reception

data

7th reception

data

8th reception

data 9th reception

data 10th reception

data

SCL

SDA

TDRE

IRIC

RDRF

[11]

[13]

[14]

[11]

[13]

[14]

[11]

[13]

[14]

[11]

[18]

[14]

[12]

[17]

[15]

[16]

···

No processing

Reads reception data from ICDR0

Clears IRIC to 0 to judge reception end

Clears IRIC to 0 to judge output end of

the 9th reception clock

Sets master transmission mode

(MST = 1, TRS = 0)

Issues stop conditions

(BBSY = 0, SCP = 0)

[11]

[12]

[13]

[14]

[15]

[16]

[17]

IRIC = 1, RDRF = 1 (WAIT = 0) (ends data reception

(at rising of 9th reception clock))

IRIC = 1, RDRF = 1 (WAIT = 1) (ends data reception

(at rising of 8th reception clock))

RDRF = 0 (reads reception data of ICDRR in reception mode)

No processing

Starts output of 9th reception clock

IRIC = 1 (at rising of 9th reception clock)

TDRE = 1 (when TRS = 0 is switched to TRS = 1

after start condition detection)

TDRE = 0 (detects stop conditions from the bus line

state after stop condition issue)

Figure 4.10 Single-Master Reception Operation Principle (2)

Rev. 2.0, 11/01, page 172 of 358

4.3.3 Software Descriptions

(1) Descriptions of modules

Table 4.4 shows the descriptions of modules in this task example.

Table 4.4 Descriptions of Modules

Module Name Label Name Function

Main routine main Sets stack pointer, sets MCU mode, and enables an

interrupt.

Initial setting intialize Initially sets IIC0 and RAM area to be used.

Single master

reception mst_rec Receives 10-byte data from EEPROM by single master

reception.

Start condition issue set_start Issues start conditions.

Stop condition issue set_stop Issues stop conditions.

Slave address + W

transmission trs_slvadr_a0 Transmits slave address + W data (H'A0) of EEPROM.

Slave address + R

transmission trs _ slvadr_a1 Transmits slave address + R data (H'A1) of EEPROM.

EEPROM memory

address tran sm iss iontrs_memadr Transmits memory address data (H'00) of EEPROM.

Data reception rec_data Receives 10-byte data.

Rev. 2.0, 11/01, page 173 of 358

(2) Descriptions of internal registers

Table 4.5 shows the descriptions of internal registers to be used in this task example.

Table 4.5 Descriptions of Registers

ICDR0 Stores reception data. H'FFDE —

SAR0 FS Sets transmission format by using bit FSX of SAR0

and bit SW of DDCSWR. H'FFDF bit00

SARX0 FSX Sets transmission format by using bit FS of SAR0

and bit SW of DDCSWR. H'FFDE bit01

MLS Sets data transmission by MSB-first. H'FFDF bit70

WAIT Sets whether waits are inserted between data and

acknowledge. H'FFDF bit60/1

CKS2

CKS0

Set transmission clock frequency to 100 kHz by

using bit IICX0 of STCR. H'FFDF

bit5 to

bit3

CKS2=1

CKS1=0

CKS0=1

ICMR0

BC2

BC0

Set 9 bits/frame to the number of bits of data to be

transmitted next in I2C bus format. H'FFDF

bit2 to

bit0

BC2=0

BC1=0

BC0=0

ICE Selects access control of registers ICMR0,

ICDR0/SAR, and SARX, and I2C bus interfac e

operation (port function for pin SCL0/SDA0)/non-

operation (bus drive state for pin SCL/SDA).

H'FFD8 bit70/1

IEIC Inhibits I2C bus interface interrupt requests. H'FFD8 bit60

MST Uses the I2C bus interface in master mode. H'FFD8 bit51

TRS Sets transmission/reception mode of the I2C bus

interface. H'FFD8 bit41/0

ACKE Halts continuous transmission when the

acknowle dge bit is 1. H'FFD8 bit3 1

BBSY Confirms that the I2C bus is occupied or releas ed,

and issues start and stop conditions by using bit

SCP.

H'FFD8 bit20/1

IRIC Detects start conditions, decides data transmission

end, and detects acknowledge = 1. H'FFD8 bit10/1

ICCR0

SCP Issues start and stop conditions by using bit BBSY. H'FFD8 bit00

ICSR0 ACKB Stores acknowledge received from EEPROM at

transmissi on, and sets acknowle dge to be

transmitted to EEPROM at reception.

H'FFD9 bit0—

Rev. 2.0, 11/01, page 174 of 358

Table 4.5 Descriptions of Registers (cont)

IICX0 Sets transmission clock frequency to 100 kHz by

using CKS2 to CKS0 of ICMR0. H'FFC3 bit51

IICE Enables CPU ac cess to the data register and

control register of the I2C bus interface. H'FFC3 bit4 1

STCR

FLSHE Sets a non-select state to the control register of

flash memory. H'FFC3 bit30

SWE Inhibits automatic switching from format-less to I2C

bus format for IIC channel 0. H'FEE6 bit7 0

SW Uses IIC channel 0 in the I2C bus format. H'FEE6 bit60

IE Inhibits an interrupt in automatic format switching. H'FEE6 bit50

DDCSWR

CLR3

CLR0

Control initialization of the internal state of IIC0. H'FEE6

bit3 to

bit0

CLR3=1

CLR2=1

CLR1=1

CLR0=1

MSTP7 Cancels module stop mode of SCI channel 0. H'FF87 bit7 0MSTPCRL

MSTP4 Cancels module stop mode of IIC channel 0. H'FF87 bit4 0

SCR0 CKE1, 0 Set the P52/SCK0/SCL0 pi n to an I/O port. H'FFDA

bit1, 0 CKE1=0

CKE0=0

SMR0 C/$Sets SCI0 operating mode to asynchronous mode. H'FFD8 bit7 0

SYSCR INTM1, 0 Set interrupt control mode of the interrupt controller

to control by bit 1. H'FFC4

bit5, 4 INTM1=0

INTM0=0

MDCR MDS1, 0 Set MCU operating mode to mode 3 by latching the

input level of pins MD1 and MD0. H'FFC5

bit1, 0 MDS1=1

MDS0=1

(3) Descriptions of variables

Table 4.6 shows the descriptions of variables in this task example.

Table 4.6 Descriptions of Variables

Variable Function Data

Length Initial

Value Used Module

Name

dummy MDCR read value 1 byte — Main

i Transmission-data counter 1 byte H'00 initialize rec_data

Rev. 2.0, 11/01, page 175 of 358

(4) Used RAM descr ipt ions

Table 4.7 shows the descriptions of used RAM in this task example.

Table 4.7 Descriptions of Used R AM

Label Function Data

Length Address Used Module

Name

dt_rec[i] Stores received data 10 bytes H'E100

H'E109

initialize

rec_data

4.3.4 Flowchart

(1) Main routine

main

SP H'F000 Set stack pointer (SP) to H'F000.

Call initial-setting subroutine.

Clear bit 1 to 0 to enable an interrupt.

Call single master transmission subroutine.

Latch the input level of pins MD1 and MD0

in bits MDS1 and MDS0 by reading MDCR.

Set interrupt control mode of the interrupt

controller to interrupt control by bit 1.

SYSCR H'09

initialize

CCR Ibit 0

mst_rec

Read MDCR

············

Rev. 2.0, 11/01, page 176 of 358

(2) Initial-setting subroutine

STCR H'00

MSTPCRL H'7F

DDCSWR H'0F

MSTPCRL H'EF

ICMR0 H'28

ICCR0 H'01

SAR0 H'00

ICSR0 H'00

STCR H'30

ICCR0 H'89

SARX0 H'01

ICCR0 H'81

SMR0 H'00

SCR0 H'00

STCR H'10

initialize

rts

············

······

············

······

Set bit FLSHE of STCR to 0 to set the control register

of flash memory to non-select state.

Set bit MSTP7of MSTPCRL to 0 to cancel module stop mode of SCI0.

Set bit C/ of SMR to 0 to set SCI0 operating mode to asynchronous mode.

Set bits CKE1 and CKE of SMR to 0 to set pin SCK0 to an I/O port.

Set bit MSTP7 of MSTPCRL to 1 and bit MSTP4 to 0 to set module

stop mode of SCI0 and cancel module stop mode of IIC0.

Set bit IICE of STCR to 1 to enable CPU access to the data register

and control register of the I

C bus interface.

Set ICE of ICCR0 to 0 to enable access to SAR0 and SARX0.

Set SWE, SW, and IE of DDCSWR to 0. Inhibit automatic switch from

format-less of IIC0 to I

C bus format, use IIC0 in I

C bus format,

and inhibit an interrupt in automatic format switching.

Set FS of SAR0 and FSX of SARX0 to 0 to select I

C bus format

for IIC0 transmission format (recognize SAR slave address and

ignore SARX slave address).

Set ICE of ICCR0 to 1 to enable access to ICMR0 and ICDR0.

Set ACKB of ICSR0 to 0.

Set IICX0 of STCR and CKS2 and CKS0 of ICMR0 to 1 and

CKS1 to 0. Set IIC0 transmission clock frequency to 100 kHz,

set WAI to 0, and continuously transfer data and acknowledge.

Set IEIC ICCR0 to 0 to inhibit IIC0 interrupt request.

Set ACKE to 1 to halt continuous transmission when

the acknowledge bit is 1.

Rev. 2.0, 11/01, page 177 of 358

(3) Single master reception subroutine

set_start

mst_rec

rts

MST 1

TRS 1

trs_slvadr_a0

trs_memadr

trs_slvadr_a1

set_stop

set_start

rec_data

ACKB 0

WAIT 0

set_start

ACKB = 0 ?

Yes

BBSY = 0 ?

············

······

Transmit the EEPROM slave address + W data.

Bus release state?

Set MST and TRS of ICCR0 to 1 to set IIC0 mode

to master transmission mode.

Issue the start condition.

Are there acknowledge from EEPROM?

Transmit the EEPROM memory address data.

Are there acknowledge from EEPROM?

············ Issue the restart condition.

············ Transmit the EEPROM slave address + R data.

············ Are there acknowledge from EEPROM?

············ Receive 10-byte data.

············ ACKB = 0

············ WAIT = 0

············ Issue the stop condition.

ACKB = 0 ?

set_start

ACKB = 0 ?

Rev. 2.0, 11/01, page 178 of 358

(4) Subroutine that sets the start condition

set_start

rts

IRIC 0

ICCR0 H'BC

············

······

IRIC = 1 ? No

Yes

Clear IRIC to decide start condition detection.

Set BBSY of ICCR0 to 1 and SCP to 0 to issue the start condition.

Is the start condition detected from the bus line state?

(5) Subroutine that sets the stop condition

set_stop

rts

ICCR0 H'B8 ····················

·········

BBSY = 0 ? No

Yes

Set BBSY and SCP of ICCR0 to 0 to issue the stop condition.

Bus release state?

Rev. 2.0, 11/01, page 179 of 358

(6) Slave address + W transmission subroutine

trs_slvadr_a0

rts

ICCR0 H'A0

IRIC 0

············

······

IRIC = 1 ? No

Yes

Transmit the EEPROM slave address + W data (H'A0).

Clear IRIC to 0 to decide data-transmission end

(at rising of ninth clock of transmission clocks).

EEPROM slave address + W data transmission end?

(7) Slave address + R transmission subroutine

trs_memadr

rts

ICCR0 H'A1

IRIC 0

···············

·········

IRIC = 1 ? No

Yes

Transmit the EEPROM slave address + R data (H'A1).

Clear IRIC to 0 to decide data-transmission end

(at rising of ninth clock of transmission clocks).

EEPROM memory address data transmission end?

Rev. 2.0, 11/01, page 180 of 358

(8) EEPROM memory address transmissio n subroutine

trs_memadr

rts

ICCR0 H'00

IRIC 0

···············

·········

IRIC = 1 ? No

Yes

Transmit EEPROM memory address data (H'00).

Clear IRIC to 0 to decide data-transmission end

(at rising of ninth clock of transmission clocks).

EEPROM memory address data transmission end?

Rev. 2.0, 11/01, page 181 of 358

(9) Data reception subroutine

ACKB 0

rec_data

i 0

TRS 0

WAIT 0

dt_rec[i] ICDR0

IRIC 0

dt_rec[i] ICDR0

IRIC 0

IRIC = 1 ?

Yes

IRIC = 1 ?

i 8 ?

i++

···············

············

Clear IRIC to 0 to decide data-reception end

(at rising of ninth clock of reception clocks).

Dummy read (start reception)

Data reception end?

···············

Initially set the reception data counter.

TRS = 0 (set master reception mode)

ACKB = 0 (output 0 at acknowledge output timing in reception)

WAIT = 0 (continuously transmit data and acknowledge)

Initially set the reception data counter.

8-byte reception end?

Read reception data and store it in RAM.

Clear IRIC to 0 to decide data-reception end

(at rising of ninth clock of reception clocks).

Data reception end?

Increment the reception data counter.

Rev. 2.0, 11/01, page 182 of 358

dt_rec[i]

ICDR0

WAIT

TRS

ACKB

IRIC

i++

dt_rec[i]

ICDR0

IRIC = 1 ?

Yes

IRIC = 1 ?

··················

···············

Clear IRIC to 0 to decide data-reception end

(at falling of eighth clock of reception clocks).

··················

Read ninth-byte reception data and store it in RAM.

Data reception end?

·················· WAIT = 1 (Insert wait between data and acknowledge)

·················· ACKB = 1 (output 1 at acknowledge output timing in reception)

TRS = 1 (set master transmission mode)

IRIC = 0 (start output of ninth reception clock)

Is output of ninth reception clock completed

(at rising of ninth clock of reception clocks)?

Read tenth-byte reception data and store it in RAM.

·················· Increment the reception data counter.

rts

Rev. 2.0, 11/01, page 183 of 358

4.3.5 Program List

/*****************************************************

* H8S/2138 IIC bus application note *

* 2.Single master receive from EEPROM *

* File name : SMRxd.c *

* Fai : 20MHz *

* Mode : 3 *

******************************************************/

#include <stdio.h>

#include <machine.h>

#include "2138s.h"

/*****************************************************

* Prototype *

******************************************************/

void main(void); /* Main routine */

void initialize(void); /* RAM & IIC0 initialize */

void mst_rec(void); /* Matser receive from EEPROM */

void set_start(void); /* Start condition set */

void set_stop(void); /* Stop condition set */

void trs_slvadr_a0(void); /* Slave address + W data transmit */

void trs_slvadr_a1(void); /* Slave address + R data transmit */

void trs_memadr(void); /* EEPROM memory address data transmit */

void rec_data(void); /* 10-byte data receive */

/*****************************************************

* RAM allocation *

******************************************************/

#pragma sect ion rama re a

unsigned char dt_rec[10]; /* Receive data store area */

/*****************************************************

* main : Main routine *

******************************************************/

#pragma sect ion

void main(void)

Rev. 2.0, 11/01, page 184 of 358

#pragma asm

mov.l #h'f000,sp /* Stack pointer initialize */

#pragma enda sm

{

unsigned char dummy;

dummy = MDCR.BYTE; /* MCU mode set */

SYSCR.BYTE = 0x09; /* Interrupt control mode set */

initialize(); /* Initialize */

set_imask_ccr(0); /* Interrupt enable */

mst_rec(); /* Master receive from EPROM */

while(1); /* End */

}

/*****************************************************

* initialize : RAM & IIC0 Initialize *

******************************************************/

void initialize(void)

{

unsigned char i=0;

for(i=0; i<10; i++) /* Receive data store area initialize */

{

dt_rec[i] = 0x00;

}

/* IIC0 module initialize */

STCR.BYTE = 0x00; /* FLSHE = 0 */

MSTPCR.BYTE.L = 0x7f; /* SCI0 module stop mode reset */

SCI0.SMR.BYTE = 0x00; /* SCL0 pin function set */

SCI0.SCR.B YTE = 0x00 ;

MSTPCR.BYTE.L = 0xef; /* IIC0 module stop mode reset */

STCR.BYTE = 0x10; /* IICE = 1 */

DDCSWR.BYTE = 0x0f; /* IIC bus format initialize */

IIC0.ICCR.BYTE = 0x01; /* ICE = 0 */

IIC0.SAR.BYTE = 0x00; /* FS = 0 */

IIC0.SARX.BYTE = 0x01; /* FSX = 1 */

IIC0.ICCR.BYTE = 0x81; /* ICE = 1 */

Rev. 2.0, 11/01, page 185 of 358

IIC0.ICSR.BYTE = 0x00; /* ACKB = 0 */

STCR.BYTE = 0x30; /* IICX0 = 1 */

IIC0.ICMR.BYTE = 0x28; /* Transfer rate = 100kHz */

IIC0.ICCR.BYTE = 0x89; /* IEIC = 0, ACKE = 1 */

}

/*****************************************************

* mst_rec : Master receive from EEPROM *

******************************************************/

void mst_rec(void)

{

while(IIC0.ICCR.BIT.BBSY == 1); /* Bus empty (BBSY=0) ? */

IIC0.ICCR.BIT.MST = 1; /* Mster transmit mode set */

IIC0.ICCR.BIT.TRS = 1; /* MST = 1, TRS = 1 */

set_start(); /* Start condition set */

trs_slvadr_a0(); /* EEPROM slave address + W data transmit */

if(IIC0.ICSR.BIT.ACKB == 0) /* ACKB = 0 ? */

{

trs_memadr(); /* EEPROM memory address data transmit */

if(IIC0.ICSR.BIT.ACKB == 0) /* ACKB = 0 ? */

{

set_start(); /* Re-start condition set */

trs_slvadr_a1(); /* EEPROM slave address + R data transmit */

if(IIC0.ICSR.BIT.ACKB == 0) /* ACKB = 0 ? */

{

rec_data(); /* Data recieve */

}

set_stop();

}

/*****************************************************

* set_start : Start condition set *

******************************************************/

Rev. 2.0, 11/01, page 186 of 358

void set_start(void)

{

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

IIC0.ICCR.BYTE = 0xbc; /* Start condition set (BBSY=1,SCP=0) */

while(IIC0.ICCR.BIT.IRIC == 0); /* Start condition set (IRIC=1) ? */

}

/*****************************************************

* set_stop : Stop condition set *

******************************************************/

void set_stop(void)

{

IIC0.ICCR.BYTE = 0xb8; /* Stop condition set (BBSY=0,SCP=0) */

while(IIC0.ICCR.BIT.BBSY == 1); /* Bus empty (BBSY=0) ? */

}

/*****************************************************

* trs_slvadr_a0 : Slave address + W data transmit *

******************************************************/

void trs_slvadr_a0(void)

{

IIC0.ICDR = 0xa0; /* Slave address + W data(H'A0) write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

/*****************************************************

* trs_slvadr_a1 : Slave address + R data transmit *

******************************************************/

void trs_slvadr_a1(void)

{

IIC0.ICDR = 0xa1; /* Slave address + R data(H'A1) write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

Rev. 2.0, 11/01, page 187 of 358

/*****************************************************

* trs_memadr : EEPROM memory address data transmit *

******************************************************/

void trs_memadr(void)

{

IIC0.ICDR = 0x00; /* EEPROM memory address data(H'00) write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

/*****************************************************

* rec_data : 10-byte data receive *

******************************************************/

void rec_data(void)

{

unsigned char i=0; /* Receive data counter initialize */

IIC0.ICCR.BIT.TRS = 0; /* Master transmit mode set (MST=1,TRS=0) */

IIC0.ICSR.BIT.ACKB = 0; /* ACKB = 0 */

IIC0.ICMR.BIT.WAIT = 0; /* WAIT = 0 */

dt_rec[i] = IIC0.ICDR; /* Dummy read */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* receive end (IRIC=1) ? */

for(i=0; i<8; i++) /* 1st to 8th data receive */

{

dt_rec[i] = IIC0.ICDR; /* Receive data read */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Receive end ? */

}

IIC0.ICMR.BIT.WAIT = 1; /* WAIT = 1 */

IIC0.ICSR.BIT.ACKB = 1; /* ACKB = 1 */

dt_rec[i] = IIC0.ICDR; /* 9th receive data read */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Receive end (IRIC=1) ? */

Rev. 2.0, 11/01, page 188 of 358

IIC0.ICCR.BIT.TRS = 1; /* Master transmit mode set (MST=1,TRS=1) */

IIC0.ICCR.BIT.IRIC = 0; /* 9th clock transmit (IRIC=0) */

while(IIC0.ICCR.BIT.IRIC == 0); /* 9th clock transmit end (IRIC=1) ? */

dt_rec[++i] = IIC0.ICDR; /* 10th (last) receive data read */

IIC0.ICSR.BIT.ACKB = 0; /* ACKB = 0 */

IIC0.ICMR.BIT.WAIT = 0; /* WAIT = 0 */

}

Rev. 2.0, 11/01, page 189 of 358

4.4 One-Byte Data Transmission by Single-Master Transmission

4.4.1 Specifications

• The I2C bus interface of channel 0 in H8S/2138 is used to write 1-byte data to EEPROM

(HN58X2408).

• The slave address o f EEPROM to be co nnected is “1010000”, and data is written to H'00 of

EEPROM memory addresses.

• Devices connected to the I2C bus of this system consist of a master device (H8S/2138) and a

slave device (EEPROM) (single master configuration).

• The frequency of a transmission clock is 100 kHz.

• Figure 4.11 shows the connection example of H8S/2138 and EEPROM.

SCL0 SCL

SDA

SDA0

H8S/2138

Master

SCL

SDA

EEPROM

Slave

Figure 4.11 Connection Example of H8S/2138 and EEPROM

• Figure 4.12 shows the I2C bus format used in this task example.

Rev. 2.0, 11/01, page 190 of 358

S SLA A MEA A DATA A

71 11 1

111

118

Number of transmission bits

Number of transmission frames

Legend:

SLA

MEA

DATA

: Start condition

: EEPROM slave address

: Transmission/reception direction

: Acknowledge

: EEPROM memory address

: Transmission data

: Stop condition

Figure 4.12 Transmission Format Used in this Task Example

Rev. 2.0, 11/01, page 191 of 358

4.4.2 Operation Descriptions

Figure 4.13 shows an operation principle.

10µs Transmission clock frequency = 100 kHz

Start condition Stop condition

Ack Ack

1st transmission data

=H'38

Memory address

=H'00

Slave address

+ R/ =H'A0

SCL

SDA

TDRE

IRIC

[5] [4]

Ack

[1]

[2]

[3] [4]

[1]

[2]

[3] [3] [6]

[4]

[1]

[2]

Writes transmission data to ICDR0

No processing

Clears IRIC to 0 to judge transmission end

Issues start conditions (BBSY = 1, SCP = 0)

Issues stop conditions (BBSY = 0, SCP = 0)

Software Processing Hardware Processing

[1]

[2]

[3]

[4]

[5]

[6]

TDRE = 0 (writes data to ICDRT when TRS = 1)

TDRE = 1 (transmits data to ICDRS from ICDRT)

IRIC = 1 (ends data transmission

(at rising of 9th reception clock))

No processing

IRIC = 1, TDRE = 1

(detects start conditions from the bus line state)

TDRE = 0 (detects stop conditions from the bus line state)

Figure 4.13 One-byte Data Transmission Operation Principle by Single Master

Transmission

Rev. 2.0, 11/01, page 192 of 358

4.4.3 Software Descriptions

(1) Descriptions of modules

Table 4.8 shows the descriptions of modules in this task example.

Table 4.8 Descriptions of Modules

Module Name Label Name Function

Main routine main Sets stack pointer, sets MCU mode, and enables an

interrupt.

Initial setting Intialize Initially sets IIC0.

Single master

transmission mst_trs Transmits 1-byte data to EEPROM by single master

transmission.

Start condition issue set_start Issues start conditions.

Stop condition issue set_stop Issues stop conditions.

Slave address + W

transmission trs_slvadr_a0 Transmits slave address + W data (H'A0) of EEPROM.

EEPROM memory

address tran sm iss iontrs_memadr Transmits memory address data (H'00) of EEPROM.

(2) Descriptions of internal registers

Table 4.9 shows the descriptions of internal registers to be used in this task example.

Rev. 2.0, 11/01, page 193 of 358

Table 4.9 Descriptions of Registers

ICDR0 Stores transmission data. H’FFDE —

SAR0 FS Sets transmission format by using bit FSX of SAR0

and bit SW of DDCSWR. H’FFDF bit00

SARX0 FSX Sets transmission format by using bit FS of SAR0

and bit SW of DDCSWR. H’FFDE bit01

MLS Sets data transmission by MSB-first. H’FFDF bit70

WAIT Sets continuous transmission of data and

acknowledge. H’FFDF bit60

CKS2

CKS0

Set transmission clock frequency to 100 kHz by

using bit IICX0 of STCR. H’FFDF

bit5 to

bit3

CKS2=1

CKS1=0

CKS0=1

ICMR0

BC2

BC0

Set 9 bits/frame to the number of bits of data to be

transmitted next in I2C bus format. H’FFDF

bit2 to

bit0

BC2=0

BC1=0

BC0=0

ICE Selects access control of registers ICMR0,

ICDR0/SAR, and SARX, and I2C bus interfac e

operation (port function for pin SCL0/SDA0)/non-

operation (bus drive state for pin SCL/SDA).

H’FFD8 bit70/1

IEIC Inhibits I2C bus interface interrupt requests. H’FFD8 bit60

ICCR0

MST Uses the I2C bus interface in master mode. H’FFD8 bit51

TRS Sets transmission mode of the I2C bus interface. H’FFD8 bit41/0

ACKE Halts continuous transmission when the

acknowle dge bit is 1. H’FFD8 bit31

BBSY Confirms that the I2C bus is occupied or releas ed,

and issues start and stop conditions by using bit

SCP.

H’FFD8 bit20/1

IRIC Detects start conditions, decides data transmission

end, and detects acknowledge = 1. H’FFD8 bit10/1

ICCR0

SCP Issues start and stop conditions by using bit BBSY. H’FFD8 bit00

ICSR0 ACKB Stores acknowledge transmitted from EEPROM. H’FFD9 bit0—

IICX0 Sets transmission clock frequency to 100 kHz by

using CKS2 to CKS0 of ICMR0. H’FFC3 bit51

IICE Enables CPU ac cess to the data register and

control register of the I2C bus interface. H’FFC3 bit41

STCR

FLSHE Sets a non-select state to the control register of

flash memory. H’FFC3 bit30

Rev. 2.0, 11/01, page 194 of 358

Table 4.9 Descriptions of Registers (cont)

SWE Inhibits automatic switching from format-less to I2C

bus format for IIC channel 0. H’FEE6 bit70

SW Uses IIC channel 0 in the I2C bus format. H’FEE6 bit60

IE Inhibits an interrupt in automatic format switching. H’FEE6 bit5 0

DDCSWR

CLR3

CLR0

Control initialization of the internal state of IIC0. H’FEE6

bit3 to

bit0

CLR3=1

CLR2=1

CLR1=1

CLR0=1

MSTP7 Cancels module stop mode of SCI channel 0. H’FF87 bit7 0MSTPCRL

MSTP4 Cancels module stop mode of IIC channel 0. H’FF87 bit4 0

SCR0 CKE1,0 Sets the P52/SCK0/SCL0 pin to an I/O port. H’FFDA

bit1,0 CKE1=0

CKE0=0

SMR0 C/$Sets SCI0 operating mode to asynchronous mode. H’FFD8 bit70

SYSCR INTM1,0 Set interrupt control mode of the interrupt controller

to control by bit 1. H’FFC4

bit5,4 INTM1=0

INTM0=0

MDCR MDS1,0 Set MCU operating mode to mode 3 by latching the

input level of pins MD1 and MD0. H’FFC5

bit1,0 MDS1=1

MDS0=1

(3) Descriptions of variables

Table 4.10 shows the descriptions of variables in this task example.

Table 4.10 Descriptions of Variables

Variable Function Data

Length Initial

Value Used Module

Name

dt_trs One-byte transmission data 1 byte H’38 mst_trs

dummy MDCR read value 1 byte — main

(4) Used RAM descr ipt ions

RAM for other than variables is not u sed in th is task example.

Rev. 2.0, 11/01, page 195 of 358

4.4.4 Flowchart

(1) Main routine

main

SP H'F000

Set stack pointer (SP) to H'F000.

Call initial-setting subroutine.

Clear bit 1 to 0 to enable an interrupt.

Call single master transmission subroutine.

Latch the input level of pins MD1 and MD0

in bits MDS1 and MDS0 by reading MDCR.

Set interrupt control mode of the interrupt

controller to interrupt control by bit 1.

SYSCR H'09

initialize

CCR 1bit 0

mst_rec

MDCR read

············

Rev. 2.0, 11/01, page 196 of 358

(2) Initial-setting subroutine

STCR H'00

MSTPCRL H'7F

DDCSWR H'0F

MSTPCRL H'EF

ICMR0 H'28

ICCR0 H'01

SAR0 H'00

ICSR0 H'00

STCR H'30

ICCR0 H'89

SARX0 H'01

ICCR0 H'81

SMR0 H'00

SCR0 H'00

STCR H'10

initialize

rts

············

······

············

······

Set bit FLSHE of STCR to 0 to set the control register of

flash memory to non-select state.

Set bit MSTP7of MSTPCRL to 0 to cancel module stop

mode of SCI0.

Set bit C/ of SMR to 0 to set SCI0 operating mode to asy

nchronous mode.

Set bits CKE1 and CKE of SMR to 0 to set pin

SCK0 to an I/O port.

Set bit IICE of STCR to 1 to enable CPU access to the data

C bus interface.

Set IEIC ICCR0 to 0 to inhibit IIC0 interrupt request.

Set ACKE to 1 to halt continuous transmission when the

acknowledge bit is 1.

Set ICE of ICCR0 to 0 to enable access to SAR0 and SARX0.

Set ICE of ICCR0 to 1 to enable access to ICMR0 and ICDR0.

Set ACKB of ICSR0 to 0.

Set SWE, SW, and IE of DDCSWR to 0. Inhibit automatic switch from

format-less of IIC0 to I

C bus format, use IIC0 in I

C bus format,

and inhibit an interrupt in automatic format switching.

Set FS of SAR0 and FSX of SARX0 to 0 to select I

C bus

format for IIC0 transmission format (recognize SAR slave

address and ignore SARX slave address).

Set IICX0 of STCR and CKS2 and CKS0 of ICMR0 to 1 and CKS1 to 0.

Set IIC0 transmission clock frequency to 100 kHz, set WAI to 0,

and continuously transfer data and acknowledge.

Set bit MSTP7 of MSTPCRL to 1 and bit MSTP4 to 0 to set module

stop mode of SCI0 and cancel module stop mode of IIC0.

Rev. 2.0, 11/01, page 197 of 358

(3) Single master transmissio n subroutine

set_start

mst_trs

rts

MST 1

TRS 1

trs_slvadr_a0

trs_memadr

IRIC 0

set_stop

ICCR0 dt_trs

set_start

ACKB = 0 ?

Yes

BBSY = 0 ?

···············

············

Transmit the EEPROM slave address + W data.

Bus release state?

Set MST and TRS of ICCR0 to 1 to set IIC0

mode to master transmission mode.

Issue the start condition.

Are there acknowledge from EEPROM?

Transmit the EEPROM memory address data.

Are there acknowledge from EEPROM?

··············· Transmit 1-byte data (H'38).

··············· Clear IRIC to 0 to decide data-transmission end

(at rising of ninth clock of transmission clocks).

One-byte data transmission end?

··············· Issue the stop condition.

ACKB = 0 ?

set_start

IRIC = 1?

Rev. 2.0, 11/01, page 198 of 358

(4) Subroutine that sets the start condition

set_start

rts

IRIC 0

ICCR0 H'BC

··················

············

IRIC = 1 ? No

Yes

Clear IRIC to decide start condition detection.

Set BBSY of ICCR0 to 1 and SCP to

0 to issue the start condition.

Is the start condition detected from the bus line state?

(5) Subroutine that sets the stop condition

set_stop

rts

ICCR0 H'B8 ··················

············

BBSY = 0 ? No

Yes

Set BBSY and SCP of ICCR0 to 0 to issue the stop condition.

Bus release state?

Rev. 2.0, 11/01, page 199 of 358

(6) Slave address + W transmission subroutine

trs_slvadr_a0

rts

ICCR0 H'A0

IRIC 0

··················

············

IRIC = 1 ? No

Yes

Transmit the EEPROM slave address + W data (H'A0).

Clear IRIC to 0 to decide data-transmission end

(at rising of ninth clock of transmission clocks).

EEPROM slave address + W data transmission end?

(7) EEPROM memory address transmissio n subroutine

trs_memadr

rts

ICCR0 H'00

IRIC 0

··················

············

IRIC = 1 ? No

Yes

Transmit EEPROM memory address data (H'00).

Clear IRIC to 0 to decide data-transmission end

(at rising of ninth clock of transmission clocks).

EEPROM memory address data transmission end?

Rev. 2.0, 11/01, page 200 of 358

4.4.5 Program List

/*****************************************************

* H8S/2138 IIC bus application note *

* 3.Single master transmit 1byte data to EEPROM *

* File name : BYTxd.c *

* Fai : 20MHz *

* Mode : 3 *

******************************************************/

#include <stdio.h>

#include <machine.h>

#include "2138s.h"

/*****************************************************

* Prototype *

******************************************************/

void main(void); /* Main routine */

void initialize(void); /* IIC0 initialize */

void mst_trs(void); /* Master transmit to EEPROM */

void set_start(void); /* Start condition set */

void set_stop(void); /* Stop condition set */

void trs_slvadr_a0(void); /* Slave address + W data transmit */

void trs_memadr(void); /* EEPROM memory address data transmit */

unsigned char dt_trs = 0x38; /* Transmit data (1byte) */

/*****************************************************

* main : Main routine *

******************************************************/

void main(void)

#pragma asm

mov.l #h'f000,sp ;Stack pointer initialize

#pragma enda sm

{

unsigned char dummy;

dummy = MDCR.BYTE; /* MCU mode set */

Rev. 2.0, 11/01, page 201 of 358

SYSCR.BYTE = 0x09; /* Interrupt control mode set */

initialize(); /* Initialize */

set_imask_ccr(0); /* Interrupt enable */

mst_trs(); /* Master transmit to EPROM */

while(1); /* End */

}

/*****************************************************

* initialize : IIC0 initialize *

******************************************************/

void initialize(void)

{

STCR.BYTE = 0x00; /* FLSHE = 0 */

MSTPCR.BYTE.L = 0x7f; /* SCI0 module stop mode reset */

SCI0.SMR.BYTE = 0x00; /* SCL0 pin function set */

SCI0.SCR.B YTE = 0x00 ;

MSTPCR.BYTE.L = 0xef; /* IIC0 module stop mode reset */

STCR.BYTE = 0x10; /* IICE = 1 */

DDCSWR.BYTE = 0x0f; /* IIC bus format initialize */

IIC0.ICCR.BYTE = 0x01; /* ICE = 0 */

IIC0.SAR.BYTE = 0x00; /* FS = 0 */

IIC0.SARX.BYTE = 0x01; /* FSX = 1 */

IIC0.ICCR.BYTE = 0x81; /* ICE = 1 */

IIC0.ICSR.BYTE = 0x00; /* ACKB = 0 */

STCR.BYTE = 0x30; /* IICX0 = 1 */

IIC0.ICMR.BYTE = 0x28; /* Transfer rate = 100kHz */

IIC0.ICCR.BYTE = 0x89; /* IEIC = 0, ACKE = 1 */

}

/*****************************************************

* mst_trs : Master transmit to EEPROM *

******************************************************/

void mst_trs(void)

{

while(IIC0.ICCR.BIT.BBSY == 1); /* Bus empty (BBSY=0) ? */

IIC0.ICCR.BIT.MST = 1; /* Master transmit mode set */

Rev. 2.0, 11/01, page 202 of 358

IIC0.ICCR.BIT.TRS = 1; /* MST = 1, TRS = 1 */

set_start(); /* Start condition set */

trs_slvadr_a0(); /* Slave address + W data transmit */

if (IIC0.ICSR.BIT.ACKB == 0)

{

trs_memadr(); /* EEPROM memory address data transmit */

if (IIC0.ICSR.BIT.ACKB == 0)

{

IIC0.ICDR = dt_trs; /* 1 byte data transmit */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* transmit end (IRIC=1) ? */

}

set_stop(); /* Stop condition set */

}

/*****************************************************

* set_start : Start condition set *

******************************************************/

void set_start(void)

{

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

IIC0.ICCR.BYTE = 0xbc; /* Start condition set (BBSY=1,SCP=0) */

while(IIC0.ICCR.BIT.IRIC == 0); /* Start condition set (IRIC=1) ? */

}

/*****************************************************

* set_stop : Stop condition set *

******************************************************/

void set_stop(void)

{

IIC0.ICCR.BYTE = 0xb8; /* Stop condition set (BBSY=0,SCP=0) */

while(IIC0.ICCR.BIT.BBSY == 1); /* Bus empty (BBSY=0) ? */

}

Rev. 2.0, 11/01, page 203 of 358

/*****************************************************

* trs_slvadr_a0 : Slave address + W data transmit *

******************************************************/

void trs_slvadr_a0(void)

{

IIC0.ICDR = 0xa0; /* Slave address + W data(H'A0) write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

/*****************************************************

* trs_memadr : EEPROM memory address data transmit *

******************************************************/

void trs_memadr(void)

{

IIC0.ICDR = 0x00; /* EEPROM memory address data(H'00) write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

Rev. 2.0, 11/01, page 204 of 358

4.5 One-Byte Data Reception by Single-Master Reception

4.5.1 Specifications

• One-byte data is read from EEPROM (HN58X2408) using channel 0 of the I 2C bus interface in

the H8S/2138.

• The slave address of EEPROM to be connected is 1010000, and data in address H'00 of the

EEPROM memory address is read.

• Data to be read is stored at address H'E100 in RAM.

• The device connected to the I2C b us in this system is a sin gle–master configurationone

master device (H8S/2138) and on e slave device (EEPROM).

• The transfer clock frequency is 100 kHz.

• Figure 4.14 shows an example of the H8S/2138 and EEPROM connection.

SCL0 SCL

SDA

SDA0

H8S/2138

Master

SCL

SDA

EEPROM

Slave

Figure 4.14 Example of H8S/2138 and EEPROM Connection

• Figure 4.15 shows the I2C bus format used in this task example.

Rev. 2.0, 11/01, page 205 of 358

S SLA A MEA A

71 11 1 1

1 1

S SLA DATAA A P

11 11

R/ R/

Number of

transmission bits

Number of

transmission frames

Legend:

SLA

MEA

DATA

: Start condition

: EEPROM slave address

: Transmission/reception destination

: Acknowledge

: EEPROM memory address

: Reception data

: Stop condition

Figure 4.15 Transfer Format Used in This Task Example

4.5.2 Operation Description

Figure 4.16 shows the operation principle.

Rev. 2.0, 11/01, page 206 of 358

10µs Transmission/reception clock frequency = 100 kHz

Stop

condition

Ack Ack Ack Ack

Start

condition Start condition

1st reception data

SCL

SDA

TDRE

IRIC

RDRF

[3]

[5] [5] [5] [12]

Memory address

=H'00

Slave address

+ R/ =H'A0 Slave address

+ R/ =H'A1

[1]

[2] [2]

[3]

[4] [4] [4] [11]

[1]

[2] [10][6]

[3] [9]

[7] [8]

Hardware processingSoftware processing

Issues start conditions

(BBSY = 1, SCP = 0)

Writes transfer data to ICDR0

No processing

Clears IRIC to 0 to judge transfer end

Clears IRIC to 0 to judge detection of

start conditions

Sets in master reception mode (MST = 1, TRS = 0)

Clears IRIC to 0

to judge

reception end

No processing

Clears IRIC to 0 to judge output end of 9th

reception clock

Sets in master transfer mode

(MST = 1, TRS = 1)

Issues stop conditions

(BBSY = 0, SCP = 0)

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[11]

[12]

IRIC = 1, TDRE = 1 (detects start condition from the bus

line state)

TDRE = 0 (writes data to ICDRT while TRS = 1)

TDRE = 1 (transmits data from ICDRT to ICDRS)

IRIC = 1 (ends data transmission (at rising of 9th

transmission clock))

No processing

TDRE = 0 (when TRS = 0)

No processing

IRIC = 1, RDRF = 1 (WAIT = 1) (ends data reception

(at falling of 8th reception clock))

Starts output at 9th reception clock

IRIC = 1 (at rising of 9th reception clock)

TDRE = 1 (after detecting start conditions, when switching

from TRS = 0 to TRS = 1)

TDRE = 0 (after issuing stop condition, detects stop

conditions from the bus line state)

Figure 4.16 Principle of Reception Operation in One-Byte Data by Single-Master Reception

Rev. 2.0, 11/01, page 207 of 358

4.5.3 Software Description

(1) Module Description

Table 4.11 describes the module in this task example.

Table 4.11 Module De scription

Module Name Label Name Function

Main routine main Sets stack pointer and MCU mode, and enables interrupts.

Initial setting initialize Initial settings of using RAM area and IIC0.

Single-master

reception mst_rec Receives one-byte data from EEPROM by single-master

reception.

Start condition

issuance set_start Issues start condition.

Stop condition

issuance set_stop Issues stop condition.

Slave address + W

transmission trs _ slvadr_a0 Transmits slave address + W data (H’A0) in EEPROM.

Slave address + R

transmission trs _ slvadr_a1 Transmits slave address + R data (H’A1) in EEPROM.

EEPROM memory

address tran sm iss iontrs_memadr Transmits memory address data (H’00) in EEPROM.

Data reception rec_data Receives one-byte data.

(2) On-Chip Register Description

Table 4.12 describes the on-chip register in this task example.

Rev. 2.0, 11/01, page 208 of 358

Table 4.12 On-Chip Register Description

Value

ICDR0 Stores transmission/reception data. H'FFDE —

SAR0 FS Sets transfer format with the FSX bit in SARX0 and

the SW bit in DDCSWR. H'FFDF bit00

SARX0 FSX Sets transfer format with the FS bit in SAR0 and the

SW bit in DDCSWR. H'FFDE bit01

MLS Sets data transfer by MSB first. H'FFDF bit70

WAIT Sets whether wait is input or not between data and

acknowle dge bit. H'FFDF bit60/1

CKS2

CKS0

Set transfer clock frequency to 100 kHz in

conjunction with the IICX0 bit in STCR. H'FFDF

Bit5 to

Bit3

CKS2=1

CKS1=0

CKS0=1

ICMR0

BC2

BC0

Set number of data bits to be transferred next to 9

bits/frame by the I2C bus format. H'FFDF

Bit2 to

Bit0

BC2=0

BC1=0

BC0=0

ICE Controls access to ICMR0, ICDR0/SAR, SARX, and

selects the I2C bus interface to operate (SCL0 and

SDA0 pins function as port) or not to operate

(SCL/SDA pins are in the bus drive state).

H'FFD8 bit70/1

IEIC Disables an interrupt request of the I 2C bus

interface. H'FFD8 bit6 0

MST Uses the I2C bus interface in master mode. H'FFD8 bit51

TRS Sets transmission/reception mode in the I2C bus

interface. H'FFD8 bit40/1

ACKE Suspends continuous transfer when an

acknowle dge bit is 1. H'FFD8 bit3 1

BBSY Confirms the I2C bus is occupied or released, and

issues start or stop condition in conjunction with the

SCP bit.

H'FFD8 bit20/1

IRIC Detects start condition, judges end of data transfer,

and detects an acknowledge bit = 1. H'FFD8 bit10/1

ICCR0

SCP Issues start or stop condit ion in con jun cti on wit h the

BBSY bit. H'FFD8 bit0 0

ICSR0 ACKB Stores an acknowledge bit received from EEPROM

in transmitting.

Sets an acknowledge bit to be transferred to

EEPROM in reception.

H'FFD9 bit0-

Rev. 2.0, 11/01, page 209 of 358

Table 4.12 On-chip Register Description (c ont)

Value

IICX0 Sets the transfer clock frequency to 100 kHz in

conjunction with CKS2 to CKS0 bits in ICMR0. H'FFC3 bit51

IICE Enables access to CPU by the data and control

registers of the I2C bus interfa ce. H'FFC3 bit4 1

STCR

FLSHE Sets the control register in flash memory to be in

non-selecta ble state. H'FFC3 bit30

SWE Disables automatic switching from formatless of

channel 0 in IIC to the I2C bus format. H'FEE6 bit7 0

SW Uses channel 0 in IIC in the I2C bus format. H'FEE6 bit60

IE Disables interrupts when format is switched

automatically. H'FEE6 bit50

DDCSWR

CLR3

CLR0

Control initialization of an internal state in IIC0. H'FEE6

bit3 to

bit0

CLR3=1

CLR2=1

CLR1=1

CLR0=1

MSTP7 Cancels module stop mode in channel 0 in SCI. H'FF87 bit7 0MSTPCRL

MSTP4 Cancels module stop mode in channel 0 in IIC. H'FF87 bit4 0

SCR0 CKE1,0 Set P52/SCK0/SCL0 pin as I/O port. H'FFDA

bit1, 0 CKE1=0

CKE0=0

SMR0 C/$Sets operating mode in SCI0 to synchronous mode.H'FFD8 bit70

SYSCR INTM1, 0 Set interrupt control mode in interrupt controller to

be controlled by the 1 bi t. H'FFC4

bit5, 4 INTM1=0

INTM0=0

MDCR MDS1, 0 Set MCU operating mode to mode 3 by latching

input levels of MD1 and MD0 pins. H'FFC5

bit1, 0 MDS1=1

MDS0=1

(3) Variable Description

Table 4.13 d escribes the variable in this task example.

Table 4.13 Variable Description

Variable Function Data

Length Initial

Value Module in Use

dummy MDCR read value 1 byte — main

Rev. 2.0, 11/01, page 210 of 358

(4) Using RAM Description

Table 4.14 describes the RAM used in this task example.

Table 4.14 Description of RAM Used

Label Function Data

Length Address Module in Use

dt_rec[0] Stores received data. 1 byte H'E100 Initialize

rec_data

4.5.4 Flowchart

(1) Main Routine

main

SP H'F000 Set SP (stack pointer) to H'F000.

Call subroutine in initial setting.

Enable interrupts by clearing the 1 bit to 0.

Call subroutine in single-master reception.

Latch input levels of the MD1 to MD0 pins

to the MDS1 to MDS0 bits by reading MDCR.

Set interrupt control mode in the interrupt

controller to control interrupts by the 1 bit.

SYSCR H'09

initialize

CCR 1bit 0

mst_rec

Read MDCR

············

Rev. 2.0, 11/01, page 211 of 358

(2) Initial Setting Subrout ine

dt_rec[0] H'00

STCR H'00

STCR H'10

SCR0 H'00

STCR H'30

DDCSWR H'0F

ICCR0 H'01

ICCR0 H'81

ICCR0 H'89

ICSR0 H'00

ICMR0 H'28

SAR0 H'00

SARX0 H'01

MSTPCRL H'7F

SMR0 H'00

MSTPCRL H'EF

Initialize RAM area for storing received data.

Clear the FLSHE bit in STCR to 0 and set the control

Set the IICE bit in STCR to 1 and enable access to CPU

by the data register and control register in the I

C bus interface.

Clear the ICE bit in ICCR0 to 0 and enable access to SAR0

and SARX0.

Set the ICE bit in ICCR0 to 1 and enable access to ICMR0 and ICDR0.

Clear the IEIC bit in ICCR to 0, disable the IIC0 interrupt

request, set ACKE to 1, and suspend continuous transfer

when acknowledge bit is 1.

Clear the ACKB bit in ICSR0 to 0.

Clear the SWE, SW, and IE bits in DDCSWR to 0, disable

automatic switching from IIC0 formatless to the I

C bus format,

use IIC0 in the I

C bus format, and disable interrupts when

format is switched automatically.

Clear the CKE1 and CKE bits in SCR to 0 and

set the SCK0 pin as I/O port.

Clear the MSTP7 bits in MSTPCRL to 0 and cancel

module stop mode in SCI0.

Set the MSTP7 bit to 1, clear the MSTP4 bit to 0 in

MSTPCRL, set module stop mode in SCI0, and

cancel module stop mode in IIC0.

Clear the C/ bit in SMR to 0 and set operating

mode in SCI0 to synchronous mode.

Clear the FS bit in SAR0 and the FSX bit in SARX0 to 0 and

select the I

C bus format as the transfer format in IIC0

(confirm a slave address in SAR and ignore a slave address in SARX).

Set the IICX0 bit in STCR and the CKS2 and CKS0 bits in

ICMR0 to 1, clear the CKS1 bit to 0, set the transfer clock

frequency in IIC0 to 100 kHz, clear WAIT to 0, and transfer

data and acknowledge bits continuously.

initialize

rts

············

······

············

······

············

Rev. 2.0, 11/01, page 212 of 358

(3) Single-Master Reception Subroutine

set_start

trs_slvadr_a0

mst_rec

MST 1

TRS 1

trs_slvadr_a1

set_start

ACKB = 0 ?

Yes

BBSY = 0 ?

ACKB = 0 ?

trs_memadr

set_stop

rts

rec_data

············

···············

··················

·····················

··················

·····················

··················

········ Bus release state?

Set the MST and TRS bits in ICCR0 to 1 and

set IIC0 mode to master transmission mode.

Call start condition issuance subroutine.

Call EEPROM slave address + W data transmission subroutine.

Acknowledge from EEPROM?

Call subroutine of EEPROM memory address data transmission.

Acknowledge from EEPROM?

Call EEPROM slave address + R data transmission subroutine.

Call data reception subroutine.

Call stop condition issuance subroutine.

Call start condition issuance subroutine.

Rev. 2.0, 11/01, page 213 of 358

(4) St art Condition Issuance Subro utine

set_start

rts

IRIC 0

ICCR0 H'BC

·····················

··········

IRIC = 1 ? No

Yes

Clear IRIC to 0 for judging detection of start condition.

Set the BBSY bit in ICCR0 to 1, clear the SCP bit to 0,

and issue the start condition

Detect the start condition from the bus line state?

(5) Stop Condition Issuance Subroutine

set_stop

rts

ICCR0 H'B8 ·····················

··········

BBSY = 0 ? No

Yes

Bus release state?

Clear the BBSY and SCP bits in ICCR0 to 0,

and issue the stop condition.

Rev. 2.0, 11/01, page 214 of 358

(6) Slave Address + W Transmission Subroutine

trs_slvadr_a0

rts

ICCR0 H'A0

IRIC 0

·····················

··········

IRIC = 1 ? No

Yes

Transmit EEPROM slave address + W data (H'A0).

Clear IRIC to 0 for judging end of data transmission

(at rising of 9th transmission clock).

EEPROM slave address + W data has been transmitted?

(7) Slave Address + R Transmission Subroutine

trs_slvadr_a1

rts

ICCR0 H'A1

IRIC 0

·····················

·········

IRIC = 1 ? No

Yes

Transmit EEPROM slave address + R data (H'A1).

Clear IRIC to 0 for judging end of data transmission

(at rising of 9th transmission clock).

EEPROM slave address + R data has been transmitted?

Rev. 2.0, 11/01, page 215 of 358

(8) Subrout ine of EEPROM Me mory Address Transmission

trs_memadr

rts

ICCR0 H'00

IRIC 0

·····················

·········

IRIC = 1 ? No

Yes

Transmit EEPROM memory address data (H'00).

Clear IRIC to 0 for judging end of data transmission

(at rising of 9th transmission clock).

EEPROM memory address data has been transmitted?

Rev. 2.0, 11/01, page 216 of 358

(9) Data Reception Subroutine

rec_data

TRS 0

WAIT 1

ACKB 1

dt_rec[0] ICDR0

IRIC 0

WAIT 0

dt_rec[0] ICDR0

IRIC = 1 ?

Yes

IRIC 0

TRS 1

rts

ACKB 0

············

······ Data reception ended?

TSR = 1 (Set to master transmission mode)

IRIC = 0 (Start output at 9th reception clock)

TRS = 0 (Set to master reception mode)

WAIT = 1 (Insert wait between data and acknowledge bit)

ACKB = 1 (Output 1 at acknowledge output timing in reception)

Dummy read (Start reception)

Clears IRIC to 0 for judging end of data reception

(at falling of 8th reception clock).

····· Ends output at 9th reception clock

(at rising of 9th reception clock)?

Read received data in first-byte and store the data in RAM.

WAIT = 0

ACKB = 0

Rev. 2.0, 11/01, page 217 of 358

4.5.5 Program List

/*****************************************************

* H8S/2138 IIC bus application note *

* 4.Single master receive 1byte data from EEPROM *

* File na me : BYRxd.c *

* Fai : 20MHz *

* Mode : 3 *

******************************************************/

#include <stdio.h>

#include <machine.h>

#include "2138s.h"

/*****************************************************

* Prototype *

******************************************************/

void main(void); /* Main routine */

void initialize(void); /* RAM & IIC0 initialize */

void mst_rec(void); /* Master receive from EEPROM */

void set_start(void); /* Start condition set */

void set_stop(void); /* Stop condition set */

void trs_slvadr_a0(void); /* Slave address + W data transmit */

void trs_slvadr_a1(void); /* Slave address + R data transmit */

void trs_memadr(void); /* EEPROM memory address data transmit */

void rec_data(void); /* 1-byte data receive */

/*****************************************************

* RAM allocation *

******************************************************/

#pragma sect ion rame re a

unsigned char dt_rec[1]; /* Receive data store area */

/*****************************************************

* main : Main routine *

******************************************************/

#pragma sect ion

void main(void)

Rev. 2.0, 11/01, page 218 of 358

#pragma asm

mov.l #h'f000,sp ;Stack pointer initialize

#pragma enda sm

{

unsigned char dummy;

dummy = MDCR.BYTE; /* MCU mode set */

SYSCR.BYTE = 0x09; /* Interrupt control mode set */

initialize(); /* Initialize */

set_imask_ccr(0); /* Interrupt enable */

mst_rec(); /* Master receive from EPROM */

while(1); /* End */

}

/*****************************************************

* initialize : RAM & IIC0 Initialize *

******************************************************/

void initialize(void)

{

dt_rec[0] = 0x00; /* Receive data store area initialize */

STCR.BYTE = 0x00; /* FLSHE = 0 */

MSTPCR.BYTE.L = 0x7f; /* SCI0 module stop mode reset */

SCI0.SMR.BYTE = 0x00; /* SCL0 pin function set */

SCI0.SCR.B YTE = 0x00 ;

MSTPCR.BYTE.L = 0xef; /* IIC0 module stop mode reset */

STCR.BYTE = 0x10; /* IICE = 1 */

DDCSWR.BYTE = 0x0f; /* IIC bus format initialize */

IIC0.ICCR.BYTE = 0x01; /* ICE = 0 */

IIC0.SAR.BYTE = 0x00; /* FS = 0 */

IIC0.SARX.BYTE = 0x01; /* FSX = 1 */

IIC0.ICCR.BYTE = 0x81; /* ICE = 1 */

IIC0.ICSR.BYTE = 0x00; /* ACKB = 0 */

STCR.BYTE = 0x30; /* IICX0 = 1 */

IIC0.ICMR.BYTE = 0x28; /* Transfer rate = 100kHz */

IIC0.ICCR.BYTE = 0x89; /* IEIC = 0, ACKE = 1 */

}

Rev. 2.0, 11/01, page 219 of 358

/*****************************************************

* mst_rec : Master receive from EEPROM *

******************************************************/

void mst_rec(void)

{

while(IIC0.ICCR.BIT.BBSY == 1); /* Bus empty (BBSY=0) ? */

IIC0.ICCR.BIT.MST = 1; /* Master transmit mode set */

IIC0.ICCR.BIT.TRS = 1; /* MST = 1, TRS = 1 */

set_start(); /* Start condition set */

trs_slvadr_a0(); /* Slave address + W data transmit */

if(IIC0.ICSR.BIT.ACKB == 0) /* ACKB = 0 ? */

{

trs_memadr(); /* EEPROM memory address data transmit */

if(IIC0.ICSR.BIT.ACKB == 0) /* ACKB = 0 ? */

{

set_start(); /* Re-start condition set */

trs_slvadr_a1(); /* Slave address + R data transmit */

if(IIC0.ICSR.BIT.ACKB == 0) /* ACKB = 0 ? */

{

rec_data(); /* 1-byte data receive */

}

set_stop(); /* Stop condition set */

}

/*****************************************************

* set_start : Start condition set *

******************************************************/

void set_start(void)

{

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

IIC0.ICCR.BYTE = 0xbc; /* Start condition set (BBSY=1,SCP=0) */

while(IIC0.ICCR.BIT.IRIC == 0); /* Start condition set (IRIC=1) ? */

Rev. 2.0, 11/01, page 220 of 358

}

/*****************************************************

* set_stop : Stop condition set *

******************************************************/

void set_stop(void)

{

IIC0.ICCR.BYTE = 0xb8; /* Stop condition set (BBSY=0,SCP=0) */

while(IIC0.ICCR.BIT.BBSY == 1); /* Bus empty (BBSY=0) ? */

}

/*****************************************************

* trs_slvadr_a0 : Slave addres + W data transmit *

******************************************************/

void trs_slvadr_a0(void)

{

IIC0.ICDR = 0xa0; /* Slave address + W data(H'A0) write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

/*****************************************************

* trs_slvadr_a1 : Slave addres + R data transmit *

******************************************************/

void trs_slvadr_a1(void)

{

IIC0.ICDR = 0xa1; /* Slave address + R data(H'A1) write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

/*****************************************************

* trs_memadr : EEPROM memory address data transmit *

******************************************************/

void trs_memadr(void)

{

Rev. 2.0, 11/01, page 221 of 358

IIC0.ICDR = 0x00; /* EEPROM memory address data(H'00) write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

/*****************************************************

* rec_data : 1-byte data receive *

******************************************************/

void rec_data(void)

{

IIC0.ICCR.BIT.TRS = 0; /* Master receive mode set (MST=1,TRS=0) */

IIC0.ICMR.BIT.WAIT = 1; /* WAIT = 1 */

IIC0.ICSR.BIT.ACKB = 1; /* ACKB = 1 */

dt_rec[0] = IIC0.ICDR; /* Dummy read (Receive start) */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Receive end (IRIC=1) ? */

IIC0.ICCR.BIT.TRS = 1; /* Master transmit mode set (MST=1,TRS=1) */

IIC0.ICCR.BIT.IRIC = 0; /* 9th clock transmit start (IRIC=0) */

while(IIC0.ICCR.BIT.IRIC == 0); /* 9th clock transmit end (IRIC=1) ? */

dt_rec[0] = IIC0.ICDR; /* 1-byte receive data read */

IIC0.ICMR.BIT.WAIT = 0; /* WAIT = 0 */

IIC0.ICSR.BIT.ACKB = 0; /* ACKB = 0 */

}

Rev. 2.0, 11/01, page 222 of 358

4.6 Single-Master Transmission by DTC

4.6.1 Specifications

• 10-byte d ata is written to EEPROM (HN58X2 408) using channe l 0 of the I2C bus interface in

the H8S/2138 and the data transfer controller (DTC).

• The slave addr ess of EEPROM to be connected is 1 010000, and data is written to addresses

H'00 to H'09 of the EEPROM memory.

• 10-byte data to be written is stored at addresses H'E102 to H'E10B in RAM.

• The device connected to the I2C b us in this system is a sin gle–master configurationone

master device (H8S/2138) and on e slave device (EEPROM).

• The transfer clock frequency is 100 kHz.

• Figure 4.17 shows an example of the H8S/2138 and EEPROM connection.

SCL0 SCL

SDA

SDA0

H8S/2138

Master

SCL

SDA

EEPROM

Slave

Figure 4.17 Example of H8S/2138 and EEPROM Connection

• Figure 4.18 shows the I2C bus format used in this task example.

Rev. 2.0, 11/01, page 223 of 358

S SLA A MEA A DATA A

71 11 1

1 1

A P

111

Number of

transmission bits

Number of

transmission frames

Legend:

SLA

MEA

DATA

: Start condition

: EEPROM slave address

: Transmission/reception destination

: Acknowledge

: EEPROM memory address

: Reception data

: Stop condition

Figure 4.18 Transfer Format Used in This Task Example

• An example usage of the data transfer controller (DTC) in the H8S/2138 series used in this

task example is described belo w.

(a) The DTC is activated by an interrupt request of channel 0 in the I2C bus interface (IICI0) and

transmission data is transferred.

(b) Normal mode is used for the DTC transfer mode.

Rev. 2.0, 11/01, page 224 of 358

IICI0

(IIC0 interrupt request)

CPU interrupt request

Legend:

MRA, MRB

CRA, CRB

SAR

DAR

DTCERA to DTCERE

DTVECR

: DTC mode register A, B

: DTC count register A, B

: DTC source address register

: DTC destination register

: DTC enables registers A to E

: DTC vector register

Interrupt

controller

DTCERA

DTCERE

DTVECR

DTC

Control logic

MRA

CRA

CRB MRB

DAR

SAR

MRB

On-chip RAM

C bus data register 0 (ICDR0)

Internal I/O register

Internal address bus

Internal data bus

DTC

activate

request

Transfer data

Figure 4.19 Block Diagram of DTC in This Task Example

Rev. 2.0, 11/01, page 225 of 358

(d) Figure 4.20 shows the location of transfer data on on-chip RAM.

Address

H'E100

H'E101

H'E102

H'E103

H'E104

H'E105

H'E106

H'E107

H'E108

H'E109

H'E10A

H'E10B

H'A0

H'00

H'01

H'23

H'45

H'67

H'89

H'98

H'76

H'54

H'32

H'10

Slave address + R/W data

EEPROM memory address data

1st-byte transmission data

2nd-byte transmission data

3rd-byte transmission data

4th-byte transmission data

5th-byte transmission data

6th-byte transmission data

7th-byte transmission data

8th-byte transmission data

9th-byte transmission data

10th-byte transmission data

On-chip RAM Transfer data

Figure 4.20 Location of Transfer Data on On-Chip RAM

(e) Figure 4.21 shows the location of DTC vector table and register information on the on-chip

RAM in this task example. DTC register information is provided from address H'EC00 to the

MRA, SAR, MRB, DAR, CRA, and CRB registers in that order.

Address Address

H'EC00

H'EC01

H'EC02

H'EC03

H'EC04

H'EC05

H'EC06

H'EC07

H'EC08

H'EC09

H'EC0A

H'EC0B

H'80

H'00

H'E1

H'00

H'FF

H'DE

H'00

H'0C

H'00

MRA register information (MRA1)

SAR register information (SAR1)

MRB register information (MRB1)

DAR register information (DAR1)

CRA register information (CRA1)

CRB register information (CRB1)

DTC vector table On-chip RAM

H'04B8

H'04B9 H'EC

H'00

Figure 4.21 Location of DTC Vector Table and Register Information on On-Chip RAM

Rev. 2.0, 11/01, page 226 of 358

(f) Table 4.15 describes the register of the DTC used in this task example.

Table 4.15 DTC Register Description

MRA DTC mode register A

Controls DTC operating mode.

SM1, 0

(bit7, 6) Source address mode 1, 0

Specify whether SAR is incremented, decremented, or fixed after data

transfer is performed.

When SM1 =0 and SM0 = *, SAR is fixed (*: 0 or 1)

When SM1 =1 and SM0 = 0, SAR is incremented after transfer (when Sz = 0:

+ 1, when Sz = 1: + 2)

When SM1 =1 and SM0 = 1, SAR is decremented after transfer (when Sz =

0: − 1, when Sz = 1: − 2)

DM1, 0

(bit5, 4) Destination address mode 1, 0

Specify whether DAR is incremented, decremented, or fixed after data

transfer is performed.

When DM1 =0 and DM0 = *, DAR is fixed (*: 0 or 1)

When DM1 =1 and DM0 = 0, DAR is incremented after transfer (when Sz =

0: + 1, when Sz = 1: + 2)

When DM1 =1 and DM0 = 1, DAR is decremented after transfer (when Sz =

0: − 1, when Sz = 1: − 2)

MD1, 0

(bit3, 2) DTC mode 1, 0

Specify DTC transfer mode.

When MD1 = 0 and MD0 = 0, normal mode

When MD1 = 0 and MD0 = 1, repeat mode

When MD1 = 1 and MD0 = 0, block transfer mode

When MD1 = 1 and MD0 = 1, setting prohibited

DTS

(bit1) DTC transfer mode select

Specifies either source side or destination side becomes repeat area or block

area in repeat mode or block.

When DTS = 0, destination side becomes repeat area or block area.

When DTS = 1, source side becomes repeat area or block area.

(bit0) DTC data transfer size

Specifies data size in data transfer.

Rev. 2.0, 11/01, page 227 of 358

Table 4.15 DTC Register Description (cont)

MRB DTC mode register B

Controls DTC mode.

CHEN

(bit7) DTC chain transfer enable

Specifies chain transfer

When CHEN = 0, DTC data tran sfer is ended.

When CHEN = 1, DTC chain transfer.

MRB DISEL

(bit6) DTC interrupt select

Specifies an interrupt request to CPU is disabled or enabled after one data

transfer is performed.

When DISEL = 0, an interrupt to CPU is disabled if transfer counter is not 0

after the DTC data transfer is ended.

When DISEL = 1, an interrupt to CPU is enabled after the DTC data transfer

is ended.

SAR DTC source address register

Specifies the transfer source address of data to be transferred by the DTC.

DAR DTC destination address register

Specifies the transfer destination address of data to be transferred by the

DTC.

CRA DTC transfer count register A

Specifies the number of data transfers by the DTC.

CRB DTC transfer count register B

Specifies the number of block data transfers by the DTC in block transfer

mode.

DTVECR(H’FEF3) DTC vector register

Sets the DTC activation to be enabled or disabled by software and sets the

vector address for the software activation interrupt.

SWDTE

(bit7) DTC software activation enable

Sets the DTC software activation to be enabled or disabled.

When SWDTE = 0, the DTC software activation is disabled.

When SWDTE = 1, the DTC software activation is enabled.

DTVEC

6-0

(bit6-0)

DTC software activation vectors 6 to 0

Set the vector address for the DTC software activation.

Rev. 2.0, 11/01, page 228 of 358

Table 4.15 DTC Register Description (cont)

DTCERD(H’FEF1) DTC enable register

Controls the enabling or disabling of DTC activation by each interrupt source.

DTCED4

(bit4) DTC activation enable D4

When DTCED4 = 0, the DTC activation is disabled by the IICI0 interrupt.

When DTCED4 = 2, the DTC ac tivation is enabled by the IICI0 interrupt.

(g) The I2C bus format provides for selection of the slave device and transfer direction by means

of the slave address and the R/: bit, confirmation of reception with the acknowledge bit,

indication of the last frame, and so on. Therefore, continuous data transfer using the DTC

must be carried out in conjunction with CPU processing by means of interrupts. Table 4.16

shows an example of processing using the DTC in master transmission mode in this task

example.

Table 4.16 Operation Example by DTC (master transmission mode)

Item Master Transmission Mode

Slave address + R/: bit

transmission Tra nsmission by DTC (ICDR write)

Dummy data read —

Actual data transmission Transmission by DTC (ICDR write)

Dummy data (H’FF) write —

Last frame processing Not necessary

Transfer request processing after

last frame processing 1st time: Clearing by CPU

2nd time: End condition issuance by CPU

Setting of number of DTC transfer

data frames Transmission: Actual data count + 1(+ 1 equivalent to slave

address + R/W bits)

Rev. 2.0, 11/01, page 229 of 358

4.6.2 Operation Description

Figure 4.22 shows the operation principle.

SCL

SDA

[1]

[2]

[3]

[4]

[5]

[1] [2] [2] [2] [3] [4] [5]

10µs Transmission clock frequency = 100 kHz

Ack

Start

condition

Slave address

+ R/ = H’A0

Memory address

= H’00 1st transmission

data = H’01 9th transmission

data = H’32 10th transmission

data = H’10

Stop

condition

Ack Ack Ack Ack Ack

Issues start condition (BBSY = 1, SCP = 0)

No processing

Clears IRIC to 0 (1st IICI0 interrupt processing)

Clears IRIC to 0 (2nd IICI0 interrupt processing)

Issues stop condition (BBSY = 0, SCP = 0)

No processing

Writes transmission data to ICDR and clears IRIC to 0

Writes transmission data to ICDR

No processing

CPU processing DTC processing

···

Figure 4.22 Principle of Transmission Operation in Single Master by DTC

4.6.3 Software Description

(1) Module Description

Table 4.17 describes the module in this task example.

Table 4.17 Module De scription

Module Name Label Name Function

Main routine main Sets the stack pointer and MCU mode, and enables

interrupts.

Initial setting initialize Initial settings of using RAM area, IIC0 and the DTC

Transmission setup trs_stup Sets master transmission mode and issues start condition.

IIC0 interrupt

processing iici0 Clears IRIC and issues stop condition.

Rev. 2.0, 11/01, page 230 of 358

(2) On-Chip Register Description

Table 4.18 shows an on-chip register description in this task example.

Table 4.18 On-Chip Register Description

Value

ICDR0 Stores transmission/reception data. H'FFDE —

SAR0 FS Sets transfer format with the FSX bit in SARX0 and

the SW bit in DDCSWR. H'FFDF bit00

SARX0 FSX Sets transfer format with the FS bit in SAR0 and the

SW bit in DDCSWR. H'FFDE bit01

MLS Sets data transfer by MSB first. H'FFDF bit70

WAIT Sets whether wait is input or not between data and

acknowle dge bit. H'FFDF bit60

CKS2

CKS0

Set transfer clock frequency to 100 kHz in

conjunction with the IICX0 bit in STCR. H'FFDF

bit5 to

bit3

CKS2=1

CKS1=0

CKS0=1

ICMR0

BC2

BC0

Set number of data bits to be transferred next to 9

bits/frame by the I2C bus format. H'FFDF

bit2 to

bit0

BC2=0

BC1=0

BC0=0

ICE Controls access to ICMR0, ICDR0/SAR, SARX, and

selects the I2C bus interface to operate (SCL0 and

SDA0 pins function as port) or not to operate

(SCL/SDA pins are in the bus drive state).

H'FFD8 bit70/1

IEIC Disables an interrupt request of the I 2C bus

interface. H'FFD8 bit6 0

MST Uses the I2C bus interface in master mode. H'FFD8 bit51

TRS Sets transmission/reception mode in the I2C bus

interface. H'FFD8 bit4 1

ACKE Suspends continuous transfer when an

acknowle dge bit is 1. H'FFD8 bit3 1

ICCR0

BBSY Confirms the I2C bus is occupied or released, and

issues start or stop condition in conjunction with the

SCP bit.

H'FFD8 bit20/1

Rev. 2.0, 11/01, page 231 of 358

Table 4.18 On-Chip Register Description ( c ont)

Value

IRIC Detects start condition, judges end of data transfer,

and detects an acknowledge bit = 1. H'FFD8 bit10/1ICCR0

SCP Issues start or stop condit ion in con jun cti on wit h the

BBSY bit. H'FFD8 bit0 0

ICSR0 ACKB Stores an acknowledge bit received from EEPROM

in transmitting.

Sets an acknowledge bit to be transferred to

EEPROM in reception.

H'FFD9 bit0-

IICX0 Sets the transfer clock frequency to 100 kHz in

conjunction with CKS2 to CKS0 bits in ICMR0. H'FFC3 bit51

IICE Enables access to CPU by the data and control

registers of the I2C bus interfa ce. H'FFC3 bit4 1

STCR

FLSHE Sets the control register in flash memory to be in

non-selecta ble state. H'FFC3 bit30

SWE Disables automatic switching from formatless of

channel 0 in IIC to the I2C bus format. H'FEE6 bit7 0

SW Uses channel 0 in IIC in the I2C bus format. H'FEE6 bit60

IE Disables interrupts when format is switched

automatically. H'FEE6 bit50

DDCSWR

CLR3

CLR0

Control initialization of an internal state in IIC0. H'FEE6

bit3 to

bit0

CLR3=1

CLR2=1

CLR1=1

CLR0=1

MSTP7 Cancels module stop mode in channel 0 in SCI. H'FF87 bit7 0MSTPCRL

MSTP4 Cancels module stop mode in channel 0 in IIC. H'FF87 bit4 0

SCR0 CKE1, 0 Set P52/SCK0/SCL0 pin as I/O port. H'FFDA

bit1, 0 CKE1=0

CKE0=0

SMR0 C/$Sets operating mode in SCI0 to synchronous mode.H'FFD8 bit70

SYSCR INTM1, 0 Set interrupt control mode in interrupt controller to

be controlled by the 1 bi t. H'FFC4

bit5, 4 INTM1=0

INTM0=0

MDCR MDS1, 0 Set MCU operating mode to mode 3 by latching

input levels of MD1 and MD0 pins. H'FFC5

bit1, 0 MDS1=1

MDS0=1

Rev. 2.0, 11/01, page 232 of 358

Table 4.18 On-Chip Register Description ( c ont)

Value

SM1, 0 Set SAR to be incremented after data transfer. H'EC00

bit7, 6 SM1=1

SM0=0

DM1, 0 Set DAR to be fixed after data transfer. H'EC00

bit5, 4 DM1=0

DM0=0

MD1, 0 Set DTC transfer mode to normal mode. H'EC00

bit3, 2 MD1=0

MD0=0

DTS Sets the destination source to be repeat area or

block area. H'EC00

bit1 DTS=0

MRA

Sz Sets data size in data transfer to be in byte size. H'EC00

bit0 Sz=0

CHNE Sets the DTC chain transfer to be disabled. H'EC04

bit7 CHNE=0MRB

DISEL Sets an interrupt to CPU to be disabled if the

transfer counter is not 0 after one data transfer is

performed.

H'EC04

bit6 DISSEL=

SAR Sets the transfer source address of data transferred

by the DTC to H’E100. H'EC01 H'00E100

DAR Sets the transfer destination address of data

transferred by the DTC to H’FFDE. H'EC05 H'00FFDE

CRA Sets the number of data transfers by the DTC to 12.H'EC08 H'000C

CRB Sets the number of block data transfers by the DTC

in block transfer mode to 0. H'EC0A H'0000

SWDTE Sets the DTC software activation to be disabled. H'FEF3 bit7 0DTVECR

DTVEC6

DTVEC0

Set the vector address of the DTC software

activation to H’00. H'FEF3

bit6 to

bit0

H'00

DTCERD DTCED4 Enables the DTC activation by the IICI0 interrupt. H'FEF1 bit4 1

MSTPCR

HMSTP14 Cancels module stop mode of the DTC. H'FF86 bit6 0

Rev. 2.0, 11/01, page 233 of 358

(3) Variable Description

Table 4.19 d escribes the variable in this task example.

Table 4.19 Variable Description

Variable Function Data

Length Initial

Value Module in Use

dummy MDCR read value 1 byte — main

i Transmi t data counter 1 byte H'00 initialize

dt_trs[0] Slave address + W data 1 byte H'A0 initialize

dt_trs[1] EEPROM memory address data 1 byte H'00 initialize

dt_trs[2] 1st-byte transmission data 1 byte H'01 initialize

dt_trs[3] 2nd-byte transmission data 1 byte H'23 initialize

dt_trs[4] 3rd-byte transmission data 1 byte H'45 initialize

dt_trs[5] 4th-byte transmission data 1 byte H'67 initialize

dt_trs[6] 5th-byte transmission data 1 byte H'89 initialize

dt_trs[7] 6th-byte transmission data 1 byte H'98 initialize

dt_trs[8] 7th-byte transmission data 1 byte H'76 initialize

dt_trs[9] 8th-byte transmission data 1 byte H'54 initialize

dt_trs[10] 9th-byte transmission data 1 byte H'32 initialize

dt_trs[11] 10th-byte transmission data 1 byte H'10 initialize

Rev. 2.0, 11/01, page 234 of 358

(4) Description of RAM Used

Table 4.20 describes the RAM used in this task example.

Table 4.20 Description of RAM Used

Label Function Data

Length Address Module in Use

MRA1 DTC mode register A (MRA) 1 byte H'EC00 initialize

SAR1 DTC source address register (SAR) 4 bytes H'EC00 initialize

MRB1 DTC mode register B (MRB) 1 byte H'EC04 initialize

DAR1 DTC destination address register (DAR) 4 bytes H'EC04 initialize

CRA1 DTC transfer count register A (CRA) 2 bytes H'EC08 initialize

CRB1 DTC transfer count register B (CRB) 2 bytes H'EC0A initialize

txedf Transmiss ion end jud gem ent flag 1 byte H'E200 main

iici0

dt_trs_ram

[0] Stores slave address + R/W data. 1 byte H'E100 initialize

dt_trs_ram

[1] Stores EEPROM memory address data. 1 byte H'E101 initialize

dt_trs_ram

[2]

dt_trs_ram

[11]

Stores 10-byte transmission data. 10 bytes H'E102

H’E10B

initialize

Rev. 2.0, 11/01, page 235 of 358

4.6.4 Flowchart

(1) Main Routine

main

SP H'F000 Set SP (stack pointer) to H'F000.

Call subroutine in initial setting.

Call subroutine in transmission setup.

Enable an interrupt request by the IIC0.

Latch input levels of the MD1 to MD0 pins

to the MDS1 to MDS0 bits by reading MDCR.

Set interrupt control mode in the interrupt

controller to control interrupts by the 1 bit.

SYSCR H'09

initialize

trs_stup

IEIC 1

CCR 1bit 0

Read MDCR

·····················

Enable interrupts by clearing the 1 bit to 0.

·····················

txedf < 2 ? No

Yes

············· Transmission end?

Rev. 2.0, 11/01, page 236 of 358

(2) Initial Setting Subrout ine

i 0

i++

dt_trs_ram[i]

dt_trs[i]

Initialize the transmission data counter.

Clear the FLSHE bit in STCR to 0 and set the control register

in flash memory to be in non-selectable state.

Set MRA to H'80 and set SAR to be incremented, DAR to be fixed,

the DTC transfer mode to normal mode, and data size of data

transfer to be in byte size after data is transferred.

Set DAR to H'00FFDE and set the transfer destination address

of data transferred by the DTC to H'FFDE (ICDR0).

Set DTVECR to H'00 and disable the DTC software activation.

Set DTCDE4 to 1 and enable the DTC activation by the IICI0

interrupt.

Increment the transmission data counter.

Initialize the transmission end judgement flag.

Transmission data counter < 12?

Copy transmission data on ROM to RAM.

Set the MSTP14 bits in MSTPCRH to 0 and cancel module

stop mode in the DTC.

Set SAR to H'00E100 and set the transfer source address

of data transferred by the DTC to H'E100.

Set MRB to H'00 and the DTC chain transfer to be disabled.

Set an interrupt to CPU to be disabled if the transfer counter

is not 0 after the DTC data transfer is ended.

Set CRA to H'000C and set the number of data transfers by the

DTC to 12.

Set CRB to H'0000 and set the number of block data transfers

by the DTC to 0.

initialize

·····················

···············

·····················

i < 12 ? No

Yes

MRB1 H'00

txedf H'00

STCR H'00

MRA1 H'80

CRB1 H'0000

DAR1 H'0000FFDE

CRA1 H'000C

DTCED4 1

DTVECR H'00

MSTPCRH H'3F

SAR1 H'0000E100

Rev. 2.0, 11/01, page 237 of 358

SMR0 H'00

ICCR0 H'01

STCR H'10

ICCR0 H'89

SAR0 H'00

SARX0 H'01

STCR H'30

ICMR0 H'28

ICCR0 H'81

ICSR0 H'00

SCR0 H'00

MSTPCRL H'EF

DDCSWR H'0F

Clear the MSTP7 bits in MSTPCRL to 0 and

cancel module stop mode in SCI0.

Clear the C/ bit in SMR to 0 and set operating

mode in SCI0 to synchronous mode.

Clear the ICE bit in ICCR0 to 0 and enable access to SAR0

and SARX0.

Clear the ACKB bit in ICSR0 to 0.

Set the IICX0 bit in STCR and the CKS2 and CKS0 bits in ICMR0

to 1, clear the CKS1 bit to 0, set the transfer clock frequency in

IIC0 to 100 kHz, clear WAIT to 0, and transfer data and acknowledge

bits continuously.

Clear the IEIC bit in ICCR to 0, disable the IIC0 interrupt request,

set ACKE to 1, and suspend continuous transfer when acknowledge

bit is 1.

Clear the FS bit in SAR0 and the FSX bit in SARX0 to 0 and select the

C bus format as the transfer format in IIC0 (confirm a slave address

in SAR and ignore a slave address in SARX).

Set the IICE bit in STCR to 1 and enable access to CPU

by the data register and control register in the I

C bus interface.

Clear the CKE1 and CKE bits in SCR to 0 and

set the SCK0 pin as I/O port.

Clear the SWE, SW, and IE bits in DDCSWR to 0, disable automatic

switching from IIC0 formatless to the I

C bus format, use IIC0 in the

C bus format, and disable interrupts when format is switched

automatically.

Set the MSTP7 bit to 1, clear the MSTP4 bit to 0

in MSTPCRL, set module stop mode in SCI0, and

cancel module stop mode in IIC0.

Set the ICE bit in ICCR0 to 1 and enable access to ICMR0 and ICDR0.

rts

·················

·············

·················

·············

MSTPCRL H'7F

Rev. 2.0, 11/01, page 238 of 358

(3) Transmission Setup S ubroutine

IRIC 0

ICCR0 H’BC

trs_stup

rts

MST 1

TRS 1

Yes

BBSY = 0 ?

IRIC = 1 ?

·········

··················

·········

Set the MST and TRS bits in ICCR0 to 1

and set IIC0 mode to master transmission mode.

Clear IRIC to 0 for judging detection of start condition.

Set the BBSY bit in ICCR0 to 1, clear the SCP bit to 0,

and issue the start condition.

Detect the start condition from the bus line state?

Bus release state?

Rev. 2.0, 11/01, page 239 of 358

(4) IIC0 Interrupt Processing Routine

IEIC 0

ICCR0 H'BC

iici0

rts

IRIC 0

txedf++

Yes

BBSY = 0 ?

Yes

IRIC = 1 ?

txedf > 1 ?

·········

··················

·········

Increment the transmission end judgement flag.

Second IICI0 interrupt request?

Disable the IICI0 interrupt request.

Wait for the last transmission data to be transferred.

Bus release state?

Clear the BBSY and SCP bits in ICCR0 to 0,

and issue the stop condition

Clear the interrupt request flag (IRIC) to 0.

Rev. 2.0, 11/01, page 240 of 358

4.6.5 Program List

/*****************************************************

* H8S/2138 IIC bus application note *

* 5.Single master transmit by DTC *

* File na me : DTCtx.c *

* Fai : 20MHz *

* Mode : 3 *

******************************************************/

#include <stdio.h>

#include <machine.h>

#include "2138s.h"

/*****************************************************

* Prototype *

******************************************************/

void main(void); /* Main routine */

void initialize(void); /* RAM & DTC & IIC0 initialize */

void trs_stup(void); /* Master transmit by DTC set up */

/*****************************************************

* RAM allocation *

******************************************************/

#define MRA1 (*(volatile unsigned char *)0xec00) /* DTC mode register A */

#define SAR1 (*(volatile unsigned long *)0xec00) /* DTC source address register */

#define MRB1 (*(volatile unsigned char *)0xec04) /* DTC mode register B */

#define DAR1 (*(volatile unsigned long *)0xec04) /* DTC destination address register */

#define CRA1 (*(volatile unsigned short *)0xec08) /* DTC transfer count register A */

#define CRB1 (*(volatile unsigned short *)0xec0a) /* DTC transfer count register B */

#define txedf (*(volatile unsigned char *)0xe200) /* Transmit end flag */

#pragma sect ion rame re a

unsigned char dt_trs_ram[12]; /* Transmit data store area */

#pragma sect ion

Rev. 2.0, 11/01, page 241 of 358

/*****************************************************

* Data table *

******************************************************/

const unsigned char dt_trs[12] =

{

0xa0, /* Slave address + W data */

0x00, /* EEPROM memory address data */

0x01, /* 1st transmit data */

0x23, /* 2nd tr ansmit data */

0x45, /* 3rd tr ansmit data */

0x67, /* 4th transmit data */

0x89, /* 5th transmit data */

0x98, /* 6th transmit data */

0x76, /* 7th transmit data */

0x54, /* 8th transmit data */

0x32, /* 9th transmit data */

0x10 /* 10th transmit data */

};

/*****************************************************

* main : Main routine *

******************************************************/

void main(void)

#pragma asm

mov.l #h'f000,sp ;Stack pointer initialize

#pragma enda sm

{

unsigned char dummy;

dummy = MDCR.BYTE; /* MCU mode set */

SYSCR.BYTE = 0x09; /* Interrupt control mode set */

initialize(); /* Initialize */

trs_stup(); /* Master transmit by DTC set up */

IIC0.ICCR.BIT.IEIC = 1; /* IIC0 interrupt enable */

set_imask_ccr(0); /* Interrupt enable */

Rev. 2.0, 11/01, page 242 of 358

while(txedf < 2); /* Transmit end ? */

while(1); /* End */

}

/*****************************************************

* initialize : RAM & IIC0 Initialize *

******************************************************/

void initialize(void)

{

unsigned char i; /* Transmit data counter */

for(i=0; i<12; i++) /* Transmit data copy ROM -> RAM */

{

dt_trs_ram [i] = dt_t rs [i];

}

txedf = 0x00; /* Tra nsmit en d flag ini ti alize */

STCR.BYTE = 0x00; /* FLSHE = 0 */

MSTPCR.BYTE.H = 0x3f; /* DTC module stop mode reset */

SAR1 = 0x0000e100; /* SAR = H'00E100 */

MRA1 = 0x80; /* MRA = H'80 */

DAR1 = 0x0000ffde; /* DAR = H'00FFED (ICDR0) */

MRB1 = 0x00; /* MRB = H'00 */

CRA1 = 0x000c; /* CRA = H'000C */

CRB1 = 0x0000; /* CRB = H'0000 */

DTC.VECR.BYTE = 0x00; /* SWDTE = 0, DTVEC = H'00 */

DTC.ED.BIT.B4 = 1; /* DTCED4 = 1 */

MSTPCR.BYTE.L = 0x7f; /* SCI0 module stop mode reset */

SCI0.SMR.BYTE = 0x00; /* SCL0 pin function set */

SCI0.SCR.B YTE = 0x00 ;

MSTPCR.BYTE.L = 0xef; /* IIC0 module stop mode reset */

STCR.BYTE = 0x10; /* IICE = 1 */

DDCSWR.BYTE = 0x0f; /* IIC bus format initialize */

IIC0.ICCR.BYTE = 0x01; /* ICE = 0 */

Rev. 2.0, 11/01, page 243 of 358

IIC0.SAR.BYTE = 0x00; /* FS = 0 */

IIC0.SARX.BYTE = 0x01; /* FSX = 1 */

IIC0.ICCR.BYTE = 0x81; /* ICE = 1 */

IIC0.ICSR.BYTE = 0x00; /* ACKB = 0 */

STCR.BYTE = 0x30; /* IICX0 = 1 */

IIC0.ICMR.BYTE = 0x28; /* Transfer rate = 100kHz */

IIC0.ICCR.BYTE = 0x89; /* IEIC = 0, ACKE = 1 */

}

/*****************************************************

* trs_stup : Master transmit by DTC set up *

******************************************************/

void trs_stup(void)

{

while(IIC0.ICCR.BIT.BBSY == 1); /* Bus empty (BBSY=0) ? */

IIC0.ICCR.BIT.MST = 1; /* Matser transmit mode set */

IIC0.ICCR.BIT.TRS = 1; /* MST = 1, TRS = 1 */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

IIC0.ICCR.BYTE = 0xbc; /* Start condition set (BBSY=1,SCP=0) */

while(IIC0.ICCR.BIT.IRIC == 0); /* Start condition set (IRIC=1) ? */

}

/*****************************************************

* iici0 : IIC0 interrupt routine *

******************************************************/

#pragma inte rrupt( ii ci0)

void iici0(void)

{

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

txedf++;

if(txedf > 1)

{

IIC0.ICCR.BIT.IEIC = 0; /* IIC0 interrupt disable */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=0) ? */

Rev. 2.0, 11/01, page 244 of 358

IIC0.ICCR.BYTE = 0xb8; /* Stop condition set (BBSY=0,SCP=0) */

while(IIC0.ICCR.BIT.BBSY == 1); /* Bus empty (BBSY=0) ? */

}

Rev. 2.0, 11/01, page 245 of 358

4.7 Single-Master Reception by DTC

4.7.1 Specifications

• 10-byte data is read from EEPROM (HN58X2408) using channel 0 of the I2C bus interface in

the H8S/2138 and the data transfer controller (DTC).

• The slave address of EEPROM to be connected is 1010000, and data is read from addresses

H'00 to H'09 of the EEPROM memory.

• 10-byte data to be read is stored at addresses H'E100 to H'E109 in RAM.

• The device connected to the I2C b us in this system is a sin gle–master configurationone

master device (H8S/2138) and on e slave device (EEPROM).

• The transfer clock frequency is 100 kHz.

• Figure 4.23 shows an example of the H8S/2138 and EEPROM connection.

SCL0 SCL

SDA

SDA0

H8S/2138

Master

SCL

SDA

EEPROM

Slave

Figure 4.23 Example of H8S/2138 and EEPROM Connection

• Figure 4.24 shows the I2C bus format used in this task example.

Rev. 2.0, 11/01, page 246 of 358

S SLA

7111118

11 1 10

7811 1 11Number of

transmission bits

Number of

transmission frames

Legend:

SLA

MEA

DATA

: Start condition

: EEPROM slave address

: Transmission/reception destination

: Acknowledge

: EEPROM memory address

: Reception data

: Stop condition

A MEA A S SLA A A A PDATA

R/ R/

Figure 4.24 Transfer Format Used in This Task Example

• An example usage of the data transfer controller (DTC) in the H8S/2138 Series used in this

task example is described belo w.

(a) The DTC is activated by an interrupt request of channel 0 in the I2C bus interface (IICI0) and

reception data is transferred.

(b) Normal mode is used for the DTC transfer mode.

Rev. 2.0, 11/01, page 247 of 358

IICI0

(IIC0 interrupt request)

CPU interrupt request

Legend:

MRA, MRB

CRA, CRB

SAR

DAR

DTCERA to DTCERE

DTVECR

: DTC mode register A, B

: DTC count register A, B

: DTC source address register

: DTC destination register

: DTC enables registers A to E

: DTC vector register

Interrupt

controller

DTCERA

DTCERE

DTVECR

DTC

Control logic

MRA

CRA

CRB MRB

DAR

SAR

MRB

On-chip RAM

C bus data register 0 (ICDR0)

Internal I/O register

Internal address bus

Internal data bus

DTC

activate

request

Transfer data

Figure 4.25 Block Diagram of DTC in This Task Example

Rev. 2.0, 11/01, page 248 of 358

(d) Figure 4.26 shows the location of transfer data on on-chip RAM.

Address

H'E100

H'E101

H'E102

H'E103

H'E104

H'E105

H'E106

H'E107

H'E108

H'E109

—

1st-byte reception data

2nd-byte reception data

3rd-byte reception data

4th-byte reception data

5th-byte reception data

6th-byte reception data

7th-byte reception data

8th-byte reception data

9th-byte reception data

10th-byte reception data

On-chip RAM Transfer data

Figure 4.26 Location of Transfer Data on On-Chip RAM

(e) Figure 4.27 shows the location of DTC vector table and register information on the on-chip

RAM in this task example. DTC register information is provided from address H'EC00 to the

MRA, SAR, MRB, DAR, CRA, and CRB registers in that order.

Address Address

H'EC00

H'EC01

H'EC02

H'EC03

H'EC04

H'EC05

H'EC06

H'EC07

H'EC08

H'EC09

H'EC0A

H'EC0B

H'20

H'00

H'FF

H'DE

H'00

H'E1

H'00

H'09

H'00

MRA register information (MRA1)

SAR register information (SAR1)

MRB register information (MRB1)

DAR register information (DAR1)

CRA register information (CRA1)

CRB register information (CRB1)

DTC vector table On-chip RAM

H’04B8

H’04B9 H'EC

H'00

Figure 4.27 Location of DTC Vector Table and Register Information on On-Chip RAM

Rev. 2.0, 11/01, page 249 of 358

(f) Table 4.21 describes the register of the DTC used in this task example.

Table 4.21 DTC Register Description

MRA DTC mode register A

Controls DTC operating mode.

SM1, 0

(bit7, 6) Source address mode 1, 0

Specify whether SAR is incremented, decremented, or fixed after data

transfer is performed.

When SM1 =0 and SM0 = *, SAR is fixed (*: 0 or 1).

When SM1 = 1 and SM0 = 0, SAR is incremented after transfer (when Sz =

0: + 1, when Sz = 1: + 2).

When SM1 =1 and SM0 = 1, SAR is decremented after transfer (when Sz =

0: − 1, when Sz = 1: − 2).

DM1, 0

(bit5, 4) Destination address mode 1, 0

Specify whether DAR is incremented, decremented, or fixed after data

transfer is performed.

When DM1 = 0 and DM0 = *, DAR is fixed (*: 0 or 1).

When DM1 = 1 and DM0 = 0, DAR is incremented after transfer (when Sz

= 0: + 1, when Sz = 1: + 2).

When DM1 = 1 and DM0 = 1, DAR is decremented after transfer (when Sz

= 0: − 1, when Sz = 1: − 2).

MD1, 0

(bit3, 2) DTC mode 1, 0

Specify DTC transfer mode.

When MD1 = 0 and MD0 = 0, normal mode.

When MD1 = 0 and MD0 = 1, repeat mode .

When MD1 = 1 and MD0 = 0, block transfer mode.

When MD1 = 1 and MD0 = 1, setting prohibited.

DTS

(bit1) DTC transfer mode select

Specifies either source side or destination side becomes repeat area or

block area in repeat mode or block transfer mode.

When DTS = 0, destination side becomes repeat area or block area.

When DTS = 1, source side becomes repeat area or block area.

(bit0) DTC data transfer size

Specifies data size in data transfer.

Rev. 2.0, 11/01, page 250 of 358

Table 4.21 DTC Register Description (cont)

MRB DTC mode register B

Controls DTC mode.

CHEN

(bit7) DTC chain transfer enable

Specifies chain transfer.

When CHEN = 0, DTC data tran sfer is ended.

When CHEN = 1, DTC chain transfer.

MRB DISEL

(bit6) DTC interrupt select

Specifies an interrupt request to CPU is disabled or enabled after one data

transfer is performed.

When DISEL = 0, an interrupt to CPU is disabled if transfer counter is not 0

after the DTC data transfer is ended.

When DISEL = 1, an interrupt to CPU is enabled after the DTC data transfer

is ended.

SAR DTC source address register

Specifies the transfer source address of data to be transferred by the DTC.

DAR DTC destination address register

Specifies the transfer destination address of data to be transferred by the

DTC.

CRA DTC transfer count register A

Specifies the number of data transfers by the DTC.

CRB DTC transfer count register B

Specifies the number of block data transfers by the DTC in block transfer

mode.

DTVECR (H'FEF3) DTC vector register

Sets the DTC activation to be enabled or disabled by software and sets the

vector address for the software activation interrupt.

SWDTE

(bit7) DTC software activation enable

Sets the DTC software activation to be enabled or disabled.

When SWDTE = 0, the DTC software activation is disabled.

When SWDTE = 1, the DTC software activation is enabled.

DTVEC

6-0

(bit6-0)

DTC software activation vectors 6 to 0

Set the vector address for the DTC software activation.

Rev. 2.0, 11/01, page 251 of 358

Table 4.21 DTC Register Description (cont)

DTCERD (H'FEF1) DTC enable register

Controls the enabling or disabling of DTC activation by each interrupt source.

DTCED4

(bit4) DTC activation enable D4

When DTCED4 = 0, the DTC activation is disabled by the IICI0 interrupt.

When DTCED4 = 2, the DTC ac tivation is enabled by the IICI0 interrupt.

(g) The I2C bus format provides for selection of the slave device and transfer direction by means

of the slave address and the R/: bit, confirmation of reception with the acknowledge bit,

indication of the last frame, and so on. Therefore, continuous data transfer using the DTC must

be carried out in conjunction with CPU processing by means of interrupts. Table 4.22 shows

an example of processing using the DTC in master transmission mode in this task example.

Table 4.22 Operation Example by DTC (master reception mode)

Item Master Transmission Mode

Slave address + R/W bit

transmission Tra nsmission by CPU (ICDR write)

Dummy data read Processing by CPU (ICDR read)

Actual data transmission Reception by DTC (ICDR read)

Dummy data (H’FF) write —

Last frame processing Not necessary

Transfer request processing after

last frame processing Not necessary

Setting of number of DTC transfer

data frames Reception: Actual data count

Rev. 2.0, 11/01, page 252 of 358

4.7.2 Description of Operation

Figure 4.28 shows the principle of operation.

SCL

SDA

SCL

SDA

[1] [2] [3] [4] [5] [5]

[5] [5] [5] [6] [7] [8]

10µs Transmission/reception clock frequency= 100kHz

Ack

Start

condition

Slave address

+ R/ =H'A0 Slave address

+ R/ =H'A1

Memory address

=H'00

1st reception

data

6th reception

data

7th reception

data 8th reception

data 9th reception

data

10th reception

data

2nd reception

data

3rd reception

data

Start

condition

Ack

···

No operation

No operation, IRIC = 0

Reading of the data for reception

No operation

CPU processing DTC processing

Stop condition

Ack Ack Ack

Ack Ack Ack Ack

Ack

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

IRIC=0, Setting of start condition (BBSY=1, SCP

=0), transmission of slave address + W bit, IRIC=0

EEPROM address transmission, IRIC=0

IRIC=0, Setting of start condition (BBSY=1, SCP

=0), transmission of slave address + R bit, IRIC=0

Dummy read, IRIC=0, IEIC=1

No operation

IEIC=1, ACKB=1, WAIT=1 Reading of the

9th byte of data for reception, IRIC=0

TRS=1 Reading of the 10th byte of data

for reception, IRIC=0

Setting of the stop condition (BBSY=1, SCP=0)

Figure 4.28 Principle of a Single-Master Receive Operation by DTC

Rev. 2.0, 11/01, page 253 of 358

4.7.3 Description of Software

(1) Description of Modules

Table 4.23 describes the modules of this example of a task.

Table 4.23 Description of Modules

Module Name Label Name Function

Main routine main Sets the stack pointer and the MCU mode, and enables the

interrupt.

Initial settings initialize Sets the RAM area to be used, and makes initial settings

for IIC0 and DTC.

Setting of start

condition set_start Sets the start condition.

Setting of stop

condition set_stop Sets the stop condition.

Transmiss ion of

slave address + W trs_slvadr_a0 Transmits the EEPROM’s slave address and W data

(H’A0).

Transmiss ion of

slave address + R trs_slvadr_a1 Transmits the EEPROM’s slave address and W data

(H’A1).

Transmission of the

EEPROM memory

address

trs_memadr Transmits the EEPROM’s address in memory (H’00).

Processing of the

IIC0 interrupt iici0 Clears IrIC, disables the IICI0 interrupt, and sets the

reception-comp leted flag .

Rev. 2.0, 11/01, page 254 of 358

(2) Description of the On-chip Registers

Table 4.24 describes the on-chip registers used in this example of a task.

Table 4.24 Description of the On-c hip Registers

ICDR0 Stores the received data. H'FFDE —

SAR0 FS Along with the settings of the FSX bit of SARX0 and

the SW bit of DDCSWR, sets the transfer format. H'FFDF bit00

SARX0 FSX Along with the settings of the FS bit of SAR0 and

the SW bit of DDCSWR, sets the transfer format. H'FFDE bit01

MLS Sets the transfer of data as MSB first. H'FFDF bit70

WAIT Selects insertion and non-insertion of wait cycles

between the data and the acknowledge bit. H'FFDF bit60/1

CKS2

CKS0

Along with the setting in the IICX0 bit of STCR, set

the frequency of the transfer clock to 100 kHz. H'FFDF

bit5 to

bit3

CKS2=1

CKS1=0

CKS0=1

ICMR0

BC2

BC0

Set the number of bits of data for the next transfer

in the I2C bus format to 9 bits/frame. H'FFDF

bit2 to

bit0

BC2=0

BC1=0

BC0=0

ICE Controls access to the ICMR0, ICDR0/SAR, and

SARX registers, and selects operation (port function

for the SCL0/SDA0 pin) or non-operation (bus-drive

state for the SCL/SDA pin) of the I2C bus interface.

H'FFD8 bit70/1

ICCR0

IEIC Disables the generation of interrupt requests by the

I2C bus interface. H'FFD8 bit60/1

MST Uses the I2C bus interface in the master mode. H'FFD8 bit51

TRS Sets transmission/reception mode for the I2C bus

interface. H'FFD8 bit40/1

ACKE Suspends continuous transfer when the

acknowle dge bit is 1. H'FFD8 bit3 1

BBSY Confirms whether or not the I2C bus is occup ied,

and uses the SCP bit to set the start and stop

conditions.

H'FFD8 bit20/1

IRIC Detects the start condition, determines the end of

data transfer, and detects acknowledge = 1. H'FFD8 bit1 0/1

ICCR0

SCP Along with the BBSY bit, sets the start/stop

conditions. H'FFD8 bit00

Rev. 2.0, 11/01, page 255 of 358

Table 4.24 Description of On-chip Registers (c ont)

ICSR0 ACKB Stores the acknowledgement received from the

EEPROM during transmission. Sets the

acknowledge bit for transmission to the EEPROM

during reception.

H'FFD9 bit0—

IICX0 Along with the settings in CKS2 to CKS0 of ICMR0,

selects the frequency of the transfer clock. H'FFC3 bit5 1

IICE Enables CPU access to the data and control

registers of the I2C bus interfa ce. H'FFC3 bit4 1

STCR

FLSHE Sets the control registers of the flash memory to

non-selected. H'FFC3 bit3 0

SWE Prohibits automatic change from format-less

transfer to transfer in the I2C bus format on the

channel 0 I2C interfac e.

H'FEE6 bit70

SW Uses the channel 0 I2C interface in the I2C bus

format. H'FEE6 bit60

IE Prohibits interrupts during automatic changes of

format. H'FEE6 bit50

DDCSWR

CLR3

CLR0

Control the initialization of the internal state of the

I2C interface H'FEE6

bit3 to

bit0

CLR3=1

CLR2=1

CLR1=1

CLR0=1

MSTP7 Cancels the module-stopped mode for SCI channel

0. H'FF87 bit7 0MSTPCRL

MSTP4 Cancels the module stopped mode for I2C channel

0. H'FF87 bit4 0

SCR0 CKE1, 0 Makes the I/O port setting for the P52/SCK0/SCL0

pin. H'FFDA

bit1, 0 CKE1=0

CKE0=0

SMR0 C/$Sets the mode for SCI transfer on channel 0 as

asynchronous. H'FFD8 bit70

SYSCR INTM1, 0 Set the interrupt control mode of the interrupt

controller to 1-bit control. H'FFC4

bit5, 4 INTM1=0

INTM0=0

MDCR MDS1, 0 Set the MCU’s operating mode to mode 3 by

latching the input levels on the MD1 and 0 pins. H'FFC5

bit1, 0 MDS1=1

MDS0=1

Rev. 2.0, 11/01, page 256 of 358

Table 4.24 Description of On-chip Registers (c ont)

SM1, 0 Set SAR to remain fixed after data has been

transferred. H'EC00

bit7, 6 SM1=0

SM0=0

DM1, 0 Set DAR to be incremented after data has been

transferred. H'EC00

bit5, 4 DM1=1

DM0=0

MRA

MD1, 0 Set the DTC transfer mode to normal. H'EC00

bit3, 2 MD1=0

MD0=0

DTS Sets the destination area to the repeat area or the

block area. H'EC00

bit1 DTS=0MRA

Sz Sets bytes as the unit for data transfer. H'EC00

bit0 Sz=0

CHNE Disables DTC-chain transfer. H'EC04

bit7 CHNE=0MRB

DISEL Prohibits the generati on of an interr upt si gnal for the

CPU after a single transfer of data unless the

transfer counter is 0.

H'EC04

bit6 DISEL=0

SAR Sets the transfer source address transferred by the

DTC to H’FFDE. H'EC01 H'00FFDE

DAR Sets the transfer destination address transferred by

the DTC to H’E100. H'EC05 H'00E100

CRA Sets the DTC transfer count to 12. H'EC08 H'000C

CRB Sets the DTC block-data transfer count to 0 during

transfer in block-transfer mode. H'EC0A H'0000

SWDTE Prohibits the activation of the DTC software. H'FEF3 bit7 0DTVECR

DTVEC6

DTVEC0

Set the vector number of for the acti vation of the

DTC software to H’00. H'FEF3

bit6 to

bit0

H'00

DTCERD DTCED4 Enables DTC activation by the I2CI0 interrupt. H'FEF1 bit4 1

MSTPCR

HMSTP14 Removes the DTC from its module-stopped mode. H'FF86 bit6 0

Rev. 2.0, 11/01, page 257 of 358

(3) Description of Variables

Table 4.25 describes the variables used in this task.

Table 4.25 Description of Variables

Variable Function Size Initial

Value Module Name

dummy MDCR read value 1 byte — Main

i Received data counter 1 byte H'00 Initialize

(4) Description of RAM Usage

Table 4.26 describes the usage of RAM in this example of a task.

Table 4.26 Description of RAM Usage

Label Function Size Address Module Name

MRA1 DTC mode register 1 byte H'EC00 initialize

SAR1 DTC source address register 4 bytes H'EC00 initialize

MRB1 DTC mode register B 1 byte H'EC04 initialize

DAR1 DTC destination address register 4 bytes H'EC04 initialize

CRA1 DTC transfer count register A 2 bytes H'EC08 initialize

CRB1 DTC transfer count register B 2 bytes H'EC0A initialize

rxedf Reception-completed flag 1 byte H'E200 main

iici0

dt_rec_ram

[0]

dt_rec_ram

[9]

Stores 10 bytes of received data. 10 bytes H'E100

H'E109

main

initialize

Rev. 2.0, 11/01, page 258 of 358

4.7.4 Flowchart

(1) Main Routine

initalize

main

SYSCR H'09

MST 1

TRS 1

SP H'F000

trs_memadr

trs_slvadr_a0

set_start

ACKB = 0 ?

Yes

BBSY = 0 ?

ACKB = 0 ?

ACKB 0

trs_slvadr_a1

set_start

············

··············

············

··············

············

······ Bus released?

Set the MST and TRS bits of ICCR0 to 1 to select

the master transmission mode for IIC0.

Acknowledgement received from the EEPROM?

Call the subroutine for transmitting the slave address + W bit.

Call the subroutine to transmit the EEPROM memory-address.

Acknowledgement received from the EEPROM?

·············· Call the subroutine that sends the start-condition signal.

·············· Call the subroutine for transmitting the slave address + R bit.

············ Acknowledgement received from the EEPROM?

·············· ACKB = 0 (0 output in the time slot for output of the acknowledge

bit during a receive operation).

Call the subroutine that sends the start-condition signal.

·············· Set SP (stack pointer) to H'F000.

··············

Latch the input levels on the MD1 and MD0 pins to

the MDS1 and MDS0 bits by reading MDCR.

··············

Set the interrupt-control mode of the interrupt

controller to 1-bit interrupt control.

Call the subroutine that makes the initial settings.

ACKB = 0 ? 1

Read MDCR

Rev. 2.0, 11/01, page 259 of 358

IRIC 0

IEIC 1

CCR 1bit 0

WAIT 1

TRS 0

dt_rec_ram[8]

ICDR0

dt_rec_ram[0]

ICDR0

ACKB 1

Yes

rxedf ! = 0 ?

Yes

IRIC = 1 ?

Yes

IRIC = 1 ?

TRS 1

IRIC 0

··············

··· Receiving of data by the DTC complete?

WAIT = 1 (insert a wait cycle between the data and acknowledge bits)

··· Receiving of data completed?

··· Output of the 9th cycle of the receive clock completed

(on the rising edge of the 9th cycle of the receive clock)?

Clear IRIC to 0 to determine whether or not the data has been

completely received (on the falling edge of the 8th cycle of the

receive clock).

Read the 9th byte of received data and store the data in RAM.

·············· TRS = 1 (set to the master transmission mode)

·············· IRIC = 0 (start outputting the 9th cycle of the receive clock)

ACKB = 1 (1 output in the time slot for output of the acknowledge bit

during a receive operation)

·············· TRS = 0 (set this interface to run in the master-receive mode)

··············

Dummy read (start of the receive operation)

··············

Clear IRIC to determine whether or not the data has been completely

received (on the rising edge of the 9th cycle of the receive clock).

IEIC = 1 (enable the IICI0 interrupt request)

·············· Clear the 1 bit to 0 to enable interrupts.

Rev. 2.0, 11/01, page 260 of 358

dt_rec_ram[9]

ICDR0 Read the 10th byte of received data and store the data in the RAM.

Set the stop condition.

ACKB = 0

WAIT = 0

WAIT 0

ACKB 0

··············

set_stop

Rev. 2.0, 11/01, page 261 of 358

(2) Subrout ine for Making Init ial Settings

i 0

i++

dt_rec_ram[i] 0

Initialize the received-data counter.

Set the FLSHE bit of STCR to 0 to set the control register

of the flash memory to non-selective.

Set MRA to H'20, SAR to "fixed" after data has been transferred,

DAR to increment, the DTC transfer mode to normal, and the

unit for the transfer of data to bytes.

Set DAR to H'00E100 and the destination address for data

transfer by the DTC to H'E100.

Set DTVECR to H'00 to disable initiation of the DTC software.

Set DTCED4 to 1 to allow the IICI0 interrupt to activate the DTC.

Increment the received-data counter.

Initialize the reception-completed flag.

Received-data counter < 10?

Initialize the received-data storage area.

Set the MSTP14 bit of MSTPCRH to 0 to take the DTC out

of its module-stopped mode.

Set SAR to H'00FFDE and the source address of the data

for transfer by the DTC to H'FFDE (ICDR0).

Set MRB to H'00 and disable DTC chain transfer. Prohibit the

generation of an interrupt for the CPU after data has been

transferred by the DTC unless the transfer counter is at 0.

Set CRA to H'000C and the DTC data transfer count to nine.

Set CRB to H'0000 and the DTC block data transfer count to 0.

initialize

···················

·············

···················

·············

···················

i < 10 ? No

Yes

MRB1 H'00

rxedf H'00

STCR H'00

MRA1 H'20

CRB1 H'0000

DAR1 H'0000E100

CRA1 H'0009

DTCED4 1

DTVECR H'00

MSTPCRH H'3F

SAR1 H'0000FFDE

Rev. 2.0, 11/01, page 262 of 358

MSTPCRL H'7F

SMR0 H'00

ICCR0 H'01

STCR H'10

ICCR0 H'89

SAR0 H'00

SARX0 H'01

STCR H'30

ICMR0 H'28

ICCR0 H'81

ICSR0 H'00

SCR0 H'00

MSTPCRL H'EF

DDCSWR H’0F

Set the MSTP7 bit of MSTPCRL to 0 to take the SC10 out of its

module-stopped mode.

Set the SMR's C/ bit to 0 to set the SCI0 to operate in its

asynchronous mode.

Set ICCR0's ICE bit to 0 to enable access to SAR0 and SARX0.

Set ICSR0's ACKB bit to 0.

Set IICX0 in STR to 1, ICMR0's CKS2 bit to 1, TCKS1 bit to 0, and CKS0

bit to 1 so that the frequency of the IIC0 transfer clock is set to 100 kHz.

Set WAIT to 0 for the continuous transfer of data and acknowledge bits.

Set IEIC in ICCR0 to 0 to disable the generation of IIC0 interrupt requests,

and set ACKE to 1 to suspend continuous transfer when the acknowledge

bit is 1.

Set FS in SAR0 and FSX in SARX0 to 0 to select the I

C bus format

(enables the SAR slave address and disables the SARX slave address)

as the format for transfer on IIC0.

Set the STCR's IICE bit to 1 so that the data and control registers

of the I

C bus interface are accessible by the CPU.

Set the SCR's CKE1 bit to 0 and CKE bit to 0 to set the SCK0 pin

for use as an I/O port.

Set the SWE, SW, and IE bits of DDCSWR to 0 to disable automatic

changeover from IIC0 format-less to I

C bus format, select use of IIC0

in the I

C bus format, and disable interrupts during the execution

of automatic format changeover.

Set the MSTPCRL's MSTP7 bit to 1 and MSTP4 bit to 0 to put SCI0

in its module-stopped mode and take IIC0 out of its module-stopped mode.

Set ICCR0's ICE bit to 1 to enable access to ICMR0 and ICDR0.

rts

················

··········

················

··········

Rev. 2.0, 11/01, page 263 of 358

(3) Subroutine for Setting the Sta r t Conditio n

set_start

rts

IRIC 0

ICCR0 H'BC

················

·······

IRIC = 1 ? No

Yes

Clear IRIC to determine detection of the start condition.

Set ICCR0's BBSY bit to 1 and SCP bit to 0 to set the start condition.

Detect the start condition from the bus-line state?

(4) Subroutine for Setting the Sto p Co ndition

set_stop

rts

ICCR0 H'B8 ················

·······

BBSY = 0 ? No

Yes

Set ICCR0's BBSY bit to 0 and SCP bit to 0 to set the

stop condition.

Bus-released state?

Rev. 2.0, 11/01, page 264 of 358

(5) Subroutine for Transmitting the Sla ve Address + W

trs_slvadr_a0

rts

ICCR0 H'A0

IRIC 0

················

·······

IRIC = 1 ? No

Yes

Transmit the EEPROM's slave address + the W bit (H'A0)

Clear IRIC to 0 to determine whether or not the data has been

transmitted (on the rising edge of the 9th cycle of the

transmission clock).

End of the transmission of the EEPROM slave address + W?

(6) Subroutine for Transmitting the Sla ve Address + R

trs_memadr

rts

ICCR0 H'A1

IRIC 0

················

·······

IRIC = 1 ? No

Yes

Transmit the EEPROM's slave address + the R bit (H'A1)

Clear IRIC to 0 to determine whether data has been transmitted

(at the rising edge of the 9th clock of the transmission clock).

Transmission of the EEPROM memory address complete?

Rev. 2.0, 11/01, page 265 of 358

(7) Subroutine for Transmitting the EEPROM memory a ddress

trs_memadr

rts

ICCR0 H'00

IRIC 0

················

·······

IRIC = 1 ? No

Yes

Transmit EEPROM memory address data (H'00).

Clear IRIC to 0 to determine whether data has been transmitted

(on the rising edge of the 9th cycle of the transmission clock).

Transmission of EEPROM memory address as data complete?

(8) IIC0 Interrupt-Processing Routine

iici0

IRIC 0 IRIC = 0 (clearing of the interrupt request flag)

IEIC = 0 (prohibition of IICI0 interrupt requests)

Set reception-completed flag.

rxedf++

IEIC 0

················

rts

Rev. 2.0, 11/01, page 266 of 358

4.7.5 Program List

/*****************************************************

* H8S/2138 IIC bus application note *

* 6.Single master receive by DTC *

* File na me : DTCrx.c *

* Fai : 20MHz *

* Mode : 3 *

******************************************************/

#include <stdio.h>

#include <machine.h>

#include "2138s.h"

/*****************************************************

* Prototype *

******************************************************/

void main(void); /* Main routine */

void initialize(void); /* RAM & DTC & IIC0 initialize */

void set_start(void); /* Start condition set */

void set_stop(void); /* Stop condition set */

void trs_slvadr_a0(void); /* Slave address + W data transmit */

void trs_slvadr_a1(void); /* Slave address + R data transmit */

void trs_memadr(void); /* EEPROM memory address data transmit */

/*****************************************************

* RAM allocation *

******************************************************/

#define MRA1 (*(volatile unsigned char *)0xec00) /* DTC mode register A */

#define SAR1 (*(volatile unsigned long *)0xec00) /* DTC source address register */

#define MRB1 (*(volatile unsigned char *)0xec04) /* DTC mode register B */

#define DAR1 (*(volatile unsigned long *)0xec04) /* DTC destination address register */

#define CRA1 (*(volatile unsigned short *)0xec08) /* DTC transfer count register A */

#define CRB1 (*(volatile unsigned short *)0xec0a) /* DTC transfer count register B */

#define rxedf (*(volatile unsigned char *)0xe200) /* Receive end flag */

#pragma sect ion rama re a

Rev. 2.0, 11/01, page 267 of 358

unsigned char dt_rec_ram[10]; /* Receive data store erea */

#pragma sect ion

/*****************************************************

* main : Main routine *

******************************************************/

void main(void)

#pragma asm

mov.l #h'f000,sp ;Stack pointer initialize

#pragma enda sm

{

unsigned char dummy;

dummy = MDCR.BYTE; /* MCU mode set */

SYSCR.BYTE = 0x09; /* Interrupt control mode set */

initialize(); /* Initialize */

while(IIC0.ICCR.BIT.BBSY == 1); /* Bus empty (BBSY=0) ? */

IIC0.ICCR.BIT.MST = 1; /* Master transmit mode set */

IIC0.ICCR.BIT.TRS = 1; /* MST=1, TRS=1 */

set_start(); /* Start condition set */

trs_slvadr_a0(); /* Slave address + W data transmit */

if(IIC0.ICSR.BIT.ACKB == 0) /* ACKB = 0 ? */

{

trs_memadr(); /* EEPROM memory address data transmit */

if(IIC0.ICSR.BIT.ACKB == 0) /* ACKB = 0 ? */

{

set_start(); /* Re-start condition set */

trs_slvadr_a1(); /* Slave address + R data transmit */

if(IIC0.ICSR.BIT.ACKB == 0) /* ACKB = 0 ? */

{

IIC0.ICSR.BIT.ACKB = 0; /* ACKB = 0 */

IIC0.ICCR.BIT.TRS = 0; /* Master receive mode set */

dt_rec_ram[0] = IIC0.ICDR; /* Dummy read */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

IIC0.ICCR.BIT.IEIC = 1; /* IEIC = 1 (IICI0 interrupt enable) */

Rev. 2.0, 11/01, page 268 of 358

set_imask_ccr(0); /* Inte rrupt enable */

while(rxedf == 0x00); /* rxedf != 0 ? */

IIC0.ICMR.BIT.WAIT = 1; /* WAIT = 1 */

IIC0.ICSR.BIT.ACKB = 1; /* ACKB = 1 */

dt_rec_ram[8] = IIC0.ICDR; /* 9th receive data read */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Receieve end (IRIC=1) ? */

IIC0.ICCR.BIT.TRS = 1; /* Master transmit mode set */

IIC0.ICCR.BIT.IRIC = 0; /* 9th clock transmit (IRIC=0) */

while(IIC0.ICCR.BIT.IRIC == 0); /* 9th clock transmit end (IRIC=1) ? */

dt_rec_ram[9] = IIC0.ICDR; /* 10th (last) receive data read */

IIC0.ICSR.BIT.ACKB = 0; /* ACKB = 0 */

IIC0.ICMR.BIT.WAIT = 0; /* WAIT = 0 */

}

set_stop(); /* Stop condition set */

while(1); /* End */

}

/*****************************************************

* initialize : RAM & IIC0 Initialize *

******************************************************/

void initialize(void)

{

unsigned char i; /* Receive data counter */

for(i=0; i<10; i++) /* Receive data store area initialize */

{

Rev. 2.0, 11/01, page 269 of 358

dt_rec_ram [i] = 0x00 ;

}

rxedf = 0x00; /* Receive end flag initialize */

STCR.BYTE = 0x00; /* FLSHE = 0 */

MSTPCR.BYTE.H = 0x3f; /* DTC module stop mode reset */

SAR1 = 0x0000ffde; /* SAR = H'00FFDE (ICDR0) */

MRA1 = 0x20; /* MRA = H'20 */

DAR1 = 0x0000e100; /* DAR = H'00E100 */

MRB1 = 0x00; /* MRB = H'00 */

CRA1 = 0x0009; /* CRA = H'0009 */

CRB1 = 0x0000; /* CRB = H'0000 */

DTC.VECR.BYTE = 0x00; /* SWDTE = 0, DTVEC = H'00 */

DTC.ED.BIT.B4 = 1; /* DTCED4 = 1 */

MSTPCR.BYTE.L = 0x7f; /* SCI0 module stop mode reset */

SCI0.SMR.BYTE = 0x00; /* SCL0 pin function set */

SCI0.SCR.B YTE = 0x00 ;

MSTPCR.BYTE.L = 0xef; /* IIC0 module stop mode reset */

STCR.BYTE = 0x10; /* IICE = 1 */

DDCSWR.BYTE = 0x0f; /* IIC bus format initialize */

IIC0.ICCR.BYTE = 0x01; /* ICE = 0 */

IIC0.SAR.BYTE = 0x00; /* FS = 0 */

IIC0.SARX.BYTE = 0x01; /* FSX = 1 */

IIC0.ICCR.BYTE = 0x81; /* ICE = 1 */

IIC0.ICSR.BYTE = 0x00; /* ACKB = 0 */

STCR.BYTE = 0x30; /* IICX0 = 1 */

IIC0.ICMR.BYTE = 0x28; /* Transfer rate = 100kHz */

IIC0.ICCR.BYTE = 0x89; /* IEIC = 0, ACKE = 1 */

}

/*****************************************************

* set_start : Start condition set *

******************************************************/

void set_start(void)

Rev. 2.0, 11/01, page 270 of 358

{

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

IIC0.ICCR.BYTE = 0xbc; /* Start condition set (BBSY=1,SCP=0) */

while(IIC0.ICCR.BIT.IRIC == 0); /* Start condition set (IRIC=1) ? */

}

/*****************************************************

* set_stop : Stop condition set *

******************************************************/

void set_stop(void)

{

IIC0.ICCR.BYTE = 0xb8; /* Stop condition set (BBSY=0,SCP=0) */

while(IIC0.ICCR.BIT.BBSY == 1); /* Bus empty (BBSY=0) ? */

}

/*****************************************************

* trs_slvadr_a0 : Slave address + W data transmit *

******************************************************/

void trs_slvadr_a0(void)

{

IIC0.ICDR = 0xa0; /* Slave address + W data(H'A0) write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

/*****************************************************

* trs_slvadr_a1 : Slave address + R data transmit *

******************************************************/

void trs_slvadr_a1(void)

{

IIC0.ICDR = 0xa1; /* Slave address + R data(H'A1) write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

Rev. 2.0, 11/01, page 271 of 358

/*****************************************************

* trs_memadr : EEPROM memory address data transmit *

******************************************************/

void trs_memadr(void)

{

IIC0.ICDR = 0x00; /* EEPROM memory address data(H'00) write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

/*****************************************************

* iici0 : IIC0 interrupt routine *

******************************************************/

#pragma inte rrupt( ii ci0)

void iici0(void)

{

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

IIC0.ICCR.BIT.IEIC = 0; /* IEIC = 0 (IICI0 interrupt disable) */

rxedf++; /* rxedf flag set */

}

Rev. 2.0, 11/01, page 272 of 358

4.8 Slave Transmission

4.8.1 Specifications

• Channel 0 of the I2C bus interface is used to transmit, from one H8S/2138 in the slave-

transmission mode, 10 bytes of data to the master H8S/2138.

• The slave addr ess of the H8S/2138 that acts as th e slave transmitter is [0011100].

• The data to be transmitted is H'00, H'11, H'22, H'33, H'44, H'55, H'66, H'77, H'88, and H'99 .

• The connection of devices to the I2C bus in this system is in the sin gle-master configuration:

there is one master device (H8S/2138) and one slave device (H8S/2138).

• The frequency of the transfer clock is 100 kHz.

• Figure 4.29 shows an example of such a connection between two H8S/2138s.

SCL

SDA

SCL0

SDA0

H8S/2138

SCL0

SDA0

H8S/2138

Slave

Master

Figure 4.29 Example of Two H8S/2138s Connected in a Single-Master Configuration

• The I2C bus format used in this example of a task is shown in Fig. 4.30.

Rev. 2.0, 11/01, page 273 of 358

171

1818

111

Number of

transmission bits

Number of

transmission frames

SLA A A A A PDATA DATA

Legend: : Start condition

: Slave address

: Direction, as transmission/reception

: Acknowledge

: Transmitted data

: Stop condition

SLA

DATA

Figure 4.30 Transfer Format used in this Example of a Task

4.8.2 Description of Operation

Figure 4.31 shows this example's principle of operation.

Rev. 2.0, 11/01, page 274 of 358

SCL

SDA

TDRE

IRIC

[1]

[5] [5]

[3]

[2]

10µs Reception clock frequency

Slave-reception mode

Start condition

Slave address

+ R/ = H'39

1st transmission

data = H'00 2nd transmission

data = H' 11 3rd transmission

data = H'22 10th transmission

data = H'99

Stop

condition

Ack

Slave-transmission mode

No operation

IRIC = 1 (at rising of 9th clock)

TDRE =1 (TRS = 0 TRS = 1)

TDRE = 0 (writes data to ICDRT with TRS being 1)

TDRE = 1 (transfers data from ICDRT to ICDRS)

No operation

IRIC=1, TDRE=0 (detects stop condition from the bus line

state)

Software processing Hardware processing

···

AckAck

[5]

Ack Ack Ack

[4] [4] [4]

[6] [6] [6]

[5]

[4]

[6]

[5] [7]

[4] [4]

[6] [6]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

No operation

Writes the data for transmission

to ICDR0

No operation

Clear IRIC to 0.

Figure 4.31 Slave Transmission: Principle of Operation

Rev. 2.0, 11/01, page 275 of 358

4.8.3 Description of Software

(1) Description of Modules

Table 4.27 describes the details of the modules used in this example of a task.

Table 4.27 Description of Modules

Name Label Function

Main routine main Sets stack pointers and the MCU mode, and enables an

interrupt.

Initial settings initialize Makes initial settings of IIC0.

Slave transmission slv_trs Uses slave transmission to transmit 10 bytes of data to

the other H8S/2138.

(2) Description of On-chip Registers

Table 4.28 describes the usage of on-chip registers in this example of a task.

Table 4.28 On-chip Registers

ICDR0 Stores the data for transmission. H'FFDE —

FS Along with the settings in the FSX bit of SARX0 and

the SW bit of DDCSWR, sets the format for transfer.H'FFDF bit00SAR0

SVA6

SVA0

Hold the slave address of the slave H8S/2138. H'FFDF

bit7 to

bit1

SVA6=0

SVA5=0

SVA4=1

SVA3=1

SVA2=1

SVA1=0

SVA0=0

SARX0 FSX Along with the settings in the FS bit of SAR0 and

the SW bit of DDSWR, sets the format for transfer. H'FFDE bit01

Rev. 2.0, 11/01, page 276 of 358

Table 4.28 On-chip Registers (Continued)

MLS Sets data transfer as MSB first. H'FFDF bit70

WAIT Sets continu ous tran sfer of data and ack nowl edge

bits. H'FFDF bit60

CKS2

CKS0

Along with the setting in the IICX0 bit of STCR, set

the frequency of the transfer clock to 100 kHz. H'FFDF

bit5 to

bit3

CKS2=1

CKS1=0

CKS0=1

ICMR0

BC2

BC0

Set the number of bits for the next transfer in the I2C

bus format to 9 (9 bits/frame). H'FFDF

bit2 to

bit0

BC2=0

BC1=0

BC0=0

ICE Controls access to the ICMR0, ICDR0/SAR, and

SARX registers, and selects the operation (the port

function for the SCL0/SDA0 pin) or non-operation

(bus-drive state for the SCL/SDA pin) of the I2C bus

interface.

H'FFD8 bit70/1

ICCR0

IEIC Disables the generation of interrupt requests by the

I2C bus interface. H'FFD8 bit60

MST Uses the I2C bus interface in its slave mode. H'FFD8 bit5 1

TRS Uses the I2C bus interface in its transmission mode. H'FFD8 bit41

ACKE Suspends the continuous transfer of data when the

acknowle dge bit is 1. H'FFD8 bit3 1

BBSY Confirms whether or not the I2C bus is occup ied,

and, in combination with the SCP bit, sets the start

and stop condit ion s.

H'FFD8 bit20/1

IRIC Detects the start condition, determines the end of

data transfer, and detects acknowledge = 1. H'FFD8 bit1 0/1

ICCR0

SCP Along with the BBSY bit, sets the start/stop

conditions. H'FFD8 bit00

ICSR0 ACKB Stores the acknowledgement received from the

EEPROM during transmission. Sets the

acknowledge bit for transmission to the EEPROM

during reception.

H'FFD9 bit0-

IICX0 Along with the settings in CKS2 to CKS0 of ICMR0,

selects the frequency of the transfer clock. H'FFC3 bit5 1

IICE Enables CPU access to the data and control

registers of the I2C bus interfa ce. H'FFC3 bit4 1

STCR

FLSHE Sets the control registers of the flash memory to

non-selected. H'FFC3 bit3 0

Rev. 2.0, 11/01, page 277 of 358

Table 4.28 On-chip Registers (Continued)

SWE Prohibits automatic change from format-less

transfer to transfer in the I2C bus format on the

channel 0 I2C interfac e.

H'FEE6 bit70

SW Uses the channel 0 I2C interface in the I2C bus

format. H'FEE6 bit60

IE Prohibits interrupts during automatic changes of

format. H'FEE6 bit50

DDCSWR

CLR3

CLR0

Control the initialization of the internal state of the

I2C interface H'FEE6

bit3 to

bit0

CLR3=1

CLR2=1

CLR1=1

CLR0=1

MSTP7 Cancels the module-stopped mode for SCI channel

0. H'FF87 bit7 0MSTPCRL

MSTP4 Cancels the module stopped mode for I2C channel

0. H'FF87 bit4 0

SCR0 CKE1, 0 Make the I/O port setting for the P52/SCK0/SCL0

pin. H'FFDA

bit1, 0 CKE1=0

CKE0=0

SMR0 C/$Sets the mode for SCI transfer on channel 0 as

asynchronous. H'FFD8 bit70

SYSCR INTM1, 0 Set the interrupt control mode of the interrupt

controller to 1-bit control. H'FFC4

bit5, 4 INTM1=0

INTM0=0

MDCR MDS1, 0 Set the MCU’s operating mode to mode 3 by

latching the input levels on the MD1 and 0 pins. H'FFC5

bit1, 0 MDS1=1

MDS0=1

Rev. 2.0, 11/01, page 278 of 358

(3) Description of Variables

Table 4.29 describes the variables used in this task.

Table 4.29 Description of Variables

Variable Function Size Initial

Value Module Name

dt_trs[0] Stores first byte of data for transmission. 1 byte H'00 slv_trs

dt_trs[1] Stores second byte of data for transmission. 1 byte H'11 slv_trs

dt_trs[2] Stores third byte of data for transmission. 1 byte H'22 slv_trs

dt_trs[3] Stores fourth byte of data for transmission. 1 byte H'33 slv_trs

dt_trs[4] Stores fifth byte of data for transmission. 1 byte H'44 slv_trs

dt_trs[5] Stores sixth byte of data for transmission. 1 byte H'55 slv_trs

dt_trs[6] Stores seventh byte of data for transmission. 1 byte H'66 slv_trs

dt_trs[7] Stores eighth byte of data for transmission. 1 byte H'77 slv_trs

dt_trs[8] Stores nineth byte of data for transmission. 1 byte H'88 slv_trs

dt_trs[9] Stores tenth byte of data for transmission. 1 byte H'99 slv_trs

i Transmiss ion data co unter 1 byte H'00 slv_trs

dummy Sto res the MDCR value. 1 byte — main

dmyrd Storage for the value obtained by the dummy

read. 1 byte — slv_trs

(4) Description of RAM Usage

In this example of a task, the only RAM used is that required for the variables.

Rev. 2.0, 11/01, page 279 of 358

4.8.4 Flowcharts

(1) Main Routine

main

SP H'F000

dummy MDCR

SYSCR H’09

initialize

CCR 1bit 0

MST 0

TRS 0

ACKB 0

IRIC 0

IRIC = 1 ? No

Yes

AAS = 1 ?

ADZ = 0 ?

TRS = 1 ?

BBSY = 0 ?

slv_trs

···················Set SP (stack pointer) to H'F000.

Call the subroutine that makes the initial settings.

Enable an interrupt by clearing the 1 bit to 0.

Slave address = general-call address?

Transmission mode?

Call the slave-transmission subroutine.

Bus-released state?

Has receiving of this device's slave address + the R/W bit been

completed?

···················

·············

···················

·············

···················

·············

···················Read MDCR to latch the input levels on the MD1 and MD0 pins

to the bits MDS1 and MDS0.

············· Set the MST and TRS bits of ICCR9 to 0 to set the mode of the

channel 0 I

C interface to slave reception.

···················Set the interrupt-control mode of the interrupt controller

to 1-bit interrupt control.

ACKB = 0 (while receiving, zeroes are output with the

acknowledge-output timing)

···················Clear IRIC to 0 so that the bit indicates whether or not the slave

address + R/W data have been received.

Rev. 2.0, 11/01, page 280 of 358

(2) Subrout ine for Making Init ial Settings

initialize

STCR H'00

·············

MSTPCRL H'7F

SMR0 H'00

SCR0 H'00

MSTPCRL H'EF

STCR H'10

DDCSWR H'0F

ICCR0 H'01

SAR0 H'38

SARX0 H'01

ICCR0 H'81

ICSR0 H'00

STCR H'30

ICMR0 H'28

ICCR0 H'89

rts

Set the MSTP7 bit of MSTPCRL to 0 to take SCI0 out of its

module-stopped mode.

············· Set the FLSHE bit of STCR to 0 to set the control register of the

flash memory to non-selective.

············· Set the STCR's IICE bit to 1 so that the data and control registers

of the I

C bus interface are accessible by the CPU.

Set ICCR0's ICE bit to 0 to enable access to SAR0 and SARX0.

Set ICCR0's ICE bit to 1 to enable access to ICMR0 and ICDR0.

Set the ACKB bit in ICSR0 to 0.

············· Set the SWE, SW, and IE bits of DDCSWR to 0 to disable automatic

changeover from IIC0 format-less to I

C bus format, select use of IIC0

in the I

C bus format, and disable interrupts during the execution of

automatic format changeover.

Set FS in SAR0 and FSX in SARX0 to 0 to select the I

C bus format

(enables the SAR slave address and disables the SARX slave address)

as the format for transfer on IIC0.

············· Set the SMR's C/ bit to 0 to set the SCI0 to operate in its

asynchronous mode.

············· Set the SCR's CKE1 bit to 0 and CKE bit to 0 to set the

SCK0 pin for use as an I/O port.

············· Set the MSTPCRL's MSTP7 bit to 1 and MSTP4 bit to 0 to put

SCI0 in its module-stopped mode and take IIC0 out of its

module-stopped mode.

········

Set IICX0 in STR to 1, ICMR0's CKS2 bit to 1, CKS1 bit to 0, and

CKS0 bit to 1 so that the frequency of the IIC0 transfer clock is set

to 100 kHz. Set WA1 to 0 for the continuous transfer of data and

acknowledge bits.

·········

Set IEIC in ICCR0 to 0 to disable the generation of IIC0 interrupt

requests, and set ACKE to 1 to suspend continuous transfer when

the acknowledge bit is 1.

·············

Rev. 2.0, 11/01, page 281 of 358

(3) Slave Transmission Subroutine

slv_trs

i 0 ······················

······················

·············

······················

·············

ICDR0 dt_trs[i]

i++

rts

TRS 0

dmyrd ICDR0

IRIC 0

i++

ICDR0 dt_trs[i]

IRIC 0

IRIC = 1 ?

Yes

ACKB = 0 ?

IRIC = 1 ?

······················ Clear IRIC to 0 so that the bit indicates, at rising edge

of the 9th cycle of the transmission clock, whether or not

data has been transmitted.

Initialize the transmitted-data counter.

Write the 1st byte of data for transmission

Increment the transmitted-data counter.

Has the data been transmitted?

Continue with transmission (ACKB = 0)?

Write next byte for transmission to ICDR0.

Increment the transmitted-data counter.

Has all data been transmitted?

TRS = 0 (set this device in the slave-reception mode)

Dummy read (to release the SCL line)

IRIC = 0

······················ Clear IRIC to 0 so that the bit indicates, at rising edge

of the 9th cycle of the transmission clock, whether or not

data has been transmitted.

Rev. 2.0, 11/01, page 282 of 358

4.8.5 Program List

/*****************************************************

* H8S/2138 IIC bus application note *

* 7.Slave transmit to H8S/2138 *

* File na me : SVTxd.c *

* Fai : 20MHz *

* Mode : 3 *

******************************************************/

#include <stdio.h>

#include <machine.h>

#include "2138s.h"

/*****************************************************

* Prototype *

******************************************************/

void main(void); /* Main routine */

void initialize(void); /* IIC0 initialize */

void slv_trs(void); /* Slave transmit to H8S/2138 */

/*****************************************************

* Data table *

******************************************************/

const unsigned char dt_trs[10] =

{

0x00, /* 1st transmit data */

0x11, /* 2nd transmit data */

0x22, /* 3rd transmit data */

0x33, /* 4th transmit data */

0x44, /* 5th transmit data */

0x55, /* 6th transmit data */

0x66, /* 7th transmit data */

0x77, /* 8th transmit data */

0x88, /* 9th transmit data */

0x99 /* 10th transmit data */

};

Rev. 2.0, 11/01, page 283 of 358

/*****************************************************

* main : Main routine *

******************************************************/

void main(void)

#pragma asm

mov.l #h'f000,sp ;Stack pointer initialize

#pragma enda sm

{

unsigned char dummy;

dummy = MDCR.BYTE; /* MCU mode set */

SYSCR.BYTE = 0x09; /* Interrupt control mode set */

initialize(); /* Initialize */

set_imask_ccr(0); /* Interrupt enable */

IIC0.ICCR.BIT.MST = 0; /* Slave receive mode set */

IIC0.ICCR.BIT.TRS = 0; /* MST = 0, TRS = 0 */

IIC0.ICSR.BIT.ACKB = 0; /* ACKB = 0 */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Receive end (IRIC=1) ? */

if(IIC0.ICSR.BIT.AAS == 1) /* General call address receive ? */

{

if(IIC0.ICSR.BIT.ADZ == 0)

{

if(IIC0.ICCR.BIT.TRS == 1) /* Transmit mode (TRS=1) ? */

{

slv_trs(); /* Sl ave transmit */

}

while(IIC0.ICCR.BIT.BBSY == 1); /* Bus empty (BBSY=0) ? */

while(1);/* End */

}

Rev. 2.0, 11/01, page 284 of 358

/*****************************************************

* initialize : IIC0 Initialize *

******************************************************/

void initialize(void)

{

STCR.BYTE = 0x00; /* FLSHE = 0 */

MSTPCR.BYTE.L = 0x7f; /* SCI0 module stop mode reset */

SCI0.SMR.BYTE = 0x00; /* SCL0 pin function set */

SCI0.SCR.B YTE = 0x00 ;

MSTPCR.BYTE.L = 0xef; /* IIC0 module stop mode reset */

STCR.BYTE = 0x10; /* IICE = 1 */

DDCSWR.BYTE = 0x0f; /* IIC bus format initialize */

IIC0.ICCR.BYTE = 0x01; /* ICE = 0 */

IIC0.SAR.BYTE = 0x38; /* FS = 0 */

IIC0.SARX.BYTE = 0x01; /* FSX = 1 */

IIC0.ICCR.BYTE = 0x81; /* ICE = 1 */

IIC0.ICSR.BYTE = 0x00; /* ACKB = 0 */

STCR.BYTE = 0x30; /* IICX0 = 1 */

IIC0.ICMR.BYTE = 0x28; /* Transfer rat e = 100kHz */

IIC0.ICCR.BYTE = 0x89; /* IEIC = 0, ACKE = 1 */

}

/*****************************************************

* slv_trs : Slave transmit to H8S/2138 *

******************************************************/

void slv_trs(void)

{

unsigned char i = 0; /* Transmit data counter initialize */

unsigned char dmyrd; /* Dummy re ad data st ore */

IIC0.ICDR = dt_trs[i++]; /* 1st transmit data write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

while(IIC0.ICSR.BIT.ACKB == 0) /* Transmit continue (ACKB=0) ? */

{

IIC0.ICDR = dt_trs[i++]; /* Transmit data write */

Rev. 2.0, 11/01, page 285 of 358

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

IIC0.ICCR.BIT.TRS = 0; /* Slave receive mode set (MST=0,TRS=0) */

dmyrd = IIC0.ICDR; /* Dummy read */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

}

Rev. 2.0, 11/01, page 286 of 358

4.9 Slave Reception

4.9.1 Specifications

• One H8S/2138 in slave receive mode receives, through channel 0 of its I2C bus interface, 10

bytes of data from another H8S/2138.

• The slave address of the H8S/2138 that acts as the slave receiver is [0011100].

• The connection of devices to the I2C bus in this system is in the sin gle-master configuration:

there is one master device (H8S/2138) and one slave device (H8S/2138).

• The frequency of the transfer clock is 100 kHz.

• The slave receiver uses the output of its acknowledge bit to control the number of bytes it

receives.

• Figure 4.32 shows an example of such a connection between two H8S/2138s.

SCL

SDA

SCL0

SDA0

H8S/2138

SCL0

SDA0

H8S/2138

Slave

Master

Figure 4.32 Example of Two H8S/2138s Connected in a Single-Master Configuration

• The I2C bus format used in this example of a task is shown in Fig. 4.33.

Rev. 2.0, 11/01, page 287 of 358

171

1818

111

Number of

transmission bits

Number of

transmission frames

SLA A A A A PDATA DATA

Legend: : Start condition

: Slave address

: Direction, as transmission/reception

: Acknowledge

: Transmitted data

: Stop condition

SLA

DATA

Figure 4.33 Transfer Format Used in this Example of a Task

Rev. 2.0, 11/01, page 288 of 358

4.9.2 Description of Operation

Figure 4.34 shows this example's principle of operation.

SCL

SDA

RDRF

IRIC

[1] [2] [3]

[4] [4]

[5]

10µs Reception clock frequency

Ack

Start condition

Slave address

+ R/ = H'38 1st reception

data 2nd reception

data 3rd reception

data 10th reception

data

Stop

condition

···

Ack Ack Ack Ack Ack

[2]

[4]

[5]

[2]

[4]

[5]

[2]

[4]

[5] [6]

[2] [2]

[4]

Software processing Hardware processing

No operation

Dummy read of ICDR0

(start of the receive operation)

Clears IRIC to 0.

Reads the receive data from ICDR0.

No operation

[1]

[2]

[3]

[4]

[5]

[6]

No operation

RDRF = 1, IRIC = 1 (at rising of 9th clock)

RDRF = 0

No operation

RDRF = 0

IRIC = 1 (detects stop condition from the bus line state)

Figure 4.34 Slave Reception: Principle of Operation

Rev. 2.0, 11/01, page 289 of 358

4.9.3 Description of Software

(1) Descriptions of modules

Table 4.30 describes the functions of the modules used in this example of a task.

Table 4.30 Descriptions of Modules

Name Label Function

Main Routine main Sets stack pointers and the MCU mode, and enables an

interrupt.

Initial Settings initialize Sets the RAM area to be used and makes initial settings of

IIC0.

Slave reception slv_rec Uses slave reception to receiv e 10 bytes of data from the

other H8S/2138.

(2) Description of On-chip Registers

Table 4.31 describes the usage of on-chip registers in this example of a task.

Table 4.31 On-chip Registers

ICDR0 Stores the received data. H'FFDE —

SVA6

SVA0

Hold the slave address of the slave H8S/2138. H'FFDF

bit7 to

bit1

SVA6=0

SVA5=0

SVA4=1

SVA3=1

SVA2=1

SVA1=0

SVA0=0

SAR0

FS Along with the settings in the FSX bit of SARX0 and

the SW bit of DDCSWR, sets the format for transfer.H'FFDF bit00

SARX0 FSX Along with the settings in the FS bit of SAR0 and

the SW bit of DDSWR, sets the format for transfer. H'FFDE bit01

Rev. 2.0, 11/01, page 290 of 358

Table 4.31 On-chip Registers (Continued)

MLS Sets data transfer as MSB first. H'FFDF bit70

WAIT Sets continu ous tran sfer of data and ack nowl edge

bits. H'FFDF bit60

CKS2

CKS0

Along with the setting in the IICX0 bit of STCR, set

the frequency of the transfer clock to 100 kHz. H'FFDF

bit5 to

bit3

CKS2=1

CKS1=0

CKS0=1

ICMR0

BC2

BC0

Set the number of bits for the next transfer in the I2C

bus format to 9 (9 bits/frame). H'FFDF

bit2 to

bit0

BC2=0

BC1=0

BC0=0

ICE Controls access to the ICMR0, ICDR0/SAR, and

SARX registers, and selects the operation (the port

function for the SCL0/SDA0 pin) or non-operation

(bus-drive state for the SCL/SDA pin) of the I2C bus

interface.

H'FFD8 bit70/1

ICCR0

IEIC Disables the generation of interrupt requests by the

I2C bus interface. H'FFD8 bit60

MST Uses the I2C bus interface in its slave mode. H'FFD8 bit5 1

TRS Uses the I2C bus interface in its reception mode. H'FFD8 bit41

ACKE Suspends the continuous transfer of data when the

acknowle dge bit is 1. H'FFD8 bit3 1

BBSY Confirms whether or not the I2C bus is occup ied,

and, in combination with the SCP bit, sets the start

and stop condit ion s.

H'FFD8 bit20/1

IRIC Detects the start condition, determines the end of

data transfer, and detects acknowledge = 1. H'FFD8 bit1 0/1

ICCR0

SCP Along with the BBSY bit, sets the start/stop

conditions. H'FFD8 bit00

ICSR0 ACKB Stores the data that has, in accordance with the

timing of the output of the slave device’s

acknowledge bit, been output by the other device.

H'FFD9 bit00/1

IICX0 Along with the settings in CKS2 to CKS0 of ICMR0,

selects the frequency of the transfer clock. H'FFC3 bit5 1

IICE Enables CPU access to the data and control

registers of the I2C bus interfa ce. H'FFC3 bit4 1

STCR

FLSHE Sets the control registers of the flash memory to

non-selected. H'FFC3 bit3 0

Rev. 2.0, 11/01, page 291 of 358

Table 4.31 On-chip Registers (Continued)

SWE Prohibits automatic change from format-less

transfer to transfer in the I2C bus format on the

channel 0 I2C interfac e.

H'FEE6 bit70

SW Uses the channel 0 I2C interface in the I2C bus

format. H'FEE6 bit60

IE Prohibits interrupts during automatic changes of

format. H'FEE6 bit50

DDCSWR

CLR3

CLR0

Control the initialization of the internal state of the

I2C interface H'FEE6

bit3 to

bit0

CLR3=1

CLR2=1

CLR1=1

CLR0=1

MSTP7 Cancels the module-stopped mode for SCI channel

0. H'FF87 bit7 0MSTPCRL

MSTP4 Cancels the module stopped mode for I2C channel

0. H'FF87 bit4 0

SCR0 CKE1, 0 Make the I/O port setting for the P52/SCK0/SCL0

pin. H'FFDA

bit1, 0 CKE1=0

CKE0=0

SMR0 C/$Sets the mode for SCI transfer on channel 0 as

asynchronous. H'FFD8 bit70

SYSCR INTM1, 0 Set the interrupt control mode of the interrupt

controller to 1-bit control. H'FFC4

bit5, 4 INTM1=0

INTM0=0

MDCR MDS1, 0 Set the MCU’s operating mode to mode 3 by

latching the input levels on the MD1 and 0 pins. H'FFC5

bit1, 0 MDS1=1

MDS0=1

(3) Description of Variables

Table 4.32 describes the variables used in this task example.

Table 4.32 Description of Variables

Variables Function Size Initial

Value Name of Using

Module

i Received data counter 1 byte H'00 initialize

dummy Value read from MDCR 1 byte — main

dmyrd ICDR0 dummy-read value 1 byte — slv_trs

Rev. 2.0, 11/01, page 292 of 358

(4) Description of RAM Usage

Table 4.33 describes the RAM used in this task example.

Table 4.33 Description of RAM Usage

Label Function Size Address Name of Using

Module

dt_rec[i] Stores the received data. 10 bytes H'E100

H'E109

initialize

slv_rec

Rev. 2.0, 11/01, page 293 of 358

4.9.4 Flowcharts

(1) Main Routine

main

SP H'F000

dummy MDCR

SYSCR H’09

initialize

CCR 1bit 0

MST 0

TRS 0

ACKB 0

IRIC 0

IRIC = 1 ? No

Yes

AAS = 1 ?

ADZ = 0 ?

TRS = 1 ?

BBSY = 0 ?

slv_trs

···················Set SP (stack pointer) to H'F000.

Call the subroutine that makes the initial settings.

Enable an interrupt by clearing the 1 bit to 0.

Slave address = general-call address?

Transmission mode?

Call the slave reception subroutine.

Bus-released state?

Has receiving of this device's slave address + the R/W bit been

completed?

···················

·············

···················

·············

···················

·············

···················Read MDCR to latch the input levels on the MD1 and MD0 pins

to the bits MDS1 and MDS0.

············· Set the MST and TRS bits of ICCR9 to 0 to set the mode of the

channel 0 I

C interface to slave reception.

···················Set the interrupt-control mode of the interrupt controller to

1-bit interrupt control.

ACKB = 0 (while receiving, zeroes are output with the

acknowledge-output timing)

···················Clear IRIC to 0 so that the bit provides an indication of whether or

not the slave address + R/W data have been received.

Rev. 2.0, 11/01, page 294 of 358

(2) Subrout ine for Making Init ial Settings

initialize

i 0

···················

dt_rec[i] 0

i++

STCR H'00

MSTPCRL H'7F

SMR0 H'00

SCR0 H'00

MSTPCRL H'EF

STCR H'10

DDCSWR H'0F

ICCR0 H'01

SAR0 H'38

SARX0 H'01

ICCR0 H'81

···················

··················· Set the MSTP7 bit of MSTPCRL to 0 to take SCI0 out of its

module-stopped mode.

··················· Set the SMR's C/ bit to 0 to set the SCI0 to operate in its

asynchronous mode.

··················· Set the SCR's CKE1 bit to 0 and CKE bit to 0 to set the SCK0

pin for use as an I/O port.

···················

Set the STCR's IICE bit to 1 so that the data and control

registers of the I2C bus interface are accessible by the CPU.

Set ICCR0's ICE bit to 0 to enable access to SAR0 and SARX0.

Set ICCR0's ICE bit to 1 to enable access to ICMR0 and ICDR0.

Set the MSTPCRL's MSTP7 bit to 1 and MSTP4 bit to 0 to put

SCI0 in its module-stopped mode and take IIC0 out of its

module-stopped mode.

···············

··················· Set the FLSHE bit of STCR to 0 to set the control register of the

flash memory to non-selective.

Initialize the received data counter.

Received data counter < 10?

Initialize the received-data storage area.

Increment the received data counter.

Set the SWE, SW, and IE bits of DDCSWR to 0 to disable

automatic changeover from IIC0 format-less to I2C bus format,

select use of IIC0 in the I2C bus format, and disable interrupts

during the execution of automatic format changeover.

···················

Set FS in SAR0 and FSX in SARX0 to 0 to select the I2C bus

format (enables the SAR slave address and disables the SARX

slave address) as the format for transfer on IIC0.

···········

···················

i<10? No

Rev. 2.0, 11/01, page 295 of 358

rts

ICSR0 H'00

···················

··············

STCR H'30

ICMR0 H'28

ICCR0 H'89

Set IICX0 in STR to 1, ICMR0's CKS2 bit to 1, CKS1 bit to 0, and

CKS0 bit to 1 so that the frequency of the IIC0 transfer clock is

set to 100 kHz. Set WA1 to 0 for the continuous transfer of data

and acknowledge bits.

Set the ACKB bit in ICSR0 to 0.

··················· Set IEIC in ICCR0 to 0 to disable the generation of IIC0 interrupt

requests, and set ACKE to 1 to suspend continuous transfer when

the acknowledge bit is 1.

(3) Slave Reception Subroutine

slv_rec

ACKB 0 ···················

···················

················

···················

············

dmyrd ICDR0

IRIC 0

i 0

(2)

IRIC 0

i++

dt_rec[i] ICDR0

IRIC = 1 ?

Yes

i < 8 ?

IRIC = 1 ?

············ This byte of data fully received?

Initialize the received-data counter

Continue to receive?

Read the received byte from ICDR0 and store the byte in RAM.

This byte of data fully received?

Increment the received-data counter.

ACKB = 0 (while receiving, zeroes are output with the

acknowledge-output timing)

Dummy read (start of reception)

··················· Clear IRIC to 0 so that the bit indicates, on the rising edge of the

9th cycle of the transmission clock, whether or not data has

been transmitted.

Clear IRIC to 0 so that the bit indicates, on the rising edge of the

9th cycle of the transmission clock, whether or not data has

been transmitted.

Rev. 2.0, 11/01, page 296 of 358

rts

ACKB 1

···················

dt_rec[8] ICDR0

IRIC 0

i 0

dt_rec[9] ICDR0

IRIC 0

IRIC = 1 ?

Yes

············ Has all data been received?

ACKB = 0 (while receiving, zeroes are output with the

acknowledge-output timing)

Read the 9th byte of the received data (to start receiving the

10th byte).

Initialize the received-data counter.

Read the 10th byte of the received data and store the byte in RAM.

IRIC = 0

Clear IRIC to 0 so that the bit indicates, on the rising edge of the

9th cycle of the receiving clock, whether or not data has been

received.

Rev. 2.0, 11/01, page 297 of 358

4.9.5 Program List

/*****************************************************

* H8S/2138 IIC bus application note *

* 8.Slave receive from H8S/2138 *

* File na me : SVRxd.c *

* Fai : 20MHz *

* Mode : 3 *

******************************************************/

#include <stdio.h>

#include <machine.h>

#include "2138s.h"

/*****************************************************

* Prototype *

******************************************************/

void main(void); /* Main routine */

void initialize(void); /* RAM & IIC0 initialize */

void slv_rec(void); /* Slave transmit to H8S/2138 */

/*****************************************************

* RAM allocation *

******************************************************/

#pragma sect ion rama re a

unsigned char dt_rec[10]; /* Receive data store area */

#pragma sect ion

/*****************************************************

* main : Main routine *

******************************************************/

void main(void)

#pragma asm

mov.l #h'f000,sp ;Stack pointer initialize

#pragma enda sm

{

unsigned char dummy;

dummy = MDCR.BYTE; /* MCU mode set */

Rev. 2.0, 11/01, page 298 of 358

SYSCR.BYTE = 0x09; /* Interrupt control mode set */

initialize(); /* Initialize */

set_imask_ccr(0); /* Interrupt enable */

IIC0.ICCR.BIT.MST = 0; /* Slave receive mode set */

IIC0.ICCR.BIT.TRS = 0; /* MST = 0, TRS = 0 */

IIC0.ICSR.BIT.ACKB = 0; /* ACKB = 0 */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Slave address receive end ? */

if(IIC0.ICSR.BIT.AAS == 1) /* General call address receive ? */

{

if(IIC0.ICSR.BIT.ADZ == 0)

{

if(IIC0.ICCR.BIT.TRS == 0) /* Slave receive mode (TRS=0) ? */

{

slv_rec(); /* Sl ave receive */

}

while(IIC0.ICCR.BIT.BBSY == 1); /* Bus empty (BBSY=0) ? */

while(1); /* End */

}

/*****************************************************

* initialize : RAM & IIC0 Initialize *

******************************************************/

void initialize(void)

{

unsigned char i=0; /* Receive data counter initialize */

for(i=0; i<10; i++) /* Receive data store area initialize */

{

dt_rec[i] = 0x 00;

}

Rev. 2.0, 11/01, page 299 of 358

STCR.BYTE = 0x00; /* FLSHE = 0 */

MSTPCR.BYTE.L = 0x7f; /* SCI0 module stop mode reset */

SCI0.SMR.BYTE = 0x00; /* SCL0 pin function set */

SCI0.SCR.B YTE = 0x00 ;

MSTPCR.BYTE.L = 0xef; /* IIC0 module stop mode reset */

STCR.BYTE = 0x10; /* IICE = 1 */

DDCSWR.BYTE = 0x0f; /* IIC bus format initialize */

IIC0.ICCR.BYTE = 0x01; /* ICE = 0 */

IIC0.SAR.BYTE = 0x38; /* FS = 0 , Slave address = b'0011100*/

IIC0.SARX.BYTE = 0x01; /* FSX = 1 */

IIC0.ICCR.BYTE = 0x81; /* ICE = 1 */

IIC0.ICSR.BYTE = 0x00; /* ACKB = 0 */

STCR.BYTE = 0x30; /* IICX0 = 1 */

IIC0.ICMR.BYTE = 0x28; /* Transfer rate = 100kHz */

IIC0.ICCR.BYTE = 0x89; /* IEIC = 0, ACKE = 1 */

}

/*****************************************************

* slv_rec : Slave receive from H8S/2138 *

******************************************************/

void slv_rec(void)

{

unsigned char i; /* Receive data counter initialize */

unsigned char dmyrd; /* Dummy re ad data st ore area */

IIC0.ICSR.BIT.ACKB = 0; /* ACKB = 0 */

dmyrd = IIC0.ICDR; /* Dummy read (Receive start) */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Receive end (IRIC=1) ? */

for(i=0; i<8; i++)

{

dt_rec[i] = IIC0.ICDR; /* Receive data read */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Receive end (IRIC=1) ? */

}

Rev. 2.0, 11/01, page 300 of 358

IC0.ICSR.BIT.ACKB = 1; /* ACKB = 1 */

dt_rec[8] = IIC0.ICDR; /* 10th data receive start */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Receive end (IRIC=1) ? */

dt_rec[9] = IIC0.ICDR; /* 10th receive data read */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

}

Rev. 2.0, 11/01, page 301 of 358

4.10 Example of Processing Bus Disconnection

4.10.1 Specification

• Writes 5 bytes of data to the EEPROM (HN58X2408) by having the H8S/2138 transmit, as the

master device, on its channel 0 I2C bus interface.

• The slave address of the EEPROM to be connected is [1010000]; th e data is written to

addresses H'00 to H'04 in the EEPROM's memory.

• The data to be written is [H'A1, H'B2, H'C3, H'D4, and H'E5].

• If the bus is disconnected during the transfer of data, the program stops the transfer clock

(from the transmitting master device) is stopped 8 cycles into the transmission of the third

byte, clears the ICE bit of ICCR0 to 0, and places the IIC0 module in its non-operational state

(i.e., the SCL0/SDA0 pin is set to have a port function). After the period of an EEPROM write

cycle has elapsed, the process of writing the 5 bytes of data to the EEPROM starts again, from

the beginning.

• The devices are connected to the I2C bus of this system in a single-master configuration with

one master device (H8S/2138) and one slave device (H8S/2138).

• The transfer clock frequency is 100 kHz.

• Figure 4.35 shows an example of such a connection between a H8S/2138 and an EEPROM.

Rev. 2.0, 11/01, page 302 of 358

SCL

SDA

SCL0

SDA0

H8S/2138

EEPROM

SCL

SDA

Figure 4.35 An Example of the Connection of a H8S/2138 and an EEPROM.

• The I2C bus format used in this example of a task is shown in figure 4.36.

171

1818

111

SLA A A A A PMEA DATA

Number of

transmission bits

Number of

transmission frames

Legend: : Start condition

: Slave address

: Direction, as transmission/reception

: Acknowledge

: Address of a location in the EEPROM

: Transmitted data

: Stop condition

SLA

MEA

DATA

Figure 4.36 Transfer Format Used in this Example of a Task

Rev. 2.0, 11/01, page 303 of 358

4.10.2 Description of Operation

Figure 4.37 describes this example's principle of operation.

SCL

SDA

SCL

SDA

[9] [3] [3] [3] [3] [3] [3] [2]

[3] [3] [3] [3] [4] [5] [6][8]

10µs Reception clock frequency

Ack

Start

condition

Slave address

+ R/ = H'40

Slave address

+ R/ = H'40

Memory address

= H'00

2nd transmission

data = H'B2

1st transmission

data = H'A1

Memory address

= H'00

1st transmission

data = H'A1

5th transmission

data = H'E5

3rd transmission

data = H'C3

EEPROM write

cycle = 10ms

EEPROM write

cycle = 10ms

Stop

condition

Sets the start condition (BBSY = 1, SCP = 0)

Sets the stop condition (BBSY=0, SCP=0)

Writes the data for transmission to ICDR0 and clears IRIC to 0 (at rising of 9th clock)

Write the data for transmission to ICDR0 and clears IRIC to 0 (at rising of 9th clock)

Outputs logic-low on the P52 (SCL0) and P97 (SDA0) pins (at falling of 8th clock).

Outputs logic-low on the P52 (SCL0) and P97 (SDA0) pins to generate 9th clock.

Outputs logic-high on the P52 (SCL0) pin to generate the stop condition.

Outputs logic-low on the P97 (SDA0) pin to generate the stop condition.

Initially sets the IIC0 module.

Software processing

······

···

Start

condition Stop

condition

Ack Ack Ack Ack Ack

Ack Ack Ack Ack

[1] [6]

[7]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

Figure 4.37 Principle of Operation when the Bus is Temporarily Disconnected

Rev. 2.0, 11/01, page 304 of 358

4.10.3 Description of Software

(1) Description of Modules

Table 4.33 describes the modules used in this example of a task.

Table 4.33 Module De scription

Name Label Function

Main routine main Sets the stack pointer and the MCU mode, and enables an

interrupt.

Initial setting initialize Makes initial settings of IIC0.

Master transmission

1mst_trs_1 Uses master transmission to transmit 5 bytes of data to the

EEPROM.

Master transmission

2mst_trs_2 Uses master transmission to transmit 5 bytes of data to the

EEPROM.

Start-condition

setting set_start Sets the start condition.

Stop-condition

setting set_stop Sets the stop condition.

Transmiss ion of

slave address + W trs_slvadr_a0 Trans mits the EEPROM’s slave address + W bit as data

(H’A0).

Transmiss ion of

location in EEPROM trs_memadr Transmits the address of a location within the EEPROM

(H’00) as da ta.

Wait1 wait_1 Waits for 5 µs (in 20-MHz operation).

Wait2 wait_2 Waits for 10 µs (in 20-MHz operation).

(2) Description of On-chip Registers

Table 4.34 the usage of on-chip registers in this example of a task.

Table 4.34 On-chip Registers

ICDR0 Stores the data for transmission. H'FFDE —

SAR0 FS Along with the settings in the FSX bit of SARX0 and

the SW bit of DDCSWR, sets the format for transfer.H'FFDF bit00

SARX0 FSX Along with the settings in the FS bit of SAR0 and

the SW bit of DDSWR, sets the format for transfer. H'FFDE bit01

Rev. 2.0, 11/01, page 305 of 358

Table 4.34 On-chip Registers (cont)

MLS Sets data transfer as MSB first. H'FFDF bit70

WAIT Sets whether to insert wait cycles between the data

bits and the acknowl edg e bit. H'FFDF bit60/1

CKS2

CKS0

Along with the setting in the IICX0 bit of STCR, set

the frequency of the transfer clock to 100 kHz. H'FFDF

bit5 to

bit3

CKS2=1

CKS1=0

CKS0=1

ICMR0

BC2

BC0

Set the number of bits for the next transfer in the I2C

bus format to 9 (9 bits/frame). H'FFDF

bit2 to

bit0

BC2=0

BC1=0

BC0=0

ICE Controls access to the ICMR0, ICDR0/SAR, and

SARX registers, and selects the operation (the port

function for the SCL0/SDA0 pin) or non-operation

(bus-drive state for the SCL/SDA pin) of the I2C bus

interface.

H'FFD8 bit70/1

IEIC Disables the generation of interrupt requests by the

I2C bus interface. H'FFD8 bit60

MST Uses the I2C bus interface in its master mode. H'FFD8 bit51

TRS Uses the I2C bus interface in its transmission mode. H'FFD8 bit41

ACKE Suspends the continuous transfer of data when the

acknowle dge bit is 1. H'FFD8 bit3 1

BBSY Confirms whether or not the I2C bus is occup ied,

and, in combination with the SCP bit, sets the start

and stop condit ion s.

H'FFD8 bit20/1

IRIC Detects the start condition, determines the end of

data transfer, and detects acknowledge = 1. H'FFD8 bit1 0/1

ICCR0

SCP Along with the BBSY bit, sets the start/stop

conditions. H'FFD8 bit00

ICSR0 ACKB Stores the acknowledgement to be transmitted to

the EEPROM during the receive operation. H'FFD9 bit0—

IICX0 Along with the settings in CKS2 to CKS0 of ICMR0,

selects the frequency of the transfer clock. H'FFC3 bit5 1

IICE Enables CPU access to the data and control

registers of the I2C bus interfa ce. H'FFC3 bit4 1

STCR

FLSHE Sets the control registers of the flash memory to

non-selected. H'FFC3 bit3 0

Rev. 2.0, 11/01, page 306 of 358

Table 4.34 On-chip Registers (cont)

SWE Prohibits automatic changeover from format-less

transfer to transfer in the I2C bus format on the

channel 0 I2C interfac e.

H'FEE6 bit70

SW Uses the channel 0 I2C interface in the I2C bus

format. H'FEE6 bit60

IE Prohibits interrupts during automatic changes of

format. H'FEE6 bit50

DDCSWR

CLR3

CLR0

Control the initialization of the internal state of the

channel 0 I2C interface H'FEE6

bit3 to

bit0

CLR3=1

CLR2=1

CLR1=1

CLR0=1

MSTP7 Cancels the module-stopped mode for SCI channel

0. H'FF87 bit7 0MSTPCRL

MSTP4 Cancels the module stopped mode for I2C channel

0. H'FF87 bit4 0

SCR0 CKE1, 0 Make the I/O port setting for the P52/SCK0/SCL0

pin. H'FFDA

bit1, 0 CKE1=0

CKE0=0

SMR0 C/$Sets the mode for SCI transfer on channel 0 as

asynchronous. H'FFD8 bit70

SYSCR INTM1, 0 Set the interrupt-control mode of the interrupt

controller to 1-bit control. H'FFC4

bit5, 4 INTM1=0

INTM0=0

MDCR MDS1, 0 Set the MCU’s operating mode to mode 3 by

latching the input levels on the MD1 and 0 pins. H'FFC5

bit1, 0 MDS1=1

MDS0=1

P5DDR P52DDR Sets the P52 pin to act as an output pin. H'FFB8 bit2 1

P5DR P52DR Sets the data for output on the P52 pin. H'FFBA bit20/1

P9DDR P97DDR Sets the P97 pin to act as an output pin. H'FFC0 bit71

P9DR P97DR Sets the data for output on the P97 pin. H'FFC1 bit70/1

Rev. 2.0, 11/01, page 307 of 358

(3) Description of Variables

Table 4.35 describes the variables used in this task.

Table 4.35 Description of Variables

Variable Function Size Initial

Value Name of Using

Module

i Transmission data counter 1 byte H'00 mst_trs_1

mst_trs_2

dummy Sto res the MDCR value. 1 byte — main

dt_trs[i] 5 bytes transmissi on data 5 bytes — mst_trs_1

mst_trs_2

(4) Description of RAM Usage

In this example of a task, the only RAM used is that required for the variables.

Rev. 2.0, 11/01, page 308 of 358

4.10.4 Flowcharts

(1) Main Routine

main

SP H'F000

dummy MDCR

SYSCR H'09

initialize

CCR 1bit 0

P5DR H'00

P5DDR H'04

P9DR H'00

P9DDR H'80

P5DR H'04

P9DR H'80

P5DR H'00

·············

·········

Set SP (stack pointer) to H'F000.

Read MDCR to latch the input levels on the MD1 and MD0 pins to the

bits MDS1 and MDS0.

Set the interrupt control mode of the interrupt controller to 1-bit

interrupt control.

Call the subroutine that makes the initial settings.

Enable an interrupt by clearing the 1 bit to 0.

Call the master transmission 1 subroutine.

Call the WAIT1 subroutine.

Output logic-high on P52.

Call the WAIT1 subroutine.

Output logic-high on P97 (generate the stop condition), high on P52,

and a low-to-high transition on P97.

Call the WAIT1 subroutine.

Output logic-low on P52.

Generate the 9th clock cycle for the frame currently being

transmitted from the port output.

mst_trs_1

wait_1

Rev. 2.0, 11/01, page 309 of 358

·············

Output logic-low on P97.

Call the WAIT2 subroutine.

Call the subroutine that makes the initial settings.

Call the master transmission 2 subroutine.

P9DR H'00

wait_2

initialize

mst_trs_2

Rev. 2.0, 11/01, page 310 of 358

(2) Subrout ine for Making Init ial Settings

initialize

rts

STCR H'00

MSTPCRL H'7F

SMR0 H'00

SCR0 H'00

MSTPCRL H'EF

STCR H'10

DDCRWR H'0F

ICCR0 H'01

SAR0 H'00

SARX0 H'01

ICCR0 H'81

ICMR0 H'28

ICCR0 H'89

·············

··········

·············

Set the FLSHE bit of STCR to 0 to set the control register of the flash

memory to non-selective.

Set the MSTP7 bit of MSTPCRL to 0 to take SCI0 out of its

module-stopped mode.

Set the SMR's C/ bit to 0 to set the SCI0 to operate in its

asynchronous mode.

Set the SCR's CKE1 bit to 0 and CKE bit to 0 to set the SCK0 pin

for use as an I/O port.

Set the STCR's IICE bit to 1 so that the data and control registers of the

C bus interface are accessible by the CPU.

Set the SWE, SW, and IE bits of DDCSWR to 0 to disable automatic

changeover from IIC0 format-less to I

C bus format, select use of IIC0

in the I

C bus format, and disable interrupts during the execution of

automatic format changeover.

Set ICCR0's ICE bit to 0 to enable access to SAR0 and SARX0.

Set ICCR0's ICE bit to 1 to enable access to ICMR0 and ICDR0.

Set the ACKB bit in ICSR0 to 0.

Set the MSTPCRL's MSTP7 bit to 1 and MSTP4 bit to 0 to put SCI0

in its module-stopped mode and take IIC0 out of its module-stopped mode.

Set FS in SAR0 and FSX in SARX0 to 0 to select the I

C bus format

(enables the SAR slave address and disables the SARX slave address)

as the format for transfer on IIC0.

Set IICX0 in STR to 1, ICMR0's CKS2 bit to 1, CKS1 bit to 0, and CKS0 bit

to 1 so that the frequency of the IIC0 transfer clock is set to 100 kHz.

Set WA1 to 0 for the continuous transfer of data and acknowledge bits.

Set IEIC in ICCR0 to 0 to disable the generation of IIC0 interrupt requests,

and set ACKE to 1 to suspend continuous transfer when the acknowledge

bit is 1.

STCR H'30

ICSR0 H'00

Rev. 2.0, 11/01, page 311 of 358

(3) Ma ster transmissio n 1 subro utine

mst_trs_1

Yes

·············

················

··························

·············

··························

Bus released?

Set the MST and TRS bits of ICCR0 to 1 to select the master

transmission mode for IIC0.

Call the subroutine that sets the start condition.

Call the subroutine for transmitting the slave address + W bit.

Call the subroutine that transmits the address of a location

in EEPROM.

Initialize the transmitted-data counter

Increment the transmitted-data counter.

2 bytes of transmission completed?

Transmission of the current byte completed?

Write the ith byte of the data for transmission data to ICDR0.

Clear IRIC to 0 so that the bit indicates whether or not the

transmission of this byte has been completed on the rising edge

of the 9th cycle of the transmission clock.

IRIC = 1 ?

Yes

i < 2 ?

Yes

BBSY = 0 ?

i 0

ICDR0 dt_trs[i]

IRIC 0

i++

MST 1

TRS 1

set_start

trs_slvadr_a0

trs_memadr

Rev. 2.0, 11/01, page 312 of 358

rts

WAIT 1

ICDR0 dt_trs[i]

IRIC 0

wait_1

····················

··········

····················

WAIT = 1 (insert wait cycles between the data bits and acknowledge bit)

Write the 3rd byte of the data for transmission to ICRD0.

Clear IRIC to 0 so that it indicates whether or not the transmission

of this byte has been completed on the falling edge of the 8th cycle

of the transmission clock).

Transmission of the 3rd byte of data completed?

Call the WAIT1 subroutine.

Yes

IRIC = 1 ?

wait_1

Rev. 2.0, 11/01, page 313 of 358

(4) Master Transmission 2 Subroutine

mst_trs_2

rts

Yes

···········

····················

···········

····················

···········

··············

····················

IRIC = 1 ?

Yes

ACKB = 0 ?

···········

i 0

ICDR0 dt_trs[i]

IRIC 0

i++

MST 1

TRS 1

trs_memadr

set_start

trs_slvadr_a0

set_stop

Yes

i < 5 ? 3

Yes

ACKB = 0 ? 3

Yes

ACKB = 0 ? 3

····················

Acknowledge bit received from the EEPROM?

Call the subroutine for transmitting the slave address + W bit.

Call the subroutine that sets the start condition.

Call EEPROM memory address transmission subroutine.

Acknowledge received from the EEPROM?

Initializes the transmission data counter.

Increment the transmitted-data counter.

Call the subroutine that sets the stop condition.

Acknowledge bit received from the EEPROM?

Have all 5 bytes of data been transmitted?

Set the MST and TRS bits of ICCR0 to 1 to select the master

transmission mode for IIC0.

Write the ith byte of the data for transmission to ICDR0.

Transmission of data completed?

Clear IRIC to 0 so that it indicates whether or not the transmission

of data has been completed at rising of the 9th transmission clock.

Rev. 2.0, 11/01, page 314 of 358

(5) Subroutine for Setting the Sta r t Condition

set_stop

rts

IRIC 0

ICCR0 H'BC

Yes

·······················

·············

Clear IRIC to 0 so that it indicates whether or not the

start condition has been detected.

Set ICCR0's BBSY to 1 and SCP to 0 to issue the

start condition.

Has the start condition been detected on the bus lines?

IRIC = 1 ?

(6) Subroutine for Setting the Sto p Co ndition

set_stop

rts

Yes

·······················

···········

Set ICCR0's BBSY and SCP bits to 0 to set the start

condition.

Bus released?

BBSY = 0 ?

ICCR0 H'B8

(7) Subrout ine for transmit ting the slave address + W bit

trs_slvadr_a0

rts

Yes

·······················

···········

Transmit the EEPROM's slave address + W bit as data (H'A0)

Clear IRIC to 0 so that it indicates whether or not data has been

transmitted (at rising of 9th transmission clock).

Transmission of the EEPROM's slave address + W data completed?

IRIC = 1 ?

ICCR0 H'A0

IRIC 0

Rev. 2.0, 11/01, page 315 of 358

(8) Subroutine for transmitting the location within the EEPROM

trs_memadr

rts

Yes

·······················

···········

Transmit the address of a location within the EEPROM as data (H'00)

Clear IRIC to 0 so that it indicates whether or not data has been

transmitted (at rising of 9th transmission clock).

Transmission of the address of a location within the EEPROM

completed?

IRIC = 1 ?

ICCR0 H'00

IRIC 0

(9) WAIT1 subroutine

wait_1

rts

PUSH R0

R0L H’1A

P0P R0

R0L R0L - 1

Yes

·······················

··············

·······················

Place the R0 register on the stack.

An initial setting for a loop that decrements R0.

Decrementing completed?

Decremented R0.

Restore the original value of the R0 register.

R0L = 0 ?

Rev. 2.0, 11/01, page 316 of 358

(10) WAIT2 subroutine

wait_2

rts

PUSH ER0

ER0 H'00010800

P0P ER0

ER0 ER0 - 1

Yes

····················

·············

····················

Place the ER0 register on the stack.

An initial setting for a loop that decrements ER0.

Decrementing completed?

Decrement ER0.

Restore the original value of the ER0 register.

ER0 = 0 ?

Rev. 2.0, 11/01, page 317 of 358

4.10.5 Program List

/*****************************************************

* H8S/2138 IIC bus application note *

* 9.Error process in single master transmit *

* File na me : Error.c *

* Fai : 20MHz *

* Mode : 3 *

******************************************************/

#include <stdio.h>

#include <machine.h>

#include "2138s.h"

/*****************************************************

* Prototype *

******************************************************/

void main(void); /* Main routine */

void initialize(void); /* IIC0 initialize */

void mst_trs_1(void); /* Master transmit 1 */

void mst_trs_2(void); /* Master transmit 2 */

void set_start(void); /* Start condition set */

void set_stop(void); /* Stop condition set */

void trs_slvadr_a0(void); /* Slave address + W data transmit */

void trs_memadr(void); /* EEPROM memory address data transmit */

void wait_1(void); /* Wait 1 (5µs) */

void wait_2(void); /* Wait 2 (10ms) */

/*****************************************************

* Data table *

******************************************************/

const unsigned char dt_trs[5] = /* Transmit data (5 byte) */

{

0xa1, /* 1st tr ansmit data */

0xb2, /* 2nd transmit data */

0xc3, /* 3rd transmit data */

0xd4, /* 4th transmit data */

0xe5 /* 5th transmit data */

Rev. 2.0, 11/01, page 318 of 358

};

/*****************************************************

* main : Main routine *

******************************************************/

void main(void)

#pragma asm

mov.l #h'f000,sp ;Stack pointer initialize

#pragma enda sm

{

unsigned char dummy;

dummy = MDCR.BYTE; /* MCU mode set */

SYSCR.BYTE = 0x09; /* Interrupt control mode set */

initialize(); /* Initialize */

set_imask_ccr(0); /* Interrupt enable */

mst_trs_1(); /* Master transmit to EEPROM 1 */

wait_1(); /* 5µs wait */

P5.DR.BYTE = 0x00; /* P52DR = 0 */

P5.DDR = 0x04; /* P52DDR = 1 */

P9.DR.BYTE = 0x00; /* P97DR = 0 */

P9.DDR = 0x80; /* P97DDR = 1 */

wait_1(); /* 5µs wait */

P5.DR.BYTE = 0x04; /* P52DR = 1 */

wait_1(); /* 5µs wait */

P9.DR.BYTE = 0x80; /* P92DR = 1 */

wait_1(); /* 5µs wait */

P5.DR.BYTE = 0x00; /* P52DR = 0 */

P9.DR.BYTE = 0x00; /* P97DR = 0 */

wait_2(); /* 10ms wait (EEPROM write cycle) */

initialize(); /* IIC0 initialzie */

mst_trs_2(); /* Master transmit to EEPROM 2 */

Rev. 2.0, 11/01, page 319 of 358

while(1);/* End */

}

/*****************************************************

* initialize : IIC0 Initialize *

******************************************************/

void initialize(void)

{

STCR.BYTE = 0x00; /* FLSHE = 0 */

MSTPCR.BYTE.L = 0x7f; /* SCI0 module stop mode reset */

SCI0.SMR.BYTE = 0x00; /* SCL0 pin function set */

SCI0.SCR.B YTE = 0x00 ;

BSC.WSCR.BYTE = 0x33; /* SDA0 pin function set */

MSTPCR.BYTE.L = 0xef; /* IIC0 module stop mode reset */

STCR.BYTE = 0x10; /* IICE = 1 */

DDCSWR.BYTE = 0x0f; /* IIC bus format initialize */

IIC0.ICCR.BYTE = 0x01; /* ICE = 0 */

IIC0.SAR.BYTE = 0x00; /* FS = 0 */

IIC0.SARX.BYTE = 0x01; /* FSX = 1 */

IIC0.ICCR.BYTE = 0x81; /* ICE = 1 */

IIC0.ICSR.BYTE = 0x00; /* ACKB = 0 */

STCR.BYTE = 0x30; /* IICX0 = 1 */

IIC0.ICMR.BYTE = 0x28; /* Transfer rate = 100kHz */

IIC0.ICCR.BYTE = 0x89; /* IEIC = 0, ACKE = 1 */

}

/*****************************************************

* mst_trs_1 : Master transmit to EEPROM 1 *

******************************************************/

void mst_trs_1(void)

{

unsigned char i; /* Transmit data counter */

while(IIC0.ICCR.BIT.BBSY == 1); /* Bus empty (BBSY=0) ? */

IIC0.ICCR.BIT.MST = 1; /* Master transmit mode set */

IIC0.ICCR.BIT.TRS = 1; /* MST = 1, TRS = 1 */

set_start(); /* Start condition set */

Rev. 2.0, 11/01, page 320 of 358

trs_slvadr_a0(); /* Slave address + W data transmit */

trs_memadr(); /* EEPROM memory address data transmit */

for(i=0; i<2; i++)

{

IIC0.ICDR = dt_trs[i]; /* Transmit data write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

IIC0.ICMR.BIT.WAIT = 1; /* WAIT = 1 */

IIC0.ICDR = dt_trs[i]; /* 3rd transmit data write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

wait_1() /* 5µs wait */

wait_1(); /* 5µs wait */

IIC0.ICCR.BIT.ICE = 0; /* ICE = 0 */

}

/*****************************************************

* mst_trs_2 : Master transmit to EEPROM 2 *

******************************************************/

void mst_trs_2(void)

{

unsigned char i; /* Transmit data counter */

IIC0.ICCR.BIT.MST = 1; /* Matser transmit mode set */

IIC0.ICCR.BIT.TRS = 1; /* MST = 1, TRS = 1 */

set_start(); /* Start condition set */

trs_slvadr_a0(); /* Slave address + W data transmit */

if(IIC0.ICSR.BIT.ACKB == 0) /* ACKB = 0 ? */

{

trs_memadr(); /* EEPROM memory address data transmit */

if(IIC0.ICSR.BIT.ACKB == 0) /* ACKB = 0 ? */

{

for(i=0; i<5; i++)

{

Rev. 2.0, 11/01, page 321 of 358

IIC0.ICDR = dt_trs[i]; /* Transmit data write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

if(IIC0.ICSR.BIT.ACKB == 1) /* ACKB = 0 ? */

{

break;

}

set_stop(); /* Stop condition set */

}

/*****************************************************

* set_start : Start condition set *

******************************************************/

void set_start(void)

{

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

IIC0.ICCR.BYTE = 0xbc; /* Start condition set (BBSY=1,SCP=0) */

hile(IIC0.ICCR.BIT.IRIC == 0); /* St art condition set (IRIC=1) ? */

}

/*****************************************************

* set_stop : Stop condition set *

******************************************************/

void set_stop(void)

{

IIC0.ICCR.BYTE = 0xb8; /* Stop condition set (BBSY=0,SCP=0) */

while(IIC0.ICCR.BIT.BBSY == 1); /* Bus empty (BBSY=0) ? */

}

/*****************************************************

* trs_slvadr_a0 : Slave addres + W data transmit *

******************************************************/

void trs_slvadr_a0(void)

Rev. 2.0, 11/01, page 322 of 358

{

IC0.ICDR = 0xa0; /* Slave address + W data(H'A0) write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

/*****************************************************

* trs_memadr : EEPROM memory address data transmit *

******************************************************/

void trs_memadr(void)

{

IIC0.ICDR = 0x00; /* EEPROM memory address data(H'00) write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

/*****************************************************

* wait_1 : xxms wait *

******************************************************/

void wait_1(void)

{

#pragma asm

push.w r0 ;Push R0

mov.b #h'1a,r0l ;Decrement data set

wait1_1:

dec.b r0l ;Decrement

bne wait1_1 ;Decrement end ?

pop.w r0 ;Pop R0

#pragma enda sm

}

/*****************************************************

* wait_2 : 10ms wait *

******************************************************/

void wait_2(void)

{

#pragma asm

Rev. 2.0, 11/01, page 323 of 358

push.l er0 ;Push ER0

mov.l #h'00010800,er0 ;Decrement data set

wait2_1:

dec.l #1,er0 ;Decrement

bne wait2_1 ;Decrement end ?

pop.l er0 ;Pop ER0

#pragma enda sm

}

Rev. 2.0, 11/01, page 324 of 358

4.11 Bus Conflict

4.11.1 Specifications

• The system is in a m ultiple-task configuration with master devices 1 and 2 (H8S/2138) and a

slave device (EEPROM: HN58X2408).

• When the IRQ interrupt switch which is connected to masters 1 and 2 is pressed, masters 1 and

2 write 2 bytes of data to the slave device.

• The data transmitted from m aster 1 disp lay s “1 0 ” in the 7-segm ent LED.

• The data transmitted from m aster 2 disp lay s “2 0 ” in the 7-segm ent LED.

• Since masters 1 and 2 attempt to start the transm ission of data at the same tim e, a bus co nflict

occurs. In this case, the m a ster that has acquired the bus righ t continues to write d a ta to the

EEPROM and lights up the LED. The master that failed to acquire the bus right reads the data

written by the other master from the EEPROM and displays the data on the 7-segm ent LED

after the other master has finished writing to the EEPROM.

• The slave address of the EEPROM, which is the slave device in this example, is [1010000].

Data is read from and written to the lo cations at addresses H'00 and H'01 in the EEPROM.

• The frequency of the transfer clock, for both receiving and transmission, is 100 kHz.

• Figure 4.38 shows the configuration of the system used in this example of a task.

Rev. 2.0, 11/01, page 325 of 358

Master 1

Vcc

LED

P20

P27

P40

P47

IRQ6

SG1 SG2

7-segment

IRQ interrupt switch

LED

VCC

SCL0

SDA0

SCL

SDA

P10

VSS

H8S/2138

Master 2

Vcc

IRQ6

P40

P20

P27

P47

VCC

SCL0

SDA0

P10

VSS

H8S/2138

EEPROM

Slave

VCC A0

SCL

SDA

VSS

Vcc Vcc

Vcc

SG1 SG2

7-segment LED LED

Vcc

Figure 4.38 System Configuration

The I2C bus format used in this example of a task is shown in figure 4.39.

Rev. 2.0, 11/01, page 326 of 358

Master transmission

Master receive

Legend:

SLA

MEA

DATA

: Start condition

: EEPROM slave address

: Direction, as transmission/reception

: Acknowledge

: Address of a location in the EEPROM

: Data for transmission

: Stop condition

S SLA

7111188111

11 5

Number of

bits transferred

Number of

frames transferred

A MEA A A A PDATA

S SLA

11 1 5

11187 811 1 11Number of

transmission bits

Number of

transmission frames

A MEA A S SLA A A A PDATA

R/ R/

Figure 4.39 The Formats for Transfer Used in this Example of a Task

• The I2C bus interface that is incorporated in H8S Series products includes the procedure for

adjusting communications shown in figure 4.40 as well as the procedures described in section

1.4, Procedures for Adjusting Communications. Each master device monitors the bus line on

the falling edge of SCL. When the level o n the bus line does not match the level a master is

attempting to put out, that master's output stage is cutoff.

Rev. 2.0, 11/01, page 327 of 358

The bus signal output

from each master

SDA1

SCL1

SDA2

SCL2

SDA

SCL

Master 2 acquires

the bus right.

The output stage

of master 1 is cutoff.

Master 1Master 2Bus line

Figure 4.40 Method of Detecting Bus Arbitration

In this example, masters 1and 2 are attempting to simultane ously transmit data to the same slave

device. Since the first lot of data sent (first frame) is the slave addr ess plus the W bit, and th is is

immediately followed by the address of a location within the EEPROM's memory, both masters

are initially sending the same data. The con f lict thus does not arise until the third frame, the data

to be stored at th e first location in the EEPROM, is sent. The third frame of the d ata for

transmission (the first byte is a transmission data) by ma ster 1 is H'F9 while the third from master

2 is H'A4, so the first difference that appears is when master 2 sets SDA to its low level. For

reasons that are explained in mo re detail in section 1.4, master 2 thus acquires bus mastership (see

figure 4.41).

Rev. 2.0, 11/01, page 328 of 358

The bus signal output from each master

SDA1

SCL1

SDA2

SCL2

SDA

SCL

Slave address+ W

H'A0

Ack Ack Ack

H'00

Memory address

Master 2 acquires

the bus right.

The output stage of

master 1 is cutoff. ···

···

H'F9

1st transmission

data 2nd transmission

data

H'C0

H'A0 H'00 H'A4 H'C0

Start

condition

Master 1Master 2Bus line

Figure 4.41 How Master 2 Becomes the Bus Master

• The connections between the 7-segment LED and the H8S/2138 used in this example of a task

is shown in figure 4.42. The segments of each of the LEDs are lit by the output of low levels

from ports 2 or 4.

Rev. 2.0, 11/01, page 329 of 358

Vcc SG2

P40

P41

P42

P43

P44

P45

P46

P47

gfedcba

Vcc SG1

P20

P21

P22

P23

P24

P25

P26

P27

gfedcba

The display on SG1 and the data output from port 2

Display

P20

P21

P22

P23

P24

P25

P26

P27

P20

P21

P22

P23

P24

P25

P26

P27

Display

Figure 4.42 7-segment LED Connection Diagram

Rev. 2.0, 11/01, page 330 of 358

4.11.2 Operation Description

Figure 4.43 shows this example's principle of operation.

10µs Reception clock frequency

Stop

condition

···

Ack

Start

condition Stop

condition

Start

condition Start

condition

1st transmission

data = H'A4 2nd

transmission

data =

H'C0

The EEPROM's

write cycle

= 10ms

SCL

SDA

SCL

SDA

[1] [5]

[2] [3]

[7] [13]

[7]

[8] [9] [10] [11]

[3] [4]

Memory address

= H'00

Slave address

+ R/ = H'A0

1st reception

data = H'A4 2nd reception

data = H'C0

The EEPROM's

write cycle

= 10ms Memory address

= H'00

Slave address

+ R/ = H'A0 Slave address

+ R/ = H'A1

Ack Ack Ack Ack Ack

Ack Ack Ack

[6] [6] [12]

Processing by master 1 Processing by master 2

Sets the start condition

Detects the start condition (IRIC = 1), writes the data for

transmission to ICDR0, and clears IRIC to 0.

Writes the data for transmission to ICDR0 at rising of 9th clock

(IRIC = 1) and clears IRIC to 0.

Fails to acquire the bus (AL = 1) and enters the slave-reception

mode (MST = 0, TRS = 0)

No operation

Sets the start condition (BBSY = 0, SCP = 1)

Detects the start condition (IRIC = 1), writes the data for

transmission to ICDR0, and clears IRIC to 0.

Writes the data for transmission to ICDR0 at rising of 9th clock

(IRIC = 1) and clears IRIC to 0.

Detects the start condition (IRC = 1), dummy-reads ICDR0,

and clears IRIC to 0.

Reads the 1st byte of the received data from ICDR0 at rising of 9th

clock (IRIC = 1) ACKB = WAIT = 1, IRIC = 0

Moves to the master receive mode (TRS = 0) and clears IRIC

to 0 at falling of 8th clock (IRIC = 1).

Reads the 2nd byte of received data from ICDR0 on the falling

edge of a 1 clock cycle (IRIC = 1).

Sets the start condition (BBSY = 0, SCP = 1)

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[11]

[12]

[13]

Sets the start condition

Detects the start condition (IRIC = 1), writes the data for

transmission to ICDR0, and clears IRIC to 0.

Writes the data for transmission to ICDR0 at rising

of 9th clock (IRIC = 1) and clears IRIC to 0.

Sets the start condition (BBSY = 0, SCP = 1)

No operation

Figure 4.43 Operation in a Bus Conflict

Rev. 2.0, 11/01, page 331 of 358

4.11.3 Description of Software

(1) Description of Modules

Table 4.36 describes the modules used in this example of a task.

Table 4.36 Description of Modules

Name Label Function

Main routine main Sets the stack pointer, MCU mode, and IRQ6 interrupt, and

enables interrupts. When this device has acquired bus

mastership, transmits 2 bytes of data by master

transmission and lights the LED. When it is unable to

acquire the bus, it ac ts as a master receiver to receive 2

bytes of data and displays the data on the 7-segment LED

to which this master is attached.

Initial setting initialize Makes initial settings for the RAM, ports, and IIC0.

Start-condition

setting set_start Sets the start condition.

Stop-condition

setting set_stop Sets the stop condition.

Transmiss ion of

slave address + W trs_slvadr_a0 Trans mits the EEPROM’s slave address + W bit as data

(H’A0).

Transmiss ion of

slave address + R trs_slvadr_a1 Trans mits the EEPROM’s slave address + R bit as data

(H’A1).

Transmiss ion of

location in EEPROM trs_memadr Transmits the address of a location within the EEPROM as

data (H’00).

Wait wait_1 Waits for completion of the EEPROM-write cycle (10 ms: in

20-MHz operation)

(2) Description of the On-chip Registers

Table 4.37 describes the usage of on-chip registers in this example of a task.

Table 4.37 On-chip Registers

ICDR0 Stores the data for transmission/received data H'FFDE —

SAR0 FS Along with the settings in the FSX bit of SARX0 and

the SW bit of DDCSWR, sets the format for transfer.H'FFDF bit00

SARX0 FSX Along with the settings in the FS bit of SAR0 and

the SW bit of DDSWR, sets the format for transfer. H'FFDE bit01

Rev. 2.0, 11/01, page 332 of 358

Table 4.37 On-chip Registers (cont)

MLS Sets data transfer as MSB first. H'FFDF bit70

WAIT Sets whether to insert wait cycles between the data

bits and the acknowl edg e bit. H'FFDF bit60/1

CKS2

CKS0

Along with the setting in the IICX0 bit of STCR, set

the frequency of the transfer clock to 100 kHz. H'FFDF

bit5 to

bit3

CKS2=1

CKS1=0

CKS0=1

ICMR0

BC2

BC0

Set the number of bits for the next transfer in the I2C

bus format to 9 (9 bits/frame). H'FFDF

bit2 to

bit0

BC2=0

BC1=0

BC0=0

ICE Controls access to the ICMR0, ICDR0/SAR, and

SARX registers, and selects the operation (the port

function for the SCL0/SDA0 pin) or non-operation

(bus-drive state for the SCL/SDA pin) of the I2C bus

interface.

H'FFD8 bit70/1

IEIC Disables the generation of interrupt requests by the

I2C bus interface. H'FFD8 bit60

MST Uses the I2C bus interface in its master mode. H'FFD8 bit51

TRS Uses the I2C bus interface in its transmission or

reception mode. H'FFD8 bit40/1

ACKE Suspends the continuous transfer of data when the

acknowle dge bit is 1. H'FFD8 bit3 1

BBSY Confirms whether or not the I2C bus is occup ied,

and, in combination with the SCP bit, sets the start

and stop condit ion s.

H'FFD8 bit20/1

IRIC Detects the start condition, determines the end of

data transfer, and detects acknowledge = 1. H'FFD8 bit1 0/1

ICCR0

SCP Along with the BBSY bit, sets the start/stop

conditions. H'FFD8 bit00

ICSR0 ACKB Stores the acknowledgement that is transmitted

from the EEPROM during transmission, and sets

the acknowledge data for output to the EEPROM

during a receive operation.

H'FFD9 bit0—

IICX0 Sets the frequency of the transfer clock to 100 kHz

with the CKS2 to CKS0 of ICMR0. H'FFC3 bit51

IICE Enables CPU ac cess to the data register and the

control register of the I 2C bus interface. H'FFC3 bit4 1

STCR

FLSHE Sets the control register of the flash memory to non-

selected. H'FFC3 bit30

Rev. 2.0, 11/01, page 333 of 358

Table 4.37 On-chip Registers (cont)

SWE Prohibits automatic changeover from format-less

transfer to transfer in the I2C bus format on the

channel 0 I2C interfac e.

H'FEE6 bit70

SW Uses the channel 0 I2C interface in the I2C bus

format. H'FEE6 bit60

IE Prohibits interrupts during automatic changes of

format. H'FEE6 bit50

DDCSWR

CLR3

CLR0

Control the initialization of the internal state of the

channel 0 I2C interfac e. H'FEE6

bit3 to

bit0

CLR3=1

CLR2=1

CLR1=1

CLR0=1

MSTP7 Cancels the module-stopped mode for SCI channel

0. H'FF87 bit7 0MSTPCRL

MSTP4 Cancels the module-stopped mode for I2C channel

0. H'FF87 bit4 0

SCR0 CKE1, 0 Make the I/O port setting for the P52/SCK0/SCL0

pin. H'FFDA

bit1, 0 CKE1=0

CKE0=0

SMR0 C/$Sets the mode for SCI transfer on channel 0 as

asynchronous. H'FFD8 bit70

SYSCR INTM1, 0 Set the interrupt-control mode of the interrupt

controller to 1-bit control. H'FFC4

bit5, 4 INTM1=0

INTM0=0

MDCR MDS1, 0 Set the MCU’s operating mode to mode 3 by

latching the input levels on the MD1 and 0 pins. H'FFC5

bit1, 0 MDS1=1

MDS0=1

P1DDR P10DDR Sets the P10 pin to act as an output pin. H'FFB0 bit0 1

P1DR P10DDR Sets the data for output on the P10 pin. H'FFB2 bit0 0/1

P2DDR Sets port 2 to act as an output port. H'FFB1 H'FF

P2DR Sets the data for output on po rt 2. H'FFB3 —

P4DDR Sets port 4 to act as an output pin. H'FFB5 H'FF

P4DR Sets the data for output on po rt 4. H'FFB7 —

ISCRH Generates an interrupt request at the fa lling edge of

the IRQ6 input. H'FEEC H'10

ISR IRQ6F Displays the state of the IRQ6-interrupt request. H'FEEB bit60/1

Rev. 2.0, 11/01, page 334 of 358

(3) Description of Variables

Table 4.38 describes the variables used in this example of a task.

Table 4.38 Description of Variables

Variable Function Size Initial

Value Name of Using

Module

dummy MDCR read value 1 byte — main

dt_trs[0] 1st byte of data for transmission 1 byte H'F9/A4 main

dt_trs[1] 2nd byte of data for transmission 1 byte H'C0 main

(4) Description of RAM Usage

Table 4.39 describes the usage of RAM in this example of a task.

Table 4.39 Description of RAM Usage

Label Function Size Address Name of Using

Module

dt_rec[0] Stores the 1st byte of received data 1 byte H'E100 main, initialize

dt_rec[1] Stores the 2nd byte of received data 1 byte H'E101 main, initialize

Rev. 2.0, 11/01, page 335 of 358

4.11.4 Flowchart

(1) Main routine

main

SP H'F000

dummy MDCR

set_start

TRS 1

MST 1

CCR 1bit 0

IRQ6F 0

ISCRH H'F000

initialize

SYSCR H'F09

Yes

··························

·················

··························

·················

··························

·················

·············

·················

Set SP (stack pointer) to H'F000.

Read MDCR to latch the input levels on the MD1 and MD0

pins to the bits MDS1 and MDS0.

Call the subroutine that makes the initial settings.

Set the interrupt control mode of the interrupt controller to

1-bit interrupt control.

Set ISCRH so that an interrupt request is generated on the

falling edge of the IRQ6 input.

Clear the IRQ6 interrupt-request flag (IRQ6F = 0)

Clear the 1 bit to enable interrupts.

Bus-released state (BBSY = 0)?

Call the start-condition setting subroutine.

AL = 0 ?

Call transmission of slave address + W subroutine

AL = 0 ?

IRQ interrupt triggered (IRQ6F = 1)?

Set master transmission mode (MST = 1, TRS = 1).

AL = 0 ?

BBSY = 0 ?

IRQ6F = 1 ?

trs_slvadr_a0

Rev. 2.0, 11/01, page 336 of 358

trs_memadr

set_stop

P10DR 0

IRIC 0 ?

ICDR0 dt_trs[1]

IRIC 0 ?

ICDR0 dt_trs[0]

Yes

·······················

···············

·······················

···············

·······················

···········

Output logic-low on P97.

AL = 0 ?

Write the 1st byte of the data for transmission to ICDR0.

Clear IRIC to 0 so that this bit indicates, at rising of 9th transmission

clock, whether or not the transmission of data has been completed.

AL = 0 ?

Write the 2nd byte of the data for transmission to ICDR0.

Call the stop-condition setting subroutine.

Light up the LED.

Clear IRIC to 0 so that this bit indicates, at rising of 9th transmission

clock, whether or not the transmission of data has been completed.

Transmission completed?

AL = 0 ?

IRIC = 1 ?

AL = 0 ? 2

Rev. 2.0, 11/01, page 337 of 358

AL = 0

wait_1

set_start

trs_slvadr_a0

trs_memadr

set_start

trs_slvadr_a1

TRS 1

MST 1

Yes

·······················

················

·······················

················

·······················

················

··········· Bus released (BBSY = 0)?

················

AL = 0

Call the wait subroutine?

Call the start-condition setting subroutine.

Transmission of slave address + W subroutine.

ACKB = 0 ?

Transmission of slave address + W subroutine.

ACKB = 0 ?

Call the start-condition setting subroutine.

Transmission of slave address + R subroutine.

ACKB = 0 ?

Set the master-transmission mode.

BBSY = 0 ?

ACKB = 0 ? 3

Rev. 2.0, 11/01, page 338 of 358

TRS 0

ACKB 0

dt_rec[0] CDR0

IRIC 0

ACKB 1

WAIT 1

TRS 1

IRIC 0

dt_rec[1] ICDR0

ACKB 0

dt_rec[0] ICDR0

IRIC 0

Yes

····················

·········

····················

·········

ACKB = 0 (output 0 with the timing for the output of an acknowledge bit)

Dummy read (start of receive)

Clear IRIC to 0 so that this bit indicates, at rising of 9th receive clock,

whether or not data has been received.

Clear IRIC to 0 so that this bit indicates, at rising of 9th receive clock,

whether or not data has been received.

ACKB = 1 (output 0 with the timing for the output of an acknowledge bit)

ACKB = 0

WAIT = 1 (Insert wait cycles between the data bits and acknowledge bit)

Read the 1st byte of the received data (to start receiving the 2nd byte).

Read the 2nd byte of the received data.

Has the 9th cycle of the reception clock already been output

(at rising of the 9th receive clock)?

Set master-reception mode.

Set this device to master-transmission mode

IRIC = 0 (start outputting the 9th clock cycle)

Receiving of data completed?

IRIC = 1 ?

IRIC = 1 ? No

Rev. 2.0, 11/01, page 339 of 358

············

WAIT = 0

IRIC = 0

Call the stop-condition setting subroutine.

Place the 1st byte of received data on P2DR to light up one of the

7-segment LEDs (SG1).

Place the 2nd byte of the receive data on P4DR to light up the other

7-segment LED (SG2).

WAIT 0

IRIC 0

set_stop

P2DR dt_rec[0]

P4DR dt_rec[1]

Rev. 2.0, 11/01, page 340 of 358

(2) Initial Setting Subrout ine

initialize

dt_rec[0] H'00

dt_rec[1] H'00

P1DR H'01

P1DDR H'01

P2DR H'FF

P2DDR H'FF

P4DR H'FF

P4DDR H'FF

STCR H'00

MSTPCRL H'7F

SMR0 H'00

STCR H'10

DDCSWR H'0F

ICCR0 H'01

SAR0 H'00

SARX0 H'01

············

······

············

Initialize the location used to store the 1st byte of received data.

Initialize the location used to store the 2nd byte of received data.

Set a high level for output on P10.

Set the data on P20 to P27 to high level.

Set pins P20 to P27 as outputs.

Set the data on P40 to P47 to high level.

Set pins P40 to P47 as outputs.

Set the FLSHE bit of STCR to 0 to set the control register of the flash

memory to non-selective.

Set the MSTP7 bit of MSTPCRL to 0 to take SCI0 out of its

module-stopped mode.

Set the SMR's C/ bit to 0 to set the SCI0 to operate in its asynchronous

mode.

Set the SCR's CKE1 bit to 0 and CKE bit to 0 to set the SCK0 pin for use

as an I/O port.

Set the STCR's IICE bit to 1 so that the data and control registers of the

C bus interface are accessible by the CPU.

Set the MSTPCRL's MSTP7 bit to 1 and MSTP4 bit to 0 to put SCI0 in its

module-stopped mode and take IIC0 out of its module-stopped mode.

Set the SWE, SW, and IE bits of DDCSWR to 0 to disable automatic

changeover from IIC0 format-less to I

C bus format, select use of IIC0

in the I

C bus format, and disable interrupts during the execution of

automatic format changeover.

Set ICCR0's ICE bit to 0 to enable access to SAR0 and SARX0.

Set FS in SAR0 and FSX in SARX0 to 0 to select the I

C bus format

(enables the SAR slave address and disables the SARX slave address)

as the format for transfer on IIC0.

Set the P10 pin as an output.

MSTPCRL H'EF

SCR0 H'00

Rev. 2.0, 11/01, page 341 of 358

rts

ICCR0 H'81

ICSR0 H'00

STCR H'30

ICMR0 H'28

ICCR0 H'89

···············

··········

Set ICCR0's ICE bit to 1 to enable access to ICMR0 and ICDR0.

Set the ACKB bit in ICSR0 to 0.

Set IEIC in ICCR0 to 0 to disable the generation of IIC0 interrupt

requests, and set ACKE to 1 to suspend continuous transfer when

the acknowledge bit is 1.

Set IICX0 in STR to 1, ICMR0's CKS2 bit to 1, CKS1 bit to 0, and CKS0

bit to 1 so that the frequency of the IIC0 transfer clock is set to 100 kHz.

Set WAIT to 0 for the continuous transfer of data and acknowledge bits.

(3) Subroutine for Setting the Sta r t Condition

set_start

rts

Yes

··················

·······

Clear IRIC to 0 so that it indicates whether or not the start

condition has been detected.

Set the start condition by setting ICCR0's BBSY bit to 1

and SCP bit to 0.

Has the start condition been detected on the bus lines?

IRIC = 1 ?

IRIC 0

ICCR0 H'BC

(4) Subroutine for Setting the Sto p Co ndition

set_stop

rts

Yes

··················

·······

Set the stop condition by setting ICCR0's BBSY and SCP bits to 0.

Bus released?

BBSY = 0 ?

ICCR0 H'B8

Rev. 2.0, 11/01, page 342 of 358

(5) Subrout ine for transmit ting the slave address + W bit

trs_slvadr_a0

rts

Yes

··················

·······

Transmit the EEPROM's slave address + W bit as data (H'A0)

Clear IRIC to 0 so that it indicates whether or not data has been

transmitted (at rising of the 9th transmission clock).

Transmission of the EEPROM's slave address + W data completed?

IRIC = 1 ?

ICCR0 H'A0

IRIC 0

(6) Subrout ine for transmit ting the slave address + R bit

trs_slvadr_a1

rts

Yes

··················

·······

Transmit the EEPROM's slave address + R bit as data (H'A0)

Clear IRIC to 0 so that it indicates whether or not data has been

transmitted (at rising of the 9th transmission clock).

Transmission of the EEPROM's slave address + R data completed?

IRIC = 1 ?

ICCR0 H'A1

IRIC 0

Rev. 2.0, 11/01, page 343 of 358

(7) Subroutine for transmitting the location within the EEPROM

trs_memadr

rts

Yes

··················

·······

Transmit the address of a location within the EEPROM as data (H'00).

Clear IRIC to 0 so that it indicates whether or not data has been

transmitted (at rising of the 9th transmission clock).

Transmission of the address of a location within the EEPROM

completed?

IRIC = 1 ?

ICCR0 H'00

IRIC 0

(8) WAIT2 subroutine

wait_2

rts

PUSH ER0

ER0 H'00010800

P0P ER0

ER0 ER0 - 1

Yes

··················

··········

··················

Place the ER0 register on the stack.

An initial setting for a loop that decrements ER0.

Decrementing completed?

Decrement ER0.

Restore the original value of the ER0 register.

ER0 = 0 ?

Rev. 2.0, 11/01, page 344 of 358

4.11.5 Master-1 program List

/*****************************************************

* H8S/2138 IIC bus application note *

* 10.Multi master transmit/receive 1 *

* File na me : Mltx1.c *

* Fai : 20MHz *

* Mode : 3 *

******************************************************/

#include <stdio.h>

#include <machine.h>

#include "2138s.h"

/*****************************************************

* Prototype *

******************************************************/

void main(void); /* Main routine */

void initialize(void); /* RAM & port & IIC0 initialize */

void set_start(void); /* Start condition set */

void set_stop(void); /* Stop condition set */

void trs_slvadr_a0(void); /* Slave address + W data transmit */

void trs_slvadr_a1(void); /* Slave address + R data transmit */

void trs_memadr(void); /* EEPROM memry address data transmit */

void wait_1(void); /* EEPROM write cycle(10ms) wait */

/*****************************************************

* Data table *

******************************************************/

const unsigned char dt_trs[2] = /* Transmit data (2 byte) */

{

0xf9, /* Master 1 1st transmit data */

0xc0 /* Master 1 2nd transmit data */

};

/*****************************************************

* RAM allocation *

******************************************************/

Rev. 2.0, 11/01, page 345 of 358

#pragma sect ion rama re a

unsigned char dt_rec[2]; /* Receive data store area (2 byte) */

#pragma sect ion

/*****************************************************

* main : Main routine *

******************************************************/

void main(void)

#pragma asm

mov.l #h'f000,sp ;Stack pointer initialize

#pragma enda sm

{

unsigned char dummy;

dummy = MDCR.BYTE; /* MCU mode set */

SYSCR.BYTE = 0x09; /* Interrupt control mode set */

initialize(); /* Initialize */

INTC.ISCR.BYTE.H = 0x10; /* IRQ6 edge sense set (faling edge) */

INTC.ISR.BIT.IRQ6F = 0; /* IRQ6 interrupt request flag clear */

set_imask_ccr(0); /* Interrupt enable */

while(INTC.ISR.BIT.IRQ6F == 0); /* IRQ interrupt switch on ? */

INTC.ISR.BIT.IRQ6F = 0; /* IRQ6F = 0 */

if(IIC0.ICCR.BIT.BBSY == 0) /* Bus empty (BBSY=0) ? */

{

IIC0.ICCR.BIT.MST = 1; /* Master transmit mode set */

IIC0.ICCR.BIT.TRS = 1; /* MST = 1, TRS = 1 */

set_start(); /* Start condition set */

if(IIC0.ICSR.BIT.AL == 0) /* AL = 0 ? */

{

trs_slvadr_a0(); /* Slave address + W data transmit */

if(IIC0.ICSR.BIT.AL == 0) /* AL = 0 ? */

{

trs_memadr(); /* EEPROM memory address transmit */

Rev. 2.0, 11/01, page 346 of 358

if(IIC0.ICSR.BIT.AL == 0) /* AL = 0 ? */

{

IIC0.ICDR = dt_trs[0]; /* 1st transmit data write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

if(IIC0.ICSR.BIT.AL == 0) /* AL = 0 ? */

{

IIC0.ICDR = dt_trs[1]; /* 2nd transmit data write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

set_stop(); /* Stop condition set */

P1.DR.BIT.B0 = 0; /* LED on */

while(1); /* End */

}

IIC0.ICSR.BIT.AL = 0; /* AL= 0 */

while(IIC0.ICCR.BIT.BBSY == 1); /* Transmit end (BBSY=0) ? */

wait_1(); /* 10ms wait */

while(IIC0.ICCR.BIT.BBSY == 1); /* Bus empty (BBSY=0) ? */

IIC0.ICCR.BIT.MST = 1; /* Master transmit mode set */

IIC0.ICCR.BIT.TRS = 1; /* MST = 1, TRS = 1 */

set_start(); /* Start condition set */

trs_slvadr_a0(); /* Slave address + W data transmit */

if(IIC0.ICSR.BIT.ACKB == 0) /* ACKB = 0 ? */

{

trs_memadr(); /* EEPROM memory address data transmit */

if(IIC0.ICSR.BIT.ACKB == 0) /* ACKB = 0 ? */

{

set_start(); /* Re-start condition set */

trs_slvadr_a1(); /* Slave address + R data transmit */

Rev. 2.0, 11/01, page 347 of 358

if(IIC0.ICSR.BIT.ACKB == 0) /* ACKB = 0 ? */

{

IIC0.ICCR.BIT.TRS = 0; /* Master receive mode set (TRS=0) */

IIC0.ICSR.BIT.ACKB = 0; /* ACKB = 0 */

dt_rec[0] = IIC0.ICDR; /* Dummy read */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Receive end (IRIC=1) ? */

IIC0.ICSR.BIT.ACKB = 1; /* ACKB = 1 */

IIC0.ICMR.BIT.WAIT = 1; /* WAIT = 1 */

dt_rec[0] = IIC0.ICDR; /* 1st receive data read */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Receive end (IRIC=1) ? */

IIC0.ICCR.BIT.TRS = 1; /* Master transmit mode set (TRS=1) */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* IRIC = 1 ? */

dt_rec[1] = IIC0.ICDR; /* 2nd receive data read */

IIC0.ICSR.BIT.ACKB = 0; /* ACKB = 0 */

IIC0.ICMR.BIT.WAIT = 0; /* WAIT = 0 */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

}

set_stop(); /* Stop condition set */

P2.DR.BYTE = dt_rec[0]; /* SG1 on */

P4.DR.BYTE = dt_rec[1]; /* SG2 on */

while(1); /* End */

}

/*****************************************************

* initialize : RAM & Port & IIC0 Initialize *

******************************************************/

void initialize(void)

Rev. 2.0, 11/01, page 348 of 358

{

dt_rec[0] = 0x00; /* Receive data store area initialize */

dt_rec[1] = 0x 00;

P1.DR.BYTE = 0x01; /* Port 1 initialize */

P1.DDR = 0x01;

P2.DR.BYTE = 0xff; /* Port 2 initialize */

P2.DDR = 0xff;

P4.DR.BYTE = 0xff; /* Port 4 initialize */

P4.DDR = 0xff;

STCR.BYTE = 0x00; /* FLSHE = 0 */

MSTPCR.BYTE.L = 0x7f; /* SCI0 module stop mode reset */

SCI0.SMR.BYTE = 0x00; /* SCL0 pin function set */

SCI0.SCR.B YTE = 0x00 ;

MSTPCR.BYTE.L = 0xef; /* IIC0 module stop mode reset */

STCR.BYTE = 0x10; /* IICE = 1 */

DDCSWR.BYTE = 0x0f; /* IIC bus format initialize */

IIC0.ICCR.BYTE = 0x01; /* ICE = 0 */

IIC0.SAR.BYTE = 0x38; /* FS = 0 */

IIC0.SARX.BYTE = 0x01; /* FSX = 1 */

IIC0.ICCR.BYTE = 0x81; /* ICE = 1 */

IIC0.ICSR.BYTE = 0x00; /* ACKB = 0 */

STCR.BYTE = 0x30; /* IICX0 = 1 */

IIC0.ICMR.BYTE = 0x28; /* Transfer rate = 100kHz */

IIC0.ICCR.BYTE = 0x89; /* IEIC = 0, ACKE = 1 */

}

/*****************************************************

* set_start : Start condition set *

******************************************************/

void set_start(void)

{

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

IIC0.ICCR.BYTE = 0xbc; /* Start condition set (BBSY=1,SCP=0) */

while(IIC0.ICCR.BIT.IRIC == 0); /* Start condition set (IRIC=1) ? */

}

Rev. 2.0, 11/01, page 349 of 358

/*****************************************************

* set_stop : Stop condition set *

******************************************************/

void set_stop(void)

{

IIC0.ICCR.BYTE = 0xb8; /* Stop condition set (BBSY=0,SCP=0) */

while(IIC0.ICCR.BIT.BBSY == 1); /* Bus empty (BBSY=0) ? */

}

/*****************************************************

* trs_slvadr_a0 : Slave addres + W data transmit *

******************************************************/

void trs_slvadr_a0(void)

{

IIC0.ICDR = 0xa0; /* Slave address + W data(H'A0) write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

/*****************************************************

* trs_slvadr_a1 : Slave addres + R data transmit *

******************************************************/

void trs_slvadr_a1(void)

{

IIC0.ICDR = 0xa1; /* Slave address + R data(H'A1) write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

/*****************************************************

* trs_memadr : EEPROM memory address data transmit *

******************************************************/

void trs_memadr(void)

{

IIC0.ICDR = 0x00; /* EEPROM memory address data(H'00) write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

Rev. 2.0, 11/01, page 350 of 358

/*****************************************************

* wait_1 : 10ms wait *

******************************************************/

void wait_1(void)

{

#pragma asm

push.l er0 ;Push ER0

mov.l #h'00010800,er0 ;Decrement data set

wait1_1:

dec.l #1,er0 ;Decrement

bne wait1_1 ;Decrement end ?

pop.l er0 ;Pop ER0

#pragma enda sm

}

Rev. 2.0, 11/01, page 351 of 358

4.11.6 Master-2 program List

/*****************************************************

* H8S/2138 IIC bus application note *

* 10.Multi master transmit/receive 2 *

* File na me : Mltx2.c *

* Fai : 20MHz *

* Mode : 3 *

******************************************************/

#include <stdio.h>

#include <machine.h>

#include "2138s.h"

/*****************************************************

* Prototype *

******************************************************/

void main(void); /* Main routine */

void initialize(void); /* RAM & port & IIC0 initialize */

void set_start(void); /* Start condition set */

void set_stop(void); /* Stop condition set */

void trs_slvadr_a0(void); /* Slave address + W data transmit */

void trs_slvadr_a1(void); /* Slave address + R data transmit */

void trs_memadr(void); /* EEPROM memry address data transmit */

void wait_1(void); /* EEPROM write cycle(10ms) wait */

/*****************************************************

* Data table *

******************************************************/

const unsigned char dt_trs[2] = /* Transmit data (2 byte) */

{

0xa4, /* Master 2 1st transmit data */

0xc0 /* Master 2 2nd transmit data */

};

Rev. 2.0, 11/01, page 352 of 358

/*****************************************************

* RAM allocation *

******************************************************/

#pragma sect ion rama re a

unsigned char dt_rec[2]; /* Receive data store area (2 byte) */

#pragma sect ion

/*****************************************************

* main : Main routine *

******************************************************/

void main(void)

#pragma asm

mov.l #h'f000,sp ;Stack pointer initialize

#pragma enda sm

{

unsigned char dummy;

dummy = MDCR.BYTE; /* MCU mode set */

SYSCR.BYTE = 0x09; /* Interrupt control mode set */

initialize(); /* Initialize */

INTC.ISCR.BYTE.H = 0x10; /* IRQ6 edge sense set (faling edge) */

INTC.ISR.BIT.IRQ6F = 0; /* IRQ6 interrupt request flag clear */

set_imask_ccr(0); /* Interrupt enable */

while(INTC.ISR.BIT.IRQ6F == 0); /* IRQ interrupt switch on ? */

INTC.ISR.BIT.IRQ6F = 0; /* IRQ6F = 0 */

if(IIC0.ICCR.BIT.BBSY == 0) /* Bus empty (BBSY=0) ? */

{

IIC0.ICCR.BIT.MST = 1; /* Master transmit mode set */

IIC0.ICCR.BIT.TRS = 1; /* MST = 1, TRS = 1 */

set_start(); /* Start condition set */

if(IIC0.ICSR.BIT.AL == 0) /* AL = 0 ? */

{

trs_slvadr_a0(); /* Slave address + W data transmit */

Rev. 2.0, 11/01, page 353 of 358

if(IIC0.ICSR.BIT.AL == 0) /* AL = 0 ? */

{

trs_memadr(); /* EEPROM memory address transmit */

if(IIC0.ICSR.BIT.AL == 0) /* AL = 0 ? */

{

IIC0.ICDR = dt_trs[0]; /* 1st transmit data write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

if(IIC0.ICSR.BIT.AL == 0) /* AL = 0 ? */

{

IIC0.ICDR = dt_trs[1]; /* 2nd transmit data write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

set_stop(); /* Stop condition set */

P1.DR.BIT.B0 = 0; /* LED on */

while(1); /* End */

}

IIC0.ICSR.BIT.AL = 0; /* AL= 0 */

while(IIC0.ICCR.BIT.BBSY == 1); /* Transmit end (BBSY=0) ? */

wait_1(); /* 10ms wait */

while(IIC0.ICCR.BIT.BBSY == 1); /* Bus empty (BBSY=0) ? */

IIC0.ICCR.BIT.MST = 1; /* Master transmit mode set */

IIC0.ICCR.BIT.TRS = 1; /* MST = 1, TRS = 1 */

set_start(); /* Start condition set */

trs_slvadr_a0(); /* Slave address + W data transmit */

if(IIC0.ICSR.BIT.ACKB == 0) /* ACKB = 0 ? */

{

trs_memadr(); /* EEPROM memory address data transmit */

if(IIC0.ICSR.BIT.ACKB == 0) /* ACKB = 0 ? */

Rev. 2.0, 11/01, page 354 of 358

{

set_start(); /* Re-start condition set */

trs_slvadr_a1(); /* Slave address + R data transmit */

if(IIC0.ICSR.BIT.ACKB == 0) /* ACKB = 0 ? */

{

IIC0.ICCR.BIT.TRS = 0; /* Master receive mode set (TRS=0) */

IIC0.ICSR.BIT.ACKB = 0; /* ACKB = 0 */

dt_rec[0] = IIC0.ICDR; /* Dummy read */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Receive end (IRIC=1) ? */

IIC0.ICSR.BIT.ACKB = 1; /* ACKB = 1 */

IIC0.ICMR.BIT.WAIT = 1; /* WAIT = 1 */

dt_rec[0] = IIC0.ICDR; /* 1st receive data read */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Receive end (IRIC=1) ? */

IIC0.ICCR.BIT.TRS = 1; /* Master transmit mode set (TRS=1) */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* IRIC = 1 ? */

dt_rec[1] = IIC0.ICDR; /* 2nd receive data read */

IIC0.ICSR.BIT.ACKB = 0; /* ACKB = 0 */

IIC0.ICMR.BIT.WAIT = 0; /* WAIT = 0 */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

}

set_stop(); /* Stop condition set */

P2.DR.BYTE = dt_rec[0]; /* SG1 on */

P4.DR.BYTE = dt_rec[1]; /* SG2 on */

while(1); /* End */

}

Rev. 2.0, 11/01, page 355 of 358

/*****************************************************

* initialize : RAM & Port & IIC0 Initialize *

******************************************************/

void initialize(void)

{

dt_rec[0] = 0x00; /* Receive data store area initialize */

dt_rec[1] = 0x 00;

P1.DR.BYTE = 0x01; /* Port 1 initialize */

P1.DDR = 0x01;

P2.DR.BYTE = 0xff; /* Port 2 initialize */

P2.DDR = 0xff;

P4.DR.BYTE = 0xff; /* Port 4 initialize */

P4.DDR = 0xff;

STCR.BYTE = 0x00; /* FLSHE = 0 */

MSTPCR.BYTE.L = 0x7f; /* SCI0 module stop mode reset */

SCI0.SMR.BYTE = 0x00; /* SCL0 pin function set */

SCI0.SCR.B YTE = 0x00 ;

MSTPCR.BYTE.L = 0xef; /* IIC0 module stop mode reset */

STCR.BYTE = 0x10; /* IICE = 1 */

DDCSWR.BYTE = 0x0f; /* IIC bus format initialize */

IIC0.ICCR.BYTE = 0x01; /* ICE = 0 */

IIC0.SAR.BYTE = 0x38; /* FS = 0 */

IIC0.SARX.BYTE = 0x01; /* FSX = 1 */

IIC0.ICCR.BYTE = 0x81; /* ICE = 1 */

IIC0.ICSR.BYTE = 0x00; /* ACKB = 0 */

STCR.BYTE = 0x30; /* IICX0 = 1 */

IIC0.ICMR.BYTE = 0x28; /* Transfer rate = 100kHz */

IIC0.ICCR.BYTE = 0x89; /* IEIC = 0, ACKE = 1 */

}

/*****************************************************

* set_start : Start condition set *

******************************************************/

void set_start(void)

{

Rev. 2.0, 11/01, page 356 of 358

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

IIC0.ICCR.BYTE = 0xbc; /* Start condition set (BBSY=1,SCP=0) */

while(IIC0.ICCR.BIT.IRIC == 0); /* Start condition set (IRIC=1) ? */

}

/*****************************************************

* set_stop : Stop condition set *

******************************************************/

void set_stop(void)

{

IIC0.ICCR.BYTE = 0xb8; /* Stop condition set (BBSY=0,SCP=0) */

while(IIC0.ICCR.BIT.BBSY == 1); /* Bus empty (BBSY=0) ? */

}

/*****************************************************

* trs_slvadr_a0 : Slave addres + W data transmit *

******************************************************/

void trs_slvadr_a0(void)

{

IIC0.ICDR = 0xa0; /* Slave address + W data(H'A0) write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

/*****************************************************

* trs_slvadr_a1 : Slave addres + R data transmit *

******************************************************/

void trs_slvadr_a1(void)

{

IIC0.ICDR = 0xa1; /* Slave address + R data(H'A1) write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

/*****************************************************

* trs_memadr : EEPROM memory address data transmit *

******************************************************/

void trs_memadr(void)

{

Rev. 2.0, 11/01, page 357 of 358

IIC0.ICDR = 0x00; /* EEPROM memory address data(H'00) write */

IIC0.ICCR.BIT.IRIC = 0; /* IRIC = 0 */

while(IIC0.ICCR.BIT.IRIC == 0); /* Transmit end (IRIC=1) ? */

}

/*****************************************************

* wait_1 : 10ms wait *

******************************************************/

void wait_1(void)

{

#pragma asm

push.l er0 ;Push ER0

mov.l #h'00010800,er0 ;Decrement data set

wait1_1:

dec.l #1,er0 ;Decrement

bne wait1_1 ;Decrement end ?

pop.l er0 ;Pop ER0

#pragma enda sm

}

Rev. 2.0, 11/01, page 358 of 358

C Bus Interface Application Note

Publication Date: 1st Edition, March 1994

2nd Edition, November 2001

Published by: Business Planning Division

Semiconductor & Integrated Circuits

Hitachi, Ltd.

Edited by: Technical Documentation Group

Hitachi Kodaira Semiconductor Co., Ltd.