This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.01 /Jul.96 Hyundai Semiconductor
HY62256A-(I) Series
32Kx8bit CMOS SRAM
DESCRIPTION
The HY62256A/ HY62256A-I is a high-speed, low
power and 32,786 x 8-bits CMOS Static Random
Access Memory fabricated using Hyundai's high
performance CMOS process technology. The
HY62256A/ HY62256A-I has a data retention
mode that guarantees data to remain valid at the
minimum power supply voltage of 2.0 volt. Using
the CMOS technology, supply voltages from 2.0
to 5.5volt has little effect on supply current in the
data retention mode. The HY62256A/HY62256A-I
is suitable for use in low voltage operation and
battery back-up application.
FEATURES
• Fully static operation and Tri-state output
• TTL compatible inputs and outputs
• Low power consumption
• Battery backup(L/LL-part)
- 2.0V(min.) data retention
• Standard pin configuration
- 28 pin 600 mil PDIP
- 28 pin 330mil SOP
- 28 pin 8x13.4 mm TSOP-I
(Standard and Reversed)
Product Voltage Speed Operation Standby Current(uA) Temperature
No. (V) (ns) Current(mA) L LL (¡É)
HY62256A 5.0 55/70/85 50 1mA 100 25 0~70(Normal)
HY62256A-I 5.0 55/70/85 50 1mA 100 --40~85(E.T.)
Note 1. E.T. : Extended Temperature, Normal : Normal Temperature
2. Current value is max.
PIN CONNECTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
/WE
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
/WE
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
/CS
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
/OE
A11
A9
A8
A13
/WE
Vcc
A14
A12
A7
A6
A5
A4
A3
I/O8
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A2
A1
I/O1
I/O2
I/O3
Vss
I/O4
I/O5
I/O6
I/O7
I/O8
/CS
A10
A3
A4
A5
A6
A7
A12
A14
Vcc
/WE
A13
A8
A9
A11
/OE
A0
PDIP SOP TSOP-I(Standard) TSOP-I(Reversed)
PIN DESCRIPTION BLOCK DIAGRAM
Pin Name Pin Function
/CS Chip Select
/WE Write Enable
/OE Output Enable
A0 ~ A14 Address Inputs
I/O1 ~ I/O8 Data Input/Output
Vcc Power(+5.0V)
Vss Ground
A14
COLUMN DECODER
A0 ROW DECODER
MEMORY ARRAY
512x512
SENSE AMP
OUTPUT BUFFER
I/O1
I/O8
ADD INPUT BUFFER
/CS
/OE
/WE
WRITE DRIVER
CONTROL
LOGIC
HY62256A-(I) Series
Rev.01 /Jul.96 2
ORDERING INFORMATION
Part No. Speed Power Temp. Package
HY62256AP 55/70/85 PDIP
HY62256ALP 55/70/85 L-part PDIP
HY62256ALLP 55/70/85 LL-part PDIP
HY62256AJ 55/70/85 SOP
HY62256ALJ 55/70/85 L-part SOP
HY62256ALLJ 55/70/85 LL-part SOP
HY62256AT1 55/70/85 TSOP-I Standard
HY62256ALT1 55/70/85 L-part TSOP-I Standard
HY62256ALLT1 55/70/85 LL-part TSOP-I Standard
HY62256AR1 55/70/85 TSOP-I Reversed
HY62256ALR1 55/70/85 L-part TSOP-I Reversed
HY62256ALLR1 55/70/85 LL-part TSOP-I Reversed
HY62256AP-I 55/70/85 E.T. PDIP
HY62256ALP-I 55/70/85 L-part E.T. PDIP
HY62256AJ-I 55/70/85 E.T. SOP
HY62256ALJ-I 55/70/85 L-part E.T. SOP
HY62256AT1-I 55/70/85 E.T. TSOP-I
HY62256ALT1-I 55/70/85 L-part E.T. TSOP-I
HY62256AR2-I 55/70/85 E.T. TSOP-I Reversed
HY62256ALR2-I 55/70/85 L-part E.T. TSOP-I Reversed
ABSOLUTE MAXIMUM RATING (1)
Symbol Parameter Rating Unit Remark
Vcc, VIN, VOUT Power Supply, Input/Output Voltage -0.5 to 7.0 V
TAOperating Temperature 0 to 70 ¡É HY62256A
-40 to 85 ¡É HY62256A-I
TSTG Storage Temperature -65 to 150 ¡É
PDPower Dissipation 1.0 W
IOUT Data Output Current 50 mA
TSOLDER Lead Soldering Temperature & Time 260 10 ¡É sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
TA=0°C to 70°C / TA= -40°C to 85°C(E.T.)
Symbol Parameter Min. Typ. Max. Unit
Vcc Power Supply Voltage 4.5 5.0 5.5 V
VIH Input High Voltage 2.2 -Vcc+0.5 V
VIL Input Low Voltage -0.5(1) -0.8 V
Note
1. VIL = -3.0V for pulse width less than 30ns
HY62256A-(I) Series
Rev.01 /Jul.96 3
TRUTH TABLE
/CS /WE /OE MODE I/O OPERATION
HX X Standby High-Z
LH H Output Disabled High-Z
LHLRead Data Out
L L XWrite Data In
Note :
1. H=VIH, L=VIL, X=Don't Care
DC CHARACTERISTICS
Vcc = 5V¡¾10%, TA = 0¡É to 70¡É(Normal)/ -40¡É to 85¡É(E.T.) unless otherwise specified
Symbol Parameter Test Condition Min. Typ. Max. Unit
ILI Input Leakage Current Vss ¡Â VIN ¡Â Vcc -1 -1uA
ILO Output Leakage Current Vss ¡Â VOUT ¡Â Vcc, /CS = VIH or
/OE = VIH or /WE = VIL -1 -1uA
Icc Operating Power Supply
Current /CS = VIL,
VIN = VIH or VIL, II/O = 0mA -30 50 mA
ICC1 Average Operating Current /CS = VIL,
Min. Duty Cycle = 100%, II/O = 0mA -40 70 mA
ISB TTL Standby Current
(TTL Inputs) /CS= VIH VIN = VIH or VIL -0.4 2mA
ISB1 CMOS
Standby HY62256A - - 1mA
Current /CS ¡Ã Vcc - 0.2V L-2 100 uA
(CMOS VIN ≤ 0.2V or LL -1 25 uA
Inputs) HY62256A-I VIN¡Ã Vcc - 0.2V - - 1mA
L-2 100 uA
VOL Output Low Voltage IOL = 2.1mA - - 0.4 V
VOH Output High Voltage IOH = -1mA 2.4 - - V
Note : Typical values are at Vcc =5.0V, TA = 25¡É
HY62256A-(I) Series
Rev.01 /Jul.96 4
AC CHARACTERISTICS
Vcc = 5V¡¾10%, TA = 0¡É to 70¡É(Normal)/ -40¡É to 85¡É(E.T.) unless otherwise specified.
-55 -70 -85
Min. Max. Min. Max. Min Max.
1tRC Read Cycle Time 55 -70 -85 -ns
2tAA Address Access Time -55 -70 -85 ns
3tACS Chip Select Access Time -55 -70 -85 ns
4tOE Output Enable to Output Valid -30 -35 -45 ns
5tCLZ Chip Select to Output in Low Z 5-5-5-ns
6tOLZ Output Enable to Output in Low Z 5-5-5-ns
7tCHZ Chip Deselection to Output in High Z 0 20 0 30 0 30 ns
8tOHZ Out Disable to Output in High Z 0 20 0 30 0 30 ns
9tOH Output Hold from Address Change 5-5-5-ns
10 tWC Write Cycle Time 55 -70 -85 -ns
11 tCW Chip Selection to End of Write 50 -65 -75 -ns
12 tAW Address Valid to End of Write 50 -65 -75 -ns
13 tAS Address Set-up Time 0-0-0-ns
14 tWP Write Pulse Width 40 -50 -55 -ns
15 tWR Write Recovery Time 0-0-0-ns
16 tWHZ Write to Output in High Z 0 20 0 30 0 30 ns
17 tDW Data to Write Time Overlap 25 -35 -40 -ns
18 tDH Data Hold from Write Time 0-0-0-ns
19 tOW Output Active from End of Write 5-5-5-ns
AC TEST CONDITIONS
TA = 0¡É to 70¡É(Normal) / -40¡É to 85¡É(E.T.) unless otherwise specified.
PARAMETER VALUE
Input Pulse Level 0.8V to 2.4V
Input Rise and Fall Time 5ns
Input and Output Timing Reference Levels 1.5V
Output Load 70/85/100ns CL = 100pF + 1TTL Load
55ns CL = 50pF + 1TTL Load
AC TEST LOADS
CL(1)
TTL
Note : Including jig and scope capacitance
Symbol Parameter
#
READ CYCLE
WRITE CYCLE
Unit
HY62256A-(I) Series
Rev.01 /Jul.96 5
CAPACITANCE
TA = 25¡É, f = 1.0MHz
Symbol Parameter Condition Max. Unit
CIN Input Capacitance VIN = 0V 6pF
CI/O Input /Output Capacitance VI/O = 0V 8pF
Note : These parameters are sampled and not 100% tested
TIMING DIAGRAM
READ CYCLE 1
ADDR
OE
CS
Data
Out
tRC
tACS
tCLZ
tOE
tOLZ
tAA
tOH
tOHZ
tCHZ
High-Z
Note(READ CYCLE):
1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referenced to output voltage levels.
2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given device
and from device to device.
3. /WE is high for the read cycle.
READ CYCLE 2
tRC
tAA
Data ValidPrevious Data
tOH tOH
ADDR
Data
Out
Note(READ CYCLE):
1. /WE is high for the read cycle.
2. Device is continuously selected /CS= VIL.
3. /OE =VIL.
HY62256A-(I) Series
Rev.01 /Jul.96 6
WRITE CYCLE 1(/OE Clocked)
ADDR
OE
CS
Data
Out
tWC
tDW
tOHZ
WE
Data Valid
tDH
tWP
tAS
Data In
tWR
tCW
tAW
WRITE CYCLE 2 (/OE Low Fixed)
tDW
tWHZ
WE
Data Valid
tDH
tWP
tAS
Data In
tWR
tCW
tAW
(7)
(8)
tOW
ADDR
CS
Data
Out
tWC
Notes(WRITE CYCLE):
1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition
among /CS going low and /WE going low: A write ends at the earliest transition among /CS going high
and /WE going high. tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the later of /CS going low to the end of write .
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as /CS,
or /WE going high.
5. If /OE and /WE are in the read mode during this period, and the I/O pins are in the output low-Z state,
input of opposite phase of the output must not be applied because bus contention can occur.
6. If /CS goes low simultaneously with /WE going low, or after /WE going low, the outputs remain in high
impedance state.
7. DOUT is the same phase of latest written data in this write cycle.
8. DOUT is the read data of the new address.
HY62256A-(I) Series
Rev.01 /Jul.96 7
DATA RETENTION CHARACTERISTIC
TA=0°C to 70°C (normal)/-40°C to 85°C(E.T.)
Symbol Parameter Test Condition Min Typ Max Unit
VDR Vcc for Data Retention /CS¡ÃVcc-0.2V,Vss¡ÂVIN¡ÂVcc 2- - V
ICCDR Data Retention HY62256A Vcc = 3.0V, L-1 50 uA
Current /CS ¡ÃVcc -0.2V LL -1 15(2) uA
HY62256A-I Vss¡ÂVIN¡ÂVcc L-1 50 uA
tCDR Chip Disable to Data Retention
Time See Data Retention Timing
Diagram 0- - ns
tR Operating Recovery Time tRC(3) - - ns
Notes
1. Typical values are under the condition of TA = 25¡É.
2. 3uA max. at TA=0¡É to 40 ¡É.
3. tRC is read cycle time.
Data Retention Timing Diagram
CS
VDR
CS>VCC-0.2V
tCDR tR
VSS
VCC
4.5V
2.2V
DATA RETENTION MODE
RELIABILITY SPEC.
TEST MODE TEST SPEC.
ESD HBM ¡Ã 2000V
MM ¡Ã 250V
LATCH - UP ¡Â -100mA
¡Ã100mA
HY62256A-(I) Series
Rev.01 /Jul.96 8
PACKAGE INFORMATION
28pin 600mil Dual In-Line Package(P)
• UNIT : INCH(mm) MIN.
MAX.
1.467(37.262)
1.447(36.754)
0.140(3.556)
0.120(3.048)
0.155(3.937)
0.145(3.683)
0.020(0.508)
0.021(0.553)
0.015(0.381)
0.100(2.54)BSC
0.065(1.650)
0.050(1.270)
0.090(2.286)
0.070(1.778)
0.014(0.356)
0.008(0.200)
0.600(15.240)BSC
0.550(13.970)
0.530(13.462)
0.035(0.889)
3 deg
11 deg
28pin 330mil Small Outline Package(J)
UNIT : INCH(mm)
0.346(8.788)
0.338(8.585)
0.480(12.192)
0.460(11.684)
0.096(2.438)
0.092(2.335)
0.014(0.356)
0.002(0.051)
0.050(1.270)BSC 0.020(0.508)
0.014(0.356)
0.728(18.491)
0.720(18.288) 0.012(0.305)
0.008(0.203)
0.050(1.270)
0.030(0.762)
MAX
.
MIN.
HY62256A-(I) Series
Rev.01 /Jul.96 9
28pin 8x13.4mm Thin Small Outline Package Standard(T1)
0.468(11.9)
0.460(11.7)
0.536(13.6)
0.520(13.2)
0.027(0.7)
0.012(0.3) 0.008(0.2)
0.004(0.1)
0.319(8.1)
0.311(7.9) 0.040(1.02)
0.036(0.91)
0.008(0.20)
0.002(0.05)
0.022(0.55 BSC)
UNIT : INCH(mm)MAX.
MIN.
28pin 8x13.4mm Thin Small Outline Package Reversed(R1)
0.027(0.7)
0.012(0.3)
0.008(0.2)
0.004(0.1)
0.319(8.1)
0.311(7.9) 0.040(1.02)
0.036(0.91)
0.008(0.20)
0.002(0.05)
0.022(0.55 BSC)
0.040(1.016)
0.291(7.391) 0.145(3.683)
0.468(11.9)
0.460(11.7)
0.536(13.6)
0.520(13.2)
UNIT : INCH(mm) MAX.
MIN.