KSZ8841-16MQL-EVAL - Micrel

KSZ8841-16/32MQL/MVL/MVLI/MBL

Single-Port Ethernet MAC Controller

with Non-PCI Interface

Rev. 1.6

LinkMD is a registered trademark of Mic rel, Inc.

Magic Packet is a tradem ark of Advanced Micro Devices, Inc. Product names used in this datasheet are for identification purposes

only and may be trademarks of their respective companies.

Micrel Inc. • 2180 Fort une Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http:// www.mic rel .c om

October 2007 M9999-102207-1.6

General Description

The KSZ8841-series single-port chip includes PCI and

non-PCI CPU interfaces, and are available in 8/16-bit and

32-bit bus designs. This datasheet describes the

KSZ8841M-series of non-PCI CPU interface chips. For

information on the KSZ8841 PCI CPU interface chips,

refer to the KSZ8841P datasheet.

The KSZ8841M is a single chip, mixed analog/digital

device offering Wake-on-LAN technology for effectively

addressin g Fast Ether net a pplicati ons. It consis ts of a Fas t

Ethernet MAC controller, an 8-bit, 16-bit, and 32-bit

generic host proces sor int e r f ac e and incorp or ates a unique

dynamic memory pointer with 4-byte buffer boundary and

a full y util izable 8KB f or both T X and RX direc tions in host

buffer interface.

The KSZ8841M is designed to be fully compliant with the

appropriate IEEE 802.3 standards. An industrial

temperature-grade version of the KSZ8841M, the

KSZ8841MVLI, also can be ordered (see “Ordering

Information section).

LinkMD®

Physical signal transmission and reception are enhanced

through the use of analog circuitry, making the design

more efficient and allowing for lower-power consumption.

The KSZ8841M is designed using a low-power CMOS

process that features a single 3.3V power supply with 5V

tolerant I/O. It has an extensive feature set that offers

management information base (MIB) counters and CPU

control/data interfaces.

The KSZ8841M includes a unique cable diagnostics

feature c alled Link MD®. This feature determ ines the length

of the cablin g plant and also ascertains if there is an open

or short condition in the cable. Accompanying software

enables the cable length and cable conditions to be

conveniently displayed. In addition, the KSZ8841M

supports Hewlett Packard (HP) Auto-MDIX thereby

eliminating the need to differentiate between straight or

crossover cables in applications.

Functional Diagram

P1 HP Auto

M D I/M D I-X Host MAC

10/100

Base-T/TX

PHY

EEPROM

In te rfa c e

LED

Driver

MIB

Counters

P1 LED[3:0]

EEPROM I/F

Non-PCI

CPU

Bus

In te rfa c e

Unit

Em bedded Processor

In te rfa c e

QMU

DMA

Channel

Control

Registers

8,16, or 32-bit G eneric

H o st In te rfa ce

RXQ

4KB

TXQ

4KB

Figure 1. KSZ8841M Functional Diagram

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 2 M9999-102207-1.6

Features

• Single chip Ethernet controller with IEEE802.3u

support

• Supports 10BASE-T/100BASE-TX

• Supports IEEE 802.3x full-duplex flow control and

half-duplex backpressure collision flow control

• Supports burst data transfers

• 8KB internal memory for RX/TX FIFO buffers

• Early TX/RX functions to minimize latency through the

device

• Optional to use external serial EEPROM configuration

for both KSZ8841-16MQL and KSZ8841-32MQL

• Single 25MHz reference clock for both PHY and MAC

Network Features

• Fully integrate d to comply with IEEE802.3u sta ndards

• 10BASE-T and 100BASE-TX physical layer support

• Auto-negoti ati on: 10/1 00M bps f ull and ha lf duplex

• Adaptive equalizer

• Baseline wander correction

Power Modes, Power Supplies, and Packaging

• Single power supply (3.3V) with 5V tolerant I/O

buffers

• Enhanced power management feature with power-

down feature to ensure low-power dissipation during

device idle periods

• Comprehensive LED indicator support for link,

activity, full/half duplex, and 10/100 speed (4 LEDs)

– User programmable

• Low-power CMOS design

• Commercial Temperature Range: 0oC to +70oC

• Industrial Temperature Range: –40oC to +85oC

• Availab le in 128-p in PQ FP and 100- b al l LFBG A (1 28-

pin LQFP opt ion al)

Additional Features

In addition to offering all of the features of a Layer 2

controller, the KSZ8841M offers:

• Dynamic buffer memory scheme

– Essential for applications such as Video over IP

where image jitter is unacceptable

• Flexible 8-bit , 16-b it, and 32-bit gen er ic host

processor interfaces

• Micrel LinkMD™ cable diagnostic capabilities to

determine cable length, diagnose faulty cables, and

determine distance to fault

• Wake-on-LAN functionality

– Incorporates Magic Packet™, network link state,

and wake-up frame technology

• HP Auto MDI-X™ crossover with disable/enable

option

• Ability to transmit and receive frames up to 1916

bytes

Applications

• Video Distribution Systems

• High-end Cable, Satellite, and IP set-top boxes

• Video over IP

• Voice over IP (VoIP) and Analog Telephone Adapters

(ATA)

• Industrial Control in Latency Critical Applications

• Motion Control

• Industrial Control Sensor Devices (Temperature,

Pressure, Levels, and Valves)

• Security and Sur veil lance Cameras

Markets

• Fast Ethernet

• Embedded Ethernet

• Industrial Ethernet

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 3 M9999-102207-1.6

Ordering Information

Part Number Temperature Range Package

KSZ8841-16MQL 0oC to 70oC 128-Pin PQFP

KSZ8841-32MQL 0oC to 70oC 128-Pin PQFP

KSZ8841-16MVL 0oC to 70oC 128-Pin LQFP

KSZ8841-32MVL 0oC to 70oC 128-Pin LQFP

KSZ8841-16MVLI –40oC to +85oC 128-Pin LQFP

KSZ8841-32MVLI –40oC to +85oC 128-Pin LQFP

KSZ8841-16MBL 0oC to 70oC 100-Ball LFBGA

KSZ8841-16MBLI –40oC to +85oC 100-Ball LFBGA

KSZ8841-16MQL-Eval Evaluation Board for the KSZ8841-16MQL

KSZ8841-16MBL-Eval Evaluation Board for the KSZ8841-16MBL

Revision History

Revision Date Summary of Changes

1.0 06/30/05 First released Preliminary Information.

1.1 08/08/05 Updated General Description, Functional Diagram, Pin Description and Features.

Added this Revision History Table and Loopback support sections.

1.2 10/04/05 Update Power Saving bit description in P1PHYCTRL and P1SCSLMD registers.

1.3 11/01/05 Updated Figure 12/13/14 Asynchronous Timing and Table 16/17/18 parameters, PQFP

package information.

1.4 03/31/06 Added QMU RX Flow Control High Watermark QRFCR register and updated body text

1.5 4/10/07 Improve the ARDY low time in read cycle to 40 ns and in write cycle to 50 ns during QMU

data register access

1.6 10/22/07 Add KSZ8841-16MBL 100-Ball BGA package information

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 4 M9999-102207-1.6

Contents

General Description..............................................................................................................................................................1

Functional Diagram...............................................................................................................................................................1

Features .................................................................................................................................................................................2

Network Features ...........................................................................................................................................................2

Power Modes, Power Supp lies , and Pack agin g .............................................................................................................2

Applications...........................................................................................................................................................................2

Markets...................................................................................................................................................................................2

Ordering Information ............................................................................................................................................................3

Revision History....................................................................................................................................................................3

Pin Configuration for KSZ8841-16 Chip (8/16-Bit)...........................................................................................................10

Ball Configuration for KSZ8841-16 Chip (8/16-Bit)..........................................................................................................11

Pin Description for KSZ8841-16 Chip (8/16-Bit)...............................................................................................................12

Ball Description for KSZ8841-16 Chip (8/16-Bit)..............................................................................................................17

Pin Configuration for KSZ8841-32 Chip (32-Bit) ..............................................................................................................21

Pin Description for KSZ8841-32 Chip (32-Bit)..................................................................................................................22

Functional Description .......................................................................................................................................................27

Functional Overview...........................................................................................................................................................27

Power Management .....................................................................................................................................................27

Power down ...............................................................................................................................................................................27

Wake-on-LAN.............................................................................................................................................................................27

Link Change...............................................................................................................................................................................27

Wake-up Packet.........................................................................................................................................................................27

Magic Packet..............................................................................................................................................................................27

Physical Layer Transceiver (PHY)................................................................................................................................28

100BASE-TX Transmit...............................................................................................................................................................28

100BASE-TX Receive................................................................................................................................................................29

PLL Clock Synthesizer (Recovery).............................................................................................................................................29

Scrambler/De-scrambler (100BASE-TX Only)...........................................................................................................................29

10BASE-T Transmit...................................................................................................................................................................29

10BASE-T Receive....................................................................................................................................................................29

MDI/MDI-X Auto Crossover ........................................................................................................................................................29

Straight Cable........................................................................................................................................................................30

Crossover Cable....................................................................................................................................................................30

Auto Negotiation.........................................................................................................................................................................31

LinkMD Cable Diagnostics.........................................................................................................................................................32

Access...................................................................................................................................................................................32

Usage....................................................................................................................................................................................32

Media Access Control (MAC) Operation......................................................................................................................32

Inter Packet Gap (IPG)...............................................................................................................................................................32

Back-Off Algorithm.....................................................................................................................................................................32

Late Collision..............................................................................................................................................................................32

Flow Control...............................................................................................................................................................................32

Half-Duplex Backpressure .........................................................................................................................................................33

Clock Generator.........................................................................................................................................................................33

Bus Interface Unit (BIU)................................................................................................................................................33

Supported Transfers ..................................................................................................................................................................33

Physical Data Bus Size..............................................................................................................................................................33

Asynchronous Interface .............................................................................................................................................................35

Synchronous Interf ac e...............................................................................................................................................................36

BIU Summation..........................................................................................................................................................................36

BIU Implementation Principles...................................................................................................................................................37

Queue Management Unit (QMU)..................................................................................................................................38

Transmit Queue (TXQ) Frame Format.......................................................................................................................................38

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 5 M9999-102207-1.6

Receive Queue (RXQ) Frame Format........................................................................................................................................39

EEPROM Interf ace.......................................................................................................................................................40

Loopback Support ........................................................................................................................................................42

Near-end (Remote) Loopback....................................................................................................................................................42

CPU Interface I/O Registers ...............................................................................................................................................43

I/O Registers..............................................................................................................................................................................43

Internal I/O Space Mapping .......................................................................................................................................................44

Register Map: MAC and PHY .............................................................................................................................................52

Bit Type Definition ........................................................................................................................................................52

Bank 0-63 Bank Select Register (0x0E): BSR (same location in all Banks)................................................................52

Bank 0 Base Address Register (0x00): BAR................................................................................................................52

Bank 0 QMU RX Flow Control High Watermark Configuration Register (0x04): QRFCR ...........................................53

Bank 0 Bus Error Status Register (0x06): BESR .........................................................................................................53

Bank 0 Bus Burst Length Register (0x08): BBLR.........................................................................................................53

Bank 1: Reserved.........................................................................................................................................................53

Bank 2 Host MAC Address Register Low (0x00): MARL .............................................................................................54

Bank 2 Host MAC Address Register Middle (0x02): MARM........................................................................................54

Bank 2 Host MAC Address Register High (0x04): MARH............................................................................................54

Bank 3 On-Chip Bus Control Register (0x00): OBCR..................................................................................................55

Bank 3 EEPROM Control Register (0x02): EEPCR.....................................................................................................55

Bank 3 Memory BIST Info Register (0x04): MBIR........................................................................................................56

Bank 3 Global Reset Register (0x06): GRR.................................................................................................................56

Bank 3 Power Management Capabilities Register (0x08): PMCR...............................................................................56

Bank 3 Wakeup Frame Control Register (0x0A): WFCR.............................................................................................57

Bank 4 Wakeup Frame 0 CRC0 Register (0x00): WF0CRC0......................................................................................58

Bank 4 Wakeup Frame 0 CRC1 Register (0x02): WF0CRC1......................................................................................58

Bank 4 Wakeup Frame 0 Byte Mask 0 Register (0x04): WF0BM0..............................................................................58

Bank 4 Wakeup Frame 0 Byte Mask 1 Register (0x06): WF0BM1..............................................................................58

Bank 4 Wakeup Frame 0 Byte Mask 2 Register (0x08): WF0BM2..............................................................................58

Bank 4 Wakeup Frame 0 Byte Mask 3 Register (0x0A): WF0BM3..............................................................................59

Bank 5 Wakeup Frame 1 CRC0 Register (0x00): WF1CRC0......................................................................................59

Bank 5 Wakeup Frame 1 CRC1 Register (0x02): WF1CRC1......................................................................................59

Bank 5 Wakeup Frame 1 Byte Mask 0 Register (0x04): WF1BM0..............................................................................59

Bank 5 Wakeup Frame 1 Byte Mask 1 Register (0x06): WF1BM1..............................................................................59

Bank 5 Wakeup Frame 1 Byte Mask 2 Register (0x08): WF1BM2..............................................................................60

Bank 5 Wakeup Frame 1 Byte Mask 3 Register (0x0A): WF1BM3..............................................................................60

Bank 6 Wakeup Frame 2 CRC0 Register (0x00): WF2CRC0......................................................................................60

Bank 6 Wakeup Frame 2 CRC1 Register (0x02): WF2CRC1......................................................................................60

Bank 6 Wakeup Frame 2 Byte Mask 0 Register (0x04): WF2BM0..............................................................................60

Bank 6 Wakeup Frame 2 Byte Mask 1 Register (0x06): WF2BM1..............................................................................61

Bank 6 Wakeup Frame 2 Byte Mask 2 Register (0x08): WF2BM2..............................................................................61

Bank 6 Wakeup Frame 2 Byte Mask 3 Register (0x0A): WF2BM3..............................................................................61

Bank 7 Wakeup Frame 3 CRC0 Register (0x00): WF3CRC0......................................................................................61

Bank 7 Wakeup Frame 3 CRC1 Register (0x02): WF3CRC1......................................................................................61

Bank 7 Wakeup Frame 3 Byte Mask 0 Register (0x04): WF3BM0..............................................................................62

Bank 7 Wakeup Frame 3 Byte Mask 1 Register (0x06): WF3BM1..............................................................................62

Bank 7 Wakeup Frame 3 Byte Mask 2 Register (0x08): WF3BM2..............................................................................62

Bank 7 Wakeup Frame 3 Byte Mask 3 Register (0x0A): WF3BM3..............................................................................62

Bank 8 – 15: Reserved.................................................................................................................................................62

Bank 16 Transmit Control Register (0x00): TXCR.......................................................................................................63

Bank 16 Transmit Status Register (0x02): TXSR.........................................................................................................63

Bank 16 Receive Control Register (0x04): RXCR........................................................................................................64

Bank 16 TXQ Memory Information Register (0x08): TXMIR........................................................................................64

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 6 M9999-102207-1.6

Bank 16 RXQ Memory Information Register (0x0A): RXMIR.......................................................................................65

Bank 17 TXQ Command Register (0x00): TXQCR......................................................................................................65

Bank 17 RXQ Command Register (0x02): RXQCR.....................................................................................................65

Bank 17 TX Frame Data Pointer Register (0x04): TXFDPR........................................................................................66

Bank 17 RX Frame Data Pointer Register (0x06): RXFDPR.......................................................................................66

Bank 17 QMU Data Register Low (0x08): QDRL.........................................................................................................67

Bank 17 QMU Data Register High (0x0A): QDRH.......................................................................................................67

Bank 18 Interrupt Enable Register (0x00): IER............................................................................................................68

Bank 18 Interrupt Status Register (0x02): ISR.............................................................................................................69

Bank 18 Receive Status Register (0x04): RXSR .........................................................................................................70

Bank 18 Receive Byte Count Register (0x06): RXBC..................................................................................................70

Bank 18 Early Transmit Register (0x08): ETXR...........................................................................................................71

Bank 18 Early Receive Register (0x0A): ERXR...........................................................................................................71

Bank 19 Multicast Table Register 0 (0x00): MTR0.......................................................................................................71

Bank 19 Multicast Table Register 1 (0x02): MTR1.......................................................................................................72

Bank 19 Multicast Table Register 2 (0x04): MTR2.......................................................................................................72

Bank 19 Multicast Table Register 3 (0x06): MTR3.......................................................................................................72

Bank 19 Power Man agement Control and Status Register (0x08): PMCS..................................................................72

Banks 20 – 31: Reserved.............................................................................................................................................73

Bank 32 Chip ID and Enable Register (0x00): CIDER.................................................................................................73

Bank 32 Chip Global Control Register (0x0A): CGCR.................................................................................................74

Banks 33 – 41: Reserved.............................................................................................................................................74

Bank 42 Indirect Access Control Register (0x00): IACR..............................................................................................75

Bank 42 Indirect Access Data Register 1 (0x02): IADR1.............................................................................................75

Bank 42 Indirect Access Data Register 2 (0x04): IADR2.............................................................................................75

Bank 42 Indirect Access Data Register 3 (0x06): IADR3.............................................................................................75

Bank 42 Indirect Access Data Register 4 (0x08): IADR4.............................................................................................75

Bank 42 Indirect Access Data Register 5 (0x0A): IADR5 ............................................................................................75

Bank 43– 44: Reserved................................................................................................................................................75

Bank 45 PHY 1 MII-Register Basic Control Register (0x00): P1MBCR.......................................................................76

Bank 45 PHY 1 MII-Register Basic Status Register (0x02): P1MBSR.........................................................................77

Bank 45 PHY 1 PHYID Low Register (0x04): PH Y1IL R...............................................................................................77

Bank 45 PHY 1 PHYID High Register (0x06): PHY1IHR.............................................................................................78

Bank 45 PHY 1 Auto-N egot iation Advert isement Register (0x08): P1ANAR...............................................................78

Bank 45 PHY 1 Auto-N egot iat ion Li nk Partner Ability Register ( 0x0 A) : P1 ANL PR .....................................................78

Bank 46: Reserved.......................................................................................................................................................79

Bank 47 PHY1 LinkMD Control/Status (0x00): P1VCT................................................................................................79

Bank 47 PHY1 Special Control/Status Register (0x02): P1PHYCTRL........................................................................80

Bank 48: Reserved.......................................................................................................................................................80

Bank 49 Port 1 PHY Speci al Contro l/Status, LinkMD (0x00): P1SCSLMD .................................................................81

Bank 49 Port 1 Control Register 4 (0x02): P1CR4.......................................................................................................82

Bank 49 Port 1 Status Register (0x04): P1SR .............................................................................................................83

Banks 50 – 63: Reserved.............................................................................................................................................84

MIB (Management Information Base) Counters...............................................................................................................85

Additiona l MIB Information ...........................................................................................................................................86

Absolute Maximum Ratings(1) ............................................................................................................................................87

Operating Ratings(1) ............................................................................................................................................................87

Electrical Characteristics(1) ................................................................................................................................................88

Timing Specifications.........................................................................................................................................................89

Asynchronous Timing without using Address Strobe (ADSN = 0) ...............................................................................89

Asynchronous Timing using Address Strobe (ADSN)..................................................................................................90

Asynchronous Timing using DATACSN.......................................................................................................................91

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 7 M9999-102207-1.6

Address Latching Timing for All Modes......................................................................................................................................92

Synchronous Timing in Burst Write (VLBUSN = 1)....................................................................................................................93

Synchronous Timing in Burst Read (VLBUSN = 1)....................................................................................................................94

Synchronous Write Timing (VLBUSN = 0).................................................................................................................................95

Synchronous Read Timing (VLBUSN = 0).................................................................................................................................96

Auto Negotiation Timing.............................................................................................................................................................97

Reset Timing..............................................................................................................................................................................98

EEPROM Timing........................................................................................................................................................................99

Selection of Isolation Transformers................................................................................................................................100

Selection of Reference Crystal........................................................................................................................................100

Package Information.........................................................................................................................................................101

Acronyms and Glossary...................................................................................................................................................104

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 8 M9999-102207-1.6

List of Figures

Figure 1. KSZ8841M Func tiona l Diagram...............................................................................................................................1

Figure 2. Standard – KSZ8 841-16 MQ L 128- Pin PQFP........................................................................................................10

Figure 3. Option – KSZ8841-16MVL 128-Pin LQFP.............................................................................................................10

Figure 4. KSZ8841- 16MBL 100-Ball LFBGA (Top View)......................................................................................................11

Figure 5. Standard – KSZ8 841-32 MQ L 128- Pin PQFP........................................................................................................21

Figure 6. Option – KSZ8841-32MVL 128-Pin LQFP.............................................................................................................21

Figure 7. Typica l Stra ight C abl e Connec t ion ........................................................................................................................30

Figure 8. Typical Crossover Cable Connection ....................................................................................................................30

Figure 9. Auto Negotiati on and Par a ll el Operation ...............................................................................................................31

Figure 10. Mapping fr om the ISA, EISA, and VLBus to the KSZ8 841 M Bus Interf ace .........................................................37

Figure 11. KSZ8841M 8- B it, 16-B it, and 32-Bit Data Bus Connections................................................................................37

Figure 12. PHY Por t 1 Near-end (Remote) Loopback Path..................................................................................................42

Figure 13. Asynchrono us Cycle – ADSN = 0........................................................................................................................89

Figure 14. Asynchrono us Cycle – Using ADSN....................................................................................................................90

Figure 15. Asynchrono us Cycle – Using DAT ACSN .............................................................................................................91

Figure 16. Address Latching Cycle for All Modes.................................................................................................................92

Figure 17. Synchronous Burs t W rite Cycles – VLBUSN = 1.................................................................................................93

Figure 18. S ynchronous Bu rs t Read Cycles – VLBUSN = 1 ................................................................................................94

Figure 19. Synchronous Write Cycle – VLBUSN = 0............................................................................................................95

Figure 20. Synchronous Read C ycle – VLBUSN = 0............................................................................................................96

Figure 21. Auto Negotiat ion Tim ing.......................................................................................................................................97

Figure 22. Reset Tim ing........................................................................................................................................................98

Figure 23. EEPROM Read Cycle Timing Diagram..............................................................................................................99

Figure 24. 128-Pi n PQFP Package.....................................................................................................................................101

Figure 25. Optional 128-Pin LQFP Package.......................................................................................................................102

Figure 26. Optional 100-Ball LFBGA Package ...................................................................................................................103

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 9 M9999-102207-1.6

List of Tables

Table 1. MDI/MDI-X Pin Definitions ......................................................................................................................................30

Table 2. Bus Interface Unit Signal Groupin g.........................................................................................................................35

Table 3. Frame Format for Transmit Queue.........................................................................................................................38

Table 4. Transmit Control Wo rd Bit Fields............................................................................................................................38

Table 5. Transmit Byte Count Format...................................................................................................................................39

Table 6. Frame Format for Receive Queue..........................................................................................................................39

Table 7. RXQ Receive Packet Status Word .........................................................................................................................40

Table 8. RXQ Receive Packet Byte Count Word..................................................................................................................40

Table 9. KSZ8841M EEPROM Format.................................................................................................................................40

Table 10. ConfigParam Word in EEPROM Format...............................................................................................................41

Table 11. Format of MIB Counters........................................................................................................................................85

Table 12. Port 1 MIB Counters Indirect Memory Offsets......................................................................................................86

Table 13. Maximum Ratings .................................................................................................................................................87

Table 14. Operating Ratings.................................................................................................................................................87

Table 15. Electrical Characteristics.......................................................................................................................................88

Table 16. Asynchronous Cycle (ADSN = 0) Timing Parameters..........................................................................................89

Table 17. Asynchronous Cycle using ADSN Timing Parameters.........................................................................................90

Table 18. Asynchronous Cycle using DATACSN Timing Parameters..................................................................................91

Table 19. Address Latching Timing Parameters...................................................................................................................92

Table 20. Synchronous Burst Write Timing Parameters.......................................................................................................93

Table 21. Synchronous Burst Read Timing Parameters ......................................................................................................94

Table 22. Synchronous Wri te (VLBUSN = 0) Timing Parameters........................................................................................95

Table 23. Synchronous Read (VLBUSN = 0) Timing Parameters........................................................................................96

Table 24. Auto Negotiation Tim ing Param eters....................................................................................................................97

Table 25. Reset Timing Parameters .....................................................................................................................................98

Table 26. EEPROM Timing Parameters..............................................................................................................................99

Table 27. Transformer Selection Criteria............................................................................................................................100

Table 28. Qualified Single Port Magn etic s..........................................................................................................................100

Table 29. Typical Reference Crystal Characteristics..........................................................................................................100

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 10 M9999-102207-1.6

Pin Configuration for KSZ8841-16 Chip (8/16-Bit)

P1LED2

P1LED1

P1LED0

DGND

VDDIO

RDYRTNN

ARDY

VLBUSN

EESK

SWR

WRN

DGND

PWRDN

AGND

VDDA

103

BCLK

PMEN

SRDYN

INTRN

LDEVN

RDN

EECS

CYCLEN

DGND

VDDCO

EEEN

P1LED3

EEDO

EEDI

AEN

ADSN

VDDA

ISET

AGND

RXP1

RXM1

AGND

TXP1

TXM1

VDDATX

VDDARX

AGND

VDDA

AGND

VDDAP

A10

A12

A14

A15

RSTN

VDDC

DGND

BE0N

BE1N

VDDIO

DGND

A11

A13

102

101

100

SCANEN

TESTEN

VDDIO

DGND

D10

D11

D12

D13

D14

D15

VDDIO

DGND

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

KSZ8841-16

MQL

AGND

(Top View )

VDDIO

DGND

Figure 2. Standard – KSZ8841-16MQL 128-Pin PQFP

P1LED2

P1LED1

P1LED0

DGND

VDDIO

RDYRTNN

ARDY

VLBUSN

EESK

SWR

WRN

DGND

PWRDN

AGND

VDDA

103

BCLK

PMEN

SRDYN

INTRN

LDEVN

RDN

EECS

CYCLEN

DGND

VDDCO

EEEN

P1LED3

EEDO

EEDI

AEN

ADSN

VDDA

ISET

AGND

RXP1

RXM1

AGND

TXP1

TXM1

VDDATX

VDDARX

AGND

VDDA

AGND

VDDAP

A10

A12

A14

A15

RSTN

VDDC

DGND

BE0N

BE1N

VDDIO

DGND

A11

A13

102

101

100

SCANEN

TESTEN

VDDIO

DGND

D10

D11

D12

D13

D14

D15

VDDIO

DGND

NC 104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

KSZ8841-16

MVL

AGND

(Top View)

DGND

VDDIO

Figure 3. Option – KSZ8841-16MVL 128-Pin LQFP

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 11 M9999-102207-1.6

Ball Configuration for KSZ8841-16 Chip (8/16-Bit)

Figure 4. KSZ8841-16MBL 100-Ball LFBGA (Top View)

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 12 M9999-102207-1.6

Pin Description for KSZ8841-16 Chip (8/16-Bit)

Pin Number Pin Name Type Pin Function

1 TEST_EN I Test Enable

For normal operation, pull-down this pin-to-ground.

2 SCAN_EN I Scan Test Scan Mux Enable

For normal operation, pull-down this pin-to-ground.

3 P1LED2 Opu

4 P1LED1 Opu

5 P1LED0 Opu

Port 1 LED indicators1 def ine d as follows:

Chip Global Control Register: CGCR

bit [15,9]

[0,0] Default [0,1]

P1LED32 — —

P1LED2 Link/Act 100Link/Act

P1LED1 Full duplex/Col 10Link/Act

P1LED0 Speed Full duplex

Reg. CGCR bit [15,9]

[1,0] [1,1]

P1LED32 Act —

P1LED2 Link —

P1LED1 Full duplex/Col —

P1LED0 Speed —

Notes:

1. Link = On; Activity = Blink; Link/Act = On/Blink; Full Dup/Col = On/Blink;

Full Duplex = On (Full duplex); Off (Half duplex)

Speed = On (100BASE-T); Off (10BASE-T)

2. P1LED3 is pin 27.

6 NC Opu No Connect.

7 NC Opu No Connect.

8 NC Opu No Connect.

9 DGND Gnd Digital ground

10 VDDIO P 3.3V digital VDDIO input power supply for IO with well decoupling capacitors.

11 RDYRTNN Ipd Ready Return Not:

For VLBus-like mode: Asserted by the host to complete synchronous read cycles. If the

host doesn’t connect to this pin, assert this pin.

For burst mode (32-bit interface only): Host drives this pin low to signal waiting states.

12 BCLK Ipd Bus Interface Clock

Local bus clock for synchronous bus systems. Maximum frequency is 50MHz.

This pin should be tied Low or unconnected if it is in asynchronous mode.

13 NC Ipu No Connect.

14 PMEN Opu Power Management Event Not

When asserted (Low), this signal indicates that a power management event has occurred

in the system when a wake-up signal is detected by KSZ8841M.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 13 M9999-102207-1.6

Pin Number Pin Name Type Pin Function

15 SRDYN Opu Synchronous Ready Not

Ready signal to interface with synchronous bus for both EISA-like and VLBus-like extend

accesses.

For VLBus-like mode, the falling edge of this signal indicates ready. This signal is

synchronous to the bus clock signal BCLK.

For burst mode (32-bit interface only), the KSZ8841M drives this pin low to signal wait

states.

16 INTRN Opd Interrupt

Active Low signal to host CPU to indicate an interrupt status bit is set, this pin need an

external 4.7K pull-up resistor.

17 LDEVN Opd Local Device Not

Active Low output signal, asserted when AEN is Low and A15-A4 decode to the

KSZ8841M address programmed into the high byte of the base address register. LDEVN

is a combinational decode of the Address and AEN signal.

18 RDN Ipd Read Strobe Not

Asynchronous read strobe, active Low.

19 EECS Opu EEPROM Chip Select

This signal is used to select an external EEPROM device.

20 ARDY Opd Asynchronous Ready

ARDY may be used when interfacing asynchronous buses to extend bus access cycles. It

is asynchronous to the host CPU or bus clock. this pin need an external 4.7K pull-up

resistor.

21 CYCLEN Ipd Cycle Not

For VLBus-like mode cycle signal; this pin follows the addressing cycle to signal the

command cycle.

For burst mode (32-bit interface only), this pin stays High for read cycles and Low for write

cycles.

22 NC Opd No Connect

23 DGND Gnd Digital IO ground

24 VDDCO P 1.2V digital core voltage output (internal 1.2V LDO power suppl y output), this 1.2V output

pin provides power to VDDC, VDDA and VDDAP pins. It is recommended this pin should

be connected to 3.3V power rail by a 100 ohm resistor for the internal LDO application

Note: Internally generated power voltage. Do not connect an external power supply to this

pin. This pin is used for connecting external filter (Ferrite bead and capacitors).

25 VLBUSN Ipd VLBus-like Mode

Pull-down or float: Bus interface is configured for synchronous mode.

Pull-up: Bus interface is configured for 8-bit or 16-bit asynchronous mode or EISA-like

burst mode.

26 EEEN Ipd EEPROM Enable

EEPROM is enabled and connected when this pin is pull-up.

EEPROM is disabled when this pin is pull-down or no connect.

27 P1LED3 Opd Port 1 LED indicator

See the description in pins 3, 4, and 5.

28 EEDO Opd EEPROM Data Out

This pin is connected to DI input of the serial EEPROM.

29 EESK Opd EEPROM Serial Clock

A 4µs (OBCR[1:0]=11 on-chip bus spe ed @ 25 MHz) or 800 ns (OBCR[1:0]=00 on-chip

bus speed @ 125 MHz) serial output clock cycle to load configuration data from the serial

EEPROM.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 14 M9999-102207-1.6

Pin Number Pin Name Type Pin Function

30 EEDI Ipd EEPROM Data In

This pin is connected to DO output of the serial EEPROM when EEEN is pull-up.

This pin can be pull-down for 8-bit bus mode, pull-up for 16-bus mode or don’t care for 32-

bus mode when EEEN is pull-down (without EEPROM).

31 SWR Ipd Synchronous Write/Read

Write/Read signal for synchronous bus accesses. Write cycles when high and Read

cycles when low.

32 AEN Ipu Address Enable

Address qualifier for the address decoding, active Low.

33 WRN Ipd Write Strobe Not

Asynchronous write strobe, active Low.

34 DGND Gnd Digital IO ground

35 ADSN Ipd Address Strobe Not

For systems that require address latching, the rising edge of ADSN indicates the latching

moment of A15-A1 and AEN.

36 PWRDN Ipu Full-chip power-down. Active Low (Low = Power down; High or floating = Normal

operation).

37 AGND Gnd Analog ground

38 VDDA P 1.2V analog VDD input power supply from VDDCO (pin24) through external Ferrite bead

and capacit or.

39 AGND Gnd Analog ground

40 NC — No Connect

41 NC — No Connect

42 AGND Gnd Analog ground

43 VDDA P 1.2V analog VDD input power supply from VDDCO (pin24) through external Ferrite bead

and capacit or.

44 NC — No Connect

45 RXP1 I/O Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential)

46 RXM1 I/O Port 1 physical receive (MDI) or transmit (MDIX) signal (– differential)

47 AGND Gnd Analog ground

48 TXP1 I/O Port 1 physical transmit (MDI) or receive (MDIX) signal (+ differential)

49 TXM1 I/O Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential)

50 VDDATX P 3.3V analog VDD input power supply with well decoupling capacitors.

51 VDDARX P 3.3V analog VDD input power supply with well decoupling capacitors.

52 NC — No Connect

53 NC — No Connect

54 AGND Gnd Analog ground

55 NC — No Connect

56 NC — No Connect

57 VDDA P 1.2 analog VDD input power supply from VDDCO (pin24) through external Ferrite bead and

capacitor.

58 AGND Gnd Analog ground

59 NC Ipu No connect

60 NC Ipu No connect

61 ISET O Set physical transmits output current.

Pull-down this pin with a 3.01K 1% resistor to ground.

62 AGND Gnd Analog ground

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 15 M9999-102207-1.6

Pin Number Pin Name Type Pin Function

63 VDDAP P 1.2V analog VDD for PLL input power supply from VDDCO (pin24) through external Ferrite

bead and capacitor.

64 AGND Gnd Analog ground

65 X1 I

66 X2 O

25MHz crystal or oscillator clock connection.

Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant

oscillator and X2 is a no connect.

Note: Clock requirement is  50ppm for either crystal or oscillator.

67 RSTN Ipu Reset Not

Hardware reset pin (active Low). This reset input is required minimum of 10ms low after

stable supply voltage 3.3V.

68 A15 I Address 15

69 A14 I Address 14

70 A13 I Address 13

71 A12 I Address 12

72 A11 I Address 11

73 A10 I Address 10

74 A9 I Address 9

75 A8 I Address 8

76 A7 I Address 7

77 A6 I Address 6

78 DGND Gnd Digital IO ground

79 VDDIO P 3.3V digital VDDIO input power supply for IO with well decoupling capacitors.

80 A5 I Address 5

81 A4 I Address 4

82 A3 I Address 3

83 A2 I Address 2

84 A1 I Address 1

85 NC I No Connect

86 NC I No Connect

87 BE1N I Byte Enable 1 Not, Active low for Data byte 1 enable (don’t care in 8-bit bus mode).

88 BE0N I Byte Enable 0 Not, Active low for Data byte 0 enable (there is an internal inverter enabled

and connected to the BE1N for 8-bit bus mode).

89 NC I No Connect

90 DGND Gnd Digital core ground

91 VDDC P

1.2V digital core VDD input power supply from VDDCO (pin24) through external Ferrite

bead and capacitor.

92 VDDIO P 3.3V digital VDDIO input power supply for IO with well decoupling capacitors.

93 NC I No Connect

94 NC I No Connect

95 NC I No Connect

96 NC I No Connect

97 NC I No Connect

98 NC I No Connect

99 NC I No Connect

100 NC I No Connect

101 NC I No Connect

102 NC I No Connect

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 16 M9999-102207-1.6

Pin Number Pin Name Type Pin Function

103 NC I No Connect

104 NC I No Connect

105 NC I No Connect

106 NC I No Connect

107 DGND Gnd Digital IO ground

108 VDDIO P

3.3V digital VDDIO input power supply for IO with well decoupling capacitors.

109 NC I No Connect

110 D15 I/O Data 15

111 D14 I/O Data 14

112 D13 I/O Data 13

113 D12 I/O Data 12

114 D11 I/O Data 11

115 D10 I/O Data 10

116 D9 I/O Data 9

117 D8 I/O Data 8

118 D7 I/O Data 7

119 D6 I/O Data 6

120 D5 I/O Data 5

121 D4 I/O Data 4

122 D3 I/O Data 3

123 DGND Gnd Digital IO ground

124 DGND Gnd Digital core ground

125 VDDIO P 3.3V digital VDDIO input power supply for IO with well decoupling capacitors.

126 D2 I/O Data 2

127 D1 I/O Data 1

128 D0 I/O Data 0

Legend:

P = Power supply Gnd = Ground

I/O = Bi-directional I = Input O = Output.

Ipd = Input with internal pull-down.

Ipu = Input with internal pull-up.

Opd = Output with internal pull-down.

Opu = Output with internal pull-up.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 17 M9999-102207-1.6

Ball Description for KSZ8841-16 Chip (8/16-Bit)

Ball Number Ball Name Type Ball Function

E8 TEST_EN I

Test Enable

For normal operation, pull-down this ball to ground.

D10 SCAN_EN I

Scan Test Scan Mux Enable

For normal operation, pull-down this ball to ground.

A10 P1LED2 Opu

B10 P1LED1 Opu

C10 P1LED0 Opu

Port 1 LED indicators1 def ine d as follows:

Switch Global Control Register 5:

SGCR5 bit [15,9]

[0,0] Default [0,1]

P1LED32 — —

P1LED2 Link/Act 100Link/Act

P1LED1 Full duplex/Col 10Link/Act

P1LED0 Speed Full duplex

Reg. SGCR5 bit [15,9]

[1,0] [1,1]

P1LED32 Act —

P1LED2 Link —

P1LED1 Full duplex/Col —

P1LED0 Speed —

Notes:

1. Link = On; Activity = Blink; Link/Act = On/Blink; Full Dup/Col = On/Blink;

Full Duplex = On (Full duplex); Off (Half duplex)

Speed = On (100BASE-T); Off (10BASE-T)

2. P1LED3 is ball A4.

D9 RDYRTNN Ipd

Ready Return Not:

For VLBus-like mode: Asserted by the host to complete synchronous read

cycles. If the host doesn’t connect to this ball, assert this ball.

A8 BCLK Ipd

Bus Interface Clock

Local bus clock for synchronous bus systems. Maximum frequency is 50MHz.

This ball should be tied Low or unconnected if it is in asynchronous mode.

D8 PMEN Opu

Power Management Event Not

When asserted (Low), this signal indicates that a power management event has

occurred in the system when a wake-up signal is detected by KSZ8841M.

B8 SRDYN Opu Synchronous Ready Not

Ready signal to interface with synchronous bus for both EISA-like and VLBus-

like extend accesses.

For VLBus-like mode, the falling edge of this signal indicates ready. This signal

is synchronous to the bus clock signal BCLK.

C8 INTRN Opd Interrupt

Active Low signal to host CPU to indicate an interrupt status bit is set, this ball

need an external 4.7K pull-up resi stor.

A7 LDEVN Opd Local Device Not

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 18 M9999-102207-1.6

Ball Number Ball Name Type Ball Function

Active Low output signal, asserted when AEN is Low and A15-A4 decode to the

KSZ8841M address programmed into the high byte of the base address register.

LDEVN is a combinational decode of the Address and AEN signal.

B7 RDN Ipd Read Strobe Not

Asynchronous read strobe, active Low.

C7 EECS Opu EEPROM Chip Select

A6 ARDY Opd Asynchronous Ready

ARDY may be used when interfacing asynchronous buses to extend bus access

cycles. It is asynchronous to the host CPU or bus clock. This ball needs an

external 4.7K pull-up resistor.

B6 CYCLEN Ipd

Cycle Not

For VLBus-like mode cycle signal; this ball follows the addressing cycle to signal

the command cycle.

For burst mode (32-bit interface only), this ball stays High for read cycles and

Low for write cycles.

A5 VLBUSN Ipd VLBus-like Mode

Pull-down or float: Bus interface is configured for synchronous mode.

Pull-up: Bus interface is configured for 8-bit or 16-bit asynchronous mode or

EISA-like burst mode.

B5 EEEN Ipd EEPROM Enable

EEPROM is enabled and connected when this ball is pull-up.

EEPROM is disabled when this ball is pull-down or no connect.

A4 P1LED3 Opd Port 1 LED indicator

See the description in balls A10, B10, and C10.

B4 EEDO Opd EEPROM Data Out

This ball is connected to DI input of the serial EEPROM.

A3 EESK Opd

EEPROM Serial Clock

A 4µs (OBCR[1:0]=11 on-chip bus speed @ 25 MHz) or 800 ns (OBCR[1:0]=00

on-chip bus speed @ 125 MHz) serial output clock cycle to load configuration

data from the serial EEPROM.

B3 EEDI Ipd

EEPROM Data In

This ball is connected to DO output of the serial EEPROM when EEEN is pull-

up.

This ball can be pull-down for 8-bit bus mode, pull-up for 16-bit bus mode or

don’t care for 32-bit bus mode when EEEN is pull-down (without EEPROM).

C3 SWR Ipd Synchronous Write/Read

Write/Read signal for synchronous bus accesses. Write cycles when high and

Read cycles when low.

A2 AEN Ipu Address Enable

Address qualifier for the address decoding, active Low.

B2 WRN Ipd Write Strobe Not

Asynchronous write strobe, active Low.

A1 ADSN Ipd

Address Strobe Not

For systems that require address latching, the rising edge of ADSN indicates the

latching moment of A15-A1 and AEN.

B1 PWRDN Ipu Full-chip power-down. Low = Power down; High or floating = Normal operation.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 19 M9999-102207-1.6

Ball Number Ball Name Type Ball Function

C1 RXP1 I/O Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential)

C2 RXM1 I/O Port 1 physical receive (MDI) or transmit (MDIX) signal (– differential)

D1 TXP1 I/O Port 1 physical transmit (MDI) or receive (MDIX) signal (+ differential)

D2 TXM1 I/O Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential)

H2 TEST2 Ipu

Test input 2

For normal operation, left this ball open.

G3 ISET O Set physical transmits output current.

Pull-down this ball with a 3.01K 1% resistor to ground.

J1 X1 I

K1 X2 O

25MHz crystal or oscillator clock connection.

Balls (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V

tolerant oscillator and X2 is a no connect.

Note: Clock requirement is ± 50ppm for either crystal or oscillator.

J2 RSTN Ipu Hardware reset ball (active Low). This reset input is required minimum of 10ms

low after stable supply voltage 3.3V.

K2 A15 I Address 15

K3 A14 I Address 14

J3 A13 I Address 13

H3 A12 I Address 12

K4 A11 I Address 11

J4 A10 I Address 10

H4 A9 I Address 9

K5 A8 I Address 8

J5 A7 I Address 7

H5 A6 I Address 6

K6 A5 I Address 5

J6 A4 I Address 4

H6 A3 I Address 3

K7 A2 I Address 2

J7 A1 I Address 1

H7 BE1N I Byte Enable 1 Not, Active low for Data byte 1 enable (don’t care in 8-bit bus

mode).

K8 BE0N I Byte Enable 0 Not, Active low for Data byte 0 enable (there is an internal inverter

enabled and conne cted to the BE1N for 8-bit bus mode).

K9 D15 I/O Data 15

K10 D14 I/O Data 14

J9 D13 I/O Data 13

J10 D12 I/O Data 12

J8 D11 I/O Data 11

H9 D10 I/O Data 10

H10 D9 I/O Data 9

H8 D8 I/O Data 8

G9 D7 I/O Data 7

G10 D6 I/O Data 6

G8 D5 I/O Data 5

F9 D4 I/O Data 4

F10 D3 I/O Data 3

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 20 M9999-102207-1.6

Ball Number Ball Name Type Ball Function

F8 D2 I/O Data 2

E9 D1 I/O Data 1

E10 D0 I/O Data 0

C4 VDDCO P

1.2V digital core voltage output (internal 1.2V LDO power supply output), this

1.2V output ball provides power to all VDDC/VDDA balls. It is recommended this

ball should be connected to 3.3V power rail by a 100 ohm resistor for the internal

LDO application.

Note: Internally generated power voltage. Do not connect an external power

supply to this ball. This ball is used for connecting external filter (Ferrite bead

and capacit ors).

C5 VDDC P

1.2V digital core VDD input power supply from VDDCO (ball C4) through external

Ferrite bead and capacitor.

D3, E3, F3 VDDA P 1.2V analog VDD input power supply from VDDCO (ball C4) through external

Ferrite bead and capacitor.

E1 VDDATX P 3.3V analog VDD input power supply with well decoupling capacitors.

E2 VDDARX P 3.3V analog VDD input power supply with well decoupling capacitors.

D7, E7, F7,

G4, G5, G6,

VDDIO P

3.3V digital VDDIO input power supply for IO with well decoupling capacitors.

D4, D5, D6,

E4, E5, E6,

F4, F5, F6

GND Gnd All digital and analog grounds

H1, A9, B9,

C9, C6, F2,

F1, G2, G1

NC I/O No Connect

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 21 M9999-102207-1.6

Pin Configuration for KSZ8841-32 Chip (32-Bit)

P1LED2

P1LED1

P1LED0

DGND

VDDIO

RDYRTNN

ARDY

VLBUSN

EESK

SWR

WRN

DGND

PWRDN

AGND

VDDA

103

BCLK

DATACSN

PMEN

SRDYN

INTRN

LDEVN

RDN

EECS

CYCLEN

DGND

VDDCO

EEEN

P1LED3

EEDO

EEDI

AEN

ADSN

VDDA

ISET

AGND

RXP1

RXM1

AGND

TXP1

TXM1

VDDATX

VDDARX

AGND

VDDA

AGND

VDDAP

D21

D22

D23

D24

D25

D26

D28

D27

BE2N

A10

A12

A14

A15

RSTN

D29

D30

VDDC

DGND

D31

BE0N

BE1N

BE3N

VDDIO

DGND

A11

A13

102

101

100

SCANEN

D17

TESTEN

VDDIO

DGND

D10

D11

D12

D13

D14

D15

D16

VDDIO

DGND

D18

D19 104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

KSZ8841-32

MQL

AGND

(Top View )

VDDIO

DGND

D20

Figure 5. Standard – KSZ8841-32MQL 128-Pin PQFP

P1LED2

P1LED1

P1LED0

DGND

VDDIO

RDYRTNN

ARDY

VLBUSN

EESK

SWR

WRN

DGND

PWRDN

AGND

VDDA

103

BCLK

DATACSN

PMEN

SRDYN

INTRN

LDEVN

RDN

EECS

CYCLEN

DGND

VDDCO

EEEN

P1LED3

EEDO

EEDI

AEN

ADSN

VDDA

ISET

AGND

RXP1

RXM1

AGND

TXP1

TXM1

VDDATX

VDDARX

AGND

VDDA

AGND

VDDAP

D20

D21

D22

D23

D24

D25

D26

D28

D27

BE2N

A10

A12

A14

A15

RSTN

D29

D30

VDDC

DGND

D31

BE0N

BE1N

BE3N

VDDIO

DGND

A11

A13

102

101

100

SCANEN

D17

TESTEN

VDDIO

DGND

D10

D11

D12

D13

D14

D15

D16

VDDIO

DGND

D18

D19 104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

KSZ8841-32

MVL

AGND

(Top View)

DGND

VDDIO

Figure 6. Option – KSZ8841-32MVL 128-Pin LQFP

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 22 M9999-102207-1.6

Pin Description for KSZ8841-32 Chip (32-Bit)

Pin Number Pin Name Type Pin Function

1 TEST_EN I Test Enable

For normal operation, pull-down this pin-to-ground.

2 SCAN_EN I Scan Test Scan Mux Enable

For normal operation, pull-down this pin-to-ground.

3 P1LED2 Opu

4 P1LED1 Opu

5 P1LED0 Opu

Port 1 LED indicators1 def ine d as follows:

Chip Global Control Register: CGCR

bit [15,9]

[0,0] Default [0,1]

P1LED32 — —

P1LED2 Link/Act 100Link/Act

P1LED1 Full duplex/Col 10Link/Act

P1LED0 Speed Full duplex

Reg. CGCR bit [15,9]

[1,0] [1,1]

P1LED32 Act —

P1LED2 Link —

P1LED1 Full duplex/Col —

P1LED0 Speed —

Notes:

1. Link = On; Activity = Blink; Link/Act = On/Blink; Full Dup/Col = On/Blink;

Full Duplex = On (Full duplex); Off (Half duplex)

Speed = On (100BASE-T); Off (10BASE-T)

2. P1LED3 is pin 27.

6 NC Opu No Connect.

7 NC Opu No Connect.

8 NC Opu No Connect.

9 DGND Gnd Digital ground

10 VDDIO P 3.3V digital VDDIO input power supply for IO with well decoupling capacitors.

11 RDYRTNN Ipd Ready Return Not:

For VLBus-like mode: Asserted by the host to complete synchronous read cycles. If the

host doesn’t connect to this pin, assert this pin.

For burst mode (32-bit interface only): Host drives this pin low to signal waiting states.

12 BCLK Ipd Bus Interface Clock

Local bus clock for synchronous bus systems. Maximum frequency is 50MHz.

This pin should be tied Low or unconnected if it is in asynchronous mode.

13 DATACSN Ipu DATA Chip Select Not (For KSZ8841-32 Mode only)

Chip select signal for QMU data register (QDRH, QDRL), active Low.

When DATACSN is Low, the data path can be accessed regardless of the value of AEN,

A15-A1, and the content of the BANK select register.

14 PMEN Opu Power Management Event Not

When asserted (Low), this signal indicates that a power management event has occurred

in the system when a wake-up signal is detected by KSZ8841M.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 23 M9999-102207-1.6

Pin Number Pin Name Type Pin Function

15 SRDYN Opu Synchronous Ready Not

Ready signal to interface with synchronous bus for both EISA-like and VLBus-like extend

accesses.

For VLBus-like mode, the falling edge of this signal indicates ready. This signal is

synchronous to the bus clock signal BCLK.

For burst mode (32-bit interface only), the KSZ8841M drives this pin low to signal wait

states.

16 INTRN Opd Interrupt

Active Low signal to host CPU to indicate an interrupt status bit is set, this pin need an

external 4.7K pull-up resistor

17 LDEVN Opd Local Device Not

Active Low output signal, asserted when AEN is Low and A15-A4 decode to the

KSZ8841M address programmed into the high byte of the base address register. LDEVN

is a combinational decode of the Address and AEN signal.

18 RDN Ipd Read Strobe Not

Asynchronous read strobe, active Low.

19 EECS Opu EEPROM Chip Select

This signal is used to select an external EEPROM device.

20 ARDY Opd Asynchronous Ready

ARDY may be used when interfacing asynchronous buses to extend bus access cycles. It

is asynchronous to the host CPU or bus clock. this pin need an external 4.7K pull-up

resistor.

21 CYCLEN Ipd Cycle Not

For VLBus-like mode cycle signal; this pin follows the addressing cycle to signal the

command cycle.

For burst mode (32-bit interface only), this pin stays High for read cycles and Low for write

cycles.

22 NC Opd No Connect

23 DGND Gnd Digital IO ground

24 VDDCO P 1.2V digital core voltage output (internal 1.2V LDO power suppl y output), this 1.2V output

pin provides power to VDDC, VDDA and VDDAP pins. It is recommended this ball should

be connected to 3.3V power rail by a 100 ohm resistor for the internal LDO application.

Note: Internally generated power voltage. Do not connect an external power supply to this

pin. This pin is used for connecting external filter (Ferrite bead and capacitors).

25 VLBUSN Ipd VLBus-like Mode

Pull-down or float: Bus interface is configured for synchronous mode.

Pull-up: Bus interface is configured for 32-bit asynchronous mode or EISA-like burst

mode.

26 EEEN Ipd EEPROM Enable

EEPROM is enabled and connected when this pin is pull-up.

EEPROM is disabled when this pin is pull-down or no connect.

27 P1LED3 Opd Port 1 LED indicator

See the description in pins 3, 4, and 5.

28 EEDO Opd EEPROM Data Out

This pin is connected to DI input of the serial EEPROM.

29 EESK Opd EEPROM Serial Clock

A 4µs (OBCR[1:0]=11 on-chip bus spe ed @ 25 MHz) or 800 ns (OBCR[1:0]=00 on-chip

bus speed @ 125 MHz) serial output clock cycle to load configuration data from the serial

EEPROM.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 24 M9999-102207-1.6

Pin Number Pin Name Type Pin Function

30 EEDI Ipd EEPROM Data In

This pin is connected to DO output of the serial EEPROM when EEEN is pull-up.

This pin can be pull-down for 8-bit bus mode, pull-up for 16-bus mode or don’t care for 32-

bus mode when EEEN is pull-down (without EEPROM).

31 SWR Ipd Synchronous Write/Read

Write/Read signal for synchronous bus accesses. Write cycles when high and Read

cycles when low.

32 AEN Ipu Address Enable

Address qualifier for the address decoding, active Low.

33 WRN Ipd Write Strobe Not

Asynchronous write strobe, active Low.

34 DGND Gnd Digital IO ground

35 ADSN Ipd Address Strobe Not

For systems that require address latching, the rising edge of ADSN indicates the latching

moment of A15-A1 and AEN.

36 PWRDN Ipu Fu ll-chip power-down. Active Low (Low = Power down; High or floating = Normal

operation).

37 AGND Gnd Analog ground

38 VDDA P 1.2V analog VDD input power supply from VDDCO (pin24) through external Ferrite bead

and capacit or.

39 AGND Gnd Analog ground

40 NC — No Connect

41 NC — No Connect

42 AGND Gnd Analog ground

43 VDDA P 1.2V analog VDD input power supply from VDDCO (pin24) through external Ferrite bead

and capacit or.

44 NC — No Connect

45 RXP1 I/O Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential)

46 RXM1 I/O Port 1 physical receive (MDI) or transmit (MDIX) signal (– differential)

47 AGND Gnd Analog ground

48 TXP1 I/O Port 1 physical transmit (MDI) or receive (MDIX) signal (+ differential)

49 TXM1 I/O Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential)

50 VDDATX P 3.3V analog VDD input power supply with well decoupling capacitors.

51 VDDARX P 3.3V analog VDD input power supply with well decoupling capacitors.

52 NC — No Connect

53 NC — No Connect

54 AGND Gnd Analog ground

55 NC — No Connect

56 NC — No Connect

57 VDDA P 1.2 analog VDD input power supply from VDDCO (pin24) through external Ferrite bead and

capacitor.

58 AGND Gnd Analog ground

59 NC Ipu No connect

60 NC Ipu No connect

61 ISET O Set physical transmits output current.

Pull-down this pin with a 3.01K 1% resistor to ground.

62 AGND Gnd Analog ground

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 25 M9999-102207-1.6

Pin Number Pin Name Type Pin Function

63 VDDAP P 1.2V analog VDD for PLL input power supply from VDDCO (pin24) through external Ferrite

bead and capacitor.

64 AGND Gnd Analog ground

65 X1 I

66 X2 O

25MHz crystal or oscillator clock connection.

Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant

oscillator and X2 is a no connect.

Note: Clock requirement is  50ppm for either crystal or oscillator.

67 RSTN Ipu Reset Not

Hardware reset pin (active Low). This reset input is required minimum of 10ms low after

stable supply voltage 3.3V.

68 A15 I Address 15

69 A14 I Address 14

70 A13 I Address 13

71 A12 I Address 12

72 A11 I Address 11

73 A10 I Address 10

74 A9 I Address 9

75 A8 I Address 8

76 A7 I Address 7

77 A6 I Address 6

78 DGND Gnd Digital IO ground

79 VDDIO P 3.3V digital VDDIO input power supply for IO with well decoupling capacitors.

80 A5 I Address 5

81 A4 I Address 4

82 A3 I Address 3

83 A2 I Address 2

84 A1 I Address 1

85 BE3N I Byte Enable 3 Not, Active low for Data byte 3 enable

86 BE2N I Byte Enable 2 Not, Active low for Data byte 2 enable

87 BE1N I Byte Enable 1 Not, Active low for Data byte 1 enable

88 BE0N I Byte Enable 0 Not, Active low for Data byte 0 enable

89 D31 I/O Data 31

90 DGND Gnd Digital core ground

91 VDDC P

1.2V digital core VDD input power supply from VDDCO (pin24) through external Ferrite

bead and capacitor.

92 VDDIO P 3.3V digital VDDIO input power supply for IO with well decoupling capacitors.

93 D30 I/O Data 30

94 D29 I/O Data 29

95 D28 I/O Data 28

96 D27 I/O Data 27

97 D26 I/O Data 26

98 D25 I/O Data 25

99 D24 I/O Data 24

100 D23 I/O Data 23

101 D22 I/O Data 22

102 D21 I/O Data 21

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 26 M9999-102207-1.6

Pin Number Pin Name Type Pin Function

103 D20 I/O Data 20

104 D19 I/O Data 19

105 D18 I/O Data 18

106 D17 I/O Data 17

107 DGND Gnd Digital IO ground

108 VDDIO P

3.3V digital VDDIO input power supply for IO with well decoupling capacitors.

109 D16 I/O Data 16

110 D15 I/O Data 15

111 D14 I/O Data 14

112 D13 I/O Data 13

113 D12 I/O Data 12

114 D11 I/O Data 11

115 D10 I/O Data 10

116 D9 I/O Data 9

117 D8 I/O Data 8

118 D7 I/O Data 7

119 D6 I/O Data 6

120 D5 I/O Data 5

121 D4 I/O Data 4

122 D3 I/O Data 3

123 DGND Gnd Digital IO ground

124 DGND Gnd Digital core ground

125 VDDIO P 3.3V digital VDDIO input power supply for IO with well decoupling capacitors.

126 D2 I/O Data 2

127 D1 I/O Data 1

128 D0 I/O Data 0

Legend:

P = Power supply Gnd = Ground

I/O = Bi-directional I = Input O = Output.

Ipd = Input with internal pull-down.

Ipu = Input with internal pull-up.

Opd = Output with internal pull-down.

Opu = Output with internal pull-up.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 27 M9999-102207-1.6

Functional Description

The KSZ8841M is a single-chip Fast Ethernet MAC controller consisting of a 10/100 physical layer transceiver (PHY), a

MAC, and a Bus Interface Unit (BIU) that controls the KSZ8841M via an 8-bit, 16-bit, or 32-bit host bus interface.

The KSZ8841M is fully compliant to IEEE802.3u standards.

Functional Overview

Power Management

Power down

The KSZ8 841M featur es a port p o wer- do wn mode. To s ave po wer , t he us er can power-down the port tha t is not in use by

setting bit 11 in either P1CR4 or P1MBCR register for this port. To bring the port back up, reset bit 11 in these registers.

In addition, there is a f ull chip power-down mode PWRDN (pin 36). When this pin is pulled-down, the entire chip powers

down. Transitioning this pin from pull-down to pull-up results in a power up and chip reset.

Wake-on-LAN

Wake-up frame events are used to wake the system whenever meaningful data is presented to the system over the

network. Examples of meaningful data include the reception of a Magic Packet, a management request from a remote

adminis trator, or sim ply network tr affic dir ectly target ed to the loc al s ystem. In all o f thes e instanc es, the networ k device is

pre-programmed by the policy owner or other software with information on how to identify wake frames from other network

traffic.

A wake-up event is a request for hardware and/or software external to the network device to put the system into a

powered state (working).

A wake-up signal is caused by:

1. Detection of a change in the network link state

2. Receipt of a network wake-up frame

3. Receipt of a Magic Packet

There ar e als o oth er types of wak e-up e ve nts tha t ar e not listed here as manufac turer s m a y choose to implem ent these in

their own wa y.

Link Change

Link status wake events are useful to indicate a change in the network’s availability, especially when this change may

impac t the le ve l at which the syst em should re-enter the sleep in g s tate. For exam ple, a c han ge f r om link off to link on m a y

trigger the system to re- enter s leep at a high er leve l ( D2 vers us D3 1) so that wake f rames can be detec ted. Convers el y, a

transition from link on to link off may trigger the system to re-enter sleep at a deeper level (D3 versus D2) since the

network is not currently available.

Wake-up Packet

Wake-up packets are certain types of packets with specific CRC values that a system recognizes as a ‘wake up’ frame.

The KSZ8841M supports up to four users defined wake-up frames as below:

1. Wake-up frame 0 is defined in registers 0x00-0x0A of Bank 4 and is enabled by bit 0 in wakeup frame control register.

2. Wake-up frame 1 is defined in registers 0x00-0x0A of Bank 5 and is enabled by bit 1 in wakeup frame control register.

3. Wake-up frame 2 is defined in registers 0x00-0x0A of Bank 6 and is enabled by bit 2 in wakeup frame control register.

4. Wake-up frame 4 is defined in registers 0x00-0x0A of Bank 7 and is enabled by bit 3 in wakeup frame control register.

Magic Packet

Magic Packet technolog y is used to remotely wake up a sleeping or powered off PC on a LAN. This is accomplished b y

sending a specific packet of information, called a Magic Packet frame, to a node on the network. W hen a PC capable of

receivin g the specific fr am e goes to sleep, it e na bles th e Ma gic Packet RX mode in th e L AN controller, and when the L AN

controller receives a Magic Packet frame, it will alert the system to wake up.

1 References to D0, D1, D2, and D3 are power management states defined in a similar fashion to the way they are defined for PCI. For

more information, refer to the PCI specification at www.pcisig.com/specifications/conventional/pcipm1.2.pdf.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 28 M9999-102207-1.6

Magic Packet is a standard feature integrated into the KSZ8841M. The controller implements multiple advanced power-

down modes including Magic Packet to conserve power and operate more efficiently.

Once the KSZ 8841M has been put i nto Magic Pack et Enabl e mode (W F CR[7]=1), it sc ans all incom ing f rames address ed

to the node for a specific data sequence, which indicates to the controller this is a Magic Packet (MP) frame.

A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as Source Address

(SA), Destination Address (DA), which may be the receiving station’s IEEE address or a multicast or broadcast address

and CRC.

The specific sequence consists of 16 duplications of the IEEE address of this node, with no break s or interruptions. T his

sequence can be located anywhere within the packet, but must be preceded by a synchronization stream. The

synchron ization stream allows th e scanning s tate machin e to be muc h simpler. T he synchroniza tion stream is define d as

6 bytes of FFh. The device will a lso accept a broa dcast fram e, as long as the 16 duplicati ons of the IEEE a ddress match

the address of the machine to be awakened.

example

If the IEEE address for a particular node on a network is 11h 22h, 33h, 44h, 55h, 66h, the LAN controller would be

scanning for the data sequence (assuming an Ethernet frame):

DESTINAT ION SOURCE – MI SC - FF FF FF FF FF FF - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 -

11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 -

11 22 33 44 55 66 - MISC - CRC.

There ar e no fur ther restric tions on a Magic Pack et fram e. For instance, the sequ ence could be in a TCP/IP pack et or an

IPX pack et. The fr ame m ay be bri dged or route d across the network witho ut affecting its abilit y to wake-up a node at the

frame’s destination.

If the LAN contr oll er sc ans a fr ame and does not find t he specif ic s equence s how n above, it disc ards the f ram e and tak es

no further action. If the KSZ8841M controller detects the data sequence, however, it then alerts the PC’s power

management circuitry (assert the PMEN pin) to wake up the system.

Physical Layer Transceiver (PHY)

100BASE-TX Transmit

The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI

conversion, and MLT3 encoding and transmission.

The c ircuitry starts with a p arallel-t o-seria l conversi on, which c onverts the MII dat a from the MAC into a 1 25MHz seria l bit

stream . The data and contr ol stream is then converted into 4 B/5B coding, f ollowed by a scr ambler. The ser ialized data is

further c onverte d from NRZ-to-NRZI f orm at, and then t ransm itted in MLT 3 curr ent outpu t. An exter nal 1% 3. 01KΩ resistor

for the 1:1 transformer ratio sets the output current.

The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude

balance, o vers ho ot, a nd t i ming jitter. T he wave- s ha p ed 10 BA S E-T output driver is also i nc orpor a ted into the 100BASE-T X

driver.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 29 M9999-102207-1.6

100BASE-TX Receive

The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and

clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.

The rec eiving side starts with the equalizat ion filter to c ompens ate for inter-s ymbol int erference ( ISI) over the twisted p air

cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer has to adjust its

characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on

compar isons of i ncom ing signal s trength against som e known cab le charac teristic s, and th en tunes itself for optim ization.

This is an ongoing process and self-adjusts against environmental changes such as temperature variations.

Next, the equal ized s ignal goes t hroug h a DC restor ation and data con versi on bl ock . The DC res torati on c ircuit is use d to

compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit

converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.

The c lock recovery circuit extr ac ts the 125MHz clock from the edges of the NRZ I sign al. T his r ecover ed c lock is then used

to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B

decoder. Finally, the NRZ serial data is converted to an MII format and provided as the input data to the MAC.

PLL Clock Synthesizer (Recovery)

The internal PLL clock synthesizer generates 125MHz, 62.5MHz, 41.66MHz, and 25MHz clocks by setting the on-chip

bus speed control register for KSZ8841M system timing. These internal clocks are generated from an external 25Mhz

crystal or oscillator.

Scrambler/De-scrambler (100BASE-TX Only)

The purpos e of the scram bler is to s pread th e power s pectrum of the s ignal to r educe elec tromagnet ic inter ference ( EMI)

and baselin e wander .

Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). The scrambler

generates a 2047-bit non- repetitive se quence. T hen the receiver d e-scrambles the incoming data s tream using th e same

sequence as at the transmitter.

10BASE-T Transmit

The 10BASE-T driver is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetics.

They are internally wave-shaped and pre-emphasized into outputs with a t ypical 2.4V amplitude. The harmonic contents

are at least 27dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal.

10BASE-T Receive

On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit and

a phase-locked loop (PLL) perform the decoding function.

The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with

levels less than 400mV or with short pulse widths to prevent noise at the RXP-or-RXM input from falsely triggering the

decoder. When the input e x c eeds the sq ue lc h l imit, the PLL loc k s onto the i nc om ing s ign al and th e K SZ8 841M decodes a

data frame.

The receiver clock is maintained active during idle periods in between data reception.

MDI/MDI-X Auto Crossover

To eliminate the need for crossover cables between similar devices, the KSZ8841M supports HP-Auto MDI/MDI-X and

IEEE 802.3u standard MDI/MDI-X auto crossover. HP-Auto MDI/MDI-X is the default.

The auto-s ens e f unc tio n de tect s r em ote trans mit and receive pa ir s and c or rec tly assigns the trans mit and recei ve pa irs f or

the KSZ8841M device. This feature is extremely useful when end users are unaware of cable types in addition to saving

on an additional uplink configuration connection. The auto-crossover feature can be disabled through the port control

registers.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 30 M9999-102207-1.6

The IEEE 802.3u standard MDI and MDI-X definitions are:

MDI MDI-X

RJ45 Pins Signals RJ45 Pins Signals

1 TD+ 1 RD+

2 TD- 2 RD-

3 RD+ 3 TD+

6 RD- 6 TD-

Table 1. MDI/MDI-X Pin Definitions

Straight Cab le

A straig ht cable c onnec ts an MDI dev ice to a n MDI-X dev ice or an MDI-X dev ice to an MDI de vice. T he foll owing dia gram

shows a typical straight cable connection between a network interface card (NIC) and a chip (MDI), or hub (MDI-X).

Rec eiv eP air

T r a n s m i t P a i r

R e c e i v e P a i r

Tra n s mit Pa ir

( R J - 4 5 )

N I C

S tra ig ht

Cable

1 0 / 1 0 0 E t h e r n et

M e d i a D e p e n d e n t I n terfac e 10 /100 Ethe rnet

Me d ia D ep e nden t Inte rfac e

M odu la r C onn ec to r

(R J -45 )

H U B

(R ep e ater or S

itc h)

M o d u

l a r C o n n e c tor

Figure 7. Typical Straight Cable Connection

Crossover Cable

A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. The

following diagram shows a typical crossover cable connection between two chips or hubs (two MDI-X devices).

ReceivePair ReceivePair

Transmit Pair

10/100 Ethernet

Media Dependent Interface 10/100Ethernet

Media Dependent Interface

ModularConnector(RJ-45)

HUB

(Repeater or Switch)

Modular Connector(RJ-45)

HUB

(Repeater or Switch)

Crossover

Cable

Figure 8. Typical Crossover Cable Connection

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 31 M9999-102207-1.6

Auto Negotiation

The KSZ8841M conforms to the auto negotiation protocol as described by the 802.3 committee to allow the port to

operate at either 10Base-T or 100Base-TX.

Auto negot iation a llows u nshielded twis ted pair ( UTP) li nk partners to sele ct the bes t comm on mode of oper ation. In a uto

negotiat ion, th e link partners advert ise capab ilit ies acr oss the link to eac h other . If auto negot iatio n is not su pporte d or the

link par tner to the KSZ8 841 M is forced to b ypass aut o nego tia tion, the m ode is s et b y obs erv in g th e s ignal at the recei ver.

This is known as parallel mode because while the tr ansmitter is sending auto negotiation advert isements, the receiver is

listening for advertisements or a fixed signal protocol.

The link setup is shown in the following flow diagram (Figure 9).

Force Link Setting

Listen for 10BASE-T L i n k

Pulse s

Listen for 100BASE-TX

Idles

ttempt Auto

Negotiation

Link Mode Set

B y p a s s

u t o N e g o t i a t i o n

and Set Link Mode

Link Mode Set ?

Parallel

Operation

Join Flow

YES

Start Auto Negotiation

Figure 9. Auto Negotiation and Parallel Operation

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 32 M9999-102207-1.6

LinkMD Cable Diagnostics

The KSZ88 41M L ink MD uses time dom ain ref lectom etry (TDR) to a nal yze the c abli ng pla nt for comm on cablin g pro blem s

such as open circuits, short circuits, and impedance mismatches.

LinkMD wor ks b y sending a pulse of known am plitu de and durat ion do wn the MD I and MDI-X pairs an d then anal yzes the

shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with a

maximum distance of 200m and an accuracy of +/–2m. Internal circuitry displays the TDR information in a user-readable

digital format in register P1VCT[8:0].

Note: cable diagnostics are only valid for copper connections – fiber-optic operation is not supported.

Access

LinkMD is initiate d by access ing register P1VCT, the Link MD Contro l/Status regi ster, in conj unction with r egister P1CR 4,

the 100BASE-TX PHY Controller register.

Usage

LinkMD can be run at any time by ensuring that Auto-MDIX has been disabled. To disable Auto-MDIX, write a ‘1’ to

P1CR4[10] to enable m anual control over the pair used to transmit the LinkMD pulse. The self-clearing cable diagnostic

test enable bit, P1VCT[15], is set to ‘1’ to start the test on this pair.

W hen bit P1VCT[15] r eturns to ‘0 ’, the test is complet e. The test res ult is retur ned in b its P1VCT[14: 13] and the dis tance

is returned in bits P1VCT[8:0]. The cable diagnostic test results are as follows:

00 = Valid test, normal condition

01 = Valid test, open circuit in cable

10 = Valid test, short circuit in cable

11 = Invalid test, LinkMD failed

If P1VCT[14:13]=11, this indicates an invalid test, and occurs when the KSZ8841M is unable to shut down the link

partner. In t his ins tance, th e test is not r un, as it is not possible f or the KSZ88 41M to determine if the detec ted signa l is a

reflection of the signal generated or a signal from another source.

Cable distance can be approximated by the following formula:

P1VCT[8:0] x 0.4m for port 1 cable distance

This constant m ay be calibrated f or diff erent cabling c onditi ons, inclu ding cab les with a v elocity of propagati on that varies

significantly from the norm.

Med ia Access Cont rol (M AC) Operat ion

The KSZ8841M strictly abides by IEEE 802.3 standards to maximize compatibility.

Inter Packet Gap (IPG)

If a frame is successfully transmitted, then the minimum 96-bit time for IPG is measured between two consecutive

packets. If the current packet is exper iencing collisions, the minimum 96-bit time for IPG is m easured from carrier sense

(CRS) to the next transmit packet.

Back-Off Algorithm

The KSZ8 841M im plements the I EEE stand ard 802.3 binary expon ential bac k-off algorit hm in half -duplex mode. After 16

collis ions, the pac ket is dropped.

Late Collision

If a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped.

Flow Control

The KSZ8841M supports standard 802.3x flow control frames on both transmit and receive sides.

On the receive side, if the KSZ8841M receives a pause control frame, the KSZ8841M will not transmit the next normal

frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the current

timer expires, the tim er will be updated with the new value in the second pause frame. During this period (while it is flow

controlled), only flow control packets from the KSZ8841M are transmitted.

On the tr ansm it side, the KSZ8841M has in telligent a nd eff icient wa ys to determ ine wh en to in voke flo w contr ol. The f low

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 33 M9999-102207-1.6

control is based on availability of the system resources.

The KSZ8841M issues a flow control frame (Xoff, or transm itter off), containing the m aximum pause time defined in IEEE

standard 802.3x. Once the resource is freed up, the KSZ8841M sends out the another flow control frame (Xon, or

transmitter on) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is

provided to prevent the flow control mechanism from being constantly activated and deactivated.

Half-Duplex Backpressure

A half-duplex backpressure option (non-IEEE 802.3 standards) is also provided. The activation and deactivation

conditio ns are the sam e as in f ull-dupl ex mode. If backpr essure is r equired, the KSZ 8841M s ends pream bles to def er the

other stations' transmission (carrier sense deference).

To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the KSZ8841M

discontinues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents other

stations from sending out pack ets thus keepin g other statio ns in a carr ier sense def erred state. If the port has packets to

send during a backpressure situation, the carrier sense type backpressure is interrupted and those packets are

transmitted instead. If there are no additional packets to send, carrier sense type backpressure is reactivated again until

chip resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is

generated immediately, thus reducing the chance of further collision and carrier sense is maintained to prevent packet

reception.

Clock Generator

The X1 and X2 pins are connected to a 25MHz crystal. X1 can also serve as the connector to a 3.3V, 25MHz oscillator

(as descr ibed in the pin d esc r iptio n).

The bus interface unit (BIU) uses BCLK (Bus Clock) for synchronous accesses. The maximum frequency is 50MHz for

VLBus-like and EISA-like slave direct memory access (DMA).

Bus Interface Unit (BIU)

The BIU host interface is a generic bus interface, designed to communicate with embedded processors. The use of glue

logic may be required when it talks to various standard buses and processors.

Supported Transfers

In terms of transf er type, the BIU c an support two tran sfers: asynchrono us transfer and s ynchronous transfer. To suppor t

these transfers (asynchronous and synchronous), the BIU provides three groups of signals:

Synchronous signals

Asynchronous signals

Common signals are used for both synchronous and asynchronous transfers.

Since both synchronous and asynchronous signals are independent of each other, synchronous transfer and

asynchronous transfer can be mixed or interleaved but cannot be overlapped (due to the sharing of common signals).

Physical Data Bus Size

The BIU supports an 8-bit, 16-bit, or 32-bit host standard data bus. Depending on the size of the physical data bus, the

KSZ8841M supports 8-bit, 16-bit, or 32-bit data transfers

For example,

For a 32-bit system/host data bus, the KSZ8841M allows an 8-bit, 16-bit, and 32-bit data transfer (KSZ8841-32MQL).

For a 16-bit system/host data bus, the KSZ8841M allows an 8-bit and 16-bit data transfer (KSZ8841-16MQL).

For an 8-bit system/host data bus, the KSZ8841M only allows an 8-bit data transfer (KSZ8841-16MQL).

The KSZ8841M does not support internal data byte-swap but it does support internal data word-swap. This means that

the system/host data bus HD[7:0] must connect to both D[7:0] and D[15:8] for an 8-bit data bus interface. For a 16-bit data

bus, the system /host data bus HD[ 15:8] and HD[ 7:0] onl y need t o connec t to D[15:8] and D[7:0] r esp ectivel y, and th ere is

no need to connect HD[15:8] and HD[7:0] to D[31:24] and D[23:16].

Table 2 describes the BIU signal grouping.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 34 M9999-102207-1.6

Signal Type(1) Function

Common Signals

A[15:1] I Address

AEN I Address Enable

Address Enable asserted indicates memory address on the bus for DMA access

and since the device is an I/O device, address decoding is only enabled when AEN

is Low.

BE3N, BE2N,

BE1N, BE0N I Byte Enable

BE0N BE1N BE2N BE3N Description

0 0 0 0 32-bit access

0 0 1 1 Lower 16-bit (D[15:0]) access

1 1 0 0 Higher 16-bit (D[31:16]) access

0 1 1 1 Byte 0 (D[7:0]) access

1 0 1 1 Byte 1 (D[15:8]) access

1 1 0 1 Byte 2 (D[23:16]) access

1 1 1 0 Byte 3 (D[31:24]) access

Note 1: BE3N, BE2N, BE1N and BE0N are ignored when DATACSN is low because

32 bit transfers are assumed.

Note 2: BE2N and BE3N are valid only for the KSZ8841-32 mode, and are No

Connect for the KSZ8841-16 mode.

D[31:16] I/O Data

For KSZ8841M-32 mode only.

D[15:0] I/O Data

For both KSZ8841-32 and KSZ8841-16 Modes

ADSN I Address Strobe

The rising edge of ADSN is used to latch A[15:1], AEN, BE3N, BE2N, BE1N and

BE0N.

LDEVN O Local Device

This signal is a combinatorial decode of AEN and A[15:4]. This A[15:4] is used to

compare against the Base Address Register.

DATACSN I Data Register Chip Select (For KSZ8841-32MQL Mode only)

This signal is used for central decoding architecture (mostly for embedded

application). When asserted, the device’s local decoding logic is ignored and the 32-

bit access to QMU Data Register is assumed.

INTR O Interrupt

Synchronous Transfer Signals

VLBUSN I VLBUS

VLBUSN = 0, VLBus-like cycle.

VLBUSN = 1, burst cycle (both host/system and KSZ8841M can insert wait state)

CYCLEN I CYCLEN

For VLBus-like access: used to sample SWR when asserted.

For burst access: used to connect to IOWC# bus signal to indicate burst write.

SWR I Write/Read

For VLBus-like access: used to indicate write (High) or read (Low) transfer.

For burst access: used to connect to IORC# bus signal to indicate burst read.

SRDYN O Synchronous Ready

For VLBus-like access: exactly the same signal definition of nSRDY in VLBus.

For burst access: insert wait state by KSZ8841M whenever necessary during the

Data Register access.

RDYRTNN I Ready Return

For VLBus-like access: exactly like RDYRTNN signal in VLBus to end the cycle.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 35 M9999-102207-1.6

Signal Type(1) Function

For burst access: exactly like EXRDY signal in EISA to insert wait states. Note that

the wait states are inserted by system logic (memory) not by KSZ8841M.

BCLK I Bus Clock

Asynchronous Transfer Signals

RDN I Asynchronous Read

WRN I Asynchronous Write

ARDY O Asynchronous Ready

This signal is asserted (Low) to insert wait states.

Note 1: I = Input. O = Output. I/O = Bi-directional.

Table 2. Bus Interface Unit Signal Grouping

Regardless of whether the transfer is synchronous or asynchronous, if the address latch is required, use the rising edge of

ADSN to latch the incoming signals A[15:1], AEN, BE3N, BE2N, BE1N, and BE0N.

Note: If the local device decoder is used in either synchronous or asynchronous transfers, LDEVN will be asserted to

indicate that the KSZ8841M is successfully targeted. The signal LDEVN is a combinatorial decode of AEN and A[15:4].

Asynchronous Interface

For asynchronous transfers, the asynchronous dedicated signals RDN (for read) or WRN (for write) toggle, but the

synchronous dedicated signals CYCLEN, SWR, and RDYRTNN are de-asserted and stay at the same logic level

throughout the entire asynchronous transfer.

There is no data burst support for asynchronous transfer. All asynchronous transfers are single-data transfers. The BIU,

however, provides flexible asynchronous interfacing to communicate with various applications and architectures. Three

major ways of interfacing with the system (host) are.

1. Interfac ing with th e system /host rel ying on loca l device decoding and hav ing stabl e address throughout th e whole

transf er: The typica l example f or this appl ication is IS A-like bus interface us ing latc hed address s ignals as s hown

in Figure 13. No addition al addr es s latc h is required, t her ef ore ADSN shou ld be connected L o w. T he BIU decodes

A[15:4] and qua lifies with AEN (Addr ess Enab le) to determ ine if the KSZ884 1M devic e is the intend ed target. T he

host utilizes the rising edge of RDN to latch read data and the BIU will use rising edge of WRN to latch write data.

Interfacing with the system/host relying on local device decoding but not having stable address throughout the entire

transfer: The typical example for this application is EISA-like bus (non-burst) interface as shown in the Figure 14. This

type of interface requires ADSN to latch the address on the rising edge. The BIU decodes latched A[15:4] and qualifies

with AEN to determine if the KSZ8841M device is the intended target. The data transfer is the same as the first case.

Interfacing with the system/host relying on central decoding (KSZ8841-32MQL only).

The typical example for this application is for an embedded processor having a central decoder on the system board or

within t he process or. Conn ecting the chip selec t (CS) from s ystem /host to DAT ACSN b ypasses the local d evice dec oder.

W hen the DAT ACSN is as s erted, it on ly al lo ws acc es s to the Data Reg ister in 32 b its and BE 3N, BE 2N, B E1 N , and BE 0N

are ignor ed as sho wn in the Fi gure 15. No other regis ters can be accessed b y asser ting DATACSN . The data tr ansfer is

the sam e as in the first c ase. Independent of the type of as ync hronous inter face used. T o insert a wait s tate, the BIU will

assert ARDY to prolong the cycle.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 36 M9999-102207-1.6

Synchronous Interface

For synchronous transfers, the synchronous dedicated signals CYCLEN, SWR, and RDYRTNN will toggle but the

asynchronous dedicated signals RDN and WRN are de-asserted and stay at the same logic level throughout the entire

synchronous transfer.

The s ynchron ous inter fac e m ainl y supports t wo appl ications , one f or VLBus -lik e and the ot her f or EIS A-lik e ( DMA t ype C)

burst transfers. The VLBus-like interface supports only single-data transfer. The pin option VLBUSN determines if it is a

VLBus-like or EISA-like burst transfer – if VLBUSN = 0, the interface is for VLBus-like transfer; if VLBUSN = 1, the

interface is for EISA-like burst transfer.

For VLBus-like transfer interface (VLBUSN = 0):

This interface is used in an architecture in which the device’s local decoder is utilized; that is, the BIU decodes latched

A[15:4] and q ualifies with AEN (Addres s Enable) to de termine if the KSZ8841M dev ice is the intend ed target. No bur st is

supporte d in this ap plication. T he M/nIO s ignal conne ction in VL Bus is route d to AEN. T he CYCLEN i n this app lication is

used to sample the SWR signal when it is asserted. Usually, CYCLEN is one clock delay of ADSN. There is a

handshak ing pr oces s to en d the c ycle of VL Bus- lik e transf ers. W hen the KSZ 884 1M is r ead y to f inish th e c ycle, it as serts

SRDYN. The system/host acknowledges SRDYN by asserting RDYRTNN after the system/host has latched the read

data. The KSZ8841M holds the read data until RDYRTNN is asserted. The timing waveform is shown in Figures 19 and

20.

For EISA-like burst transfer interface (VLBUSN = 1):

The SWR is connected to IORC# in EISA to indicate the burst read and CYCLEN is connected to IOWC# in EISA to

indicate the burst write. Note that in this application, both the system/host/memory and KSZ8841M are capable of

inserting wait states. For system/host/memory to insert a wait state, assert the RDYRTNN signal; for the KSZ8841M to

insert the wait state, assert the SRDYN signal. The timing waveform is shown in Figures 17 and 18.

BIU Summation

Figure 10 shows the mapping from ISA-like, EISA-like and VLBus-like transactions to the chip’s BIU.

Figure 11 shows the connection for different data bus sizes.

Note: For the 8-bit d ata bus m ode, the inter nal invert er is enab led and co nnected bet ween BE0N a nd BE1N, so a n even

address will enable the BE0N and an odd address will enable the BE1N.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 37 M9999-102207-1.6

KSZ8841M BIU

Asynchronous

Interface

Synchronous

Interface

Address Latch

No Addr Latch

(ADSN = 0)

Central decode

Local

decode

Address Latch

Central decode

(VLBUSN = 1)

Local

decode

(VLBUSN = 0)

Host Interface

ISA

EISA

VLBus

Burst

Non-burst

Note: To use DATACSN & 32-bit only for Central decode

Figure 10. Mapping from the ISA, EISA, and VLBus to the KSZ8841M Bus Interface

D[7:0]

D[15:8]

D[23:16]

D[31:24]

GND

HD[7:0]

nHBE[0]

nHBE[2]

nHBE[3]

HD[15:8]

nHBE[1]

HD[23:16]

HD[31:24]

A[15:2]

A[1]

D[7:0]

D[15:8]

BE0N

BE1N

8-bit Data Bus

HA[1]

HA[15:2]

HD[7:0]

HA[0]

VDD

A[15:2]

A[1]

D[7:0]

D[15:8]

BE0N

BE1N

16-bit Data B us

(for example : ISA -like )

HA[1]

HA[15:2]

HD[7:0]

HA[0]

nSBHE

A[15:2]

A[1]

BE0N

BE1N

BE2N

BE3N

32-bit Data Bus

(for example: E IS A-like)

HA[15:2]

HD[15:8]

KSZ8841-16 KSZ8841-16 KSZ8841-32

Figure 11. KSZ8841M 8-Bit, 16-Bit, and 32-Bit Data Bus Connections

BIU Implementation Principles

Since KSZ 8 841 M is a n I/O devic e wit h 16 addres sable loca tio ns , a ddr es s d e coding is bas e d o n t he v alu es of A15-A4 a nd

AEN. Whenever DATACSN is asserted, the address decoder is disabled and a 32-bit transfer to Data Register is

assumed (BE3N – BE0N are ignored).

If address latching is required, the address is latched on the rising edge of ADSN and is transparent when ADSN=0.

1. Byte, word, and double word data buses and accesses (transfers) are supported.

2. Internal byte swapping is not implemented and word swapping is supported internally. Refer to Figure 11 for the

appropriate 8-bit, 16-bit, and 32-bit data bus connection.

3. Since independent sets of synchronous and asynchronous signals are provided, synchronous and asy nchronous

cycles can be mixed or interleaved as long as they are not active simultaneously.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 38 M9999-102207-1.6

4. The asynchronous interface uses RDN and WRN signal strobes for data latching. If necessary, ARDY is de-

asserted on the leading edge of the strobe.

5. The VLBUS-like synchronous interface uses BCLK, ADSN, and SWR and CYCLEN to control read and write

operations and generate SRDYN to insert the wait state, if necessary, when VLBUSN = 0. For read, the data must

be held until RDYRTNN is asserted.

The EIS A-like burs t transfe r is suppor ted using s ynchr onous interf ace sig nals and DAT ACSN when I/O signa l VLBUSN =

1. Both the system/host/memory and KSZ8841M are capable of inserting wait states. To set the system/host/memory to

insert a wait state, assert RDYRTNN signal. To set the KSZ8841M to insert a wait state, assert SRDYN signal.

Queue Management Unit (QMU)

The Queue Man agem ent Unit (Q MU) m anages pack et traff ic between the MA C/PH Y interfac e and the s ystem hos t. It has

built-in pac ket m emory for rec eive and trans mit f unctions c alled TX Q (Transm it Queue) and RX Q (Recei ve Queue). Each

queue cont ains 4KB of m emory for back -to-back , non-blocking f rame transf er performanc e. It provides a gr oup of control

registers for sys tem control, frame status registers for current packet transmit/receive status, and interrupts to inform the

host of the real time TX/RX status.

Transmit Queue (TXQ) Frame Format

The fram e format for the tr ansmit queue is sho wn in the follo wing Table 3. T he first word cont ains the contr ol inform ation

for the frame to transmit. The second word is used to specify the total number of bytes of the frame. The packet data

follows. The packet data area holds the frame itself. It may or may not include the CRC checksum depending upon

whether hardware CRC checksum generation is enabled.

Multiple frames can be pipelined in both the transmit queue and receive queue as long as there is enough queue memory,

thus avoiding overrun. For each transmitted frame, the transmit status information for the frame is located in the TXSR

Address Offset Bit 15 Bit 0

2nd Byte 1st Byte

0 Control Word

2 Byte Count

4 - up Transmit Packet Data

(maximum size is 1916)

Table 3. Frame Format for Transmit Queue

Since multiple pack ets can be pipelined into the TX pack et memor y for transmit, the transmit status reflects the status of

the packet that is currently being transferred on the MAC interface, which may or may not be the last queued packet in the

TX queue.

The transmit control word is the first 16-bit word in the TX packet memory, followed by a 16-bit byte count. It must be word

aligned. Each control word corresponds to one TX packet. Table 4 gives the transmit control word bit fields.

Bit Description

15 TXIC Transmit Interrupt on Completion

When this bit is set, the KSZ8841M sets the transmit interrupt after the present frame has

been transmitted.

14-6 Reserved.

5-0 TXFID Transmit Frame ID

This field specifies the frame ID that is used to identify the frame and its associated status

information in the transmit status register.

Table 4. Transmit Control Word Bit Fields

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 39 M9999-102207-1.6

The transmit Byte Count specifies the total number of bytes to be transmitted from the TXQ. Its format is given in Table 5.

Bit Description

15-11 Reserved.

10-0 TXBC Transmit Byte Count

Transmit Byte Count. Hardware uses the byte count information to conserve the TX buffer

memory for better utilization of the packet memory.

Note: The hardware behavior is unknown if an incorrect byte count information is written to this

field. Writing a 0 value to this field is not permitted.

Table 5. Transmit Byte Count Format

The data ar ea contains six b ytes of Des ti nat io n Addr es s ( DA) f oll o wed by six bytes of Sourc e Ad dr es s ( S A) , f oll o wed by a

variable-length number of bytes. On transmit, all bytes are provided by the CPU, including the source address. The

KSZ8841 M does not insert its o wn SA. The 802. 3 Fram e Length word (Fram e Type in Ether net) is not interpr eted by the

KSZ8841M. It is treated transparently as data both for transmit operations.

Receive Queue (RXQ) Frame Format

The frame format for the receive queue is shown in Table 6. The first word contains the status information for the frame

received. The second word is the total number of bytes of the RX frame. Following that is the packet data area. The

packet data area holds the frame itself. It may or may not include the CRC checksum depending on whether hardware

CRC stripping is enabled. Packet Memory

Address Offset Bit 15 Bit 0

2nd Byte 1st Byte

0 Status Word

2 Byte Count

4 - up Receive Packet Data

(maximum size is 1916)

Table 6. Frame Format for Receive Queue

For receive, the packet receive status alwa ys reflects the receive status of the packet received in the current RX packet

memory (see Table 7). The RXSR register indicates the status of the current received frame.

Bit Description

15 RXFV Receive Frame Valid

When set, this field indicates that the present frame in the receive packet memory is valid. The status

information currently in this location is also valid.

When clear, it indicates that there is either no pending receive frame or that the current frame is still

in the process of receiving.

14-8 Reserved.

7 RXBF Receive Broadcast Frame

When set, it indicates that this frame has a broadcast address.

6 RXMF Receive Multicast Frame

When set, it indicat es that thi s frame ha s a multic ast address (including the broadcas t addre ss).

5 RXUF Receive Unicast Frame

When set, it indicates that this frame has a unicast address.

4 Reserved.

3 RXFT Receive Frame Type

When set, it indicates that the frame is an Ethernet-type frame (frame length is greater than 1500

bytes). When clear, it indicates that the frame is an IEEE 802.3 frame.

This bit is not valid for runt frames.

2 RXTL Receive Frame Too Long

When set, it indicates that the frame length exceeds the maximum size of 1518 bytes. Frames that

are too long are passed to the host only if the pass bad frame bit is set.

Note: Frame too long is only a frame length indication and does not cause any frame truncation.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 40 M9999-102207-1.6

Bit Description

1 RXRF Receive Runt Frame

When set, it indicates that a frame was damaged by a collision or had a premature termination

before the collision window passed.

Runt frames are passed to the host only if the pass bad frame bit is set.

0 RXCE Receive CRC Error

When set, it indicates that a CRC error has occurred on the current received frame.

CRC error frames are passed to the host only if the pass bad frame bit is set.

Table 7. RXQ Receive Packet Status Word

Table 8 gives the format of the RX byte count field.

Bit Description

15-11 Reserved

10-0 RXBC Receive Byte Count

Receive Byte Count up to 1916 bytes

Table 8. RXQ Receive Packet Byte Count Word

EEPROM Interface

It is opti ona l in the K SZ8841M to us e an ex ternal EEP ROM. In the cas e t hat an E EPROM is not us ed, the E EEN pi n must

be tied Low or floating .

An externa l ser ia l EEPROM with a standar d microwir e bus inter f ac e is used f o r non-vol ati le s torage of information such as

the host MAC address, base address, and default configuration settings. The KSZ8841 M can detect if the EEPROM is a

1KB (93C 46) or 4KB (93C 66) EEPROM device (the 9 3C46 and the 93C 66 are t ypical EEPRO M devices). T he EEPROM

is organized as 16-bit mode.

If the EEEN p in is pul led high, then th e KSZ8841 M perf orms an autom atic read o f the external EEPROM words 0H to 6H

after the d e-ass ertio n of Re set. T he EEPRO M val ues are plac ed in cer tai n host-a cc essible reg isters . EE PROM r ead/wr ite

functions can also be performed by software read/writes to the EEPCR registers.

The KSZ8841M EEPROM format is given in Table 9.

WORD 15 8 7 0

0H Base Address

1H Host MAC Address Byte 2 Host MAC Address Byte 1

2H Host MAC Address Byte 4 Host MAC Address Byte 3

3H Host MAC Address Byte 6 Host MAC Address Byte 5

4H Reserved

5H Reserved

6H ConfigParam (see Table 10)

7H-3FH Not used for KSZ8841M (available for user to use)

Table 9. KSZ8841M EEPROM Format

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 41 M9999-102207-1.6

The format for ConfigParam is shown in Table 10.

Bit Bit Name Description

15 Reserved Reserved

14 NO_SRST

No Soft Reset

When this bit is set, indicates that KSZ8841M transitioning from D3_hot to D0 because

of PowerState commands do not perform an internal reset. Configuration Context is

preserved. Upon transition from the D3_hot to the D0 Initialized state, no additional

operating system intervention is required to preserve Configuration Context beyond

writing the PowerState bits.

When this bit is clear, KSZ8841M performs an internal reset upon transitioning from

D3_hot to D0 via software control of the PowerState bits. Configuration Context is lost

when performing the soft reset. Upon trasition from the D3_hot to the D0 state, full

reinitialization sequence is needed to return the device to D0 Initialized.

Regardless of this bit, devices that transition from D3_hot to D0 by a system or bus

segment reset will return to the device state D0 Uninitialized with only PME context

preserved if PME is supported and enabled.

This bit is loaded to bit 3 of PMCS register

13 Reserved Reserved.

12 PME_D2

PME Support D2

When this bit is set, the KSZ8841M asserts PME event (pin 14) when the KSZ8841M is

in D2 state and PME_EN is set. Otherwise, the KSZ8841M does not assert PME event

when the KSZ8841M is in D2 state.

This bit is loaded to bit 13 of PMCR register

11 PME_D1

PME Support D1

When this bit is set, the KSZ8841M asserts PME event (pin 14) when the KSZ8841M is

in D1 state and PME_EN is set. Otherwise, the KSZ8841M does not assert PME event

when the KSZ8841M is in D1 state.

This bit is loaded to bit 12 of PMCR register.

10 D2_SUP

D2 Support

When this bit is set, the KSZ8841M supports D2 power state. This bit is loaded to bit 10

of PMCR register.

9 D1_SUP

D1 Support

When this bit is set, the KSZ8841M supports D1 power state. This bit is loaded to bit 9

of PMCR register.

8-2 Reserved Reserved.

1 Clock_Rate Internal clock rate selection

0: 125 MHz

1: 25 MHz

Note: At power up, this chip operates on 125 MHz clock. The internal frequency can be

dropped to 25 MHz via the external EEPROM.

0 ASYN_8bit

Async 8-bit bus select

1= bus is configured for 16-bit width

0= bus is configured for 8-bit wi dth

This bit is loaded to bit 0 of PMCR register

(32-bit width, KSZ8841-32MQL, don’t care this bit setting)

Table 10. ConfigParam Word in EEPROM Format

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 42 M9999-102207-1.6

Loopback Support

The KSZ8841M provides Near-end (Remote) loopback support for remote diagnostic of failure. In loopback mode, the

speed at the PHY port will be set to 100BASE-TX full-duplex mode.

Near-end (Remote) Loopback

Near-end (Remote) loopback is conducted at PHY port 1of the KSZ8841M. The loopback path starts at the PHY port’s

receive inputs (RXP1/RXM1), wraps around at the same PHY port’s PMD/PMA, and ends at the PHY port’s transmit

outputs (TXP1/TXM1).

Bit [1] of register P1PH YCT RL is used to e nable n ear- end loopbac k for port 1. Alt ernati vel y, Bit [9] of regis ter P1SCSL MD

can also be used to enable near-end loopback. The ports 1 near-end loopback path is illustrated in the following Figure

12.

Bus I/F Unit

QMU/DMA

RXQ/TXQ

MAC1

PCS1

PMD1/PMA1

RXP1 /

RXM1 TXP1 /

TXM1

PHY Port 1

Near-end (remote)

Loopback

Figure 12. PHY Port 1 Near-end (Remote) Loopback Path

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 43 M9999-102207-1.6

CPU Interface I/O Registers

The KSZ8841M provides an EISA-like, ISA-like, or VLBUS-like bus interface for the CPU to access its internal I/O

registers. I/O registers serve as the address that the microprocessor uses when communicating with the device. This is

used for c onf iguring op er ati ona l s ettin gs, readi ng or writing con trol, s tat us inf ormation, and trans f er ring pac k ets b y reading

and writing through the packet data registers.

I/O Registers

Input/Output (I/O) registers are limited to 16 locations as required by most ISA bus-based systems; therefore, registers

are assig ned to dif ferent bank s. The las t word of t he I/O register locations ( 0xE - 0x F) is shar ed by all ba nks and ca n be

used to change the bank in use.

The following I/O Space Mapping Tables apply to 8, 16 or 32-bit bus products. Depending upon the bus interface used

and byte enable signals (BE[3:0]N control byte access), each I/O access can be performed as an 8-bit, 16-bit, or 32-bit

operation. (The KSZ8841M is not limited to 8/16-bit performance and 32-bit read/write are also supported).

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 44 M9999-102207-1.6

Internal I/O Space Mapping

I/O Regi ster Location Bank Location

32-Bit 16-Bit 8-Bit Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7

0x0 Base

Address

[7:0]

Host MAC

Address

Low [7:0]

On-Chip Bus

Control

[7:0]

Wakeup

Frame0

CRC0 [7:0]

Wakeup

Frame1

CRC0 [7:0]

Wakeup

Frame2

CRC0 [7:0]

Wakeup

Frame3

CRC0 [7:0]

0x0

- 0x1 0x1 Base

Address

[15:8]

Reserved Host MAC

Address

Low [15:8]

On-Chip Bus

Control

[15:8]

Wakeup

Frame0

CRC0 [15:8]

Wakeup

Frame1

CRC0

[15:8]

Wakeup

Frame2

CRC0

[15:8]

Wakeup

Frame3

CRC0 [15:8]

0x2 Host MAC

Address

Mid [7:0]

EEPROM

Control

[7:0]

Wakeup

Frame0

CRC1 [7:0]

Wakeup

Frame1

CRC1 [7:0]

Wakeup

Frame2

CRC1 [7:0]

Wakeup

Frame3

CRC1 [7:0]

0x0

0x3

0x2

- 0x3 0x3

Reserved Reserved

Host MAC

Address

Mid [15:8]

EEPROM

Control

[15:8]

Wakeup

Frame0

CRC1 [15:8]

Wakeup

Frame1

CRC1

[15:8]

Wakeup

Frame2

CRC1

[15:8]

Wakeup

Frame3

CRC1 [15:8]

0x4

QMU RX

Flow

Control

Watermark

[7:0]

Host MAC

Address

High [7:0]

Memory

BIST Info

[7:0]

Wakeup

Frame0

Byte Mask0

[7:0]

Wakeup

Frame1

Byte Mask0

[7:0]

Wakeup

Frame2

Byte Mask0

[7:0]

Wakeup

Frame3 Byte

Mask0 [7:0]

0x4

- 0x5

0x5

QMU RX

Flow

Control

Watermark

[15:8]

Reserved Host MAC

Address

High [15: 8]

Memory

BIST Info

[15:8]

Wakeup

Frame0

Byte Mask0

[15:8]

Wakeup

Frame1

Byte Mask0

[15:8]

Wakeup

Frame2

Byte Mask0

[15:8]

Wakeup

Frame3 Byte

Mask0 [15:8]

0x6 Bus Error

Status

[7:0]

Global

Reset

[7:0]

Wakeup

Frame0

Byte Mask1

[7:0]

Wakeup

Frame1

Byte Mask1

[7:0]

Wakeup

Frame2

Byte Mask1

[7:0]

Wakeup

Frame3 Byte

Mask1 [7:0]

0x4

0x7

0x6

- 0x7

0x7 Bus Error

Status

[15:8]

Reserved Reserved

Global

Reset

[15:8]

Wakeup

Frame0

Byte Mask1

[15:8]

Wakeup

Frame1

Byte Mask1

[15:8]

Wakeup

Frame2

Byte Mask1

[15:8]

Wakeup

Frame3 Byte

Mask1 [15:8]

0x8 Bus Burst

Length

[7:0]

Power

Management

Capabilities

[7:0]

Wakeup

Frame0

Byte Mask2

[7:0]

Wakeup

Frame1

Byte Mask2

[7:0]

Wakeup

Frame2

Byte Mask2

[7:0]

Wakeup

Frame3 Byte

Mask2 [7:0]

0x8

- 0x9

0x9 Bus Burst

Length

[15:8]

Reserved Reserved

Power

Management

Capabilities

[15:8]

Wakeup

Frame0

Byte Mask2

[15:8]

Wakeup

Frame1

Byte Mask2

[15:8]

Wakeup

Frame2

Byte Mask2

[15:8]

Wakeup

Frame3 Byte

Mask2 [15:8]

0xA Wakeup

Frame

Control [7:0]

Wakeup

Frame0 Byte

Mask3 [7:0]

Wakeup

Frame1

Byte Mask3

[7:0]

Wakeup

Frame2

Byte Mask3

[7:0]

Wakeup

Frame3 Byte

Mask3 [7:0]

0x8

0xB

0xA

- 0xB

0xB

Reserved Wakeup

Frame

Control [15:8]

Wakeup

Frame0 Byte

Mask3 [15:8]

Wakeup

Frame1

Byte Mask3

[15:8]

Wakeup

Frame2

Byte Mask3

[15:8]

Wakeup

Frame3 Byte

Mask3 [15:8]

0xC

- 0xD 0xD Reserved

0xE Bank Select [7:0]

0xC

0xF 0xE

- 0xF 0xF Bank Select [15:8]

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 45 M9999-102207-1.6

Internal I/O Space Mapping (continued)

I/O Regi ster Location Bank Location

32-Bit 16-Bit 8-Bit Bank 8 Bank 9 Bank 10 Bank 11 Bank 12 Bank 13 Bank 14 Bank 15

0x0

- 0x1 0x1 Reserved

0x2

0x0

0x3 0x2

- 0x3 0x3 Reserved

0x4

- 0x5 0x5 Reserved

0x6

0x4

0x7 0x6

- 0x7 0x7 Reserved

0x8

- 0x9 0x9 Reserved

0xA

0x8

0xB 0xA

- 0xB 0xB Reserved

0xC

- 0xD 0xD Reserved

0xE Bank Select [7:0]

0xC

0xF 0xE

- 0xF 0xF Bank Select [15:8]

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 46 M9999-102207-1.6

Internal I/O Space Mapping (continued)

I/O Regi ster Location Bank Location

32-Bit 16-Bit 8-Bit Bank 16 Bank 1 7 Bank 18 Bank 19 Bank 2 0 Bank 21 Bank 22 Bank 23

0x0 Transmit

Control

[7:0]

TXQ

Command

[7:0]

Interrupt

Enable

[7:0]

Multicast Table 0

[7:0]

0x0

- 0x1 0x1 Transmit

Control

[15:8]

TXQ

Command

[15:8]

Interrupt

Enable

[15:8]

Multicast Table 0

[15:8]

Reserved

0x2 Transmit

Status

[7:0]

RXQ

Command

[7:0]

Interrupt

Status

[7:0]

Multicast Table 1

[7:0]

0x0

0x3

0x2

- 0x3 0x3 Transmit

Status

[15:8]

RXQ

Command

[15:8]

Interrupt

Status

[15:8]

Multicast Table 1

[15:8]

Reserved

0x4 Receive

Control

[7:0]

TX Frame

Data

Pointer

[7:0]

Receive

Status

[7:0]

Multicast Table 2

[7:0]

0x4

- 0x5

0x5 Receive

Control

[15:8]

TX Frame

Data

Pointer

[15:8]

Receive

Status

[15:8]

Multicast Table 2

[15:8]

Reserved

0x6

RX Frame

Data

Pointer

[7:0]

Receive

Byte

Counter

[7:0]

Multicast Table 3

[7:0]

0x4

0x7

0x6

- 0x7

0x7

Reserved RX Fr ame

Data

Pointer

[15:8]

Receive

Byte

Counter

[15:8]

Multicast Table 3

[15:8]

Reserved

0x8

TXQ

Memory

Information

[7:0]

QMU Data

Low

[7:0]

Early

Transmit

[7:0]

Power

Management

Control/Status

[7:0]

0x8

- 0x9

0x9 TXQ

Memory

Information

[15:8]

QMU Data

Low

[15:8]

Early

Transmit

[15:8]

Power

Management

Control/Status

[15:8]

Reserved

0xA RXQ

Memory

Information

[7:0]

QMU Data

High

[7:0]

Early

Receive

[7:0]

0x8

0xB

0xA

- 0xB

0xB

RXQ

Memory

Information

[15:8]

QMU Data

High

[15:8]

Early

Receive

[15:8]

Reserved

0xC

- 0xD 0xD Reserved

0xE Bank Select [7:0]

0xC

0xF 0xE

- 0xF 0xF Bank Select [15:8]

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 47 M9999-102207-1.6

Internal I/O Space Mapping (continued)

I/O Regi ster Location Bank Location

32-Bit 16-Bit 8-Bit Bank 24 Bank 25 Bank 26 Bank 27 Bank 28 Bank 2 9 Bank 30 Bank 31

0x0

- 0x1 0x1 Reserved

0x2

0x0

0x3 0x2

- 0x3 0x3 Reserved

0x4 0x4

- 0x5 0x5 Reserved

0x6

0x4

0x7 0x6

- 0x7 0x7 Reserved

0x8 0x8

- 0x9 0x9 Reserved

0xA

0x8

0xB 0xA

- 0xB 0xB Reserved

0xC 0xC

- 0xD 0xD Reserved

0xE

Bank Select [7:0]

0xC

0xF 0xE

- 0xF 0xF

Bank Select [15:8]

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 48 M9999-102207-1.6

Internal I/O Space Mapping (continued)

I/O Register Location Bank Location

32-Bit 16-Bit 8-Bit Bank 32 Bank 33 Bank 34 Bank 35 Bank 36 Bank 37 Bank 38 Bank 39

0x0 Chip I D and

Enable

[7:0]

0x0

- 0x1 0x1 Chip ID and

Enable

[15:8]

Reserved

0x2

0x0

0x3 0x2

- 0x3 0x3 Reserved

0x4 0x4

- 0x5 0x5 Reserved

0x6

0x4

0x7 0x6

- 0x7 0x7 Reserved

0x8 0x8

- 0x9 0x9 Reserved

0xA Chip Global

Control

[7:0]

0x8

0xB 0xA

- 0xB

0xB Chip Global

Control

[15:8]

Reserved

0xC 0xC

- 0xD 0xD Reserved

0xE

Bank Select [7:0]

0xC

0xF 0xE

- 0xF

0xF

Bank Select [15:8]

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 49 M9999-102207-1.6

Internal I/O Space Mapping (continued)

I/O Regi ster Location Bank Location

32-Bit 16-Bit 8-Bit Bank 40 Bank 41 Bank 42 Bank 43 Bank 44 Bank 45 Bank 46 Bank 47

0x0

Indirect Access

Control.

[7:0]

PHY1 MII-

Control

[7:0]

PHY1 LinkMD

Control/Status

[7:0]

0x0

- 0x1

0x1

Reserved Indirect Access

Control . [15:8]

Reserved PHY1 MII-

Control [15:8]

Reserved PHY1 LinkMD

Control/Status

[15:8]

0x2

Indirect Access

Data 1

[7:0]

PHY1 MII-

Status

[7:0]

PHY1 Special

Control/Status

[7:0]

0x0

0x3

0x2

- 0x3

0x3

Reserved Indirect Access

Data 1

[15:8]

Reserved PHY1 MII-

Status [15:8]

Reserved PHY1 Special

Control/Status

[15:8]

0x4 Indirect Access

Data 2 [7:0] PHY1 PHYID

Low

[7:0]

0x4

- 0x5 0x5

Reserved Indirect Access

Data 2 [15: 8]

Reserved PHY1 PHYID

Low

[15:8]

Reserved

0x6 Indirect Access

Data 3 [7:0] PHY1 PHYID

High

[7:0]

0x4

0x7 0x6

- 0x7 0x7

Reserved Indirect Access

Data 3 [15: 8]

Reserved PHY1 PHYID

High

[15:8]

Reserved

0x8 Indirect Access

Data 4 [7:0] PHY1 A.N.

[7:0]

0x8

- 0x9 0x9

Reserved Indirect Access

Data 4 [15: 8]

Reserved PHY1 A.N.

[15:8]

Reserved

0xA

Indirect Access

Data 5 [7:0] PHY1 A.N. Link

Partner Ability

[7:0]

0x8

0xB 0xA

- 0xB

0xB

Reserved Indirect Access

Data 5 [15: 8]

Reserved PHY1 A.N. Link

Partner Ability

[15:8]

Reserved

0xC

- 0xD 0xD

Reserved

0xE Bank Select [7:0]

0xC

0xF

0xE

- 0xF 0xF

Bank Select [15:8]

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 50 M9999-102207-1.6

Internal I/O Space Mapping (continued)

I/O Regi ster Location Bank Location

32-Bit 16-Bit 8-Bi t Bank 48 Bank 49 Bank 50 Bank 51 Bank 52 Bank 53 Bank 54 Bank 5 5

0x0

Port 1 PHY

Special

Control/Status,

LinkMD [7:0]

0x0

- 0x1

0x1

Reserved Port 1 PHY

Special

Control/Status,

LinkMD [ 15:8]

Reserved

0x2 Port 1

Control 4

[7:0]

0x0

0x3

0x2

- 0x3 0x3

Reserved Port 1

Control 4

[15:8]

Reserved

0x4 Port 1

Status

[7:0]

0x4

- 0x5 0x5

Reserved Port 1

Status

[15:8]

Reserved

0x6

0x4

0x7

0x6

- 0x7 0x7 Reserved

0x8

- 0x9 0x9 Reserved

0xA

0x8

0xB 0xA

- 0xB 0xB Reserved

0xC

- 0xD 0xD Reserved

0xE Bank Select [7:0]

0xC

0xF 0xE

- 0xF 0xF Bank Select [15:8]

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 51 M9999-102207-1.6

Internal I/O Space Mapping (continued)

I/O Regi ster Location Bank Location

32-Bit 16-Bit 8-Bit Bank 56 Bank 57 Bank 58 Bank 59 Bank 60 Bank 6 1 Bank 62 Bank 63

0x0

- 0x1 0x1 Reserved

0x2

0x0

0x3 0x2

- 0x3 0x3 Reserved

0x4 0x4

- 0x5 0x5 Reserved

0x6

0x4

0x7 0x6

- 0x7 0x7 Reserved

0x8 0x8

- 0x9 0x9 Reserved

0xA

0x8

0xB 0xA

- 0xB 0xB Reserved

0xC 0xC

- 0xD 0xD Reserved

0xE Bank Select [7:0]

0xC

0xF 0xE

- 0xF 0xF Bank Select [15:8]

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 52 M9999-102207-1.6

Do not write to bit values or to registers defined as Reserved. Manipulating reserved bits or registers causes

unpredictable and often fatal results. If the user wants to write to these reserved bits, the user has to read back these

reserved bits (RO or RW) first, then “OR” with the read value of the reserved bits and write back to these reserved bits.

Bit Type Definition

RO = Read only.

RW = Read/ Write.

W1C = Write 1 to Clear (writing a one to this bit clears it).

Bank 0-63 Bank Select Register (0x0E): BSR (same location in all Banks)

The bank select register is used to select or to switch between different sets of register banks for I/O access.

There are a total of 64 banks available to select, including the built-in switch engine registers.

Bit Default Value R/W Description

15-6 0x000 RO Reserved

5-0 0x00 R/W

BSA Bank Select Address Bits

BSA bits select the I/O register bank in use.

This register is always accessible regardless of the register bank currently selected.

Notes:

The bank select register can be accessed as a doubleword (32-bit) at offset 0xC, as a word

(16-bit) at offset 0xE, or as a byte (8-bit) at offset 0xE.

A doubleword write to offset 0xC writes to the BANK Select Register but does not write to

registers 0xC and 0xD; it only writes to register 0xE.

Bank 0 Base Address Register (0x00): BAR

This register h olds t he bas e ad dress for decoding a dev ice acc ess. Its value is l oaded from the exter nal EEPRO M (0x0 H)

upon a power-on reset if the EEPROM Enable (EEEN) pin is tied to High. Its value can also be modified after reset.

Writing to this register does not store the value into the EEPROM. When the EEEN pin is tied to Low, the default base

address is 0x300.

Bit Default Value R/W Description

15-8 0x03 if EEEN

is Low or, the

value from

EEPROM if

EEEN is High

RW BARH Base Address High

These bits are compared against the address on the bus ADDR[15:8] to determine the

BASE for the KSZ8841M registers.

7-5 0x00 if EEEN

is Low or, the

value from

EEPROM if

EEEN is High

RW BARL Base Address Low

These bits are compared against the address on the bus ADDR[7:5] to determine the BASE

for the KSZ8841M registers.

4-0 0x00 RO Reserved

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 53 M9999-102207-1.6

Bank 0 QMU RX Flow Control High Watermark Configuration Register (0x04): QRFCR

This register contains the user defined QMU RX Queue high watermark configuration bit as below.

Bit Default Value R/W Description

15-13 0x0 RO Reserved

12 0 RW

QMU RX Flow Control High Watermark Configuration

0: 3 KBytes

1: 2 KBytes

11-0 0x000 RO Reserved

Bank 0 Bus Error Stat us Reg ister (0x0 6): BESR

This register flags the different kinds of errors on the host bus.

Bit Default Value R/W Description

15 0 RO

IBEC Illegal Byte Enable Combination

1: illegal byte enable combination occurs. The illegal combination value can be found

from bit 14 to bit 11.

0: legal byte enable combination.

Write 1 to clear.

14-11 - RO IBECV Illegal Byte Enable Combination Value

Bit 14: byte enable 3.

Bit 13: byte enable 2.

Bit 12: byte enable 1.

Bit 11: byte enable 0.

This value is valid only when bit 15 is set to 1.

10 0 RO

SSAXFER Simultaneous Synchronous and Asnychronous Transfers

1: Synchronous and Asnychronous Transfers occur simultaneously.

0: normal.

Write 1 to clear.

9-0 0x000 RO Reserved.

Bank 0 Bus Burst Length Register (0x08): BBLR

Before the burst can be sent, the burst length needs to be programmed.

Bit Default Value R/W Description

15 0 RO Reserved.

14-12 0x0 RW BRL Burst Length (for burst read and write)

000: single.

011: fixed burst read length of 4.

101: fixed burst read length of 8.

111: fixed burst read length of 16.

11-0 0x000 RO Reserved.

Bank 1: Reserved

Except Bank Select Register (0xE).

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 54 M9999-102207-1.6

Bank 2 Host MAC Address Register Low (0x00): MARL

This register along with the other two Host MAC address registers are loaded starting at word location 0x1 of the

EEPROM upon hardware reset. The software driver can modify the register, but it will not modif y the original Host MAC

address value in the EEPROM. These six bytes of Host MAC address in external EEPROM are loaded to these three

registers as mapping below:

MARL[15 :0] = EE PROM 0x 1( MAC Byte 2 and 1)

MARM[15 :0] = EE PROM 0x2(MAC Byte 4 and 3)

MARH[15: 0] = EEPRO M 0x3( MAC Byte 6 and 5)

The Host MAC address is used to define the individual destination address that the KSZ8841M responds to when

receiving frames. Network addresses are generally expressed in the form of 01:23:45:67:89:AB, where the bytes are

received from left to right, and the bits within each byte are received from right to left (LSB to MSB). For example, the

actual transmitted and received bits are on the order of 10000000 11000100 10100010 11100110 10010001 11010101.

These three registers value for Host MAC address 01:23:45:67:89:AB will be held as below:

MARL[15 :0] = 0x8 9A B

MARM[15:0] = 0x4567

MARH[15: 0] = 0x0123

The following table shows the register bit fields for Low word of Host MAC address.

Bit Default Value R/W Description

15-0 - RW

MARL MAC Address Low

The least significant word of the MAC address.

Bank 2 Host MAC Address Register Middle (0x02): MARM

The following table shows the register bit fields for middle word of Host MAC address.

Bit Default Value R/W Description

15-0 - RW

MARM MAC Address Middle

The middle word of the MAC address.

Bank 2 Host MAC Address Register High (0x04): MARH

The following table shows the register bit fields for high word of Host MAC address.

Bit Default Value R/W Description

15-0 - RW

MARH MAC Address High

The Most significant word of the MAC address.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 55 M9999-102207-1.6

Bank 3 On-Chip Bus Control Register (0x00): OBCR

This register co ntrols the on-c hip bus sp eed f or the KSZ88 41M. It is used f or po wer m anagement when the ex ternal hos t

CPU is running at a slow frequency. The default of the on-chip bus speed is 125 MHz without EEPROM. When the

external host CPU is running at a higher clock rate, the on-chip bus should be adjusted for the best performance.

Bit Default Value R/W Description

15-2 - RO Reserved.

1-0 0x0 RW

OBSC On-Chip Bus Speed Control

00: 125MHz.

01: 62.5MHz.

10: 41.66MHz.

11: 25MHz.

Note: When external EEPROM is enabled, the bit 1 in Configparm word (0x6H) is used to

contol this sp eed as below:

Bit 1 = 0 , this value will be 00 for 125 MHz.

Bit 1 = 1 , this value will be 11 for 25 MHz.

(User still can write these two bits to change speed after EEPROM data loaded)

Bank 3 EEPROM Control Register (0x02): EEPCR

To support an external EEPROM, tie the EEPROM Enable (EEEN) pin to High; otherwise, tie it to Low. If an external

EEPROM is not used, the default chip Base Address (0x300), and the software programs the host MAC address. If an

EEPROM is use d in the de sign ( EEPRO M En able pin to High), the c hip Base Addres s and host MAC addr es s are lo aded

from the EEPROM imm ediately after reset. The KSZ8841M allows the software to access (read and write) the EEPROM

directl y; that is, the EE PROM acces s timing can be f ully control led by the sof tware if the EEP ROM Soft ware Acces s bit is

set.

Bit Default Value R/W Description

15-5 - RO Reserved.

4 0 RW

EESA EEPROM Software Access

1: enable software to access EEPROM through bit 3 to bit 0.

0: disable software to access EEPROM.

3 - RO

EECB EEPROM Status Bit

Data Receive from EEPROM. This bit directly reads the EEDI pin.

2-0 0x0 RW

EECB EEPROM Control Bits

Bit 2: Data Transmit to EEPROM. This bit directly controls the device’s EEDO pin.

Bit 1: Serial Clock. This bit directly controls the device’s EESK pin.

Bit 0: Chip Select for EEPROM. This bit directly controls the device’s EECS pin.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 56 M9999-102207-1.6

Bank 3 Memory BIST Info Register (0x04): MBIR

Bit Default Value R/W Description

15-13 0x0 RO Reserved.

12 - RO TXMBF TX Memory Bist Finish

When set, it indicates the Memory Built In Self Test completion for the TX Memory.

11 - RO TXMBFA TX Memory Bist Fail

When set, it indicates the Memory Built In Self Test has failed.

10-5 - RO Reserved

4 - RO

RXMBF RX Memory Bist Finish

When set, it indicates the Memory Built In Self Test completion for the RX Memory.

3 - RO

RXMBFA RX Memory Bist Fail

When set, it indicates the Memory Built In Self Test has failed.

2-0 - RO Reserved.

Bank 3 Global Reset Register (0x06): GRR

This register controls the global reset function with information programmed by the CPU.

Bit Default Value R/W Description

15-1 0x0000 RO Reserved.

0 0 RW

Global Soft Reset

= 1 software reset is active.

= 0 software reset is inactive.

Software reset will affect PHY, MAC, QMU, DMA, and the switch core, only the BIU

(base address registers) remains unaffected by a software reset.

Bank 3 Power Management Capabilities Register (0x08): PMCR

This register is a read-only register that provides information on the K8841M power management capabilities. These

bits are automatically downloaded from Configparam word of EEPROM , if pin EEEN is high (enabled EEPROM)

Bit Default Value R/W Description

15 0 RO PME Support D3 (cold)

This bit defaults to 0, so the KSZ8841M does not support D3(cold)

14 1 RO PME Support D3 (hot)

This bit is 1 only,it is indicating that the KSZ8841M can assert PME event (PMEN pin

14) in D3(hot) power state.(see bit1:0 in PMCS register)

13 0 RO PME Support D2

If this bit is set, the wake-up signals will assert PME event (PMEN pin 14) when the

KSZ8841M is in D2 power state and PME_EN (see bit8 in PMCS register) is set.

Otherwise, the KSZ8841M does not assert PME event (PMEN pin 14) when the

KSZ8841M is in D2 power state.

The value of this bit is loaded from the PME_D2 bit of 0x6 in the serial EEPROM

(without an EEPROM, this bit defaults to 0).

12 0 RO PME Support D1

If this bit is set, the wake-up signals will assert PME event (PMEN pin 14) when the

KSZ8841M is in D1 power state and PME_EN (see bit8 in PMCS register) is set.

Otherwise, the KSZ8841M does not assert PME event (PMEN pin 14) when the

KSZ8841M is in D1 power state.

The value of this bit loaded from the PME_D1 bit of 0x6 in the serial EEPROM (without

an EEPROM, this bit defaults to 0).

11 0 RO PME Support D0

This bit defaults to 0, it is indicating that the KSZ8841M does not assert PME event

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 57 M9999-102207-1.6

Bit Default Value R/W Description

(PMEN pin 14) in D0 power state.

10 0 RO D2 Support

If this bit is set, it indicates that the KSZ8841M support D2 power state. The value of

this bit is loaded from the D2_SUP bit of 0x6 in the serial EEPROM (without an

EEPROM, this bit defaults to 0).

9 0 RO D1 Support

If this bit is set, it indicates that the KSZ8841M support D1 power state. The value of

this bit is loaded from the D1_SUP bit of 0x6 in the serial EEPROM (without an

EEPROM, this bit defaults to 0).

8-1 - RO Reserved.

0 - RO Bus Configuration (only for KSZ8841-16MQL device)

1: bus width is 16 bits.

0: bus width is 8 bits.

(this bit, ASYN_8bit, is only avaiable when EEPROM is enabled)

Bank 3 Wakeup Frame Control Register (0x0A): WFCR

This register holds control information programmed by the CPU to control the wake up frame function.

Bit Default Value R/W Description

15-8 0x00 RO Reserved.

7 0 RW MPRXE

Magic Packet RX Enable

When set, it enables the magic packet pattern detection.

When reset, the magic packet pattern detection is disabled.

6-4 0x0 RO Reserved.

3 0 RW WF3E

Wake up Frame 3 Enable

When set, it enables the Wake up frame 3 pattern detection.

When reset, the Wake up frame 3 pattern detection is disabled.

2 0 RW WF2E

Wake up Frame 2 Enable

When set, it enables the Wake up frame 2 pattern detection.

When reset, the Wake up frame 2 pattern detection is disabled.

1 0 RW WF1E

Wake up Frame 1 Enable

When set, it enables the Wake up frame 1 pattern detection.

When reset, the Wake up frame 1 pattern detection is disabled.

0 0 RW WF0E

Wake up Frame 0 Enable

When set, it enables the Wake up frame 0 pattern detection.

When reset, the Wake up frame 0 pattern detection is disabled.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 58 M9999-102207-1.6

Bank 4 Wakeup Frame 0 CRC0 Register (0x00): WF0CRC0

This register contains the expected CRC values of the Wake up frame 0 pattern.

The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard; it is taken over the bytes specified in

the wake up byte mask registers.

Bit Default Value R/W Description

15-0 0x0000 RW WF0CRC0

Wake up Frame 0 CRC (lower 16 bits)

The expected CRC value of a Wake up frame 0 pattern.

Bank 4 Wakeup Frame 0 CRC1 Register (0x02): WF0CRC1

This register contains the expected CRC values of the Wake up frame 0 pattern.

The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard; it is taken over the bytes specified in

the wake up byte mask registers.

Bit Default Value R/W Description

15-0 0 RW

WF0CRC1

Wake up Frame 0 CRC (upper 16 bits).

The expected CRC value of a Wake up frame 0 pattern.

Bank 4 Wakeup Frame 0 Byte Mask 0 Register (0x04): WF0BM0

This register contains the first 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the first byte

of the Wake up frame 0, setting bit 15 selects the 16th byte of the Wake up frame 0.

Bit Default Value R/W Description

15-0 0 RW

WF0BM0

Wake up Frame 0 Byte Mask 0

The first 16 bytes mask of a Wake up frame 0 pattern.

Bank 4 Wakeup Frame 0 Byte Mask 1 Register (0x06): WF0BM1

This register contains the next 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the 17th byte

of the Wake up frame 0. Setting bit 15 selects the 32nd byte of the Wake up frame 0.

Bit Default Value R/W Description

15-0 0 RW

WF0BM1

Wake up Frame 0 Byte Mask 1.

The next 16 bytes mask covering bytes 17 to 32 of a Wake up frame 0 pattern.

Bank 4 Wakeup Frame 0 Byte Mask 2 Register (0x08): WF0BM2

This register contains the next 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the 33rd byte

of the Wake up frame 0. Setting bit 15 selects the 48th byte of the Wake up frame 0.

Bit Default Value R/W Description

15-0 0 RW

WF0BM2

Wake-up Frame 0 Byte Mask 2.

The next 16 bytes mask covering bytes 33 to 48 of a Wake-up frame 0 pattern.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 59 M9999-102207-1.6

Bank 4 Wakeup Frame 0 Byte Mask 3 Register (0x0A): WF0BM3

This register contains the last 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the 49th byte

of the Wake up frame 0. Setting bit 15 selects the 64th by te of the Wake up frame 0.

Bit Default Value R/W Description

15-0 0 RW

WF0BM3

Wake-up Frame 0 Byte Mask 3.

The last 16 bytes mask covering bytes 49 to 64 of a Wake-up frame 0 pattern.

Bank 5 Wakeup Frame 1 CRC0 Register (0x00): WF1CRC0

This register contains the expected CRC values of the Wake up frame 1 pattern.

The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard; it is taken over the bytes specified in

the wake up byte mask registers.

Bit Default Value R/W Description

15-0 0 RW

WF1CRC0

Wake-up frame 1 CRC (lower 16 bits).

The expected CRC value of a Wake-up frame 1 pattern.

Bank 5 Wakeup Frame 1 CRC1 Register (0x02): WF1CRC1

This register contains the expected CRC values of the Wake up frame 1 pattern.

The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in

the wake up byte mask registers.

Bit Default Value R/W Description

15-0 0 RW

WF1CRC1

Wake-up frame 1 CRC (upper 16 bits).

The expected CRC value of a Wake-up frame 1 pattern.

Bank 5 Wakeup Frame 1 Byte Mask 0 Register (0x04): WF1BM0

This register contains the first 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the first byte

of the Wake up frame 1, setting bit 15 selects the 16th byte of the Wake up frame 1.

Bit Default Value R/W Description

15-0 0 RW

WF1BM0

Wake-up frame 1 Byte Mask 0.

The first 16 bytes mask of a Wake-up frame 1 pattern.

Bank 5 Wakeup Frame 1 Byte Mask 1 Register (0x06): WF1BM1

This register contains the next 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the 17th byte

of the Wake up frame 1. Setting bit 15 selects the 32nd byte of the Wake up frame 1.

Bit Default Value R/W Description

15-0 0 RW

WF1BM1

Wake-up frame 1 Byte Mask 1.

The next 16 bytes mask covering bytes 17 to 32 of a Wake-up frame 1 pattern.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 60 M9999-102207-1.6

Bank 5 Wakeup Frame 1 Byte Mask 2 Register (0x08): WF1BM2

This register contains the next 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the 33rd byte

of the Wake up frame 1. Setting bit 15 selects the 48th byte of the Wake up frame 1.

Bit Default Value R/W Description

15-0 0 RW

WF1BM2

Wake-up frame 1 Byte Mask 2.

The next 16 bytes mask covering bytes 33 to 48 of a Wake-up frame 1 pattern.

Bank 5 Wakeup Frame 1 Byte Mask 3 Register (0x0A): WF1BM3

This register contains the last 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the 49th byte

of the Wake up frame 1. Setting bit 15 selects the 64th by te of the Wake up frame 1.

Bit Default Value R/W Description

15-0 0 RW

WF1BM3

Wake-up frame 1 Byte Mask 3.

The last 16 bytes mask covering bytes 49 to 64 of a Wake-up frame 1 pattern.

Bank 6 Wakeup Frame 2 CRC0 Register (0x00): WF2CRC0

This register contains the expected CRC values of the Wake up frame 2 pattern.

The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in

the wake up byte mask registers.

Bit Default Value R/W Description

15-0 0 RW

WF2CRC0

Wake-up frame 2 CRC (lower 16 bits).

The expected CRC value of a Wake-up frame 2 pattern.

Bank 6 Wakeup Frame 2 CRC1 Register (0x02): WF2CRC1

This register contains the expected CRC values of the wake-up frame 2 pattern.

The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in

the wake up byte mask registers.

Bit Default Value R/W Description

15-0 0 RW

WF2CRC1

Wake-up frame 2 CRC (upper 16 bits).

The expected CRC value of a Wake-up frame 2 pattern.

Bank 6 Wakeup Frame 2 Byte Mask 0 Register (0x04): WF2BM0

This register contains the first 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the first byte

of the Wake up frame 2, setting bit 15 selects the 16th byte of the Wake up frame 2.

Bit Default Value R/W Description

15-0 0 RW

WF2BM0

Wake-up frame 2 Byte Mask 0.

The first 16 bytes mask of a Wake-up frame 2 pattern.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 61 M9999-102207-1.6

Bank 6 Wakeup Frame 2 Byte Mask 1 Register (0x06): WF2BM1

This register contains the next 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the 17th byte

of the Wake up frame 2. Setting bit 15 selects the 32nd byte of the Wake up frame 2.

Bit Default Value R/W Description

15-0 0 RW

WF2BM1

Wake-up frame 2 Byte Mask 1.

The next 16 bytes mask covering bytes 17 to 32 of a Wake-up frame 2 pattern.

Bank 6 Wakeup Frame 2 Byte Mask 2 Register (0x08): WF2BM2

This register contains the next 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the 33rd byte

of the Wake up frame 2. Setting bit 15 selects the 48th byte of the Wake up frame 2.

Bit Default Value R/W Description

15-0 0 RW

WF2BM2

Wake-up frame 2 Byte Mask 2.

The next 16 bytes mask covering bytes 33 to 48 of a Wake-up frame 2 pattern.

Bank 6 Wakeup Frame 2 Byte Mask 3 Register (0x0A): WF2BM3

This register contains the last 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the 49th byte

of the Wake up frame 2. Setting bit 15 selects the 64th by te of the Wake up frame 2.

Bit Default Value R/W Description

15-0 0 RW

WF2BM3

Wake-up frame 2 Byte Mask 3.

The last 16 bytes mask covering bytes 49 to 64 of a Wake-up frame 2 pattern.

Bank 7 Wakeup Frame 3 CRC0 Register (0x00): WF3CRC0

This register contains the expected CRC values of the Wake up frame 3 pattern.

The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in

the wake-up byte mask registers.

Bit Default Value R/W Description

15-0 0 RW

WF3CRC0

Wake-up frame 3 CRC (lower 16 bits).

The expected CRC value of a Wake up frame 3pattern.

Bank 7 Wakeup Frame 3 CRC1 Register (0x02): WF3CRC1

This register contains the expected CRC values of the Wake up frame 3 pattern.

The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in

the wake up byte mask registers.

Bit Default Value R/W Description

15-0 0 RW

WF3CRC1

Wake-up frame 3 CRC (upper 16 bits).

The expected CRC value of a Wake up frame 3 pattern.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 62 M9999-102207-1.6

Bank 7 Wakeup Frame 3 Byte Mask 0 Register (0x04): WF3BM0

This register contains the first 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the first byte

of the Wake up frame 3, setting bit 15 selects the 16th byte of the Wake up frame 3.

Bit Default Value R/W Description

15-0 0 RW

WF3BM0

Wake up Frame 3 Byte Mask 0

The first 16 byte mask of a Wake up frame 3 pattern.

Bank 7 Wakeup Frame 3 Byte Mask 1 Register (0x06): WF3BM1

This register contains the next 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 17th byte

of the Wake up frame 3. Setting bit 15 selects the 32nd byte of the Wake up frame 3.

Bit Default Value R/W Description

15-0 0 RW

WF3BM1

Wake up Frame 3 Byte Mask 1

The next 16 bytes mask covering bytes 17 to 32 of a Wake up frame 3 pattern.

Bank 7 Wakeup Frame 3 Byte Mask 2 Register (0x08): WF3BM2

This register contains the next 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 33rd byte

of the Wake up frame 3. Setting bit 15 selects the 48th byte of the Wake up frame 3.

Bit Default Value R/W Description

15-0 0 RW

WF3BM2

Wake up Frame 3 Byte Mask 2

The next 16 bytes mask covering bytes 33 to 48 of a Wake up frame 3 pattern.

Bank 7 Wakeup Frame 3 Byte Mask 3 Register (0x0A): WF3BM3

This register contains the last 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 49th byte

of the Wake up frame 3. Setting bit 15 selects the 64th by te of the Wake up frame 3.

Bit Default Value R/W Description

15-0 0 RW

WF3BM3

Wake up Frame 3 Byte Mask 3.

The last 16 bytes mask covering bytes 49 to 64 of a Wake up frame 3 pattern.

Bank 8 – 15: Reserved

Except Bank Select Register (0xE).

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 63 M9999-102207-1.6

Bank 16 Transmit Control Register (0x00): TXCR

This register holds control information programmed by the CPU to control the QMU transmit module function.

Bit Default Value R/W Description

15 - RO Reserved.

14-13 0x0 RW Reserved.

12-4 - RO Reserved.

3 0x0 RW

TXFCE Transmit Flow Control Enable

When this bit is set and the KSZ8841M is in full-duplex mode, flow control is enabled. The

KSZ8841M transmits a PAUSE frame when the Receive Buffer capacity reaches a threshold

level that will cause the buffer to overflow.

When this bit is set and the KSZ8841M is in half-duplex mode, back-pressure flow control is

enabled. When this bit is cleared, no transmit flow control is enabled.

2 0x0 RW

TXPE Transmit Padding Enable

When this bit is set, the KSZ8841M automatically adds a padding field to a packet shorter than

64 bytes.

Note: Setting this bit requires enabling the add CRC feature to avoid CRC errors for the

transmit packet .

1 0x0 RW

TXCE Transmit CRC Enable

When this bit is set, the KSZ8841M automatically adds a CRC checksum field to the end of a

transmit frame.

0 0x0 RW

TXE Transmit Enable

When this bit is set, the transmit module is enabled and placed in a running state. When reset,

the transmit process is placed in the stopped state after the transmission of the current frame

is completed.

Bank 16 Transmit Status Register (0x02): TXSR

This register keeps the status of the last transmitted frame.

Bit Default Value R/W Description

15 0x0 RO Reserved.

14 0x0 RO

TXUR Transmit Underrun

This bit is set when underrun occurs.

Note: This is a fatal status. Software should guarantee that no underrun condition occurred

when enabling the early transmit function. The system or the QMU requires a reset or restart

to recover from an underrun condition.

To aviod transmit underun condition, the user has to make sure that the host interface speed

(bandwidth) is faster than the ethernet port.

13 0x0 RO

TXLC Transmit Late Collision

This bit is set when a transmit Late Collision occurs.

12 0x0 RO

TXMC Transmit Maximum Collision

This bit is set when a transmit Maximum Collision is reached.

11-6 - RO Reserved.

5-0 - RO

TXFID Transmit Frame ID

This field identifies the transmitted frame. All of the transmit status information in this register

belongs to the frame with this ID.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 64 M9999-102207-1.6

Bank 16 Receive Control Register (0x04): RXCR

This register holds control information programmed by the CPU to control the receive function.

Bit Default Value R/W Description

15-11 - RO Reserved.

10 0x0 RW

RXFCE Receive Flow Control Enable

When this bit is set and the KSZ8841M is in full-duplex mode, flow control is enabled, and the

KSZ8841M will acknowledge a PAUSE frame from the receive interface; i.e., the outgoing

packets are pending in the transmit buffer until the PAUSE frame control timer expires. This

field has no meaning in half-duplex mode and should be programmed to 0.

When this bit is cleared, flow control is not enabled.

9 0x0 RW

RXEFE Receive Error Frame Enable

W hen this bit is set, CRC error frames are allowed to be received into the RX queue.

When this bit is cleared, all CRC error frames are discarded.

8 - RO Reserved.

7 0x0 RW

RXBE Receive Broadcast Enable

When this bit is set, the RX module receives all the broadcast frames.

6 0x0 RW

RXME Receive Multicast Enable

When this bit is set, the RX module receives all the multicast frames (including broadcast

frames).

5 0x0 RW

RXUE Receive Unicast

When this bit is set, the RX module receives unicast frames that match the 48-bit Station MAC

address of the module.

4 0x0 RW

RXRA Receive All

When this bit is set, the KSZ8841M receives all incoming frames, regardless of the frame’s

destinat ion addr es s.

3 0x0 RW

RXSCE Receive Strip CRC

When this bit is set, the KSZ8841M strips the CRC on the received frames. Once cleared, the

CRC is stored in memory following the packet.

2 0x0 RW

QMU Receive Multicast Hash-Table Enable

When this bit is set, this bit enables the RX function to receive multicast frames that pass the

CRC Hash filtering mechanism.

1 - RO Reserved.

0 0x0 RW

RXE Receive Enable

When this bit is set, the RX block is enabled and placed in a running state.

When this bit is cleared, the receive process is placed in the stopped state upon completing

reception of the current frame.

Bank 16 TXQ Memory Information Register (0x08): TXMIR

This register indicates the amount of free memory available in the TXQ of the QMU module.

Bit Default Value R/W Description

15-13 - RO Reserved.

12-0 - RO

TXMA Transmit Memory Available

The amount of memory available is represented in units of byte. The TXQ memory is used for

both frame payload, control word.

Note: Software must be written to ensure that there is enough memory for the next transmit

frame including control information before transmit data is written to the TXQ.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 65 M9999-102207-1.6

Bank 16 RXQ Memory Information Register (0x0A): RXMIR

This register indicates the amount of receive data available in the RXQ of the QMU module.

Bit Default Value R/W Description

15-13 - RO Reserved.

12-0 - RO

RXMA Receive Packet Data Available

The amount of Receive packet data available is represented in units of byte. The RXQ

memory is used for both frame payload, status word. There is total 4096 bytes in RXQ. This

counter will update after a complete packet is received and also issues an interrupt when

receive interrupt enable IER[13] in Bank 18 is set.

Note: Software must be written to empty the RXQ memory to allow for the new RX frame. If

this is not done, the frame may be discarded as a result of insufficient RXQ memory.

Bank 17 TXQ Command Register (0x00): TXQCR

This register is programmed by the Host CPU to issue a transmit command to the TXQ. The present transmit frame in

the TXQ memory is queued for transmit.

Bit Default Value R/W Description

15-1 - RO Reserved

0 0x0 RW

TXETF Enqueue TX Frame

When this bit is written as 1, the current TX frame prepared in the TX buffer is queued for

transmit.

Note: This bit is self-clearing after the frame is finished transmitting. The software should wait

for the bit to be cleared before setting up another new TX frame.

Bank 17 RXQ Command Register (0x02): RXQCR

This register is programmed by the Host CPU to issue release command to the RXQ. The current frame in the RXQ

frame buffer is read only by the host and the memory space is released.

Bit Default Value R/W Description

15-1 - RO Reserved.

0 0x0 RW

RXRRF Release RX Frame

When this bit is written as 1, the current RX frame buffer is released.

Note: This bit is self-clearing after the frame memory is released. The software should wait for

the bit to be cleared before processing new RX frame.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 66 M9999-102207-1.6

Bank 17 TX Frame Data Pointer Register (0x04): TXFDPR

The value of this register determines the address to be accessed within the TXQ frame buffer. When the AUTO increment

is set, It will automatically increment the pointer value on Write accesses to the data register.

The counter is incremented by one for every byte access, by two for every word access, and by four for every double

word access.

Bit Default Value R/W Description

15 - RO Reserved.

14 0x0 RW

TXFPAI TX Frame Data Pointer Auto Increment

When this bit is set, the TX Frame data pointer register increments automatically on accesses

to the data register. The increment is by one for every byte access, by two for every word

access, and by four for every doubleword access.

When this bit is reset, the TX frame data pointer is manually controlled by user to access the

TX frame location.

13-11 - RO Reserved.

10-0 0x000 RW

TXFP TX Frame Pointer

TX Frame Pointer index to the Frame Data register for access.

This field reset to next available TX frame location when the TX Frame Data has been

enqueued through the TXQ command register.

Bank 17 RX Frame Data Pointer Register (0x06): RXFDPR

The value of this register determines the address to be accessed within the RXQ frame buffer. When the Auto Increment

is set, it will automatically increment the RXQ Pointer on read accesses to the data register.

The counter is incremented is by one for every byte access, by two for every word access, and by four for every double

word access.

Bit Default Value R/W Description

15 - RO Reserved.

14 0x0 RW

RXFPAI RX Frame Pointer Auto Increment

When this bit is set, the RXQ Address register increments automatically on accesses to the

data register. The increment is by one for every byte access, by two for every word access,

and by four for every double word access.

When this bit is reset, the RX frame data pointer is manually controlled by user to access the

RX frame location.

13-11 - RO Reserved.

10-0 0x000 RW

RXFP RX Frame Pointer

RX Frame data pointer index to the Data register for access.

This field reset to next available RX frame location when RX Frame release command is

issued (through the RXQ command register).

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 67 M9999-102207-1.6

Bank 17 QMU Data Register Low (0x08): QDRL

This register QDRL(0x08-0x09) contains the Low data word presently addressed by the pointer register. Reading maps

from the RXQ, and writing maps to the TXQ.

Bit Default Value R/W Description

15-0 - RW

QDRL Queue Data Register Low

This register is mapped into two uni-directional buffers for 16-bit buses, and one uni-directional

buffer for 32-bit buses, (TXQ when Write, RXQ when Read) that allow moving words to and

from the KSZ8841M regardless of whether the pointer is even, odd, or Dword aligned. Byte,

word, and Dword access can be mixed on the fly in any order. This register along with DQRH

is mapped into two consecutive word locations for 16-bit buses, or one word location for 32-bit

buses, to facilitate Dword move operations.

Bank 17 QMU Data Register High (0x0A): QDRH

This register QDRH(0x0A-0x0B) contains the High data word presently addressed by the pointer register. Reading maps

from the RXQ, and writing maps to the TXQ.

Bit Default Value R/W Description

15-0 - RW

QDRL Queue Data Register High

This register is mapped into two uni-directional buffers for 16-bit buses, and one uni-directional

buffer for 32-bit buses, (TXQ when Write, RXQ when Read) that allow moving words to and

from the KSZ8841M regardless of whether the pointer is even, odd, or dword aligned. Byte,

word, and Dword access can be mixed on the fly in any order. This register along with DQRL

is mapped into two consecutive word locations for 16-bit buses, or one word location for 32-bit

buses, to facilitate Dword move operations.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 68 M9999-102207-1.6

Bank 18 Interrupt Enable Register (0x00): IER

This register enables the interrupts from the QMU and other sources.

Bit Default Value R/W Description

15 0x0 RW

LCIE Link Change Interrupt Enable

When this bit is set, the link change interrupt is enabled.

When this bit is reset, the link change interrupt is disabled.

14 0x0 RW

TXIE Transmit Interrupt Enable

When this bit is set, the transmit interrupt is enabled.

When this bit is reset, the transmit interrupt is disabled.

13 0x0 RW

RXIE Receive Interrupt Enable

When this bit is set, the receive interrupt is enabled.

When this bit is reset, the receive interrupt is disabled.

12 0x0 RW

TXUIE Transmit Underrun Interrupt Enable

When this bit is set, the transmit underrun interrupt is enabled.

When this bit is reset, the transmit underrun interrupt is disabled.

11 0x0 RW

RXOIE Receive Overrun Interrupt Enable

When this bit is set, the Receive Overrun interrupt is enabled.

When this bit is reset, the Receive Overrun interrupt is disabled.

10 0x0 RW

RXEIE Receive Early Receive Interrupt Enable

When this bit is set, the Early Receive interrupt is enabled.

When this bit is reset, the Early Receive interrupt is disabled.

9 0x0 RW

TXPSIE Transmit Process Stopped Interrupt Enable

When this bit is set, the Transmit Process Stopped interrupt is enabled.

When this bit is reset, the Transmit Process Stopped interrupt is disabled.

8 0x0 RW

RXPSIE Receive Process Stopped Interrupt Enable

When this bit is set, the Receive Process Stopped interrupt is enabled.

When this bit is reset, the Receive Process Stopped interrupt is disabled.

7 0x0 RW

RXEFIE Receive Error Frame Interrupt Enable

When this bit is set, the Receive error frame interrupt is enabled.

When this bit is reset, the Receive error frame interrupt is disabled.

6-0 - RO Reserved.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 69 M9999-102207-1.6

Bank 18 Interrupt Status Register (0x02): ISR

This register contains the status bits for all QMU and other interrupt sources.

When the corresponding enable bit is set, it causes the interrupt pin to be asserted.

This register is usually read by the host CPU and device drivers during interrupt service routine or polling. The register

bits are not cleared when read. The user has to write “1” to clear

Bit Default Value R/W Description

15 0x0 RO

(W1C) LCIS Link Change Interrupt Status

When this bit is set, it indicates that the link status has changed from link up to link down, or

link down to link up.

This edge-triggered interrupt status is cleared by writing 1 to this bit.

14 0x0 RO

(W1C) TXIS Transmit Status

When this bit is set, it indicates that the TXQ MAC has transmitted at least a frame on the

MAC interface and the QMU TXQ is ready for new frames from the host.

This edge-triggered interrupt status is cleared by writing 1 to this bit.

13 0x0 RO

(W1C) RXIS Receive Interrupt Status

When this bit is set, it indicates that the QMU RXQ has received a frame from the MAC

interface and the frame is ready for the host CPU to process.

This edge-triggered interrupt status is cleared by writing 1 to this bit.

12 0x0 RO

(W1C) TXUIS Transmit Underrun Interrupt Status

When this bit is set, it indicates that the transmit underrun condition has occurred.

This edge-triggered interrupt status is cleared by writing 1 to this bit.

11 0x0 RO

(W1C) RXOIS Receive Overrun Interrupt Status

When this bit is set, it indicates that the Receive Overrun status has occurred.

This edge-triggered interrupt status is cleared by writing 1 to this bit.

10 0x0 RO

(W1C) RXEIS Receive Early Receive Interrupt Status

When this bit is set, it indicates that the Early Receive status has occurred.

This edge-triggered interrupt status is cleared by writing 1 to this bit.

9 0x1 RO

(W1C) TXPSIE Transmit Process Stopped Status

When this bit is set, it indicates that the Transmit Process has stopped.

This edge-triggered interrupt status is cleared by writing 1 to this bit.

8 0x1 RO

(W1C) RXPSIE Receive Process Stopped Status

When this bit is set, it indicates that the Receive Process has stopped.

This edge-triggered interrupt status is cleared by writing 1 to this bit.

7 0x0 RO

(W1C) RXEFIE Receive Error Frame Interrupt Status

When this bit is set, it indicates that the Receive error frame status has occurred.

This edge-triggered interrupt status is cleared by writing 1 to this bit.

6-0 - RO Reserved.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 70 M9999-102207-1.6

Bank 18 Receive Status Register (0x04): RXSR

This register indicates the status of the current received frame and mirrors the Receive Status word of the Receive

Frame in the RXQ.

Bit Default Value R/W Description

15 - RO

RXFV Receive Frame Valid

When set, it indicates that the present frame in the receive packet memory is valid. The status

information currently in this location is also valid.

When clear, it indicates that there is either no pending receive frame or that the current frame

is still in the process of receiving.

14-8 - RO Reserved.

7 - RO

RXBF Receive Broadcast Frame

When set, it indicates that this frame has a broadcast address.

6 - RO

RXMF Receive Multicast Frame

When set, it indicat es that thi s frame ha s a multic ast address (including the broad cast

address).

5 - RO

RXUF Receive Unicast Frame

When set, it indicates that this frame has a unicast address.

4 - RO

RXMR Receive MII Error

When set, it indicates that there is an MII symbol error on the received frame.

3 - RO

RXFT Receive Frame Type

When set, it indicates that the frame is an Ethernet-type frame (frame length is greater than

1500 bytes).

When clear, it indicate that the frame is an IEEE 802.3 frame.

This bit is not valid for runt frames.

2 - RO

RXTL Receive Frame Too Long

When set, it indicates that the frame length exceeds the maximum size of 1916 bytes. Frames

that are too long are passed to the host only if the pass bad frame bit is set (bit 9 in RXCR

Note: Frame too long is only a frame length indication and does not cause any frame

truncation.

1 - RO

RXRF Receive Runt Frame

When set, it indicates that a frame was damaged by a collision or premature termination

before the collision wi ndow has passed. Runt frames are passed to the host only if the pass

bad frame bit is set (bit 9 in RXCR register).

0 - RO

RXCE Receive CRC Error

When set, it indicates that a CRC error has occurred on the current received frame. A CRC

error frame is passed to the host only if the pass bad frame bit is set (bit 9 in RXCR register)

Bank 18 Receive Byte Count Register (0x06): RXBC

This register indicates the status of the current received frame and mirrors the Receive Byte Count word of the Receive

Frame in the RXQ.

Bit Default Value R/W Description

15-11 - RO Reserved.

10-0 - RO

RXBX Receive Byte Count

Receive byte count.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 71 M9999-102207-1.6

Bank 18 Early Transmit Register (0x08): ETXR

This register specifies the threshold for the early transmit.

Bit Default Value R/W Description

15-8 - RO Reserved.

7 0x0 RW

TXEE Early Transmit Enable

When this bit is set, the Early Transmit function is enabled.

When this bit is cleared, normal operation is assumed.

6-5 - RO Reserved.

4-0 0x00 RW

ETXTH Early Transmit Threshold

The threshold for Early Transmit. Specified in unit of 64-byte. Whenever the number of bytes

written in memory for the presently transmitting packet exceeds the threshold, Early Transmit

will be started on the network interface.

When early transmit is enabled, setting this field to 0 is invalid, and the hardware behavior is

unknown.

Bank 18 Early Receive Register (0x0A): ERXR

This register specify the threshold for early receive and interrupt condition.

Bit Default Value R/W Description

15-8 - RO Reserved.

7 0x0 RW

RXEE Early Receive Enable

When this bit is set, the Early Receive function is enabled.

When this bit is cleared, normal operation is assumed.

6-5 - RO Reserved.

4-0 0x1F RW

ERXTH Early Receive Threshold

The threshold for Early Receive and Interrupt. Specified in unit of 64-byte. Whenever the

number of bytes written in memory for the presently received packet exceeds the threshold,

early receive status will be set, and Early Receive interrupt will be asserted if its interrupt is

enabled.

When early receive is enabled, setting this field to 0 is invalid, and the hardware behavior is

unknown.

Bank 19 Multicast Table Register 0 (0x00): MTR0

The 64-bit multicast table is used for group address filtering. This value is defined as the six most significant bits from

CRC circuit calculation result that is based on 48-bit of DA input. The two most significant bits select one of the four

registers to be used, while the other s determine which bit with in the regis t er .

Multicast table register 0.

Bit Default Value R/W Description

15-0 0x0 RW

MTR0 Multicast Table 0

W hen the appropriate bit is set, if the packet received with DA matches the CRC, the hashing

function is received without being filtered.

When the appropriate bit is cleared, the packet will drop.

Note: When the receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR, all

multicast addresses are received regardless of the multicast table value.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 72 M9999-102207-1.6

Bank 19 Multicast Table Register 1 (0x02): MTR1

Multicast table register 1.

Bit Default Value R/W Description

15-0 0x0 RW

MTR0 Multicast Table 1

W hen the appropriate bit is set, if the packet received with DA matches the CRC, the hashing

function is received without being filtered.

When the appropriate bit is cleared, the packet will drop.

Note: When the receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR, all

multicast addresses are received regardless of the multicast table value.

Bank 19 Multicast Table Register 2 (0x04): MTR2

Multicast table register 2.

Bit Default Value R/W Description

15-0 0x0 RW

MTR0 Multicast Table 2

W hen the appropriate bit is set, if the packet received with DA matches the CRC, the hashing

function is received without being filtered.

When the appropriate bit is cleared, the packet will drop.

Note: When the receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR, all

multicast addresses are received regardless of the multicast table value.

Bank 19 Multicast Table Register 3 (0x06): MTR3

Multicast table register 3.

Bit Default Value R/W Description

15-0 0x0 RW

MTR0 Multicast Table 3

W hen the appropriate bit is set, if the packet received with DA matches the CRC, the hashing

function is received without being filtered.

When the appropriate bit is cleared, the packet will drop.

Note: When the receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR, all

multicast addresses are received regardless of the multicast table value.

Bank 19 Power Management Control and Status Register (0x08): P MCS

The following control and status register provides information on the KSZ8841M power management capabilities. The

following table shows the register bit fields.

Bit Default Value R/W Description

15 0 RO

(W1C) PME_Status

This bit indicates that the KSZ8841M has detected a power-management event. If bit

PME_Enable is set, the KSZ8841M also asserts the PMEN pin. This bit is cleared on power-

up reset or by write 1. It is not modified by either hardware or software reset. When this bit is

cleared, the KSZ8841M deasserts the PMEN pin.

14-9 0x00 RO Reserved.

8 0 RW

PME_Enable

If this bit is set, the KSZ8841M can assert the PMEN pin. Otherwise, assertion of the PMEN

pin is disabled.

This bit is cleared on power-up reset and will be not modified by software reset.

7-4 0x0 RO Reserved.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 73 M9999-102207-1.6

Bit Default Value R/W Description

3 0 RO

No Soft Reset

If this bit is set (“1”), the KSZ8841M does not perform an internal reset when transitioning from

D3_hot to D0 because of PowerState commands. Configuration context is preserved. Upon

transition from D3_hot to the D0 Initialized state, no additional operating system intervention is

required to preserve configuration context beyond writing the PowerState bits.

If this bit is cleared (“0”), the KSZ8841M does perform an internal reset when transitioning

from D3_hot to D0 via software control of the PowerState bits. Configuration context is lost

when performing the soft reset. Upon transition from D3_hot to the D0 state, full reinitialization

sequence is needed to return the device to D0 Initialized.

Regardless of this bit, devices that transition from D3_hot to D0 by a system or bus segment

reset will return to the device state D0 Uninitialized with only PME context preserved if PME is

supported and enabled.

The value of this bit is loaded from the NO_SRST bit in the serial EEPROM.

2 0 RO Reserved.

1-0 0x0 RW

Power State

This field is used to set the new power state of the KSZ8841M as well as to determine its

current power state. The definitions of the field values are:

00: D0 -> System is on and running

01: D1 -> Low-power state

10: D2 -> Low-power state

11: D3 (hot) -> System is off and not running

Banks 20 – 31: Reserved

Except Bank Select Register (0xE).

Bank 32 Chip ID and Enable Register (0x00): CIDER

This register contains the chip ID and the chip enable bit.

Bit Default R/W Description

15-8 0x88 RO

Family ID

Chip family ID

7-4 0x1 RO

Chip ID

0x1 is assigned to KSZ8841M

3-1 0x1 RO

Revision ID

0 0 RO Reserved.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 74 M9999-102207-1.6

Bank 32 Chip Global Control Register (0x0A): CGCR

This register contains the global control for the chip function.

Bit Default R/W Description

15 0 RW

LEDSEL1

See description for bit 9.

14-12 0 RW Reserved.

11-10 0x2 RW Reserved.

9 0 RW

LEDSEL0

This register bit sets the LEDSEL0 selection only.

Port 1 LED indicators, defined as below:

[LEDSEL1, LEDSEL0]

[0, 0] [0, 1]

P1LED3 ------ ------

P1LED2 LINK/ACT 100LINK/ACT

P1LED1 FULL_DPX/COL 10LINK/ACT

P1LED0 SPEED FULL_DPX

[LEDSEL1, LEDSEL0]

[1, 0] [1, 1]

P1LED3 ACT ------

P1LED2 LINK ------

P1LED1 FULL_DPX/COL ------

P1LED0 SPEED ------

8 0 R/W Reserved.

7-0 0x35 RW Reserved.

Banks 33 – 41: Reserved

Except Bank Select Register (0xE)

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 75 M9999-102207-1.6

Bank 42 Indirect Access Control Register (0x00): IACR

This register contains the indirect control for the MIB counter (Write IACR triggers a command. Read or write access is

determined by register bit 12).

Bit Default R/W Description

15-13 0x0 RW Reserved.

12 0 RW

Read High. Write Low

1 = read cycle.

0 = write cycle.

11-10 0x0 RW Table Select

00 = reserved.

01 = reserved.

10 = reserved.

11 = MIB counter selected.

9-0 0x000 RW

Indirect Address

Bit 9-0 of indirect address.

Bank 42 Indirect Access Data Register 1 (0x02): IADR1

This register contains the indirect data for the chip function.

Bit Default R/W Description

15-0 0x0000 RO Reserved.

Bank 42 Indirect Access Data Register 2 (0x04): IADR2

This register contains the indirect data for the chip function.

Bit Default R/W Description

15-0 0x0000 RO Reserved.

Bank 42 Indirect Access Data Register 3 (0x06): IADR3

This register contains the indirect data for the chip function.

Bit Default R/W Description

15-0 0x0000 RO Reserved.

Bank 42 Indirect Access Data Register 4 (0x08): IADR4

This register contains the indirect data for the chip function.

Bit Default R/W Description

15-0 0x0000 RW

Indirect Data

Bit 15-0 of indirect data.

Bank 42 Indirect Access Data Register 5 (0x0A): IADR5

This register contains the indirect data for the chip function.

Bit Default R/W Description

15-0 0x0000 RW

Indirect Data

Bit 31-16 of indirect data.

Bank 43– 44: Reserved

Except Bank Select Register (0xE)

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 76 M9999-102207-1.6

Bank 45 PHY 1 MII-Register Basic Control Register (0x00): P1M BCR

This register contains Media Independent Interface (MII) register for port 1 as defined in the IEEE 802.3 specification.

Bit Default R/W Description Bit is same as:

15 0 RO

Soft reset

Not supported.

14 0 RW Reserved.

13 0 RW

Force 100

1 = force 100Mbps if AN is disabled (bit 12)

0 = force 10Mbps if AN is disabled (bit 12)

Bank49 0x2 bit6

12 1 RW

AN Enable

1 = auto-negotiation enabled.

0 = auto-negotiation disabled.

Bank49 0x2 bit7

11 0 RW

Power-Down

1 = power-down.

0 = normal operation.

Bank49 0x2 bit11

10 0 RO

Isolate

Not supported.

9 0 RW

Restart AN

1 = restart auto-negotiation.

0 = normal operation.

Bank49 0x2 bit13

8 0 RW

Force Full Duplex

1 = force full duplex

0 = force half duplex.

if AN is disabled (bit 12) or AN is enabled but

failed.

Bank49 0x2 bit5

7 0 RO

Collision test

Not supported.

6 0 RO Reserved.

5 1 R/W

HP_mdix

1 = HP Auto MDI-X mode.

0 = Micrel Auto MDI-X mode.

Bank49 0x4 bit15

4 0 RW

Force MDI-X

1 = force MDI-X.

0 = normal operation.

Bank49 0x2 bit9

3 0 RW

Disable MDI-X

1 = disable auto MDI-X.

0 = normal operation.

Bank49 0x2 bit10

2 0 RW Reserved. Bank49 0x2 bit12

1 0 RW

Disable Transmit

1 = disable transmit.

0 = normal operation.

Bank49 0x2 bit14

0 0 RW

Disable LED

1 = disable LED.

0 = normal operation.

Bank49 0x2 bit15

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 77 M9999-102207-1.6

Bank 45 PHY 1 MII-Register Basic Status Register (0x02): P1MBSR

This register contains the MII register status for the chip function.

Bit Default R/W Description Bit is same as:

15 0 RO

T4 Capable

1 = 100 BASE-T4 capable.

0 = not 100 BASE-T4 capable.

14 1 RO 100 Full Capable

1 = 100BASE-TX full-duplex capable.

0 = not 100BASE-TX full duplex.capable.

13 1 RO

100 Half Capable

1= 100BASE-TX half-duplex capable.

0= not 100BASE-TX half-duplex capable.

12 1 RO

10 Full Capable

1 = 10BASE-T full-duplex capable.

0 = not 10BASE-T full-duplex capable.

11 1 RO

10 Half Capable

1 = 10BASE-T half-duplex capable.

0 = not 10BASE-T half-duplex capable.

10-7 0 RO Reserved.

6 0 RO

Preamble suppressed

Not supported.

5 0 RO

AN Complete

1 = auto-negotiation complete.

0 = auto-negotiation not completed.

Bank49 0x4 bit6

4 0 RO Reserved Bank49 0x4 bit8

3 1 RO

AN Capable

1 = auto-negotiation capable.

0 = not auto-negotiation capable.

2 0 RO

Link Status

1 = link is up.

0 = link is down.

Bank49 0x4 bit5

1 0 RO

Jabber test

Not supported.

0 0 RO

Extended Capable

1 = extended register capable.

0 = not extended register capable.

Bank 45 PHY 1 PHYID Low Register (0x04): PHY1ILR

This register contains the PHY ID (low) for the chip.

Bit Default R/W Description

15-0 0x1430 RO

PHYID Low

Low order PHYID bits.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 78 M9999-102207-1.6

Bank 45 PHY 1 PHYID High Re gister (0x06): PHY1IHR

This register contains the PHY ID (high) for the chip.

Bit Default R/W Description

15-0 0x0022 RO

PHYID High

High order PHYID bits.

Bank 45 PHY 1 Auto-Negotiation Advertisement Register (0x08): P1ANAR

This register contains the auto-negotiation advertisement for the PHY function.

Bit Default R/W Description Bit is same as:

15 0 RO

Not supported.

14 0 RO Reserved

13 0 RO

Remote fault

Not supported.

12-11 0 RO Reserved

10 1 RW

Pause (flow control capability)

1 = advertise pause capability.

0 = do not advertise pause capability.

Bank49 0x2 bit4

9 0 RW Reserved.

8 1 RW

Adv 100 Full

1 = advertise 100 full-duplex capability.

0 = do not advertise 100 full-duplex capability

Bank49 0x2 bit3

7 1 RW

Adv 100 Half

1= advertise 100 half-dup lex capability .

0 = do not advertise 100 half-duplex capability.

Bank49 0x2 bit2

6 1 RW

Adv 10 Full

1 = advertise 10 full-duplex capability.

0 = do not advertise 10 full-duplex capability.

Bank49 0x2 bit1

5 1 RW

Adv 10 Half

1 = advertise 10 half-duplex capability.

0 = do not advertise 10 half-duplex capability.

Bank49 0x2 bit0

4-0 0x01 RO

Selector Field

802.3

Bank 45 PHY 1 Auto-Negotiation Link Partner Ability Register (0x0A): P1ANLPR

This register contains the auto-negotiation link partner ability for the chip function.

Bit Default R/W Description Bit is same as:

15 0 RO

Not supported.

14 0 RO

LP ACK

Not supported.

13 0 RO

Remote fault

Not supported.

12-11 0 RO Reserved

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 79 M9999-102207-1.6

Bit Default R/W Description Bit is same as:

10 0 RO

Pause

Link partner pause capability. Bank49 0x4 bit4

9 0 RO Reserved.

8 0 RO

Adv 100 Full

Link partner 100 full capability. Bank49 0x4 bit3

7 0 RO

Adv 100 Half

Link partner 100 half capability. Bank49 0x4 bit2

6 0 RO

Adv 10 Full

Link partner 10 full capability. Bank49 0x4 bit1

5 0 RO

Adv 10 Half

Link partner 10 half capability. Bank49 0x4 bit0

4-0 0x01 RO Reserved.

Bank 46: Reserved

Except Bank Select Register (0xE)

Bank 47 PHY1 LinkMD Control/Status (0x00): P1VCT

This register contains the LinkMD control and status information of PHY 1.

Bit Default R/W Description Bit is same as:

15 0 RW

(Self-

Clear)

Vct_enable

1 = cable diagnostic test is enabled. It is self-cleared

after the VCT test is done.

0 = indicates that the cable diagnostic test is completed

and the status information is valid for read.

Bank49 0x0 bit 12

14-13 0 RO Vct_result

[00] = normal conditi on.

[01] = open condition detected in the cable.

[10] = short condition detected in the cable.

[11] = cable diagnostic test failed.

Bank49 0x0 bit 14-13

12 - RO

Vct 10M Short

1 = Less than 10m short. Bank49 0x0 bit 15

11-9 0x0 RO Reserved.

8-0 0x000 RO

Vct_fault_count

Distance to the fault. The dis ta nce is approximately

0.4m*vct_fault_count.

Bank49 0x0 bit 8-0

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 80 M9999-102207-1.6

Bank 47 PHY1 Special Control/Status Register (0x02): P1PHYCTRL

This register contains the control and status information of PHY1.

Bit Default R/W Description Bit is same as:

15-6 0x000 RO Reserved.

5 0 RO

Polarity Reverse (polrvs)

1 = polarity is reversed.

0 = polarity is not reversed.

Bank49 0x04 bit13

4 0 RO

MDIX Status (mdix_st)

1 = MDI

0 = MDIX

Bank49 0x04 bit7

3 0 RW

Force Link (force_lnk)

1 = force link pass.

0 = normal operation.

Bank49 0x00 bit11

2 1 RW

Power S aving (pwrsave)

1 = disable power saving.

0 = enable power saving.

Bank49 0x00 bit10

1 0 RW

Remote (Near-end) Loopback (rlb)

1 = perform remote loopback at PHY (RXP1/RXM1 ->

TXP1/TXM1, see Figure 12)

0 = normal operation

Bank49 0x00 bit9

0 0 RW Reserved.

Bank 48: Reserved

Except Bank Select Register (0xE)

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 81 M9999-102207-1.6

Bank 49 Port 1 PHY Special Control/Status, LinkMD (0x00): P1SCSLMD

Bit Default R/W Description Is same as:

15 0 RO

Vct_10m_short

1 = Less than 10 meter short. Bank 47 0x00 bit 12

14-13 0 RO Vct_result

VCT result.

[00] = normal conditi on.

[01] = open condition has been detected in cable.

[10] = short condition has been detected in cable.

[11] = cable diagnostic test is failed.

Bank 47 0x00 bit 14-13

12 0 RW

(Self-

Clear)

Vct_en

Vct enable.

1 = the cable diagnostic test is enabled. It is self-

cleared after the VCT test is done.

0 = it indicates the cable diagn ostic test is completed

and the status information is valid for read.

Bank 47 0x00 bit 15

11 0 RW

Force_lnk

Force link.

1 = force link pass.

0 = normal operation.

Bank 47 0x02 bit 3

10 1 RW

pwrsave

Power-saving.

1 = disable power saving.

0 = enable power saving.

Bank 47 0x02 bit 2

9 0 RW

Remote (Near-end) loopback (rlb)

1 = perform remote loopback at PHY

(RXP1/RXM1 -> TXP1/TXM1, see Figure 12)

0 = normal operation

Bank 47 0x02 bit 1

8-0 0x000 RO

Vct_fault_count

VCT fault count.

Distance to the fault. It’s approximately

0.4m*vct_fault_count.

Bank 47 0x00 bit 8-0

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 82 M9999-102207-1.6

Bank 49 Port 1 Control Register 4 (0x02): P1CR4

This register contains the global per port control for the chip function.

Bit Default R/W Description Bit is same as:

15 0 RW

LED Off

1 = Turn off all of the port 1 LEDs (P1LED3, P1LED2,

P1LED1, P1LED0). These pins are driven high if this bit

is set to one.

0 = normal operation.

Bank 45 0x00 bit 0

14 0 RW

Txids

1 = disable the port’s transmitter.

0 = normal operation.

Bank45 0x00 bit 1

13 0 RW

Restart AN

1 = restart auto-negotiation.

0 = normal operation.

Bank 45 0x00 bit 9

12 0 RW Reserved Bank 45 0x00 bit 2

11 0 RW

Power Down

1 = power down.

0 = normal operation.

Bank 45 0x00 bit 11

10 0 RW

Disable auto MDI/MDI-X

1 = disable auto MDI/MDI-X function.

0 = enable auto MDI/MDI-X function.

Bank 45 0x00 bit 3

9 0 RW

Force MDI-X

1= if auto MDI/MDI-X is disabled, force PHY into MDI-X

mode.

0 = do not force PHY into MDI-X mode.

Bank 45 0x00 bit 4

8 0 RW Reserved

7 1 RW

Auto Negotiation Enable

1 = auto negotiation is enabled.

0 = disable auto negotiation , speed, and dup lex are

decided by bits 6 and 5 of the same register.

Bank 45 0x00 bit 12

6 0 RW

Force Speed

1 = force 100BT if AN is disabled (bit 7).

0 = force 10BT if AN is disabled (bit 7).

Bank 45 0x00 bit 13

5 0

RW Force Duplex

1 = force full duplex if (1) AN is disabled or (2) AN is

enabled but failed.

0 = force half duplex if (1) AN is disabled or (2) AN is

enabled but failed.

Bank 45 0x00 bit 8

4 1 RW

Advertised flow control capability.

1 = advertise flow control (pause) capability.

0 = suppress flow control (pause) capability from

transmission to link partner.

Bank 45 0x08 bit 10

3 1 RW

Advertised 100BT full-duplex capability.

1 = advertise 100BT full-duplex capability.

0 = suppress 100BT full-duplex capability from

transmission to link partner.

Bank 45 0x08 bit 8

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 83 M9999-102207-1.6

Bit Default R/W Description Bit is same as:

2 1 RW

Advertised 100BT half-duplex capability.

1 = advertise 100BT half-duplex capability.

0 = suppress 100BT half-duplex capability from

transmission to link partner.

Bank 45 0x08 bit 7

1 1 RW

Advertised 10BT full-duplex capability.

1 = advertise 10BT full-duplex capability.

0 = suppress 10BT full-duplex capability from

transmission to link partner.

Bank 45 0x08 bit 6

0 1 RW

Advertised 10BT half-duplex capability.

1 = advertise 10BT half-duplex capability.

0 = suppress 10BT half-duplex capability from

transmission to link partner.

Bank 45 0x08 bit 5

Bank 49 Port 1 Status Register (0x04): P1SR

This register contains the global per port status for the chip function.

Bit Default R/W Description Bit is same as:

15 1 RW

HP_mdix

1 = HP Auto MDI-X mode.

0 = Micrel Auto MDI-X mode.

Bank 45 0x00 bit 5

14 0 RO Reserved

13 0 RO

Polarity Reverse

1 = polarity is reversed.

0 = polarity is not reversed.

Bank 47 0x02 bit 5

12 0 RO

Receive Flow Control Enable

1 = receive flow control feature is active.

0 = receive flow control feature is inactive.

11 0 RO

Transmit Flow Control Enable

1 = transmit flow control feature is active.

0 = transmit flow control feature is inactive.

10 0 RO

Operation Speed

1 = link speed is 100Mbps.

0 = link speed is 10Mbps.

9 0 RO

Operation Duplex

1 = link duplex is full.

0 = link duplex is half.

8 0 RO Reserved Bank 45 0x02 bit 4

7 0 RO

MDI-X status

1 = MDI.

0 = MDI-X.

Bank 47 0x02 bit 4

6 0 RO

AN Done

1 = AN done.

0 = AN not done.

Bank 45 0x02 bit 5

5 0 RO

Link Good

1= link good. Bank 45 0x02 bit 2

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 84 M9999-102207-1.6

Bit Default R/W Description Bit is same as:

0 = link not good.

4 0 RO

Partner flow control capability.

1 = link partner flow control (pause) capable.

0 = link partner not flow control (pause) capable.

Bank 45 0x0A bit 10

3 0 RO

Partner 100BT full-duplex capability.

1 = link partner 100BT full-duplex capable.

0 = link partner not 100BT full-duplex capable.

Bank 45 0x0A bit 8

2 0 RO

Partner 100BT half-duplex capability.

1 = link partner 100BT half-duplex capable.

0= link partner not 100BT half-duplex capable.

Bank 45 0x0A bit 7

1 0 RO

Partner 10BT full-duplex capability.

1= link partner 10BT full-duplex capable.

0 = link partner not 10BT full-duplex capable.

Bank 45 0x0A bit 6

0 0 RO

Partner 10BT half-duplex capability.

1 = link partner 10BT half-duplex capable.

0 = link partner not 10BT half-duplex capable.

Bank 45 0x0A bit 5

Banks 50 – 63: Reserved

Except Bank Select Register (0xE)

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 85 M9999-102207-1.6

MIB (Management Information Base) Counters

The KSZ8841M provides 32 MIB counters to monitor the port activity for network management. The MIB counters are

formatted as shown below.

Bit Name R/W Description Default

31 Overflow RO 1 = counter overflow.

0 = no counter overflow. 0

30 Count valid RO 1 = counter value is valid.

0 = 0 counter value is not valid. 0

29-0 Counter values RO Counter value (read clear) 0x00000000

Table 11. Format of MIB Counters

Ethernet port MIB counters are read using indirect memory access. The address offset range is 0x00 to 0x1F.

Offset Counter Name Description

0x0 RxLoPriorityByte Rx lo-priority (default) octet count including bad packets

0x1 Reserved Reserved.

0x2 RxUndersizePkt Rx undersize packets w/ good CRC

0x3 RxFragments Rx fragment packets w/ bad CRC, symbol errors or alignment errors

0x4 RxOversize Rx oversize packets w/ good CRC (max: 1536 bytes)

0x5 RxJabbers Rx packets longer than 1536 bytes w/ either CRC errors, alignment errors, or symbol errors

0x6 RxSymbolError Rx packets w/ invalid data symbol and legal packet size.

0x7 RxCRCError Rx packets within (64,1916) bytes w/ an integral number of bytes and a bad CRC

0x8 RxAlignmentError Rx packets within (64,1916) bytes w/ a non-integral number of bytes and a bad CRC

0x9 RxControl8808Pkts Number of MAC control frames received by a port with 88-08h in EtherType field

0xA RxPausePkts Number of PAUSE frames received by a port. PAUSE frame is qualified with EtherType (88-

08h), DA, control opcode (00-01), data length (64B min), and a valid CRC

0xB RxBroadcast Rx good broadcast packets (not including error broadcast packets or valid multicast packets)

0xC RxMulticast Rx good multicast packets (not including MAC control frames, error multicast packets or valid

broadcast packets)

0xD RxUnicast Rx good unicast packets

0xE Rx64Octets Total Rx packets (bad packets included) that were 64 octets in length

0xF Rx65to127Octets Total Rx packets (bad packets included) that are between 65 and 127 octets in length

0x10 Rx128to255Octets Total Rx packets (bad packets included) that are between 128 and 255 octets in length

0x11 Rx256to511Octets Total Rx packets (bad packets included) that are between 256 and 511 octets in length

0x12 Rx512to1023Octets Total Rx packets (bad packets included) that are between 512 and 1023 octets in length

0x13 Rx1024to1522Octets Total Rx packets (bad packets included) that are between 1024 and 1916 octets in length

0x14 TxLoPriorityByte Tx lo-priority good octet count, including PAUSE packets

0x15 Reserved Reserved.

0x16 TxLateCollision The number of times a collision is detected later than 512 bit-times into the Tx of a packet

0x17 TxPausePkts Number of PAUSE frames transmitted by a port

0x18 TxBroadcastPkts Tx good broadcast packets (not inclu din g error broadca st or v alid mult ica st packet s)

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 86 M9999-102207-1.6

Offset Counter Name Description

0x19 TxMulticastPkts Tx good multicast packets (not including error multicast packets or valid broadcast packets)

0x1A TxUnicastPkts Tx good unicast packets

0x1B TxDeferred Tx packets by a port for wh ich the 1st Tx attempt is delayed due to the busy medium

0x1C TxTotalCollision Tx total collision, half duplex only

0x1D TxExcessiveCollision A count of frames for which Tx fails due to excessive collisions

0x1E TxSingleCollision Successfully Tx frames on a port for which Tx is inhibited by exactly one collision

0x1F TxMultipleCollision Successfully Tx frames on a port for which Tx is inhibited by more than one collision

Table 12. Port 1 MIB Counters Indirect Memory Offsets

Example:

1. MIB Counter Read (read port 1 “Rx64Octets” counter at indirect address offset 0x0E)

Write to reg. IACR with 0x1C0E (set indirect address and trigger a read MIB counters operation)

Then

Read reg. IADR5 (MIB counter value 31-16) // If bit 31 = 1, there was a counter overflow

// If bit 30 = 0, restart (re-read) from this register

Read reg. IADR4 (MIB counter value 15-0)

A dditional MIB Information

In the heaviest c ondition, t he byte counter will overflo w in 2 minutes. It is rec omm ended that the softwar e read all

the counters at least every 30 seconds.

MIB counters are designed as “read clear”. That is, these counters will be cleared after they are read.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 87 M9999-102207-1.6

Absolute Maximum Ratings(1)

Description Pins Value

Supply Voltage VDDATX, VDDARX, VDDIO –0.5V to +4.0V

Input Voltage All Inputs –0.5V to +5V

Output Voltage All Outputs –0.5V to +4.0V

Lead Temperature (soldering, 10 sec) N/A 270°C

Storage Temperature (Ts) N/A –55°C to +150°C

Table 13. Maximum Ratings

Note:

Exceeding the absolute maximum rating may damage the device. Stresses greater than those listed in the table above may cause

permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating

sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Unused inputs must

always be tied to an appropriate logic voltage level.

Operating Ratings(1)

Parameter Symbol Min Typ Max

Supply Voltages VDDATX,VDDARX

VDDIO 3.1V

3.1V 3.3V

3.3V 3.5V

3.5V

Ambient Temperature

for Commercial TA 0°C +70°C

Ambient Temperature

for Industrial TA -40°C +85°C

Maximum Junction

Temperature TJ +125°C

Thermal Resistance

Junction-to-Ambient(2) θJA 42.91 °C/ W

Thermal Resistance

Junction-to-Case(2) θJC 19.6 °C/W

Table 14. Operating Ratings

Notes:

1. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic

voltage level (Ground to VDD).

2. No (HS ) heat spreader in this package. The θJC/θJA is under air velocity 0 m/s.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 88 M9999-102207-1.6

Electrical Characteristics(1)

Parameter Symbol Condition Min Typ Max

Supply Current for 100BASE-TX Operation (Single Port@100% Utilization)

100BASE-TX

(analog core + PLL + digital core +

transceiver + digital I/O) Iddxio VDDATX, VDDARX, VDDIO = 3.3V;

Chip only (no transformer) 100 mA

Supply Current for 10BASE-T Operation ( Single Port@100% Utilization)

10BASE-T

(analog core + PLL + digital core +

transceiver + digital I/O) Iddxio VDDATX, VDDARX, VDDIO = 3.3V;

Chip only (no transformer) 85 mA

TTL Inputs

Input High Voltage Vih 2.0V

Input Low Voltage Vil

0.8V

Input Current Iin Vin = GND ~ VDDIO -10µA 10µA

TTL Outputs

Output High Voltage Voh I

oh = -8 mA 2.4V

Output Low Voltage Vol I

ol = 8 mA 0.4V

Output Tri-state Leakage |Ioz|

10µA

100BaseTX Transmit (measured differentially after 1:1 transformer)

Peak Differential Output Voltage Vo 100Ω termination on the differential

output. +0.95V +1.05V

Output Voltage Imbalance Vimb 100Ω termination on the differential

output 2%

Rise/Fall Time Tr/Tf 3ns 5ns

Rise/Fall Time Imbalance 0ns 0.5ns

Duty Cycle Distortion +

0.25ns

Overshoot 5%

Reference Voltage of ISET Vset 0.5V

Output Jitter Peak-to-peak 0.7ns 1.4ns

10BaseT Receive

Squelch Threshold Vsq 5MHz square wave. 400mV

10BaseT Transmit (measured differentially after 1:1 transformer)

Peak Differential Output Voltage Vp 100Ω termination on the differential

output. 2.4V

Jitter Added 100Ω termination on the differential

output.( Peak-to-peak) 1.8ns 3.5ns

Table 15. Electrical Characteristics

Notes:

1. TA = 25°C. Specification for packaged product only.

2. S i ngle Port’s transformer consumes an additional 45mA @3.3V for 100BASE -TX and 70mA @3.3V for 10BASE-T.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 89 M9999-102207-1.6

Timing Specifications

Asynchronous Timing without using Address Strobe (ADSN = 0)

Figure 13. Asynchronous Cycle – ADSN = 0

Symbol Parameter Min Typ Max Unit

t1 A1-A15 , AEN, BExN[3:0] valid to RDN, WRN active 0 n s

A1-A15, AEN, BExN[3:0] hold after RDN inactive

(assume ADSN tied Low) 0 ns t2

A1-A15, AEN, BExN[3:0] hold after WRN inactive

(assume ADSN tied Low) 1 ns

t3 Read data valid to ARDY rising 0.8 ns

t4 Read data to hold RDN inactive 4 ns

t5 Write data setup to WRN inactive 4 ns

t6 Write data hold after WRN inactive 2 ns

t7 Read active to ARDY Low 8 ns

t8 Write inactive to ARDY Low 8 ns

ARDY low (wait time) in read cycle (Note1)

(It is 0ns to read bank select register and 40ns to

read QMU data register in turbo mode) (Note2)

0 40 ns t9

ARDY low (wait time) in read cycle (Note1)

(It is 0ns to read bank select register and 80ns to

read QMU data register in normal mode)

0 80 ns

t10 ARDY low (wait time) in write cycle (Note1)

(It is 0ns to write bank select register)

(It is 36ns to write QMU data register)

0 50 ns

Table 16. Asynchronous Cycle (ADSN = 0) Timing Parameters

Notes:

1. When CPU finished current Read or Write operation, it can do next Read or Write operation even the ARDY is low. During Read

or Write operation if the ADRY is low, the CPU has to keep the RDN/WRN low until the AR DY returns to high.

2. In order to speed up the ARDY low time to 40 ns, user has to use the turbo software driver which is only supported in the A6

device. Please refer to t he “KSZ88xx Programmer's Guide” for detail.

t5 t1

t4 t3

valid

Addr, AEN, BExN

ADSN

Read D ata

RDN, WRN

Write D ata

ARDY

(Read Cycle)

ARDY

(

Write

Cycle)

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 90 M9999-102207-1.6

Asynchronous Timing using Address Strobe (ADSN)

t2t7

t4 t3t1

valid

ddr, AEN, BExN

DSN

Read Data

RDN, WRN

Write Data

RDY

(Read Cycle)

RDY

(

Write

Cycle)

t10

t11

Figure 14. Asynchronous Cycle – Using ADSN

Symbol Parameter Min Typ Max Unit

t1 A1-A15, AEN, BExN[3:0] valid to RDN, WRN active 0 ns

t2 Read data valid to ARDY rising 0.8 ns

t3 Read data hold to RDN in active 4 ns

t4 Write data setup to WRN inactive 4 ns

t5 Write data hold after WRN inactive 2 ns

t6 A1-A15, AEN, nBE[3:0] setup to ADSN rising 4 ns

t7 Read active to ARDY Low 8 ns

t8 A1-A15, AEN, BExN[3:0] hold after ADSN rising 2 ns

t9 Write inactive to ARDY Low 8 ns

ARDY low (wait time) in read cycle (Note1)

(It is 0n s to read bank select register and 40ns to

read QMU data register in turbo mode) (Note2)

0 40 ns t10

ARDY low (wait time) in read cycle (Note1)

(It is 0n s to read bank select register and 80ns to

read QMU data register in normal mode)

0 80 ns

t11 ARDY low (wait tim e) in write cycle (Note1)

(It is 0n s to write bank select register)

(It is 36ns to write QMU data register)

0 50 ns

Table 17. Asynchronous Cycle using ADSN Timing Parameters

Notes:

1. When CPU finished current Read or W rite operation, it can do next Read or Write operat i on even the ARDY is low. During Read or Write

operation if the ADRY is low, the CPU has to keep the RDN/WRN low until the ARDY returns to high.

2. I n order t o speed up the ARDY low time to 40ns, user has to use the turbo soft ware driver which is only supported in the A6 device.

Please refer to the “KSZ88xx Programmer's Guide” for detail.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 91 M9999-102207-1.6

Asynchronous Timing using DATACSN

t3t7

t5 t4t1

valid

DATACSN

Read Data

RDN, WRN

Write Data

RDY

(Read Cycle)

RDY

( Write Cycle)

t10

Figure 15. Asynchronous Cycle – Using DATACSN

Symbol Parameter Min Typ Max Unit

t1 DATACSN setup to RDN, WRN active 2 ns

t2 DATACSN hold after RDN, WRN inactive (assume

ADSN tied Low) 0 ns

t3 Read data hold to ARDY rising 0.8 ns

t4 Read data to RDN hold 4 ns

t5 Write data setup to WRN inactive 4 ns

t6 Write data hold after WRN inactive 2 ns

t7 Read active to ARDY Low 8 ns

t8 Write inactive to ARDY Low 8 ns

ARDY low (wait time) in read cycle (Note1)

(It is 0ns to read bank select register and 40ns to

read QMU data register in turbo mode) (Note2)

0 40 ns t9

ARDY low (wait time) in read cycle (Note1)

(It is 0ns to read bank select register and 80ns to

read QMU data register in normal mode)

0 80 ns

t10 ARDY low (wait time) in write cycle (Note1)

(It is 0n s to write bank select regis t er)

(It is 36ns to write QMU data register)

0 50 ns

Table 18. Asynchronous Cycle using DATACSN Timing Parameters

Notes:

1. When CPU finished current Read or Write operation, it can do next Read or Write operation even the ARDY is low. During Read or

Write operation if the ADRY is low, the CPU has to keep the RDN/WRN low until the ARDY returns to high.

2. In order to speed up the ARD Y low time to 40 ns, user has to use the turbo software driver which is only supported in the A6

device. Please refer to the “KSZ88xx Programmer's Guide” for detail.

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 92 M9999-102207-1.6

Address Latching Timing for All Modes

ADSN

Address, AEN, BE xN

LDEVN

Figure 16. Address Latching Cycle for All Modes

Symbol Parameter Min Typ Max Unit

t1 A1-A15, AEN, BExN[3:0] setup to ADSN 4 ns

t2 A1-A15, AEN, BExN[3:0] hold after ADSN risin g 2 ns

t3 A4-A15, AEN to LDEVN delay 5 ns

Table 19. Address Latching Timing Parameters

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 93 M9999-102207-1.6

Synchronous Timing in Burst Write (VLBUSN = 1)

Figure 17. Synchronous Burst Write Cycles – VLBUSN = 1

Symbol Parameter Min Typ Max Unit

t1 SWR setup to BCLK falling 4 ns

t2 DATDCSN setup to BCLK rising 4 ns

t3 CYCLEN setup to BCLK rising 4 ns

t4 Wri te data setup to BCLK rising 6 ns

t5 Write data hold to BCLK rising 2 ns

t6 RDYRTNN setup to BCLK falling 5 ns

t7 RDYRTNN hold to BCLK falling 3 ns

t8 SRDYN setup to BCLK rising 4 ns

t9 SRDYN hold to BCLK rising 3 ns

t10 DATACSN hold to BCLK rising 2 ns

t11 SWR hold to BCLK falling 2 ns

t12 CYCLEN hold to BCLK 2 ns

Table 20. Synchronous Burst Write Timing Parameters

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 94 M9999-102207-1.6

Synchronous Timing in Burst Read (VLBUSN = 1)

t9t8

data0 data1 data2 data3

BCLK

DATACSN

SWR

CYCLEN

Read Data

RDYRTNN

SRDYN

t11

t10

t12

Figure 18. Synchronous Burst Read Cycles – VLBUSN = 1

Symbol Parameter Min Typ Max Unit

t1 SWR setup to BCLK falling 4 ns

t2 DATDCSN setup to BCLK rising 4 ns

t3 CYCLEN setup to BCLK rising 4 ns

t4 Read data setup to BCLK rising 6 ns

t5 Read data hold to BCLK rising 2 ns

t6 RDYRTNN setup to BCLK falling 5 ns

t7 RDYRTNN hold to BCLK falling 3 ns

t8 SRDYN setup to BCLK rising 4 ns

t9 SRDYN hold to BCLK rising 3 ns

t10 DATACSN hold to BCLK rising 2 ns

t11 SWR hold to BCLK falling 2 ns

t12 CYCLEN hold to BCLK 2 ns

Table 21. Synchronous Burst Read Timing Parameters

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 95 M9999-102207-1.6

Synchronous Write Timing (VLBUSN = 0)

t12t11

t10t9

t8t7

t6t5

valid

BCLK

Address, AEN, BExN

ADSN

SWR

CYCLEN

Write Data

SRDYN

RDYRTNN

Figure 19. Synchronous Write Cycle – VLBUSN = 0

Symbol Parameter Min Typ Max Unit

t1 A1-A15, AEN, BExN[3:0] setup to ADSN rising 4 ns

t2 A1-A15, AEN, BExN[3:0] hold after ADSN risin g 2 ns

t3 CYCLEN setup to BCLK rising 4 ns

t4 CYCLEN hold after BCLK rising (non-burst mode) 2 ns

t5 SWR setup to BCLK 4 ns

t6 SWR hold after BCLK rising with SRDYN active 0 ns

t7 Wri te data setup to BCLK rising 5 ns

t8 Write data hol d from BCLK rising 1 ns

t9 SRDYN setup to BCLK 8 ns

t10 SRDYN hold to BCLK 1 ns

t11 RDYRTNN setup to BCLK 4 ns

t12 RDYRTNN hold to BCLK 1 ns

Table 22. Synchronous Write (VLBUSN = 0) Timing Parameters

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 96 M9999-102207-1.6

Synchronous Read Timing (VLBUSN = 0)

t11t10

t9t8

t6t7

valid

BCLK

Address, AEN, BExN

ADSN

SWR

CYCLEN

Read Dat a

SRDYN

RDYRTNN

Figure 20. Synchronous Read Cycle – VLBUSN = 0

Symbol Parameter Min Typ Max Unit

t1 A1-A15, AEN, BExN[3:0] setup to ADSN rising 4 ns

t2 A1-A15, AEN, BExN[3:0] hold after ADSN risin g 2 ns

t3 CYCLEN setup to BCLK rising 4 ns

t4 CYCLEN hold after BCLK rising (non-burst mode) 2 ns

t5 SWR setup to BCLK 4 ns

t6 Read data hold from BCLK rising 1 ns

t7 Read data setup to BCLK 8 ns

t8 SRDYN setup to BCLK 8 ns

t9 SRDYN hold to BCLK 1 ns

t10 RDYRTNN setup to BCLK rising 4 ns

t11 RDYRTNN hold after BCLK rising 1 ns

Table 23. Synchronous Read (VLBUSN = 0) Timing Parameters

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 97 M9999-102207-1.6

Auto Negotiation Timing

Figure 21. Auto Negotiation Timing

Timing Parameter Description Min Typ Max Unit

tBTB FLP burst to FLP burst 8 16 24 ms

tFLPW FLP burst width 2 ms

tPW Clock/Data pulse width 100 ns

tCTD Clock pulse to data pul se 55.5 64 69.5 µs

tCTC Clock pulse to clo ck pul se 111 128 139 µs

Number of Clo ck /Data pul se s per burst 17 33

Table 24. Auto Negotiation Timing Para meters

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 98 M9999-102207-1.6

Reset Timing

As long as the stable supply voltages to reset High timing (minimum of 10ms) are met, there is no power-sequencing

requirement for the KSZ8841M supply voltages (3.3V).

The reset timing requirement is summarized in the Figure 22 and Table 25.

Supply

Voltage

RST_N

tsr

Figure 22. Reset Timing

Symbol Parameter Min Max Unit

tsr Stable supply voltages to reset High 10 ms

Table 25. Reset Timing Parameters

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 99 M9999-102207-1.6

EEPROM Timing

EESK

EECS

EEDI

EEDO

High-Z D15 D14 D13 D1 D0

An A0011

*1 Start bit

tcyc

Figure 23. EEPROM Read Cycle Timing Diagram

Timing Parameter Description Min Typ Max Unit

tcyc Clock cycle 4 (OBCR[1:0]=11 on-chip

bus speed @ 25 MHz)

0.8 (OBCR[1:0]=00 on-chip

bus speed @ 125 MHz)

µs

ts Setup time 20 ns

th Hold time 20 ns

Table 26. EEPROM Timing Parameters

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 100 M9999-102207-1.6

Selection of Isolation Transformers

A 1:1 isolation transformer is required at the line int erface. An isolation transf ormer with integrated common-mode choke

is recommended for exceeding FCC requirements.

Table 27 gives recommended transformer characteristics.

Parameter Value Test Condition

Turns ratio 1 CT : 1 CT

Open-circuit inductance (min) 350µH 100mV, 100kHz, 8mA

Leakage induct anc e (max) 0.4µH 1MHz (min)

Inter-winding capacitance (max) 12pF

D.C. resistance (max) 0.9Ω

Insertion loss (max) 1.0dB 0MHz – 65MHz

HIPOT (min) 1500Vrms

Table 27. Transformer Selection Criteria

Magnetic Manufacturer Part Number Auto MDI-X Number of Port

Pulse H1102 Yes 1

Pulse (low cost) H1260 Yes 1

Transpower HB726 Yes 1

Bel Fuse S558-5999-U7 Yes 1

Delta LF8505 Yes 1

LanKom LF-H41S Yes 1

TDK (Mag Jack) TLA-6T718 Yes 1

Table 28. Qualified Single Port Magnetics

Selection of Reference Crystal

Chacteristics Value Units

Frequency 25 MHz

Frequency tolerance (max) ±50 ppm

Load capacitan ce (max) 20 pF

Series resistance 25 Ω

Table 29. Typical Reference Crystal Characteristics

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 101 M9999-102207-1.6

Package Information

Figure 24. 128-Pin PQFP Package

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 102 M9999-102207-1.6

Figure 25. Optional 128-Pin LQFP Package

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 103 M9999-102207-1.6

Figure 26. Optional 100-Ball LFBGA Package

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 104 M9999-102207-1.6

Acronyms and Glossary

BIU Bus Interface Unit The host interface function that performs code conversion, buffering,

and the like required for communications to and from a network.

BPDU Bridge Protocol Data Unit A packet containing ports, addresses, etc. to make sure data being

passed through a bri dged network arrives at its proper destination.

CMOS Complementary Metal Oxide Semiconductor A common semiconductor manufacturing technique in which positive

and negative types of transistors are combined to form a current gate

that in turn forms an effectiv e means of controlling electrical current

through a chip.

CRC Cyclic Redundancy Check A common technique for detecting data transmission errors. CRC for

Ethernet is 32 bits long.

Cut-through switch A switch typically processes received packets by reading in the full

packet (storing), then processing the packet to determine where it

needs to go, then forwarding it. A cut-through switch simply reads in

the first bit of an incoming packet and forwards the packet. Cut-

through switch es do not store t he pack et.

DA Destination Address The address to send packets.

DMA Direct Memory Access A design in which memory on a chip i s controlled independently of

the CPU.

EEPROM Electronically Erasable Programmable Read-only Memory A design in which memory on a chip can be erased by exposing it to

an electrical charge.

EISA Extended Industry Standard Architecture A bus archite cture designed for PCs using 80x86 processors, or an

Intel 80386, 80486 or Pentium microprocessor. EISA buses are 32

bits wide and support mu ltipr o ces sin g.

EMI Electro-Magnetic Interference A natura lly occurring phenomena when the electromagnetic field of

one device disrupts, impedes or degrades the electromagnetic field of

another device by coming into proximity with it. In computer

technology, computer devices are susceptible to EMI because

electromagnetic fields are a byproduct of passing electricity through a

wire. D ata lines that have not been properly shielded are susceptible

to data corruption by EMI.

FCS Frame Check Sequence See CRC.

FID Frame or Filter ID Specifies the frame identifier. Alternately is the filter identifier.

IGMP Internet Group Management Protocol The protocol defined by RF C 1112 for IP multicast transmissions.

IPG Inter-Packet Gap A time delay between successive data packets mandated by the

network standard for protocol reasons. In Ethernet, the medium has

to be "silent" (i.e., no data transfer) for a short period of time before a

node can consider the network idle and start to transmit. IP G is used

to correct timing differences between a transmitt e r and receiver.

During the IPG, no data is transferred, and information in the gap can

be discarded or additions inserted without impact on data integrity.

ISI Inter-Symbol Interference The disruption of transmitted code caused by adjacent pulses

affecting or interfering with each other.

ISA Industry Standard Archit ecture A bus archite cture used in the IB M PC/XT and PC/AT.

Jumbo Packet A packet larger than the standard Ethernet packet (1500 bytes).

Large packet sizes allow for more efficient use of bandwidth, lower

overhead, less processing, etc.

MDI Medium D ependent Interface An Ethernet port connection that allows network hubs or switches to

connect to other hubs or switches without a null-modem, or

crossover, cable. MDI provides the sta ndard interface to a particular

media (copper or fiber) and is therefore 'media dependent.'

Micre l, Inc. KSZ8841-16/32 MQL/MVL/MBL

October 2007 105 M9999-102207-1.6

MDI-X Medium Dependent Inte rface Crossover An Ethernet port connection that allows networked end stations (i.e.,

PCs or workstations) to connect to each other using a null-modem, or

crossover, cable. For 10/100 full-duplex networks, an end point (such

as a computer) and a switch are wired so that each transmitter

connects to the far end receiver. When connecting two computers

together, a cable that crosses the TX and RX is required to do this.

With auto MDI-X, the PHY senses the correct TX and RX roles,

eliminating any cable confusion.

MIB Management Information Base The MIB comprises the management portion of ne twork devices. This

can include things like monitoring traffic levels and faults (statistical),

and can also chan ge operating parameters in network nodes (static

forwarding addresses).

MII Media Independent Interface The MII accesses PHY registers as defined in the IEEE 802.3

specification.

NIC Network Interface Card An expansion board inserted into a computer to allow it to be

connected to a network. Most NICs are designed for a particular type

of network, protocol, and media, although some can serve multiple

networks.

NPVID Non Port VLAN ID The Port VLAN ID value is used as a VLAN reference.

PLL Phase-Locked Loop An electronic circuit that controls an oscillator so that it maintains a

constant phase angle (i.e., lock) on the frequency of an input, or

reference, signal. A PLL ensures that a communication signal is

locked on a specific frequency and can also be used to generate,

modulate, and demodulate a signal and divide a frequency.

PME Power Management Event An occurrence that affects the directing of power to different

components of a system.

QMU Queue Management Unit Manages packet traffic between MAC/PHY interface and the system

host. The QMU has built-in packet memories for receiv e and transmit

functions called TXQ (Transmit Queue) and RXQ (Receive Queue).

SA Source Address The address from which information has been sent.

TDR Time Domain Reflectometry TDR is used to pinpoint flaws and problems in underground and aerial

wire, cabl ing, and fiber optics. They send a signal down the conductor

and measure the time it takes for the signal -- or part of the signal -- to

return.

UTP Unshielded Twisted Pa ir Commonly a cable containing 4 twisted pairs of wires. The wires are

twisted in such a manner as to cancel electrical interference

generated in each wire, therefore shielding is not required.

VLAN Virtual Local Area Network A configuration of computers that acts as if all computers are

connected by the s a me physical network but which may be located

virtually anywhere.

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed t o be accurat e and rel i able. However, no responsibility is assumed by Micrel for its use.

Micrel reserves the right to change circuitry and specific ations at any tim e without not ific at i o n to the custom er.

Micrel Products are not designed or authorized f or use as components in life support appliances, devices or systems where malfu nction of a product can

reasonably be expected t o resul t in personal i njury. Li fe support devices or systems are devices or systems that (a) are intended for surgical impl ant into

the body or (b) support or sustain life, and whose fail ure to perf o rm can be reasonably expected t o result i n a signific ant i njury to the user. A Purchaser’s

use or sale of Micrel Products for use in lif e support appli ances, devic es or sys tems is a Purchaser’s own risk and Purc haser agrees to fully indemnify

Micrel for any damages result i ng from such use or sale.

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Micrel:

KSZ8841-16MVL TR KSZ8841-16MQL KSZ8841-16MVL KSZ8841-16MVLI TR KSZ8841-16MBL KSZ8841-32MVLI

KSZ8841-16MBLI KSZ8841-32MQL KSZ8841-16MVLI KSZ8841-32MVL KSZ8841-16MQL-EVAL KSZ8841-PMQL-

EVAL KSZ8841-16MVL-TR KSZ8841-16MVLI-TR