For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
A / D CONVERTERS - SMT
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DUAL 13/12-BIT 65/80 MSPS
A/D CONVERTER
Functional Diagram
Features
• 13-bit resolution
• 65/80 MSPS Maximum Sampling Rate
• Ultra-Low Power Dissipation: 85/102 mW
• 72 dB SNR @ 8 MHz FIN
• Internal Reference Circuitry
• 1.8 V Core Supply Voltage
• 1.7 - 3.6 V I/O supply voltage
• Parallel CMOS output
• 9 x 9 mm 64-Pin QFN (LP9E) Package
• Dual Channel
Typical Applications
• Handheld Communication, PMR, SDR
• Medical Imaging
• Portable Test Equipment
• Digital Oscilloscopes
• Baseband / IF Communication
• Video Digitizing
• CCD Digitizing
General Description
The HMCAD1050-80 is a high performance low
power dual analog-to-digital converter (ADC). The
ADC employs internal reference circuitry, a CMOS
control interface, CMOS output data and is based
on a proprietary structure. Digital error correction is
employed to ensure no missing codes in the complete
full scale range.
Several idle modes with fast startup times exist. Each
channel can be independently powered down and
the entire chip can either be put in Standby Mode or
Power Down mode. The different modes are optimized
to allow the user to select the mode resulting in the
lowest possible energy consumption during idle mode
and startup.
The HMCAD1050-80 has a highly linear THA optimized
for frequencies up to 70 MHz. The differential clock
interface is optimized for low jitter clock sources and
supports LVDS, LVPECL, sine wave and CMOS clock
inputs.
Pin compatible with HMCAD1040-40, HMCAD1040-80
and HMCAD1050-40.
Figure 1. Functional Block Diagram
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
For price, delivery, and to place orders: Analog Devices, Inc.,
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
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DUAL 13/12-BIT 65/80 MSPS
A/D CONVERTER
Electrical Specications
DC Electrical Specications
AVDD=1.8V, DVDD=1.8V, DVDDCK=1.8V, OVDD=2.5V, 65/80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz
input signal, 13 bit output, unless otherwise noted
Parameter Condition Min Typ Max Unit
DC accuracy
No missing codes Guaranteed
Offset error Midscale offset 1 LSB
Gain error Full scale range deviation from typical ± 6 %FS
Gain matching Gain matching between channels. ± 3 sigma value at worst case
conditions ± 0.5 %FS
DNL Differential nonlinearity (12-bit level) ± 0.2 LSB
INL Integral nonlinearity (12-bit level) ± 0.6 LSB
VCM Common mode voltage output VAVDD/2 V
Analog Input
Input common mode Analog input common mode voltage VCM -0.1 VCM +0.2 V
Full scale range, Normal Differential input voltage range, 2 Vpp
Full scale range, Option Differential input voltage range, 1V (see section Reference Volt-
ages) 1 Vpp
Input capacitance Differential input capacitance 2 pF
Bandwidth Input Bandwidth 500 MHz
Power Supply
Core Supply Voltage Supply voltage to all 1.8V domain pins. See Pin Conguration and
Description 1.7 1.8 2 V
I/O Supply Voltage Output driver supply voltage (OVDD). Should be higher than or
equal to Core Supply Voltage (VOVDD ≥ VDVDD)1.7 2.5 3.6 V
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
For price, delivery, and to place orders: Analog Devices, Inc.,
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
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DUAL 13/12-BIT 65/80 MSPS
A/D CONVERTER
AC Electrical Specications - 65 MSPS
AVDD=1.8V, DVDD= 1.8V, DVDDCK= 1.8V, OVDD=2.5V, FS=65 MSPS clock, 50% clock duty cycle, -1 dBFS 8 MHz input signal, 13 bit output,
unless otherwise noted.
Parameter Condition Min Typ Max Unit
Performance
SNR Signal to Noise Ratio
FIN = 8 MHz 71.6 72.6 dBFS
FIN = 20 MHz 71.8 dBFS
FIN =~ FS/2 71.5 dBFS
FIN = 40 MHz 70.4 dBFS
SNDR Signal to Noise and Distortion Ratio
FIN = 8 MHz 70.5 71.7 dBFS
FIN = 20 MHz 71.7 dBFS
FIN =~ FS/2 71.1 dBFS
FIN = 40 MHz 70 dBFS
SFDR Spurious Free Dynamic Range
FIN = 8 MHz 75 81 dBc
FIN = 20 MHz 84 dBc
FIN =~ FS/2 79 dBc
FIN = 40 MHz 77 dBc
HD2 Second order Harmonic Distortion
FIN = 8 MHz -85 -95 dBc
FIN = 20 MHz -95 dBc
FIN =~ FS/2 -95 dBc
FIN = 40 MHz -95 dBc
HD3 Third order Harmonic Distortion
FIN = 8 MHz -75 -81 dBc
FIN = 20 MHz -84 dBc
FIN =~ FS/2 -79 dBc
FIN = 40 MHz -79 dBc
ENOB Effective number of Bits
FIN = 8 MHz 11.4 11.6 bits
FIN = 20 MHz 11.6 bits
FIN =~ FS/2 11.5 bits
FIN = 40 MHz 11.3 bits
Crosstalk Signal crosstalk between channels, FIN1 = 8MHz, FIN0 = 9.9MHz -95 dB
Power Supply
Analog supply current 32.8 mA
Digital supply current Digital core supply 5 mA
Output driver supply 2.5V output driver supply, sine wave input, FIN = 1 MHz, CK_EXT enabled 8.2 mA
Output driver supply 2.5V output driver supply, sine wave input, FIN = 1 MHz, CK_EXT disabled 6.6 mA
Analog power Dissipation 59 mW
Digital power Dissipation OVDD = 2.5V, ~5pF load on output bits, FIN = 1 MHz, CK_EXT disabled 25.5 mW
Total power Dissipation OVDD = 2.5V, ~5pF load on output bits, FIN = 1 MHz, CK_EXT disabled 84.5 mW
Power Down Dissipation 9.3 µW
Sleep Mode 1 Power Dissipation, Sleep mode one channel 55.3 mW
Sleep Mode 2 Power Dissipation, Sleep mode both channels 20.4 mW
Clock Inputs
Max. Conversion Rate 65 MSPS
Min. Conversion Rate 3 MSPS
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
For price, delivery, and to place orders: Analog Devices, Inc.,
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
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DUAL 13/12-BIT 65/80 MSPS
A/D CONVERTER
AC Electrical Specications - 80 MSPS
AVDD=1.8V, DVDD=1.8V, DVDDCK=1.8V, OVDD=2.5V, FS=80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13 bit output,
unless otherwise noted.
Parameter Condition Min Typ Max Unit
Performance
SNR Signal to Noise Ratio
FIN = 8 MHz 70.4 72 dBFS
FIN = 20 MHz 71.7 dBFS
FIN = 30 MHz 71.2 dBFS
FIN =~ FS/2 70.7 dBFS
SNDR Signal to Noise and Distortion Ratio
FIN = 8 MHz 69.5 70.5 dBFS
FIN = 20 MHz 70.5 dBFS
FIN = 30 MHz 70.4 dBFS
FIN =~ FS/2 70.3 dBFS
SFDR Spurious Free Dynamic Range
FIN = 8 MHz 74 77 dBc
FIN = 20 MHz 78 dBc
FIN = 30 MHz 78 dBc
FIN =~ FS/2 78 dBc
HD2 Second order Harmonic Distortion
FIN = 8 MHz -80 -95 dBc
FIN = 20 MHz -90 dBc
FIN = 30 MHz -90 dBc
FIN =~ FS/2 -85 dBc
HD3 Third order Harmonic Distortion
FIN = 8 MHz -74 -77 dBc
FIN = 20 MHz -78 dBc
FIN = 30 MHz -78 dBc
FIN =~ FS/2 -78 dBc
ENOB Effective number of Bits
FIN = 8 MHz 11.3 11.4 bits
FIN = 20 MHz 11.4 bits
FIN = 30 MHz 11.4 bits
FIN =~ FS/2 11.4 bits
Crosstalk Signal crosstalk between channels, FIN1 = 8MHz, FIN0 = 9.9MHz -95 dB
Power Supply
Analog supply current 39.7 mA
Digital supply current Digital core supply 6 mA
Output driver supply 2.5V output driver supply, sine wave input, FIN = 1 MHz, CK_EXT enabled 9.4 mA
Output driver supply 2.5V output driver supply, sine wave input, FIN = 1 MHz, CK_EXT disabled 7.7 mA
Analog power Dissipation 71.5 mW
Digital power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1 MHz, CK_EXT disabled 30 mW
Total power Dissipation OVDD = 2.5V, 5pF load on output bits, FIN = 1 MHz, CK_EXT disabled 101.5 mW
Power Down Dissipation 9.1 µW
Sleep Mode 1 Power Dissipation, Sleep mode one channel 66.4 mW
Sleep Mode 2 Power Dissipation, Sleep mode both channels 24.1 mW
Clock Inputs
Max. Conversion Rate 80 MSPS
Min. Conversion Rate 3 MSPS
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
For price, delivery, and to place orders: Analog Devices, Inc.,
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
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DUAL 13/12-BIT 65/80 MSPS
A/D CONVERTER
Digital and Timing Specications
AVDD= 1.8V, DVDD= 1.8V, DVDDCK= 1.8V, OVDD= 2.5V, Conversion Rate: Max specied, 50% clock duty cycle, -1 dBFS input signal, 5 pF capacitive
load on data outputs, unless otherwise noted
Parameter Condition Min Typ Max Unit
Clock Inputs
Duty Cycle 20 80 % high
Compliance CMOS, LVDS, LVPECL, Sine Wave
Input range Differential input swing 0.4 Vpp
Input range Differential input swing, sine wave clock input 1.6 Vpp
Input common mode voltage Keep voltages within ground and voltage of OVDD 0.3 VOVDD -0.3 V
Input capacitance Differential 2 pF
Timing
TPD Start up time from Power Down Mode to Active Mode 900 clock cycles
TSLP Start up time from Sleep Mode to Active Mode 20 clock cycles
TOVR Out of range recovery time 1 clock cycles
T
AP Aperture Delay 0.8 ns
Єrms Aperture jitter < 0.5 ps
TLAT Pipeline Delay 12 clock cycles
TDOutput delay (see timing diagram). 5pF load on output bits 3 10 ns
TDC Output delay relative to CK_EXT (see timing diagram) 1 6 ns
Logic Inputs
VHI High Level Input Voltage. VOVDD ≥ 3.0V 2 V
VHI High Level Input Voltage. VOVDD = 1.7V – 3.0V 0.8 ·VOVDD V
VLI Low Level Input Voltage. VOVDD ≥ 3.0V 0 0.8 V
VLI Low Level Input Voltage. VOVDD = 1.7V – 3.0V 0 0.2 ·VOVDD V
IHI High Level Input leakage Current ±10 µA
ILI Low Level Input leakage Current ±10 µA
CIInput Capacitance 3 pF
Logic Outputs
VHO High Level Output Voltage VOVDD -0.1 V
VLO Low Level Output Voltage 0.1 V
CL
Max capacitive load. Post-driver supply voltage equal to digital
supply voltage VOVDD = VDVDD
5 pF
CLMax capacitive load. Post-driver supply voltage above 2.25V (1) 10 pF
(1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep
dynamic currents and resulting switching noise at a minimum
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
For price, delivery, and to place orders: Analog Devices, Inc.,
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
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DUAL 13/12-BIT 65/80 MSPS
A/D CONVERTER
Timing Diagram
Figure 2: Timing Diagram
Absolute Maximum Ratings
Absolute maximum ratings are limiting values to be applied for short periods of time. Exposure to absolute maximum
rating conditions for an extended period of time may reduce device lifetime.
Table 1:
Pin Pin Rating
AVDD AVSS -0.3V to +2.3V
DVDD DVSS -0.3V to +2.3V
AVSS, DVSSCK, DVSS, OVSS DVSS -0.3V to +0.3V
OVDD OVSS -0.3V to +3.9V
IPx, INx, analog inputs and outputs AVSS -0.3V to +2.3V
Digital outputs OVSS -0.3V to +3.9V
CKP, CKN DVSSCK -0.3V to +3.9V
Digital Inputs OVSS -0.3V to +3.9V
Operating temperature -40 to +85 ºC
Storage temperature -60 to +150 ºC
Soldering Prole Qualication J-STD-020
ELECTROSTATIC SENSITIVE DEVICE
OBSERVE HANDLING PRECAUTIONS
Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This
is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in
the operational section of this specication is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
For price, delivery, and to place orders: Analog Devices, Inc.,
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
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Pin Conguration and Description
Figure 3: Package Drawing, 64-pin QFN or TQFP
Table 2: Pin Function
Pin # Name Description
1, 18, 23 DVDD Digital and I/O-ring pre driver supply voltage, 1.8V
2 CM_EXT Common Mode voltage output
3, 9, 12 AVDD Analog supply voltage, 1.8V
4, 5, 8 AVSS Analog ground
6, 7 IP0, IN0 Analog input Channel 0 (non-inverting, inverting)
10, 11 IP1, IN1 Analog input Channel 1 (non-inverting, inverting)
13 DVSSCK Clock circuitry ground
14 DVDDCK Clock circuitry supply voltage, 1.8V
15 CKP Clock input, non-inverting (Format: LVDS, LVPECL, CMOS/TTL, Sine Wave)
16 CKN Clock input, inverting. For CMOS input on CKP, connect CKN to ground.
17, 64 DVSS Digital circuitry ground
19 CK_EXT_EN CK_EXT signal enabled when low (zero). Tristate when high.
20 DFRMT Data format selection. 0: Offset Binary, 1: Two’s Complement
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
For price, delivery, and to place orders: Analog Devices, Inc.,
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
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Table 2: Pin Function
Pin # Name Description
21 PD_N Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up always
apply Power Down mode before using Active Mode to reset chip.
22 OE_N_1 Output Enable Channel 0. Tristate when high
24, 41, 58 OVDD I/O ring post-driver supply voltage. Voltage range 1.7 to 3.6V
25, 40, 57 OVSS Ground for I/O ring
26 D1_0 Output Data Channel 1 (LSB, 13 bit output or 1Vpp full scale range )
27 D1_1 Output Data Channel 1 (LSB, 12 bit output 2Vpp full scale range)
28 D1_2 Output Data Channel 1
29 D1_3 Output Data Channel 1
30 D1_4 Output Data Channel 1
31 D1_5 Output Data Channel 1
32 D1_6 Output Data Channel 1
33 D1_7 Output Data Channel 1
34 D1_8 Output Data Channel 1
35 D1_9 Output Data Channel 1
36 D1_10 Output Data Channel 1
37 D1_11 Output Data Channel 1 (MSB for 1Vpp full scale range, see Reference Voltages section)
38 D1_12 Output Data Channel 1 (MSB for 2Vpp full scale range)
39 ORNG_1 Out of Range ag Channel 1. High when input signal is out of range
42 CK_EXT Output clock signal for data synchronization. CMOS levels
43 D0_0 Output Data Channel 0 (LSB, 13 bit output or 1Vpp full scale range)
44 D0_1 Output Data Channel 0 (LSB, 12 bit output 2Vpp full scale range)
45 D0_2 Output Data Channel 0
46 D0_3 Output Data Channel 0
47 D0_4 Output Data Channel 0
48 D0_5 Output Data Channel 0
49 D0_6 Output Data Channel 0
50 D0_7 Output Data Channel 0
51 D0_8 Output Data Channel 0
52 D0_9 Output Data Channel 0
53 D0_10 Output Data Channel 0
54 D0_11 Output Data Channel 0 (MSB for 1Vpp full scale range, see Reference Voltages section)
55 D0_12 Output Data Channel 0 (MSB for 2Vpp full scale range)
56 ORNG_0 Out of Range ag Channel 0. High when input signal is out of range
59 OE_N_0 Output Enable Channel 0. Tristate when high
60, 61 CM_EXTBC_1, CM_
EXTBC_0
Bias control bits for the buffer driving pin CM_EXT
00: OFF 01: 50uA
10: 500uA 11: 1mA
62, 63 SLP_N_1, SLP_N_0
Sleep Mode
00: Sleep Mode 01: Channel 0 active
10: Channel 1 active 11: Both channels active
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
For price, delivery, and to place orders: Analog Devices, Inc.,
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
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Recommended Usage
Analog Input
The analog inputs to the HMCAD1050-80 is a switched
capacitor track-and-hold amplier optimized for differ-
ential operation. Operation at common mode voltages
at mid supply is recommended even if performance
will be good for the ranges specied. The CM_EXT pin
provides a voltage suitable as common mode voltage
reference. The internal buffer for the CM_EXT voltage
can be switched off, and driving capabilities can be
changed by using the CM_EXTBC control input.
Figure 4 shows a simplied drawing of the input net-
work. The signal source must have sufficiently low
output impedance to charge the sampling capacitors
within one clock cycle. A small external resistor (e.g.
22 Ohm) in series with each input is recommended
as it helps reducing transient currents and dampens
ringing behavior. A small differential shunt capacitor at
the chip side of the resistors may be used to provide
dynamic charging currents and may improve perfor-
mance. The resistors form a low pass lter with the
capacitor, and values must therefore be determined by
requirements for the application.
Figure 4: Input conguration
DC-Coupling
Figure 5 shows a recommended conguration for DC-
coupling. Note that the common mode input voltage
must be controlled according to specied values. Pref-
erably, the CM_EXT output should be used as refer-
ence to set the common mode voltage.
Figure 5: DC coupled input with buffer
The input amplier could be inside a companion chip
or it could be a dedicated amplier. Several suitable
single ended to differential driver ampliers exist in the
market. The system designer should make sure the
specications of the selected amplier is adequate for
the total system, and that driving capabilities comply
with the HMCAD1050-80 input specications.
Detailed conguration and usage instructions must be
found in the documentation of the selected driver, and
the values given in gure 5 must be varied according
to the recommendations for the driver.
AC-Coupling
A signal transformer or series capacitors can be used
to make an AC-coupled input network. Figure 6 shows
a recommended conguration using a transformer.
Figure 6: Transformer coupled input
Make sure that a transformer with sufficient linearity
is selected, and that the bandwidth of the transformer
is appropriate. The bandwidth should exceed the
sampling rate of the ADC with at least a factor of 10.
It is also important to minimize phase mismatch
between the differential ADC inputs for good HD2 per-
formance. This type of transformer coupled input is
the preferred conguration for high frequency signals
as most differential ampliers do not have adequate
performance at high frequencies. Magnetic coupling
between the transformers and PCB traces may impact
channel crosstalk, and must hence be taken into
account during PCB layout. If the input signal is travel-
ing a long physical distance from the signal source to
the transformer (for example a long cable), kick-backs
from the ADC will also travel along this distance. If
these kick-backs are not terminated properly at the
source side, they are reected and will add to the input
signal at the ADC input. This could reduce the ADC
performance. To avoid this effect, the source must
effectively terminate the ADC kick-backs, or the travel-
ing distance should be very short. If this problem could
not be avoided, the circuit in gure 8 can be used.
Figure 7 shows AC-coupling using capacitors. Resis-
tors from the CM_EXT output, RCM, should be used
to bias the differential input signals to the correct volt-
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
For price, delivery, and to place orders: Analog Devices, Inc.,
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
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age. The series capacitor, CI, form the high-pass pole
with these resistors, and the values must therefore be
determined based on the requirement to the high-pass
cut-off frequency.
Figure 7: AC coupled input
Note that startup time from Sleep Mode and Power
Down Mode will be affected by this lter as the time
required to charge the series capacitors is dependent
on the lter cut-off frequency.
If the input signal has a long traveling distance, and the
kick-backs from the ADC not are effectively terminated
at the signal source, the input network of gure 8 can
be used. The conguration in gure 8 is designed to
attenuate the kickback from the ADC and to provide
an input impedance that looks as resistive as possible
for frequencies below Nyquist. Values of the series
inductor will however depend on board design and
conversion rate. In some instances a shunt capaci-
tor in parallel with the termination resistor (e.g. 33pF)
may improve ADC performance further. This capacitor
attenuate the ADC kick-back even more, and minimize
the kicks traveling towards the source. However, the
impedance match seen into the transformer becomes
worse.
Figure 8: Alternative input network
Clock Input and Jitter considerations
Typically high-speed ADCs use both clock edges to
generate internal timing signals. In the HMCAD1050-
80 only the rising edge of the clock is used. Hence,
input clock duty cycles between 20% and 80% are
acceptable.
The input clock can be supplied in a variety of formats.
The clock pins are AC-coupled internally. Hence a
wide common mode voltage range is accepted. Differ-
ential clock sources as LVDS, LVPECL or differential
sine wave can be connected directly to the input pins.
For CMOS inputs, the CKN pin should be connected
to ground, and the CMOS clock signal should be con-
nected to CKP. For differential sine wave clock, the
input amplitude must be at least ± 800 mVpp.
The quality of the input clock is extremely important
for high-speed, high-resolution ADCs. The contribu-
tion to SNR from clock jitter with a full scale signal at a
given frequency is shown in equation 1,
SNRjitter = 20 · log (2 · π · ƒIN · єt) (1)
where fIN is the signal frequency, and εt is the total
rms jitter measured in seconds. The rms jitter is the
total of all jitter sources including the clock generation
circuitry, clock distribution and internal ADC circuitry.
For applications where jitter may limit the obtainable
performance, it is of utmost importance to limit the
clock jitter. This can be obtained by using precise and
stable clock references (e.g. crystal oscillators with
good jitter specications) and make sure the clock dis-
tribution is well controlled. It might be advantageous
to use analog power and ground planes to ensure
low noise on the supplies to all circuitry in the clock
distribution. It is of utmost importance to avoid cross-
talk between the ADC output bits and the clock and
between the analog input signal and the clock since
such crosstalk often results in harmonic distortion.
The jitter performance is improved with reduced rise
and fall times of the input clock. Hence, optimum jitter
performance is obtained with LVDS or LVPECL clock
with fast edges. CMOS and sine wave clock inputs will
result in slightly degraded jitter performance.
If the clock is generated by other circuitry, it should
be re-timed with a low jitter master clock as the last
operation before it is applied to the ADC clock input.
Digital Outputs
Digital output data are presented on parallel CMOS
form. The voltage on the OVDD pin set the levels of the
CMOS outputs. The output drivers are dimensioned to
drive a wide range of loads for OVDD above 2.25V,
but it is recommended to minimize the load to ensure
as low transient switching currents and resulting noise
as possible. In applications with a large fanout or large
capacitive loads, it is recommended to add external
buffers located close to the ADC chip.
The timing is described in the Timing Diagram section.
Note that the load or equivalent delay on CK_EXT
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
For price, delivery, and to place orders: Analog Devices, Inc.,
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
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always should be lower than the load on data outputs
to ensure sufficient timing margins.
The digital outputs can be set in tristate mode by set-
ting the OE_N signal high.
The HMCAD1050-80 employs digital offset correc-
tion. This means that the output code will be 4096 with
shorted inputs. However, small mismatches in para-
sitics at the input can cause this to alter slightly. The
offset correction also results in possible loss of codes
at the edges of the full scale range. With no offset
correction, the ADC would clip in one end before the
other, in practice resulting in code loss at the oppo-
site end. With the output being centered digitally, the
output will clip, and the out of range ags will be set,
before max code is reached. When out of range ags
are set, the code is forced to all ones for overrange
and all zeros for underrange.
Note that the out of range ags (ORNG) will behave
differently for 12 bit and 13 bit output. For 13 bit output
ORNG will be set when digital output data are all ones
or all zeros. For 12-bit output the ORNG ags will be
set when all twelve bits are zeros or ones and when
the thirteenth bit is equal to the rest of the bits.
Data Format Selection
The output data are presented on offset binary form
when DFRMT is low (connect to OVSS). Setting
DFRMT high (connect to OVDD) results in 2’s comple-
ment output format. Details are shown in table 3.
The data outputs can be used in three different con-
gurations.
• Normal Mode:
All 13 bits are used. MSB is Dx_12 and LSB is Dx_0.
This mode gives optimum performance
• 12-bit Mode:
The LSB is left unconnected such that only 12 bits
are used. MSB is Dx_12 and LSB is Dx_1. This mode
gives slightly reduced performance due to increased
quantization noise.
• Reduced Full Scale Range Mode:
The full scale range is reduced from 2 Vpp to 1 Vpp
which is equivalent to 6 dB gain in the ADC frontend.
Note that data are only available in 2’s complement
format in this mode. MSB is Dx_11 and LSB is Dx_0.
Note that the codes will wrap around when exceeding
the full scale range, and that out of range bits should
be used to clamp output data. See section Reference
Voltages for details. This mode gives slightly reduced
performance
Reference Voltages
The reference voltages are internally generated and
buffered based on a bandgap voltage reference. No
external decoupling is necessary, and the reference
voltages are not available externally. This simplies
usage of the ADC since two extremely sensitive pins,
otherwise needed, are removed from the interface.
If a lower full scale range is required the 13-bit output
word provides sufficient resolution to perform digital
scaling with an equivalent impact on noise compared
to adjusting the reference voltages.
A simple way to obtain 1.0Vpp input range with a
12-bit output word is shown in table 4. Note that only
2’s complement output data are available in this mode
and that out of range conditions must be determined
based on a two bit output. The output code will wrap
around when the code goes outside the full scale
range. The out of range bits should be used to clamp
the output data for overrange conditions.
Table 3: Data Format Description for 2Vpp Full Scale Range
Differential Input Voltage (IPx - INx) Output Data: Dx_12 : Dx_0
(DFRMT = 0, Offset Binary)
Output Data: Dx_12 : Dx_0
(DFRMT = 1, 2’s Complement)
1.0 V 1 1111 1111 1111 0 1111 1111 1111
+0.24mV 1 0000 0000 0000 0 0000 0000 0000
-0.24mV 0 1111 1111 1111 1 1111 1111 1111
-1.0V 0 0000 0000 0000 1 0000 0000 0000
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
For price, delivery, and to place orders: Analog Devices, Inc.,
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
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Table 4: Data Format Description for 1Vpp Full Scale Range
Differential Input Voltage
(IPx - INx)
Output data Dx_11:Dx_0
(DFRMT = 0)
(2’s Complement)
Out of Range
(Use Logical and Function
for &)
Output Data Dx_11:Dx_0
(DFRMT = 1)
(2’s Complement)
Out of Range
(Use Logical and Function
for &)
> 0.5V 0111 1111 1111 Dx_12 = 1 & Dx_11 = 1 0111 1111 1111 D_12 = 0 & D_11 = 1
0.5V 0111 1111 1111 0111 1111 1111
+0.24mV 0000 0000 0000 0000 0000 0000
-0.24mV 1111 1111 1111 1111 1111 1111
-0.5V 1000 0000 0000 1000 0000 0000
< -0.5V 1000 0000 0000 Dx_12 = 0 & Dx_11 = 0 1000 0000 0000 Dx_12 = 1 & Dx_11 = 0
Operational Modes
The operational modes are controlled with the PD_N
and SLP_N pins. If PD_N is set low, all other control
pins are overridden and the chip is set in Power Down
mode. In this mode all circuitry is completely turned off
and the internal clock is disabled. Hence, only leak-
age current contributes to the Power Down Dissipa-
tion. The startup time from this mode is longer than
for other idle modes as all references need to settle to
their nal values before normal operation can resume.
The SLP_N bus can be used to power down each
channel independently, or to set the full chip in Sleep
Mode. In This mode internal clocking is disabled, but
some low bandwidth circuitry is kept on to allow for a
short startup time. However, Sleep Mode represents
a signicant reduction in supply current, and it can be
used to save power even for short idle periods.
Startup Initialization
The HMCAD1050-80 must be reset prior to normal
operation. This is required every time the power
supply voltage has been switched off. A reset is per-
formed by applying Power Down mode. Wait until a
stable supply voltage has been reached, and pull the
PD_N pin for the duration of at least one clock cycle.
The input clock must be running continuously during
this Power Down period and until active operation
is reached. Alternatively the PD pin can be kept low
during power-up, and then be set high when the power
supply voltage is stable.
The input clock should be kept running in all idle
modes. However, even lower power dissipation is pos-
sible in Power Down mode if the input clock is stopped.
In this case it is important to start the input clock prior
to enabling active mode.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
For price, delivery, and to place orders: Analog Devices, Inc.,
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
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Outline Drawing
Table 6: 9x9 mm QFN (64 Pin LP9) Dimensions
Symbol Millimeter Inch
Min Typ Max Min Typ Max
A 0.9 0.035
A1 0 0.01 0.05 0 0.000 0.002
A2 0.65 0.7 0.026 0.028
A3 0.2 REF 0.008 REF
b 0.2 0.25 0.3 0.008 0.01 0.012
D 9.00 bsc 0.354 bsc
D1 8.75 bsc 0.344 bsc
D2 3.79 3.99 4.19 0.149 0.157 0.165
L 0.3 0.4 0.5 0.012 0.016 0.02
e 0.50 bsc 0.020 bsc
Θ1 0° 12° 0° 12°
F 1.9 0.075
G 0.24 0.42 0.6 0.010 0.017 0.024
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
For price, delivery, and to place orders: Analog Devices, Inc.,
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: apps@hittite.com
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0
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HMCAD1050-80
v01.0411
DUAL 13/12-BIT 65/80 MSPS
A/D CONVERTER
Package Information
Part Number Package Body Material Lead Finish MSL [1] Package Marking [2]
HMCAD1050-80 RoHS-compliant Low Stress Injection Molded Plastic 100% matte Sn Level 2A
ASD0500
XXXX
XXXX
[1] MSL, Peak Temp: The moisture sensitivity level rating classied according to the JEDEC industry standard and to peak solder temperature.
[2] Proprietary marking XXXX, 4-Digit lot number XXXX
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
For price, delivery, and to place orders: Analog Devices, Inc.,
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
Phone: 781-329-4700 • Order online at www.analog.com
Application Support: Phone: 1-800-ANALOG-D
