Device Engineering Incorporated 385 East Alamo Drive Chandler, AZ 85225 Phone: (480) 303-0822 Fax: (480) 303-0824 E-mail: admin@deiaz.com DEI3283 DUAL ARINC 429 LINE RECEIVER FEATURES * * * * * * * * * * Two separate analog receiver channels Converts ARINC 429 levels to serial data ARINC 429 inputs withstand +/-200V TTL inputs to test complete analog/digital RX function TTL and CMOS compatible outputs Low power dissipation Internal band gap voltage reference MIL-STD-883B burn-in screening available Package Options: 20 Lead ceramic DIP, 20 Terminal ceramic LCC, and 20 Lead SOIC Direct replacement for Fairchild/Raytheon RM3283 and RM3183 and Holt HI-8482 Function Diagram (c)2010 Device Engineering Inc Page 1 of 11 DS-MW-03283-01 Rev K 08/10/10 General Description The DEI3283 consists of two analog ARINC 429 receivers which take differentially encoded ARINC level data and convert it to serial TTL level data. The DEI3283 provides two complete analog ARINC receivers with no external components required. Input level shifting thin film resistors and bipolar technology allow ARINC input voltage transients up to 200V without damage to the DEI3283. Each channel is identical, featuring symmetrical propagation delays for better high speed performance. Input common mode rejection is excellent and threshold voltage is stable, independent of supply voltage. Data outputs are TTL and CMOS compatible. Two TTL compatible test inputs used to test the ARINC channels are available. They can be used to override the ARINC input data and set the channel outputs to a known state. The DEI ARINC line driver family IC's are companion chips to the DEI3283 line receiver. Together they provide the analog functions needed for the ARINC 429 interface. Functional Description The DEI3283 contains two discrete ARINC 429 receiver channels. Each channel contains three main sections: a resistor input network, a window comparator, and a logic output buffer stage. The first stage provides over voltage protection and biases the signal using voltage dividers and current sources, providing excellent input common mode rejection. The test inputs are provided to set the outputs to a predetermined state for built-in channel test capability. If the test inputs are not used, they should be grounded. The window comparator section detects data from the resistor input network. A LOGIC 1 corresponds to ARINC "High" state (OUTA) and a LOGIC 0, to ARINC "Low" state (OUTB). An ARINC "Null" state at the inputs forces both outputs to LOGIC 0. Threshold and hysteresis voltages are generated by a band gap voltage reference to maintain stable switching characteristics over temperature and power supply variations. The output stage generates a TTL compatible logic output capable of driving 3mA of load. Pin Assignments PIN 1 2 3 4 5 6 7 NAME -Vs TEST A CAP2B IN2B OUT2B IN2A CAP2A (c)2010 Device Engineering Inc DESCRIPTION Supply Voltage (-15V) Logic Input, see functional characteristics. A429 INPUT, Ch 2, B Capacitor node A429 INPUT, Ch 2, B input Logic Output, Ch 2, B's output A429 INPUT, Ch 2, A input A429 INPUT, Ch 2, A Capacitor node Page 2 of 11 DS-MW-03283-01 Rev K 08/10/10 PIN 8 9 10 11 12 13 14 15 16 17 18 19 20 NAME OUT2A +VL NC +VS OUT1B NC GND OUT1A IN1B CAP1B IN1A CAP1A TESTB DESCRIPTION Logic Output, Ch 2, A's output Supply Voltage (+5V) Supply Voltage (+15V) Logic Output, Ch 1, B's output Supply Return Logic Output, Ch 1, A's output A429 INPUT, Ch 1, B input A429 INPUT, Ch 1, B Capacitor node A429 INPUT, Ch 1, A input A429 INPUT, Ch 1, A Capacitor node Logic Input, see functional characteristics. Absolute Maximum Ratings Parameter Supply Voltage: Min. +VS to -VS +VS to GND -Vs to GND +VL Voltage Logic Input Voltage ARINC 429 Input Voltage Temperature Range Storage Operating Junction Temperature Ceramic Plastic Lead Soldering Temperature (60 sec., DIP, LCC) Peak Body Temperature, J-STD-020 (SOIC) Non-G Package -G Package Max. +36 +20 -20 +7 +VL + 0.3 +200 +150 +125 +175 +145 +300 -0.3 -200 -65 -55 -55 -55 +240 +260 Units V V V V V V C C C C C Recommended Operating Conditions Symbol Parameters Min. Max. Units +Vs -Vs +VL Top Positive Supply Voltage Negative Supply Voltage +VL Supply Voltage Case Temperature Ceramic Plastic: -SA -SE 13.5 -16.5 4.5 16.5 -13.5 5.5 V V V -55 -40 -55 +125 +125 +85 C C C (c)2010 Device Engineering Inc Page 3 of 11 DS-MW-03283-01 Rev K 08/10/10 Electrical Characteristics Symbol ICC IEE IL Parameter +VS (+15V) Supply Current -Vs (-15V) Supply Current +VL (+5V) Supply Current VHH NULL to 1 transition, V(INA) - V(INB) VHL 1 to NULL transition, V(INA) - V(INB) VHHYS 1 to NULL transition hysteresis NULL to 0 transition, V(INA) - V(INB) VLL VHL 0 to NULL transition, V(INA) - V(INB) VLHYS 0 to NULL transition hysteresis Input common mode voltage range Input resistance, Input to GND Input resistor, INA to CAPA, INB to CAPB Input capacitance, INA to GND, INB to GND VCM RINGND RIN CIN VIH VIL IIH LOGIC 1 input voltage LOGIC 0 input voltage LOGIC 1 input current IIL LOGIC 0 input current VOH LOGIC 1 output voltage VOL LOGIC 0 output voltage (c)2010 Device Engineering Inc Conditions (1,2) POWER SUPPLIES Supply = +/- 16.5V, Vl = 5.0V, Test Inputs = 0V Test Inputs = 5V Supply = +/- 16.5V, Vl = 5.0V, Test Inputs = 0V Test Inputs = 5V Supply = +/- 16.5V, Vl = 5.0V, Test Inputs = 0V Test Inputs = 5V A429 INPUTS Supply = +/-15.0V, Vl = 5.00V Test inputs = 0V VINB = -2.50V Supply = +/-15.0V, Vl = 5.00V Test inputs = 0V VINB = -2.50V VHH-VHL Supply = +/-15.0V, Vl = 5.00V Test inputs = 0V VINB = +2.50V Supply = +/-15.0V, Vl = 5.00V Test inputs = 0V VINB = +2.50V VLL-VLH Unpowered, INA to GND, INB to GND Unpowered INA to CAPA, INB to CAPB Min. Page 4 of 11 Units 3.5 3.5 6.0 6.0 mA 7.5 11.0 12.0 18.5 mA 4.5 10.8 9.0 17.6 mA 5.70 6.30 V 4.50 5.50 V 0.8 1.2 V -6.30 -5.70 V -5.50 -4.50 V -1.2 -0.8 V -13 +13 V 20 30 k 8.5 11.5 k 10 pF 0 0.9 300 V V A 0 40 A (3) TEST LOGIC INPUTS Functional Test Functional Test VIH = 5V Supply = +/-15.0V, Vl = 5.00V VIL = 0.8V Supply = +/-15.0V, Vl = 5.00V LOGIC OUTPUTS Vsupply = +/-15.0V, Vl = 5.0V IOH = -100uA (Room Temp) IOH = -2.8mA Vsupply = +/-15.0V, Vl = 5.0V IOL = 100uA (Room Temp) IOL = 2.0mA Max. 2.0 4.0 3.5 V V 0.1 0.8 V V DS-MW-03283-01 Rev K 08/10/10 Symbol Tr Tf TPLH TPHL DTP TPTLH TPTHL Notes: 1. 2. 3. 4. Parameter Output rise time Output Fall Time Prop delay, A429 to LH output Prop delay, A429 to HL output Matching of TPLH and TPHL Prop delay, TESTA/B to LH output Prop delay, TESTA/B to HL output Conditions (1,2) CL = 60 pF (4) CL = 60 pF (4) A429 In = 0 to 10V (4) CAPA, CAPB, OUT CL = 60 pF A429 In = 0 to 10V (4) CAPA, CAPB, OUT CL = 60 pF |TPLH-TPHL| (4) Min. 10 10 Max. 70 70 1500 Units ns ns ns 1500 ns 500 ns CL = 60 pF, VIN = 0.8V/2.0V (4) 400 600 ns CL = 60 pF, VIN = 0.8V/2.0V (4) 800 1300 ns Unless otherwise noted, currents flowing in to DUT are positive, Currents flowing out of DUT are negative, Voltages are referenced to Ground. Unless otherwise noted, Tcase = -55C to +125C for -xMx, -40C to +125C for -xAx, and -55C to +85C for -xEx versions; +VS = +13.5 to 16.5V, -Vs = -13.5 to -16.5V, +VL = 4.5 to 5.5V. Guaranteed by design. Not production tested. Sample tested. AC Test Waveforms (c)2010 Device Engineering Inc Page 5 of 11 DS-MW-03283-01 Rev K 08/10/10 Functional Characteristics ARINC Inputs V(A) - V(B) Null Low High X X X Test Inputs TEST A TEST B 0 0 0 0 0 0 0 1 1 0 1 1 Outputs OUT_A 0 0 1 0 1 0 OUT_B 0 1 0 1 0 0 Output State Null Low High Low High Null V[INA - INB] V[OUT_A] V[OUT_B] Parameter Time Y Time X Pulse rise time Pulse fall time Vhigh Vhh Vhl Vnull Vll Vlh Vlow (c)2010 Device Engineering Inc Characteristics (100KBS) min max units 9.75 10.25 us 4.87 5.13 us 0.5 2 us 0.5 2 us +7.25 11 V diff +6.5 V diff +2.5 V diff -0.5 +0.5 V diff -2.5 V diff -6.5 V diff -11 -7.25 V diff Page 6 of 11 DS-MW-03283-01 Rev K 08/10/10 Applications Discussion The standard connections for the DEI3283 are shown in the figure below. Dual 15VDC supplies are recommended for the +VS/-VS supplies. Decoupling of all supplies should be done near the IC to avoid propagation of noise spikes due to switching transients. The ground connection should be sturdy and isolated from large switching currents to provide as quiet a ground reference as possible. The noise filter capacitors are optional and are added to provide extra noise immunity by limiting bandwidth of the input signal before it reaches the window comparator stage. Two capacitors are used for each channel and they must be the same value. The suggested capacitor value for a 100 kHz operation is 39 pF. For lower data rates, larger values of capacitance may be used to yield better noise performance. To get optimum performance, the following equation can be used to calculate capacitor value for a specific data rate: Where CFILTER is the capacitor value in pF, and FO is the input frequency (10 kHz FO 150 kHz). Applications ARINC Receiver Standard Connections (c)2010 Device Engineering Inc Page 7 of 11 DS-MW-03283-01 Rev K 08/10/10 Process Flow Process Step THERMAL CYCLE MIL-STD-883B M1010.4 Condition B CONSTANT ACCELERATION MIL-STD-883B M2001, Method D. GROSS & FINE LEAK MIL-STD-883B M1014.10 PRE-BURN-IN Electrical Test BURN IN MIL-STD-883B M1015 Condition A FINAL ELECTRICAL TEST, Room Temperature FINAL ELECTRICAL TEST, High Temperature FINAL ELECTRICAL TEST, Low Temperature Plastic Standard Ceramic Standard Plastic Burn-In Ceramic Burn-In NO 10 Cycles NO 10 Cycles N/A YES N/A YES N/A YES N/A YES N/A N/A YES YES N/A N/A 100% 100% @ +85 or +125C 0.65% AQL @ -55 or -40C 100% 100% @ +125C 0.65% AQL @ -55C 160hrs @ +125 C 160hrs @ +125 C 100% 100% @ +85 or +125C 0.65% AQL @ -55 or -40C 100% 100% @ +125C 0.65% AQL @ -55C Burn-In Circuit (c)2010 Device Engineering Inc Page 8 of 11 DS-MW-03283-01 Rev K 08/10/10 Package Characteristics Package Characteristics 20L 20L CERDIP 20L CERDIP Ceramic GREEN LCC 20L SOIC 20L SOIC GREEN Reference (see ordering info) 20 CLCC 20 CERDIP 20 CERDIP G 20 SOIC 20 SOIC G JEDEC MO Reference MO-047 MS-030-AAE MS-030-AAE MS-013-AE MS-013-AE 85 C/W 30 C/W 70 C/W 28 C/W 70 C/W 28 C/W 85 C/W 30 C/W 85 C/W 30 C/W Hermetic Hermetic Hermetic SnPb solder dip na Not Pb-free SnPb solder dip na Not Pb-free SnAgCu solder dip e1 Pb free MSL 1 / 250C SnPb plate na Not Pb-free MSL 1 / 250C Matte Sn e3 PACKAGE TYPE THERMAL RESISTANCE: JA (4 layer PCB) JC JEDEC Moisture Sensitivity Level (MSL) Lead Finish Material / JEDEC Pb-free code Pb-Free DESIGNATION RoHS Compliant 20L SOIC ( - G and non - G ) Package (c)2010 Device Engineering Inc Page 9 of 11 DS-MW-03283-01 Rev K 08/10/10 20L CERDIP (-G and non-G) Package 20L Ceramic LCC Package (c)2010 Device Engineering Inc Page 10 of 11 DS-MW-03283-01 Rev K 08/10/10 Ordering Information Part Number DEI3283-CMB Marking 20 CERDIP Operating Temperature Range -55C to +125C 20 CERDIP G -55C to +125C Y 20 CERDIP -55C to +125C N 20 CERDIP G -55C to +125C N 20 CLCC -55C to +125C Y Package Burn In Y DEI3283-EMB DEI3283-CMB DEI3283-CMB E1 DEI3283-CMS DEI3283-CMS E1 DEI3283-EMB DEI3283-EMS DEI3283-EMS 20 CLCC -55C to +125C N DEI3283-SAB DEI3283-SAB DEI3283-SAB E3 DEI3283-SAS DEI3283-SAS E3 DEI3283-SEB DEI3283-SEB E3 DEI3283-SES DEI3283-SES E3 DEI3283-SMB DEI3283-SMB E3 DEI3283-SMS DEI3283-SMS E3 20 SOIC -40C to +125C Y 20 SOIC G -40C to +125C Y 20 SOIC -40C to +125C N 20 SOIC G -40C to +125C N 20 SOIC -55C to +85C Y 20 SOIC G -55C to +85C Y 20 SOIC -55C to +85C N 20 SOIC G -55C to +85C N 20 SOIC -55C to +125C Y 20 SOIC G -55C to +125C Y 20 SOIC -55C to +125C N 20 SOIC G -55C to +125C N DEI3283-CMB-G DEI3283-CMS DEI3283-CMS-G DEI3283-SAB-G DEI3283-SAS DEI3283-SAS-G DEI3283-SEB DEI3283-SEB-G DEI3283-SES DEI3283-SES-G DEI3283-SMB DEI3283-SMB-G DEI3283-SMS DEI3283-SMS-G Notes: 1. All packages marked with Lot Code and Date Code. "E1" or "E3" after Date Code denotes Pb Free category. 2. The -CMB/-EMB/-SAB/-SEB/-SMB parts may be marked as - CMS/-EMS/-SAS/-SES/-SMS with a "B" stamp to denote burn-in. DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose. (c)2010 Device Engineering Inc Page 11 of 11 DS-MW-03283-01 Rev K 08/10/10