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KK5/wD4Q3S/+frXP/B7e/8Ax6ugoAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigAooooAKKKKACiiigArj/AIj2us3fh63j0Pw5pWvXQu1LWupxo8aJsfLgOyjcDgdejHiuwooA+f8A+xfiH/0SLwN/4CW//wAeo/sX4h/9Ei8Df+Alv/8AHq+gKKAPn/8AsX4h/wDRIvA3/gJb/wDx6j+xfiH/ANEi8Df+Alv/APHq+gKKAPn/APsX4h/9Ei8Df+Alv/8AHqP7F+If/RIvA3/gJb//AB6voCigD5//ALF+If8A0SLwN/4CW/8A8eo/sX4h/wDRIvA3/gJb/wDx6voCigD5/wD7F+If/RIvA3/gJb//AB6j+xfiH/0SLwN/4CW//wAer6AooA+f/wCxfiH/ANEi8Df+Alv/APHqP7F+If8A0SLwN/4CW/8A8er6AooA+f8A+xfiH/0SLwN/4CW//wAeo/sX4h/9Ei8Df+Alv/8AHq+gKKAPn/8AsX4h/wDRIvA3/gJb/wDx6j+xfiH/ANEi8Df+Alv/APHq+gKKAPn/APsX4h/9Ei8Df+Alv/8AHqP7F+If/RIvA3/gJb//AB6voCigD5//ALF+If8A0SLwN/4CW/8A8eo/sX4h/wDRIvA3/gJb/wDx6voCigD5/wD7F+If/RIvA3/gJb//AB6j+xfiH/0SLwN/4CW//wAer6AooA+f/wCxfiH/ANEi8Df+Alv/APHqP7F+If8A0SLwN/4CW/8A8er6AooA+f8A+xfiH/0SLwN/4CW//wAeo/sX4h/9Ei8Df+Alv/8AHq+gKKAPn/8AsX4h/wDRIvA3/gJb/wDx6j+xfiH/ANEi8Df+Alv/APHq+gKKAPn/APsX4h/9Ei8Df+Alv/8AHqP7F+If/RIvA3/gJb//AB6voCigD5//ALF+If8A0SLwN/4CW/8A8eo/sX4h/wDRIvA3/gJb/wDx6voCigD5/wD7F+If/RIvA3/gJb//AB6j+xfiH/0SLwN/4CW//wAer6AooA+f/wCxfiH/ANEi8Df+Alv/APHqP7F+If8A0SLwN/4CW/8A8er6AooA+f8A+xfiH/0SLwN/4CW//wAeo/sX4h/9Ei8Df+Alv/8AHq+gKKAPn/8AsX4h/wDRIvA3/gJb/wDx6j+xfiH/ANEi8Df+Alv/APHq+gKKAPn/APsX4h/9Ei8Df+Alv/8AHqP7F+If/RIvA3/gJb//AB6voCigD5//ALF+If8A0SLwN/4CW/8A8eo/sX4h/wDRIvA3/gJb/wDx6voCigD5/wD7F+If/RIvA3/gJb//AB6j+xfiH/0SLwN/4CW//wAer6AooA+f/wCxfiH/ANEi8Df+Alv/APHqP7F+If8A0SLwN/4CW/8A8er6AooA+f8A+xfiH/0SLwN/4CW//wAeo/sX4h/9Ei8Df+Alv/8AHq+gKKAPn/8AsX4h/wDRIvA3/gJb/wDx6j+xfiH/ANEi8Df+Alv/APHq+gKKAPn/APsX4h/9Ei8Df+Alv/8AHqP7F+If/RIvA3/gJb//AB6voCigD5//ALF+If8A0SLwN/4CW/8A8eo/sX4h/wDRIvA3/gJb/wDx6voCigDz/wCGVl4is/7U/t/whofh7d5Xk/2VFGnn437t+x2zt+XGcfeNegUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAFFFFABRRRQAUUUUAfNfhz4qeNL/Q725udZ3yxCXY32WEY2xMw4CeoBrpfGPj/xPpXiGK1stT8qFr21iK+RE3yuoLDJUnmiitGl7Ob8v8jPGtxpJx00f/tn+Z53pPxm8f3Ws2NvNr+6KW4jR1+xwDILAEcJXXaF8TPF954Mu9QuNX33Ub3IWT7NEMBEQrwExwSaKKzju/l/6Ugi37a3+H/246DSfHXiS5OpedqO7ybMyx/uIxhvs6Pnhf7zE0W/jrxJJZ3EjajlkjuGU+RHwVDbf4e2BRRWeNbiqnLpb2f4xlf7+pN37Jv+/JfLlkUdd+IPiizWQ2+qbMSSgf6PEeBaeYOq/wB7n/61Q618RfFVpdXyQarsWKRlQfZ4jgC08zuv97n/AOtRRRhW5Uot9v1idsUr0/PmLv8Awn3ib+xL+4/tP97FE7I3kR8EWsMg/h/vOx/H0rjvHfxZ8b6N411HT9P1vybWFkEcf2WFsZRSeShPUmiimnr/AF2RzUdaEW97v8oiwfFnxu/gO51JtbzdpcbFk+yw8DKcY2Y7ntWn4s+J3jDTNMuJrPV/LkS6hjU/ZoThWgVyOU/vEmiipbftZr0/Kn/m/vZnNtSX9dUcT/wu34h/9DD/AOSVv/8AG69M8dfEHxRo2i3dxYap5MsdzEit9nibCsGyOVPoKKK3W0vT9Uehh4pxnddDzP8A4Xb8Q/8AoYf/ACSt/wD43T1+NfxCKMf+Eg5C5/48rf1H/TOiil0f9dTkYkfxr+ITMQfEH8JP/Hlb+n/XOm/8Lt+If/Qw/wDklb//ABuiiky/s/15Fg/Gj4gbZz/b/wB3p/ocHHOP7lPm+M3j9WlC6/jaikf6HB1P/AKKKqPxL5f+2hPdmr4c+Lfji/8AGVhYXOt77WVgHT7JCM/JnqEz1qlo/wAYvHt1cSrNr24LaySAfY4B8wBweEoorfCRUoK6/rQ5237Rr0/Nk/iv4veOtN8Q3draa55cMcjqq/ZIDgB2A5KZ6AVN4Q+LXjjVNTnhvNb82NYlYD7JCuCZY17IOzEfjRRWEvil8/1Hi24xdtNV+aLHjz4reNdF15bbT9a8mEo5K/ZYW5E0qjkoeyqPwrl/+F2/EP8A6GH/AMkrf/43RRXLhZOVJN+f5mo+T41/EJXIHiDjJ/5crf1/6509vjT8QRYxSDxB87SOpP2O36ALj+D3NFFdE9Gvl+RT3ZveGPix431C3umutb8xkD7T9lhGMQSsOif3lU/hXN/8Lt+If/Qw/wDklb//ABuiiqno/kiH8dvJfmz0fwJ8RPFWs+Hprq/1Xzplm2hvs8S4HmQjoFA6O351yniz4u+OdM117az1zy4RFGwX7JAeSoJ5KUUVz1W1ilFbc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PIC18F2XK20/4XK20
DS41303G-page 450 2010 Microchip Technology Inc.
PIR1 (Peripheral Interrupt Request 1) .....................112
PIR2 (Peripheral Interrupt Request 2) .....................113
PSTRCON (Pulse Steering Control) ........................187
PWM1CON (Enhanced PWM Control) ....................186
RCON (Reset Control) .......................................52, 118
RCON (Reset cont rol) ...... .............. ............... ...........118
RCSTA (Receive Status and Control) ......................247
SLRCON (PORT Slew Rate Control) .......................138
SSPADD (MSS P Addr ess and Baud Rate,
SPI Mode) ........................................................203
SSPCON1 (MS SP Control 1, I2C Mode) .................205
SSPCON1 (MS SP Control 1, SPI Mode) .................195
SSPCON2 (MS SP Control 2, I2C Mode) .................206
SSPMSK (SSP Mas k) ...... ..................... ...................213
SSPSTAT (MSSP Status, SPI Mode) ..............194, 204
STATUS ..................................................................... 82
STKPTR (St a ck Poin ter) ..................... .............. .........67
T0CON (Timer0 Co n tr o l) ................... ........ ...............155
T1CON (Timer1 Co n tr o l) ................... ........ ...............159
T2CON (Timer2 Co n tr o l) ................... ........ ...............167
T3CON (Timer3 Co n tr o l) ................... ........ ...............169
TRISE (PORTE/PSP Control) ..................................134
TXSTA (Transmit Status and Control) .....................246
WDTCON (Watchdog Tim er Contro l) .......................309
RESET .............................................................................345
Reset St a te of Registers ........ ..................... ..................... ..58
Resets ........................................................................ 51, 299
Brown-out Reset (BOR) ...........................................299
Oscillator Start-up Timer (OST) .......... .....................299
Power-on Res e t (POR) .............. ..................... .........299
Power-up Timer (PWRT) ..... ............... .............. .......299
RETFIE ............................................................................346
RETLW .............................................................................346
RETURN ..........................................................................347
Return Ad d ress Stack ....... ............................ .....................66
Return Stack Pointe r (STKPTR) ............ ..................... .......67
Revision History ...............................................................441
RLCF ................................................................................347
RLNCF .............................................................................348
RRCF ...............................................................................348
RRNCF .............................................................................349
S
SCK ..................................................................................193
SDI ...................................................................................193
SDO .................................................................................193
SEC_IDLE Mode ................................ .... ......... .... .... .... .......47
SEC_RUN Mode ................................................................44
Serial Clock, SCK .............................................................193
Serial Data In (SDI) ..........................................................193
Serial Data Out (SDO) .....................................................193
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 349
Shoot-through Current .....................................................185
Single-Supply ICSP Programming.
Slave Select (SS) ............................................................. 193
Slave Select Synchronization ...........................................199
SLEEP ..............................................................................350
Sleep
OSC1 and OSC2 Pin States ............... .... .. .... .. .. ....... ..36
Sleep Mode . .......................................................................45
Slew Rate .........................................................................138
SLRCON Register ............................................................138
Softwa re Simulator ( MP L AB SIM) ........................... .........367
SPBRG .............................................................................249
SPBRGH .......................................................................... 249
Special Event Trigger ...................................................... 269
Special Event Trigger. See Compare (ECCP Mode).
Special Event Trigger. See Compare (ECCP Module).
Special Features of the CPU ........................................... 299
Special Function Registers ................................................ 77
Map .. .......... ............. .............. ............. ............. ........... 78
SPI Mode (MSS P)
Associated Registers ............................................... 201
Bus Mode Compatibility ..... ......................... ............. 201
Effects of a Reset .. .............. ............... ............... ...... 201
Enabling SPI I/O ...................................................... 197
Master Mode ............................................................ 198
Master/Slave Connection .................. .... .... .. ....... .... .. 197
Operation ................................................................. 196
Operation in Power Managed Modes ...................... 201
Serial Clock .............................................................. 193
Serial Data In ........................................................... 193
Serial Data Out ........................................................ 193
Slave Mode ............................................................ .. 199
Slave Select ........................... ..................... ............. 193
Slave Select Synchronization .................................. 199
SPI Clock ................................................................. 198
Typical Connection ......................... .... .... .. ......... .... .. 197
SS .................................................................................... 193
SSPADD Registe r .............. ............... ........ ............... ........ 203
SSPCON1 Register ................................................. 195, 205
SSPCON2 Register ......................................................... 206
SSPMSK Register ..................... ............... ..................... ..213
SSPOV ............................................................................225
SSPOV Status Flag ......................................................... 225
SSPSTAT Regi ster ... ............... ..................... ........... 194, 204
R/W Bit .... ...... .. ..... ...... ...... ...... . ...... ...... ...... ..... . 207 , 2 0 8
Stack Full/Underflow Resets .............................................. 68
Standard Instructions . . ..................................................... 315
STATUS Regi ster ..... ............... ..................... ..................... 82
STKPTR Register ..... ............... ..................... ............... ...... 67
SUBFSR .......................................................................... 361
SUBFWB ......................................................................... 350
SUBLW ............................................................................351
SUBULNK ........................................................................ 361
SUBWF ............................................................................ 351
SUBWFB ......................................................................... 352
SWAPF ............................................................................352
T
T0CON Registe r ...................... ............... ............... .......... 155
T1CON Registe r ...................... ............... ............... .......... 159
T2CON Registe r ...................... ............... ............... .......... 167
T3CON Registe r ...................... ............... ............... .......... 169
Table Pointer Operations (table) ........................................ 92
Table Reads/Table Writes ................................................. 68
TBLRD ............................................................................. 353
TBLWT ............................................................................. 354
Time - ou t in Vari o u s Si t u a ti o n s (tabl e ) .. .. .. ...... ...... . ...... .. ..... 55
Timer0 .............................................................................. 155
Associated Registers ............................................... 157
Operation ................................................................. 156
Overflow In terrupt ............ ..................... ................... 157
Prescaler ................................................................. 157
Prescaler Assignment (PSA Bit) .............................. 157
Presca le r Select (T0PS2 :T0 PS0 Bits) ..................... 157
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 156
Source Edge Select (T0SE Bit) ............................... 156
Source Se lect (T0CS Bit) ........................ ................. 156
Switching Prescaler Assignment ............................. 157