INDUSTRIAL TEMPERATURE RANGE
IDT5T9310
2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II
1
GL
G1
PD
A1
A1
A2
G2
A2
SEL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
Q2
Q2
Q1
Q1
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q8
Q8
Q9
Q9
1
0
OUTPUT
CONTROL
Q10
Q10
MARCH 2005
IDT5T9310
INDUSTRIAL TEMPERATURE RANGE
2.5V LVDS 1:10
CLOCK BUFFER
TERABUFFER™ II
DESCRIPTION:
The IDT5T9310 2.5V differential clock buffer is a user-selectable differential
input to ten LVDS outputs. The fanout from a differential input to ten LVDS outputs
reduces loading on the preceding driver and provides an efficient clock
distribution network. The IDT5T9310 can act as a translator from a differential
HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to
LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to
translate to LVDS outputs. The redundant input capability allows for an
asynchronous change-over from a primary clock source to a secondary clock
source. Selectable reference inputs are controlled by SEL.
The IDT5T9310 outputs can be asynchronously enabled/disabled. When
disabled, the outputs will drive to the value selected by the GL pin. Multiple power
and grounds reduce noise.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2005 Integrated Device Technology, Inc. DSC-6175/18
FEATURES:
• Guaranteed Low Skew < 25ps (max)
• Very low duty cycle distortion < 125ps (max)
• High speed propagation delay < 1.75ns (max)
• Up to 1GHz operation
• Selectable inputs
• Hot insertable and over-voltage tolerant inputs
• 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),
CML, or LVDS input interface
• Selectable differential inputs to ten LVDS outputs
• Power-down mode
• 2.5V VDD
• Available in VFQFPN package
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
• Clock distribution
INDUSTRIAL TEMPERATURE RANGE
2
IDT5T9310
2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II
PIN CONFIGURATION
24
30
29
28
27
26
25
23
22
21
PD
G2
A2
Q7
Q7
Q6
Q6
VDD
A2
VDD
20
1611 12 13 14 15 17 18 19
Q
3
Q
3
Q
4
Q
4
V
DD
GL
Q
5
Q
5
V
DD
GND
39 38 37 36 35 34 33 32 31
40
V
DD
SEL
Q
10
Q
10
Q
9
Q
9
Q
8
Q
8
V
DD
NC
1
2
3
4
5
6
7
8
9
10
VDD
G1
Q1
Q1
Q2
Q2
GND
VDD
A1
A1
GND
VFQFPN
TOP VIEW
INDUSTRIAL TEMPERATURE RANGE
IDT5T9310
2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II
3
Symbol Description Max Unit
VDD Power Supply Voltage –0.5 to +3.6 V
VIInput Voltage –0.5 to +3.6 V
VOOutput Voltage(2) –0.5 to VDD +0.5 V
TSTG Storage Temperature –65 to +150 °C
TJJunction Temperature 1 5 0 °C
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Not to exceed 3.6V.
Symbol Parameter Min Typ. Max. Unit
CIN Input Capacitance —— 3pF
CAPACITANCE(1) (TA = +25°C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested
Symbol Description Min. Typ. Max. Unit
TAAmbient Operating Temperature –40 +25 +85 °C
VDD Internal Power Supply Voltage 2.3 2.5 2.7 V
RECOMMENDED OPERATING RANGE
PIN DESCRIPTION
Symbol I/O Type Description
A[1:2] I Adjustable(1,4) Clock input. A[1:2] is the "true" side of the differential clock input.
A[1:2] I Adjustable(1,4) Complementary clock inputs. A[1:2] is the complementary side of A[1:2]. For LVTTL single-ended operation, A[1:2] should be set to the
desired toggle voltage for A[1:2]:
3.3V LVTTL VREF = 1650mV
2.5V LVTTL VREF = 1250mV
G1I LVTTL Gate control for differential outputs Q1 and Q1 through Q5 and Q5. When G1 is LOW, the differential outputs are active. When G1 is
HIGH, the differential outputs are asynchronously driven to the level designated by GL(2).
G2I LVTTL Gate control for differential outputs Q6 and Q6 through Q10 and Q10. When G2 is LOW, the differential outputs are active. When G2 is
HIGH, the differential outputs are asynchronously driven to the level designated by GL(2).
GL I LVTTL Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary" outputs disable LOW. If LOW, "true"
outputs disable LOW and "complementary" outputs disable HIGH.
Qn O LVDS Clock outputs
Qn O LVDS Complementary clock outputs
SEL I LVTTL Reference clock select. When LOW, selects A2 and A2. When HIGH, selects A1 and A1.
PD I LVTTL Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode. Inputs and outputs are disabled. Both
"true" and "complementary" outputs will pull to VDD. Set HIGH for normal operation.(3)
VDD PWR Power supply for the device core and inputs
GND PWR Power supply return for all power
NC No connect; recommended to connect to GND
NOTES:
1. Inputs are capable of translating the following interface standards:
Single-ended 3.3V and 2.5V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL (2.5V) and LVPECL (3.3V) levels
Differential LVDS levels
Differential CML levels
2. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt
pulses or be able to tolerate them in down stream circuitry.
3. It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-
up after asserting PD.
4. The user must take precautions with any differential input interface standard being used in order to prevent instability when there is no input signal.
INDUSTRIAL TEMPERATURE RANGE
4
IDT5T9310
2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVTTL(1)
Symbol Parameter Test Conditions Min. Typ.(2) Max Unit
Input Characteristics
IIH Input HIGH Current VDD = 2.7V — — ±5 µA
IIL Input LOW Current VDD = 2.7V — — ±5
VIK Clamp Diode Voltage VDD = 2.3V, IIN = -18mA — - 0.7 - 1.2 V
VIN DC Input Voltage - 0.3 — +3.6 V
VIH DC Input HIGH 1.7 — — V
VIL DC Input LOW — — 0. 7 V
VTHI DC Input Threshold Crossing Voltage — VDD /2 — V
VREF Single-Ended Reference Voltage(3) 3.3V LVTTL — 1.65 — V
2.5V LVTTL — 1.25 —
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. Typical values are at VDD = 2.5V, +25°C ambient.
3. For A[1:2] single-ended operation, A[1:2] is tied to a DC reference voltage.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR DIFFER-
ENTIAL INPUTS(1)
Symbol Parameter Test Conditions Min. Typ.(2) Max Unit
Input Characteristics
IIH Input HIGH Current VDD = 2.7V — — ±5 µA
IIL Input LOW Current VDD = 2.7V — — ±5
VIK Clamp Diode Voltage VDD = 2.3V, IIN = -18mA — - 0.7 - 1.2 V
VIN DC Input Voltage - 0.3 — +3.6 V
VDIF DC Differential Voltage(3) 0.1 — — V
VCM DC Common Mode Input Voltage(4) 0.05 — VDD V
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. Typical values are at VDD = 2.5V, +25°C ambient.
3. VDIF specifies the minimum input differential voltage (VTR - V CP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. The DC differential
voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state.
4. VCM specifies the maximum allowable range of (VTR + VCP) /2.
DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING
RANGE FOR LVDS(1)
Symbol Parameter Test Conditions Min. Typ.(2) Max Unit
Output Characteristics
VOT(+) Differential Output Voltage for the True Binary State 247 — 454 mV
VOT(-) Differential Output Voltage for the False Binary State 247 — 454 mV
∆VOT Change in VOT Between Complementary Output States — — 50 mV
VOS Output Common Mode Voltage (Offset Voltage) 1.125 1.2 1.375 V
∆VOS Change in VOS Between Complementary Output States — — 50 mV
IOS Outputs Short Circuit Current VOUT + and VOUT - = 0V — 12 24 mA
IOSD Differential Outputs Short Circuit Current VOUT + = V OUT -—612mA
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. Typical values are at VDD = 2.5V, TA = +25°C ambient.
INDUSTRIAL TEMPERATURE RANGE
IDT5T9310
2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II
5
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR eHSTL
Symbol Parameter Value Units
VDIF Input Signal Swing(1) 1V
VXDifferential Input Signal Crossing Point(2) 900 mV
DHDuty Cycle 50 %
VTHI Input Timing Measurement Reference Level(3) Crossing Point V
tR, tFInput Signal Edge Rate(4) 2 V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2 . A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under
actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR HSTL
Symbol Parameter Value Units
VDIF Input Signal Swing(1) 1V
VXDifferential Input Signal Crossing Point(2) 750 mV
DHDuty Cycle 50 %
VTHI Input Timing Measurement Reference Level(3) Crossing Point V
tR, tFInput Signal Edge Rate(4) 2 V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2 . A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under
actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVEPECL (2.5V) AND
LVPECL (3.3V)
Symbol Parameter Value Units
VDIF Input Signal Swing(1) 732 mV
VXDifferential Input Signal Crossing Point(2) LVEPECL 1082 mV
LVPECL 1880
DHDuty Cycle 50 %
VTHI Input Timing Measurement Reference Level(3) Crossing Point V
tR, tFInput Signal Edge Rate(4) 2 V/ns
NOTES:
1 . The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. 1082mV LVEPECL (2.5V) and 1880mV LVPECL (3.3V) crossing point levels are specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment.
This device meets the VX specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
INDUSTRIAL TEMPERATURE RANGE
6
IDT5T9310
2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVDS
Symbol Parameter Value Units
VDIF Input Signal Swing(1) 400 mV
VXDifferential Input Signal Crossing Point(2) 1.2 V
DHDuty Cycle 50 %
VTHI Input Timing Measurement Reference Level(3) Crossing Point V
tR, tFInput Signal Edge Rate(4) 2 V/ns
NOTES:
1 . The 400mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. A 1.2V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under
actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
POWER SUPPLY CHARACTERISTICS FOR LVDS OUTPUTS(1)
Symbol Parameter Test Conditions Typ. Max Unit
IDDQ Quiescent VDD Power Supply Current VDD = Max., All Input Clocks = LOW(2) —295 mA
Outputs enabled
ITOT Total Power VDD Supply Current VDD = 2.7V., FREFERENCE CLOCK = 1GHz —305 mA
IPD Total Power Down Supply Current PD = LOW — 5 mA
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case conditions.
2. The true input is held LOW and the complementary input is held HIGH.
AC DIFFERENTIAL INPUT SPECIFICATIONS(1)
Symbol Parameter Min. Typ. Max Unit
VDIF AC Differential Voltage(2) 0.1 — 3.6 V
VIX Differential Input Crosspoint Voltage 0.05 — VDD V
VCM Common Mode Input Voltage Range(3) 0.05 — VDD V
VIN Input Voltage - 0.3 +3.6 V
NOTES:
1. The output will not change state until the inputs have crossed and the minimum differential voltage range defined by VDIF has been met or exceeded.
2. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. The AC differential voltage
must be achieved to guarantee switching to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2.
INDUSTRIAL TEMPERATURE RANGE
IDT5T9310
2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II
7
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE(1,5)
Symbol Parameter Min. Typ. Max Unit
Skew Parameters
tSK(O) Same Device Output Pin-to-Pin Skew(2) ——25 ps
tSK(P) Pulse Skew(3) ——125 ps
tSK(PP) Part-to-Part Skew(4) ——300 ps
Propagation Delay
tPLH Propagation Delay A, A Crosspoint to Qn, Qn Crosspoint —1.25 1.75 ns
tPHL
fOFrequency Range(6) —— 1 GHz
Output Gate Enable/Disable Delay
tPGE Output Gate Enable Crossing VTHI to Qn/Qn Crosspoint ——3.5 ns
tPGD Output Gate Disable Crossing VTHI to Qn/Qn Crosspoint Driven to GL Designated Level ——3.5 ns
Power Down Timing
tPWRDN PD Crossing VTHI to Qn = VDD, Qn = VDD ——100 µS
tPWRUP Output Gate Disable Crossing VTHI to Qn/Qn Driven to GL Designated Level ——100 µS
NOTES:
1. AC propagation measurements should not be taken within the first 100 cycles of startup.
2. Skew measured between crosspoints of all differential output pairs under identical input and output interfaces, transitions and load conditions on any one device.
3. Skew measured is the difference between propagation delay times tPHL and tPLH of any differential output pair under identical input and output interfaces, transitions and load conditions
on any one device.
4. Skew measured is the magnitude of the difference in propagation times between any single differential output pair of two devices, given identical transitions and load conditions
at identical VDD levels and temperature.
5. All parameters are tested with a 50% input duty cycle.
6. Guaranteed by design but not production tested.
INDUSTRIAL TEMPERATURE RANGE
8
IDT5T9310
2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II
tPLH tPHL
tSK(O) tSK(O)
Qn - Qn
Qm - Qm
+ VDIF
VDIF = 0
- VDIF
+ VDIF
VDIF = 0
- VDIF
A[1:2] - A[1:2]
+ VDIF
VDIF = 0
- VDIF
1/fo
DIFFERENTIAL AC TIMING WAVEFORMS
Output Propagation and Skew Waveforms
NOTES:
1. Pulse skew is calculated using the following expression:
tSK(P) = | tPHL - tPLH |
Note that the tPHL and tPLH shown above are not valid measurements for this calculation because they are not taken from the same pulse.
2. AC propagation measurements should not be taken within the first 100 cycles of startup.
INDUSTRIAL TEMPERATURE RANGE
IDT5T9310
2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II
9
Power Down Timing
NOTES:
1 . It is recommended that outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-up after
asserting PD.
2. The POWER DOWN TIMING diagram assumes that GL is HIGH.
3. It should be noted that during power-down mode, the outputs are both pulled to VDD. In the POWER DOWN TIMING diagram this is shown when Qn-Qn goes to VDIF = 0.
A1 - A1
Gx VTHI
VIH
VIL
Qn - Qn
+VDIF
VDIF=0
-
V
DIF
+VDIF
VDIF=0
-VDIF
+VDIF
VDIF=0
-VDIF
PD
A2 - A2
VTHI
VIH
VIL
Differential Gate Disable/Enable Showing Runt Pulse Generation
NOTE:
1. As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their Gx signals to avoid this problem.
tPLH
GL
Gx
Qn - Qn
tPGD tPGE
VIH
VTHI
VIL
VIH
VTHI
VIL
+ VDIF
VDIF = 0
- VDIF
A[1:2] - A[1:2]
+ VDIF
VDIF = 0
- VDIF
INDUSTRIAL TEMPERATURE RANGE
10
IDT5T9310
2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II
TEST CIRCUITS AND CONDITIONS
VDD/2
D.U.T.
A
A
Pulse
Generator
~50Ω
Transmission Line
~50Ω
Transmission Line
VIN
VIN
-VDD/2
Scope
50Ω
50Ω
Test Circuit for Differential Input
DIFFERENTIAL INPUT TEST CONDITIONS
Symbol VDD = 2.5V ± 0.2V Unit
VTHI Crossing of A and AV
INDUSTRIAL TEMPERATURE RANGE
IDT5T9310
2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II
11
VDD
D.U.T.
A
A
Qn
Qn
Pulse
Generator RL
RL
VOS VOD
VDD/2
D.U.T.
A
A
Qn
Qn
Pulse
Generator 50Ω
50Ω
Z = 50Ω
Z = 50Ω
SCOPE
CL
-VDD/2
CL
Test Circuit for DC Outputs and Power Down Tests
Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing
NOTES:
1. Specifications only apply to "Normal Operations" test condition. The TIA/EIA specification load is for reference only.
2. The scope inputs are assumed to have a 2pF load to ground. TIA/EIA - 644 specifies 5pF between the output pair. With CL = 8pF, this gives the test circuit appropriate 5pF equivalent
load.
LVDS OUTPUT TEST CONDITION
Symbol VDD = 2.5V ± 0.2V Unit
CL0(1) pF
8(1,2)
RL50 Ω
INDUSTRIAL TEMPERATURE RANGE
12
IDT5T9310
2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II
RECOMMENDED LANDING PATTERN
NL 40 pin
NOTE: All dimensions are in millimeters.
INDUSTRIAL TEMPERATURE RANGE
IDT5T9310
2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II
13
ORDERING INFORMATION
IDT XXXXX
Package
Device Type
5T9310 2.5V LVDS 1:10 Clock Buffer Terabuffer™ II
Thermally Enhanced Plastic Very Fine Pitch
Quad Flat No Lead Package
NL
XX
Process
X
-40°C to +85°C (Industrial)
I
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 clockhelp@idt.com
San Jose, CA 95138 fax: 408-284-2775
www.idt.com
