Data Sheet
V1.1 2018-09
Microcontrollers
XMC4700 / XMC4800
Microcontroller Series
for Industrial Applications
XMC4000 Family
ARM® Cortex®-M4
32-bit processor core
Edition 2018-09
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2018 Infineon Technologies AG
All Rights Reserved.
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Data Sheet
V1.1 2018-09
Microcontrollers
XMC4700 / XMC4800
Microcontroller Series
for Industrial Applications
XMC4000 Family
ARM® Cortex®-M4
32-bit processor core
XMC4700 / XMC4800
XMC4000 Family
Data Sheet V1.1, 2018-09
Trademarks
C166™, TriCore™, XMC™ and DAVE™ are trademarks of Infineon Technologies AG.
ARM®, ARM Powered®, Cortex®, Thumb® and AMBA® are registered trademarks of
ARM, Limited.
CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace Buffer™ are
trademarks of ARM, Limited.
Synopsys™ is a trademark of Synopsys, Inc.
XMC4[78]00 Data Sheet
Revision History: V1.1 2018-09
Previous Versions:
V1.0 2016-01
V0.7 2015-10 (preliminary)
Page Subjects
55 Added RMS Noise parameter in VADC Parameters table.
8Corrected EtherCAT features to 8 Fieldbus Memory Management Units
(FMMU) and 8 Sync Manager.
46 Added footnote explaining minimum VBAT requirements to start the
hibernate domain and/or oscillation of a crystal on RTC_XTAL.
53 Added HIBIO characteristics.
59 Corrected DAC INL and gain error.
71 Changed frequency dependency of the current consumption.
74 Added peripheral idle cu rrent ov erview.
128ff Updated package parameters and drawings.
133 Higher HBM and CDM ESD limits.
We Listen to Your Comments
Is there any info rmation in this document that you feel is wrong, unclear or missing?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (includin g a reference to this document) to:
mcdocu.comments@infineon.com
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Table of Contents
Data Sheet 5 V1.1, 2018-09
1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2 Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3 Device Type Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4 Definition of Feature Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 Pin Configuration and Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.1 Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.2 Port I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2.2.1 Port I/O Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3 Power Connection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.1.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.1.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.1.3 Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.1.4 Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.1.5 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.2.1 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.2.2 Analog to Digital Converters (VADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.2.3 Digital to Analog Converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.2.4 Out-of-Range Comparator (ORC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.2.5 Die Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.2.6 USB OTG Interface DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.2.7 Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.2.8 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.2.9 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.3 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.3.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.3.2 Power-Up and Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.3.3 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.3.4 Phase Locked Loop (PLL) Characteristi cs . . . . . . . . . . . . . . . . . . . . . . 81
3.3.5 Internal Clock Source Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.3.6 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.3.7 Serial Wire Debug Port (SW-DP) Timing . . . . . . . . . . . . . . . . . . . . . . . . 86
3.3.8 Embedded Trace Macro Cell (ETM) Timing . . . . . . . . . . . . . . . . . . . . . 87
3.3.9 Peripheral Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table of Contents
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Table of Contents
Data Sheet 6 V1.1, 2018-09
3.3.9.1 Delta-Sigma Demodulator Digital Interface Timing . . . . . . . . . . . . . . 88
3.3.9.2 Synchronous Serial Interface (USIC SSC) Timing . . . . . . . . . . . . . . 89
3.3.9.3 Inter-IC (IIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.3.9.4 Inter-IC Sound (IIS) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.3.9.5 SDMMC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.3.10 EBU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
3.3.10.1 EBU Asynchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
3.3.10.2 EBU Burst Mode Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
3.3.10.3 EBU Arbitration Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
3.3.10.4 EBU SDRAM Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
3.3.11 USB Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
3.3.12 Ethernet Interface (ETH) Characteristics . . . . . . . . . . . . . . . . . . . . . . . 119
3.3.12.1 ETH Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . . 119
3.3.12.2 ETH Management Signal Parameters (ETH_MDC, ETH_MDIO) . . 120
3.3.12.3 ETH MII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
3.3.12.4 ETH RMII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
3.3.13 EtherCAT (ECAT) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
3.3.13.1 ECAT Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . 123
3.3.13.2 ETH Management Signal Parameters (MCLK, MDIO) . . . . . . . . . . 123
3.3.13.3 MII Timing TX Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
3.3.13.4 MII Timing RX Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
3.3.13.5 Sync/Latch Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8
4.1.1 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5 Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
About this Document
Data Sheet 7 V1.1, 2018-09
About this Document
This Data Sheet is addressed to embedded hardware and software developers. It
provides the reader with detailed descriptions about the ordering designations, available
features, electrical and physical characteristics of th e XMC4[78]00 series devices.
The document describes the characteristics of a superset of the XMC4[78]00 series
devices. For simplicity, the various device types are referred to by the collective term
XMC4[78]00 throughout this manual.
XMC4000 Family User Documentation
The set of user documentation includes:
•Reference Manu al
– decribes the functionality of the superset of devices.
•Data Sheets
– list the complete ordering designations, available features and electrical
characteristics of derivative devices.
•Errata Sheets
– list deviations from the specifications given in the related Reference Manual or
Data Sheets. Errata Sheets are provided for the superset of devices.
Attention: Please consult all parts of the documentation set to attain consolidated
knowledge about yo ur device.
Application related guidance is provided by Users Guides and Application Notes.
Please refer to http://www.infineon.com/xmc4000 to get access to the latest versions
of those documents.
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Summary of Features
Data Sheet 8 V1.1, 2018-09
1 Summary of Features
The XMC4[78]00 devices are members of the XMC4000 Family of microcontrollers
based on the ARM Cortex-M4 processor core. The XMC4000 is a family of high
performance and energy efficient microco ntrolle rs optimized for Industrial Connecti vity,
Industrial Control, Power Conversion, Sense & Control.
Figure 1 System Block Diagram
CPU Subsystem
•CPU Core
– High Performance 32-bit ARM Cortex-M4 CPU
– 16-bit and 32-bit Thumb2 instruction set
– DSP/MAC instructions
– System timer (SysTick) for Operating System support
• Floating Point Unit
• Memory Protection Unit
• Nested Vectored Interrupt Controller
• General Purpose DMA with up-to 12 channels
• Event Request Unit (ERU) for programmable processing of external and internal
service requests
• Flexible CRC Engine (FCE) for multiple bit error detection
PMU
ROM & Flash
Bus Matrix
CPU
ARM Cortex-M4
DSRAM1 EBU
DSRAM2
PSRAM
FCE
GPDMA0 GPDMA1 USB
OTG
Ethernet
DCodeSystem ICode
Peripherals 0 Peripherals 1
PBA0
Data Code
WDT
RTC
ERU0
SCU
ERU1 VADC POSIF0 CCU40 CCU41 CCU42
USIC0 DSD POSIF1 CCU80 CCU81 LEDTS0 CCU43 PORTS DAC
SDMMC USIC2 USIC1 MultiCAN
System
Masters System
Slaves
PBA1
EtherCAT
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Summary of Features
Data Sheet 9 V1.1, 2018-09
On-Chip Memories
• 16 KB on-chip boot ROM
• 96 KB on-chip high-speed program memory
• 128 KB on-chip high speed data memory
• 128 KB on-chip high-speed communication memory
• 2,048 KB on-chip Flash Memory with 8 KB instruction cache
Communication Peripherals
• Ethernet MAC module capable of 10/100 Mbit/s transfer rates
• EtherCATSlave interface (ECAT) capable of 100 Mbit/s transfer rates with 2 MII
ports, 8 Fieldbus Memory Management Units (FMMU), 8 Sync Manager, 64 bit
distributed clocks
• Universal Serial Bus, USB 2.0 host, Full-Speed OTG, with integrated PHY
• Controller Area Network interface (MultiCAN), Full-CAN/Basic-CAN with 6 nodes,
256 message objects (MO), data rate up to 1 MBaud
• Six Universal Serial Interface Channels (USIC),providing 6 serial channels, usable as
UART, double-SPI, quad-SPI, IIC, IIS and LIN interfaces
• LED and Touch-Sense Controller (LEDTS) for Human-Machine interface
• SD and Multi-Media Card interface (SDMMC) for data storage memory cards
• External Bus Inte rface Unit (EBU) enabling commu nication with external memo ries
and off-chip peripherals
Analog Frontend Peripherals
• Four Analog-Digital Converters (VADC) of 12-bit resolution, 8 channels each, with
input out-of-range comparators
• Delta Sigma Demodulator with four channels, digital input stage for A/D signal
conversion
• Digital-Analog Converter (DAC) with two channels of 12-bit resolution
Industrial Control Peripherals
• Two Capture/Compare Units 8 (CCU8) for motor control and power conversion
• Four Capture/Compare Units 4 (CCU4) for use as general purpose timers
• Two Position In terfaces (POSIF) for servo motor positioning
• Window Watchdog Timer (WDT) for safety sensitive applications
• Die Temperature Sensor (DTS)
• Real Time Clock module with alarm support
• System Control Unit (SCU) for system configuration and control
Input/Output Li ne s
• Programmable port driver control module (PORTS)
• Individual bit addressability
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Summary of Features
Data Sheet 10 V1.1, 2018-09
• Tri-stated in input mode
• Push/pull or open drain output mode
• Boundary scan test support over JTAG interface
On-Chip Debug Suppo rt
• Full support for debug features: 8 breakpoin ts, CoreSight, trace
• Various interfaces: ARM-JTAG, SWD, single wire trace
1.1 Ordering Information
The ordering code for an Infineon microcontroller provides an exact reference to a
specific product. The code “XMC4<DDD>-<Z><PPP><T><FFFF>” identifies:
• <DDD> the derivatives function set
• <Z> the package variant
–E: LFBGA
–F: LQFP
–Q: VQFN
• <PPP> package pin count
• <T> the temperature range:
– F: -40°C to 85°C
– K: -40°C to 125°C
• <FFFF> the Fla sh me mo ry size.
For ordering codes for the XMC4[78]00 please contact your sales representative or local
distributor.
This document describes several derivatives of the XMC4[78]00 series, some
descriptions may not apply to a specific product. Please see Table 1.
For simplicity the term XMC4[78]00 is used for all derivatives throughout this document.
1.2 Device Types
These device types are available and can be ordered through Infineon’s direct and/or
distribution channels.
Table 1 Synopsis of XMC4[78]00 Device Types
Derivative1) Package Flash
Kbytes SRAM
Kbytes
XMC4700-E196x2048 PG-LFBGA-196 2048 352
XMC4700-F144x2048 PG-LQFP-144 2048 352
XMC4700-F100x2048 PG-LQFP-100 2048 352
XMC4700-E196x1536 PG-LFBGA-196 1536 276
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Summary of Features
Data Sheet 11 V1.1, 2018-09
1.3 Device Type Features
The following table lists the available features per device type.
XMC4700-F144x1536 PG-LQFP-144 1536 276
XMC4700-F100x1536 PG-LQFP-100 1536 276
XMC4800-E196x2048 PG-LFBGA-196 2048 352
XMC4800-F144x2048 PG-LQFP-144 2048 352
XMC4800-F100x2048 PG-LQFP-100 2048 352
XMC4800-E196x1536 PG-LFBGA-196 1536 276
XMC4800-F144x1536 PG-LQFP-144 1536 276
XMC4800-F100x1536 PG-LQFP-100 1536 276
XMC4800-E196x1024 PG-LFBGA-196 1024 200
XMC4800-F144x1024 PG-LQFP-144 1024 200
XMC4800-F100x1024 PG-LQFP-100 1024 200
1) x is a placeholder for the supported temperature range.
Table 2 Features of XMC4[78]00 Device Types
Derivative1) LED
TS
Intf.
SD
MMC
Intf.
EBU
Intf.2) ETH
Intf.
3)
ECAT
Slave
Intf.
USB
Intf. USIC
Chan. MultiCAN
Nodes,
MO
XMC4700-E196x2048 1 1 SDM MR - 1 3 x 2 N[0..5]
MO[0..255]
XMC4700-F144x2048 1 1 SDM MR - 1 3 x 2 N[0..5]
MO[0..255]
XMC4700-F100x2048 1 1 M16 R - 1 3 x 2 N[0..5]
MO[0..255]
XMC4700-E196x1536 1 1 SDM MR - 1 3 x 2 N[0..5]
MO[0..255]
XMC4700-F144x1536 1 1 SDM MR - 1 3 x 2 N[0..5]
MO[0..255]
XMC4700-F100x1536 1 1 M16 R - 1 3 x 2 N[0..5]
MO[0..255]
Table 1 Synopsis of XMC4[78]00 Device Types (cont’d)
Derivative1) Package Flash
Kbytes SRAM
Kbytes
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Summary of Features
Data Sheet 12 V1.1, 2018-09
XMC4800-E196x2048 1 1 SDM MR 2 x
MII 1 3 x 2 N[0..5]
MO[0..255]
XMC4800-F144x2048 1 1 SDM MR 2 x
MII 1 3 x 2 N[0..5]
MO[0..255]
XMC4800-F100x2048 1 1 M16 R 2 x
MII 1 3 x 2 N[0..5]
MO[0..255]
XMC4800-E196x1536 1 1 SDM MR 2 x
MII 1 3 x 2 N[0..5]
MO[0..255]
XMC4800-F144x1536 1 1 SDM MR 2 x
MII 1 3 x 2 N[0..5]
MO[0..255]
XMC4800-F100x1536 1 1 M16 R 2 x
MII 1 3 x 2 N[0..5]
MO[0..255]
XMC4800-E196x1024 1 1 SDM MR 2 x
MII 1 3 x 2 N[0..5]
MO[0..255]
XMC4800-F144x1024 1 1 SDM MR 2 x
MII 1 3 x 2 N[0..5]
MO[0..255]
XMC4800-F100x1024 1 1 M16 R 2 x
MII 1 3 x 2 N[0..5]
MO[0..255]
1) x is a placeholder for the supported temperature range.
2) Memory types supported S=SDRAM, D=DEMUX, M=MUX 16-bit and 32-bit, M16=MUX 16-bit
3) Supported interface s, M=MII, R=RMII.
Table 3 Features of XMC4[78]00 Device Types
Derivative1) ADC
Chan. DSD
Chan. DAC
Chan. CCU4
Slice CCU8
Slice POSIF
Intf.
XMC4700-E196x2048 32 4 2 4 x 4 2 x 4 2
XMC4700-F144x2048 32 4 2 4 x 4 2 x 4 2
XMC4700-F100x2048 24 4 2 4 x 4 2 x 4 2
XMC4700-E196x1536 32 4 2 4 x 4 2 x 4 2
XMC4700-F144x1536 32 4 2 4 x 4 2 x 4 2
XMC4700-F100x1536 24 4 2 4 x 4 2 x 4 2
XMC4800-E196x2048 32 4 2 4 x 4 2 x 4 2
Table 2 Features of XMC4[78]00 Device Types (cont’d)
Derivative1) LED
TS
Intf.
SD
MMC
Intf.
EBU
Intf.2) ETH
Intf.
3)
ECAT
Slave
Intf.
USB
Intf. USIC
Chan. MultiCAN
Nodes,
MO
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Summary of Features
Data Sheet 13 V1.1, 2018-09
1.4 Definition of Feature Variants
The XMC4[78]00 types are offered with several memory size s and number of avai lable
VADC channels. Table 4 describes the location of the available Flash memory, Table 5
describes the location of the available SRAMs, Table 6 the available VADC channels.
XMC4800-F144x2048 32 4 2 4 x 4 2 x 4 2
XMC4800-F100x2048 24 4 2 4 x 4 2 x 4 2
XMC4800-E196x1536 32 4 2 4 x 4 2 x 4 2
XMC4800-F144x1536 32 4 2 4 x 4 2 x 4 2
XMC4800-F100x1536 24 4 2 4 x 4 2 x 4 2
XMC4800-E196x1024 32 4 2 4 x 4 2 x 4 2
XMC4800-F144x1024 32 4 2 4 x 4 2 x 4 2
XMC4800-F100x1024 24 4 2 4 x 4 2 x 4 2
1) x is a placeholder for the supported temperature range.
Table 4 Flash Memory Ranges
Total Flash Size Cached Range Uncached Range
1,024 Kbytes 0800 0000H −
080F FFFFH
0C00 0000H −
0C0F FFFFH
1,536 Kbytes 0800 0000H −
0817 FFFFH
0C00 0000H −
0C17 FFFFH
2,048 Kbytes 0800 0000H −
081F FFFFH
0C00 0000H −
0C1F FFFFH
Table 3 Features of XMC4[78]00 Device Types (cont’d)
Derivative1) ADC
Chan. DSD
Chan. DAC
Chan. CCU4
Slice CCU8
Slice POSIF
Intf.
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Summary of Features
Data Sheet 14 V1.1, 2018-09
1.5 Identification Registers
The identificati on registers allow software to identify the marking.
Table 5 SRAM Memory Ranges
Total SRAM Size Program SRAM System Data SRAM Communication
Data SRAM
200 Kbytes 1FFE E000H −
1FFF FFFFH
2000 0000H −
2001 FFFFH
−
276 Kbytes 1FFE 8000H −
1FFF FFFFH
2000 0000H −
2001 FFFFH
2002 0000H −
2002 CFFFH
352 Kbytes 1FFE 8000H −
1FFF FFFFH
2000 0000H −
2001 FFFFH
2002 0000H −
2003 FFFFH
Table 6 ADC Channels1)
1) Some pins in a package may b e connected to more than one channel. For the detailed mapping see the Port
I/O Function tab l e.
Package VADC G0 VADC G1 VADC G2 VADC G3
PG-LQFP-144
PG-LFBGA-196 CH0..CH7 CH0..CH7 CH0..CH7 CH0..CH7
PG-LQFP-100 CH0..CH7 CH0..CH7 CH0..CH3 CH0..CH3
Table 7 XMC4700 Identification Registers
Register Name Value Marking
SCU_IDCHIP 0004 7001HEES-AA, ES-AA, AA
JTAG IDCODE 101D F083HEES-AA, ES-AA, AA
Table 8 XMC4800 Identification Registers
Register Name Value Marking
SCU_IDCHIP 0004 8001HEES-AA, ES-AA, AA
JTAG IDCODE 101D F083HEES-AA, ES-AA, AA
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
General Device Information
Data Sheet 15 V1.1, 2018-09
2 General Device Information
This section summarizes the logic symbols and package pin configurations with a
detailed list of the functional I/O mapping.
2.1 Logic Symbols
Figure 2 XMC4[78]00 Logic Symbol PG-LQFP-144
Port 0
16 bit
Port 1
16 bit
Port 2
16 bit
Port 3
16 bit
Port 4
8 bit
Port 5
12 bit
Port 6
7 bit
VAGND
(1)
VAREF
(1) VDDP
(4)
JTAG
3 bit
TCK ETM / SWD
5 / 1 bit
VDDC
(4)
XTAL1
XTAL2
USB_DP
USB_DM
VBUS
Port 14
14 bit
Port 15
12 bit
TMS
PORST
via Port Pins
VDDA
(1)
RTC_XTAL1
RTC_XTAL2
HIB_IO_0
HIB_IO_1
VSSA
(1)
VBAT (1)
(1) VSSO
Exp. Die Pad
(VSS)
VSS
(1)
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
General Device Information
Data Sheet 16 V1.1, 2018-09
Figure 3 XMC4[78]00 Logic Symbol PG-LFBGA-196
Port 0
16 bit
Port 1
16 bit
Port 2
16 bit
Port 3
16 bit
Port 4
8 bit
Port 5
12 bit
Port 6
7bit
V
AGND
(1)
V
AREF
(1) V
DDP
(3)
JTAG
3bit
TCK ETM / SWD
5 / 1 bit
V
DDC
(3)
XTAL1
XTAL2
USB_DP
USB_DM
VBUS
Port 14
14 bit
Port 15
12 bit
TMS
PORST
via Port Pins
V
DDA
(1)
RTC_XTAL1
RTC_XTAL2
HIB_IO_0
HIB_IO_1
V
SSA
(1)
V
BAT
(1) (1) V
SSO
V
SS
(8)
Port 7
12 bit
Port 8
12 bit
Port 9
12 bit
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
General Device Information
Data Sheet 17 V1.1, 2018-09
Figure 4 XMC4[78]00 Logic Symbol PG-LQFP-100
Port 0
13 bit
Port 1
16 bit
Port 2
13 bit
Port 3
7 bit
Port 4
2 bit
Port 5
4 bit
VAGND
(1)
VAREF
(1) VDDP
(4)
JTAG
3 bit
TCK SWD
1 bit
VDDC
(4)
XTAL1
XTAL2
USB_DP
USB_DM
VBUS
Port 14
14 bit
Port 15
4 bit
TMS
PORST
via Port Pins
VDDA
(1)
RTC_XTAL1
RTC_XTAL2
HIB_IO_0
HIB_IO_1
VSSA
(1)
VBAT (1)
(1) VSSO
Exp. Die Pad
(VSS)
VSS
(1)
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
General Device Information
Data Sheet 18 V1.1, 2018-09
2.2 Pin Configuration and Definition
The following figures summarize all pins, showing their locations on the four sides of the
different packages.
Figure 5 XMC4[78]00 PG-LQFP-144 Pin Configuration (top view)
2P0. 0 1P0.1
144 P 0 .2
143 P 0 .3
142 P 0 .4
141 P 0 .5
140 P 0 .6
128 P 0 .7
127 P 0 .8
4P0. 9 3P0. 10
139 P0.11
138 P0.12
137 P0.13
136 P0.14
135 P0.15
112 P 1 .0
111 P 1 .1
110 P1.2
109 P 1 .3
108 P1.4
107 P1.5
116 P 1 .6
115 P 1 .7
114 P 1 .8
113 P 1 .9
106 P1.10
105 P1.11
104 P1.12
103 P1.13
102 P1.14
94 P1.15
74 P2.0
73 P2.1
72
P2.2 71
P2.3 70
P2.4 69
P2.5
76 P2.6
75 P2.7
68
P2.8 67
P2.9 66
P2.10 65
P2.11 64
P2.12 63
P2.13
60
P2.14 59
P2.15
7P3. 0 6P3.1 5P3.2
132 P 3 .3
131 P 3 .4
130 P 3 .5
129 P 3 .6
14P3. 7 13P3.8 12P3.9 11P3. 10 10P3.11 9P3. 12 8P3.13
134 P3.14
133 P3.15
124 P4.0
123 P4.1
122 P 4 .2
121 P 4 .3
120 P 4 .4
119 P 4 .5
118 P 4 .6
117 P 4 .7
84 P5.0
83 P5.1
82 P5.2
81 P5.3
80 P5.4
79 P5.5
78 P5.6
77 P5.7
58
P5.8 57
P5.9 56
P5.10 55
P5.11
101 P6.0
100 P6.1
99 P6.2
98 P6.3
97 P6.4
96 P6.5
95 P6.6
42
P14.0 41
P14.1 40
P14.2 39
P14.3 38
P14.4 37
P14.5
36P14.6 35P14.7
52
P14.8 51
P14.9
34P14.12 33P14.13 32P14.14 31P14.15 30P15.2 29P15.3 28P15.4 27P15.5 26P15.6 25P15.7
54
P15.8 53
P15.9
50
P15.12 49
P15.13
44
P15.14 43
P15.15
16USB_DP 15USB_DM
21HIB_IO_0 20HIB_IO_1
93 TCK
92 TMS
91 PORST
87 XTAL1
88 XTAL2
22RTC_XTAL2 23RTC_XTAL1 24VBAT
17VBUS
46
VAREF 45
VAGND
48
VDDA 47
VSSA
19VDDC
61
VDDC
90 VDDC
12 5 V D D C
18VDDP
62
VDDP
86 VDDP
12 6 V D D P
85 VSS
89 VSSO
XMC4[78]00
(Top View)
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
General Device Information
Data Sheet 19 V1.1, 2018-09
Figure 6 XMC4[78]00 PG-LFBGA-196 Pin Configuration (top view)
P0.0P0.1
P0.2 P0.3
P0.4
P0.5 P0.6
P0.7
P0.8
P0.9
P0.10
P0. 11
P0. 12
P0. 13
P0.14
P0.15
P1.0
P1.1
P1.2 P1.3P1.4
P1.5
P1.6 P1.7
P1.8
P1.9
P1.10P1. 11
P1. 12 P1.13P1.14
P1.15
P2.0
P2.1P2.2
P2.3P2.4
P2.5
P2.6
P2.7
P2.8
P2.9
P2. 10
P2. 11
P2.12
P2.13
P2.14
P2.15
P3.0
P3.1 P3.2
P3.3
P3.4
P3.5
P3.6
P3.7P3.8
P3.9 P3.10
P3.11P3.12
P3.13
P3.14 P3.15
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6 P4.7
P5.0P5.1P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P5.8
P5.9
P5. 10
P5. 11
P6.0
P6.1
P6.2
P6.3
P6.4 P6.5 P6.6
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
P7.8
P7.9 P7.10
P7.11
P8.0
P8.1
P8.2P8.3 P8.4P8.5
P8.6
P8.7
P8.8 P8.9P8.10 P8.11
P9.0
P9.1
P9.2P9.3
P9.4P9.5
P9.6
P9.7P9.8 P9.9
P9. 10 P9.11
P14.0P14. 1
P14.2
P14.3
P14.4 P14.5
P14.6P14. 7
P14.8
P14.9
P14.12
P14.13P14.14P14.15P15.2
P15.3 P15.4P15.5 P15.6 P15.7
P15.8
P15.9
P15.12
P15.13
P15.14
P15.15
HIB_I
O_0
HIB_I
O_1
n.c.
n.c . n.c. n.c . n.c.
n.c. n.c .
n.c.
n.c.
n.c.
n.c.
n.c.
PORST
RTC _X
TAL2
RTC _X
TAL1
TCKTMS
USB_D
M
USB_D
P
VAGND VAREF
VBAT
VBUS
VD D A
VDDC
VD D C
VD D C
VD D P
VD D P
VD D P
VSS VSS
VS S
VSS VSS
VSS VSSVSSA
VSSO
XTAL1 XTAL2
AA
BB
CC
DD
EE
FF
GG
HH
JJ
KK
LL
MM
NN
PP
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
XM C 4[78 ]00‐ (topview)
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
General Device Information
Data Sheet 20 V1.1, 2018-09
Figure 7 XMC4[78]00 PG-LQFP-100 Pin Configuration (top view)
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
General Device Information
Data Sheet 21 V1.1, 2018-09
2.2.1 Package Pin Summary
The following general scheme is used to describe each pin:
The table is sorted by the “Fu nction” column, starting with the regular Port pins (Px.y),
followed by the dedicated pins (i.e. PORST) and supply pins.
The following columns, titled with the supported package variants, lists the pa ckage pin
number to which the respective function is mapped in that package.
The “Pad Type” indicates the employed pad type (A1, A1+, A2, special=special pad,
In=input pad, AN/DIG_IN=analog and digital input, Power=power supply). Details about
the pad properties are defined in the Electrical Parameters.
In the “Notes”, special information to the res pective pin/fu nction is given, i.e. deviatio ns
from the default configuration after reset. Pe r default the regu lar Port pins are c onfigured
as direct input with no internal pull device active.
Table 9 Package Pin Mapping Description
Function Package A Package B ... Pad
Type Notes
Name N Ax ... A2
Table 10 Package Pin Mapping
Function LFBGA-196 LQFP-144 LQFP-100 Pad Type Notes
P0.0 E4 2 2 A1+
P0.1 E3 1 1 A1+
P0.2 C3 144 100 A2
P0.3 C4 143 99 A2
P0.4 D5 142 98 A2
P0.5 C5 141 97 A2
P0.6 C6 140 96 A2
P0.7 D7 128 89 A2 After a system reset, via
HWSEL this pin selects
the DB.TDI function.
P0.8 C8 127 88 A2 After a system reset, via
HWSEL this pin selects
the DB.TRST function,
with a weak pull-down
active.
P0.9 F4 4 4 A2
P0.10 D4 3 3 A1+
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
General Device Information
Data Sheet 22 V1.1, 2018-09
P0.11 G5 139 95 A1+
P0.12 F5 138 94 A1+
P0.13 E5 137 - A1+
P0.14 G6 136 - A1+
P0.15 E6 135 - A1+
P1.0 F9 112 79 A1+
P1.1 G9 111 78 A1+
P1.2 E11 110 77 A2
P1.3 E12 109 76 A2
P1.4 E10 108 75 A1+
P1.5 F10 107 74 A1+
P1.6 D9 116 83 A2
P1.7 D10 115 82 A2
P1.8 C10 114 81 A2
P1.9 D11 113 80 A2
P1.10 F12 106 73 A1+
P1.11 F11 105 72 A1+
P1.12 G11 104 71 A2
P1.13 G12 103 70 A2
P1.14 G10 102 69 A2
P1.15 J12 94 68 A2
P2.0 L11 74 52 A2
P2.1 M12 73 51 A2 After a system reset, via
HWSEL this pin selects
the DB.TDO function.
P2.2 M11 72 50 A2
P2.3 N11 71 49 A2
P2.4 N10 70 48 A2
P2.5 P10 69 47 A2
P2.6 L9 76 54 A1+
P2.7 M9 75 53 A1+
P2.8 N9 68 46 A2
P2.9 P9 67 45 A2
Table 10 Package Pin Mapping (cont’d)
Function LFBGA-196 LQFP-144 LQFP-100 Pad Type Notes
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
General Device Information
Data Sheet 23 V1.1, 2018-09
P2.10 N8 66 44 A2
P2.11 P8 65 - A2
P2.12 N7 64 - A2
P2.13 P7 63 - A2
P2.14 M7 60 41 A2
P2.15 L6 59 40 A2
P3.0 E1 7 7 A2
P3.1 D2 6 6 A2
P3.2 D3 5 5 A2
P3.3 H7 132 93 A1+
P3.4 G7 131 92 A1+
P3.5 D6 130 91 A2
P3.6 C7 129 90 A2
P3.7 G4 14 - A1+
P3.8 G3 13 - A1+
P3.9 H5 12 - A1+
P3.10 H6 11 - A1+
P3.11 F3 10 - A1+
P3.12 F2 9 - A2
P3.13 E2 8 - A2
P3.14 F6 134 - A1+
P3.15 F7 133 - A1+
P4.0 D8 124 85 A2
P4.1 C9 123 84 A2
P4.2 G8 122 - A1+
P4.3 H8 121 - A1+
P4.4 E7 120 - A1+
P4.5 F8 119 - A1+
P4.6 E8 118 - A1+
P4.7 E9 117 - A1+
P5.0 K9 84 58 A1+
P5.1 K8 83 57 A1+
P5.2 K7 82 56 A1+
Table 10 Package Pin Mapping (cont’d)
Function LFBGA-196 LQFP-144 LQFP-100 Pad Type Notes
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
General Device Information
Data Sheet 24 V1.1, 2018-09
P5.3 L10 81 - A2
P5.4 M10 80 - A2
P5.5 L8 79 - A2
P5.6 M8 78 - A2
P5.7 L7 77 55 A1+
P5.8 K6 58 - A2
P5.9 M6 57 - A2
P5.10 K5 56 - A1+
P5.11 L5 55 - A1+
P6.0 J10 101 - A2
P6.1 H9 100 - A2
P6.2 K10 99 - A2
P6.3 J9 98 - A1+
P6.4 H10 97 - A2
P6.5 H11 96 - A2
P6.6 H12 95 - A2
P7.0 L13 - - A2
P7.1 M13 - - A2
P7.2 N13 - - A2
P7.3 M14 - - A2
P7.4 N14 - - A1+
P7.5 L14 - - A1+
P7.6 K14 - - A1+
P7.7 J14 - - A1+
P7.8 H14 - - A2
P7.9 G13 - - A1+
P7.10 G14 - - A1+
P7.11 F14 - - A1+
P8.0 B7 - - A2
P8.1 A7 - - A2
P8.2 B3 - - A2
P8.3 B2 - - A2
P8.4 B6 - - A1+
Table 10 Package Pin Mapping (cont’d)
Function LFBGA-196 LQFP-144 LQFP-100 Pad Type Notes
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
General Device Information
Data Sheet 25 V1.1, 2018-09
P8.5 B5 - - A1+
P8.6 A2 - - A1+
P8.7 B4 - - A1+
P8.8 A3 - - A2
P8.9 A5 - - A1+
P8.10 A4 - - A1+
P8.11 A6 - - A1+
P9.0 F13 - - A2
P9.1 E14 - - A2
P9.2 D14 - - A1+
P9.3 D13 - - A2
P9.4 A12 - - A1+
P9.5 A11 - - A1+
P9.6 B11 - - A1+
P9.7 A9 - - A1+
P9.8 A8 - - A1+
P9.9 A10 - - A1+
P9.10 B8 - - A1+
P9.11 B9 - - A1+
P14.0 N3 42 31 AN/DIG_IN
P14.1 N2 41 30 AN/DIG_IN
P14.2 M3 40 29 AN/DIG_IN
P14.3 L4 39 28 AN/DIG_IN
P14.4 M1 38 27 AN/DIG_IN
P14.5 M2 37 26 AN/DIG_IN
P14.6 L3 36 25 AN/DIG_IN
P14.7 L2 35 24 AN/DIG_IN
P14.8 P5 52 37 AN/DAC/DI
G_IN
P14.9 N5 51 36 AN/DAC/DI
G_IN
P14.12 L1 34 23 AN/DIG_IN
P14.13 K4 33 22 AN/DIG_IN
Table 10 Package Pin Mapping (cont’d)
Function LFBGA-196 LQFP-144 LQFP-100 Pad Type Notes
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
General Device Information
Data Sheet 26 V1.1, 2018-09
P14.14 K3 32 21 AN/DIG_IN
P14.15 K2 31 20 AN/DIG_IN
P15.2 K1 30 19 AN/DIG_IN
P15.3 J2 29 18 AN/DIG_IN
P15.4 J4 28 - AN/DIG_IN
P15.5 J3 27 - AN/DIG_IN
P15.6 J5 26 - AN/DIG_IN
P15.7 J6 25 - AN/DIG_IN
P15.8 P6 54 39 AN/DIG_IN
P15.9 N6 53 38 AN/DIG_IN
P15.12 M5 50 - AN/DIG_IN
P15.13 P4 49 - AN/DIG_IN
P15.14 N4 44 - AN/DIG_IN
P15.15 M4 43 - AN/DIG_IN
USB_DP G1 16 9 special
USB_DM F1 15 8 special
HIB_IO_0 H4 21 14 A1 special At the first power-up and
with every reset of the
hibernate domain this pin
is configured as open-
drain output and drives
"0".
As output the medium
driver mode is active.
HIB_IO_1 H3 20 13 A1 special At the first power-up and
with every reset of the
hibernate domain this pin
is configured as input with
no pull device active.
As output the medium
driver mode is active.
TCK J8 9 3 67 A1 Weak pull-down active.
TMS J7 92 66 A1+ Weak pull-up active.
As output the strong-soft
driver mode is active.
Table 10 Package Pin Mapping (cont’d)
Function LFBGA-196 LQFP-144 LQFP-100 Pad Type Notes
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
General Device Information
Data Sheet 27 V1.1, 2018-09
PORST J11 91 65 special Weak pull-up permanently
active, strong pull-down
controlled by EVR.
XTAL1 K11 87 61 clock_IN
XTAL2 K12 88 62 clock_O
RTC_XTAL1 H1 23 16 clock_IN
RTC_XTAL2 H2 22 15 clock_O
VBAT J1 24 17 Power When VDDP is supplied
VBAT has to be supplied
as well.
VBUS G2 17 10 special
VAREF P3 46 33 AN_Ref
VAGND P2 45 32 AN_Ref
VDDA N1 48 35 AN_Power
VSSA P1 47 34 AN_Power
VDDC - 19 12 Power
VDDC - 61 42 Power
VDDC - 90 64 Power
VDDC - 125 86 Power
VDDC C2 - - Power
VDDC D12 - - Power
VDDC P11 - - Power
VDDP - 18 11 Power
VDDP - 62 43 Power
VDDP - 86 60 Power
VDDP - 126 87 Power
VDDP C11 - - Power
VDDP D1 - - Power
VDDP N12 - - Power
VSS - 85 59 Power
VSS A1 - - Power
VSS A14 - - Power
VSS B13 - - Power
VSS C1 - - Power
Table 10 Package Pin Mapping (cont’d)
Function LFBGA-196 LQFP-144 LQFP-100 Pad Type Notes
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
General Device Information
Data Sheet 28 V1.1, 2018-09
VSS C12 - - Power
VSS P12 - - Power
VSS P14 - - Power
VSSO L12 89 63 Power
VSS - Exp. Pad Exp. Pad Power Exposed Die Pad
The exposed die pad is
connected internally to
VSS. For proper
operation, it is mandatory
to connect the exposed
pad directly to the
common ground on the
board.
For thermal aspects,
please refer to the Data
Sheet. Board layout
examples are given in an
application note.
n.c. A13 - - Power
n.c. B1 - - Power
n.c. B10 - - Power
n.c. B12 - - Power
n.c. B14 - - Power
n.c. C13 - - Power
n.c. C14 - - Power
n.c. E13 - - Power
n.c. H13 - - Power
n.c. J13 - - Power
n.c. K13 - - Power
n.c. P13 - - Power
Table 10 Package Pin Mapping (cont’d)
Function LFBGA-196 LQFP-144 LQFP-100 Pad Type Notes
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
General Device Information
Data Sheet 29 V1.1, 2018-09
2.2.2 Port I/O Functions
The following general scheme is used to describe each Port pin:
Figure 8 Simp li fie d Port Stru cture
Pn.y is the port pin name , d efi ning the con t rol and d ata bits/registers associ ate d with it.
As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT
defines the output value.
Up to four alternate output functions (ALT1/2/3/4) can be mapped to a single port pin,
selected by Pn_IOCR.PC. The output value is directly drive n by the respective module,
with the pin characteristics controlled by the port registers (within the limits of the
connected pad).
The port pin input can be connected to mult iple peripherals. Most peripherals have an
input multip l exer to select betwe en di ff erent possible in put sources.
The input path is also active while the pin is configured as output. This allows to feedback
an output to on-chip resources without wasting an additional external pin.
By Pn_HWSEL it is possible to select between different hardware “masters”
(HWO0/HWI0). The selected peripheral can take control of the pin(s). Hardware control
overrules settings in the respective port pin registers.
Table 11 Port I/O Function Desc ription
Function Outputs Inputs
ALT1 ALTn HWO0 HWI0 Input Input
P0.0 MODA.OUT MODB.OUT MODB.INA MODC.INA
Pn.y MODA.OUT MODA.INA MODC.INB
XMC4000
Pn.y
VDDP
GND
Pn.y
ALT1
...
ALTn
HWO0
HWO1
SW
Control Logic
Input 0
Input n
... PAD
HWI0
HWI1
MODB.OUT
MODB
MODA
MODA.INA
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Data Sheet 30 V1.1, 2018-09
2.2.2.1 Port I/O Function Table
Table 12 Port I/O Functions
Function Outputs Inputs
ALT1 ALT2 ALT3 ALT4 HWO0 HWO1 HWI0 HWI1 Input Input Input Input Input Input Input Input
P0.0 ECAT0.
PHY_RST CAN.
N0_TXD CCU80.
OUT21 LEDTS0.
COL2 U1C1.
DX0D ETH0.
CLK_RMIIB ERU0.
0B0 ETH0.
CLKRXB
P0.1 USB.
DRIVEVBUS U1C1.
DOUT0 CCU80.
OUT11 LEDTS0.
COL3 ETH0.
CRS_DVB ERU0.
0A0 ECAT0.
P1_RX_CLKA ETH0.
RXDVB
P0.2 ECAT0.
P1_TXD2 U1C1.
SELO1 CCU80.
OUT01 U1C0.
DOUT3 EBU.
AD0 U1C0.
HWIN3 EBU.
D0 ETH0.
RXD0B ERU0.
3B3
P0.3 ECAT0.
P1_TXD3 CCU80.
OUT20 U1C0.
DOUT2 EBU.
AD1 U1C0.
HWIN2 EBU.
D1 ETH0.
RXD1B ERU1.
3B0
P0.4 ETH0.
TX_EN CCU80.
OUT10 U1C0.
DOUT1 EBU.
AD2 U1C0.
HWIN1 EBU.
D2 U1C0.
DX0A ERU0.
2B3 ECAT0.
P1_RXD3A
P0.5 ETH0.
TXD0 U1C0.
DOUT0 CCU80.
OUT00 U1C0.
DOUT0 EBU.
AD3 U1C0.
HWIN0 EBU.
D3 U1C0.
DX0B ERU1.
3A0 ECAT0.
P1_RXD2A
P0.6 ETH0.
TXD1 U1C0.
SELO0 CCU80.
OUT30 EBU.
ADV U1C0.
DX2A ERU0.
3B2 CCU80.
IN2B ECAT0.
P1_RXD1A
P0.7 WWDT.
SERVICE_OUT U0C0.
SELO0 ECAT0.
LED_ERR EBU.
AD6 DB.
TDI EBU.
D6 U0C0.
DX2B DSD.
DIN1A ERU0.
2B1 CCU80.
IN0A CCU80.
IN1A CCU80.
IN2A CCU80.
IN3A
P0.8 SCU.
EXTCLK U0C0.
SCLKOUT ECAT0.
LED_RUN EBU.
AD7 DB.
TRST EBU.
D7 U0C0.
DX1B DSD.
DIN0A ERU0.
2A1 CAN.
N3_RXDA CCU80.
IN1B
P0.9 U1C1.
SELO0 CCU80.
OUT12 LEDTS0.
COL0 ETH0.
MDO EBU.
CS1 ETH0.
MDIA U1C1.
DX2A USB.
ID ERU0.
1B0 ECAT0.
P1_RX_DVA
P0.10 ETH0.
MDC U1C1.
SCLKOUT CCU80.
OUT02 LEDTS0.
COL1 U1C1.
DX1A ERU0.
1A0 ECAT0.
P1_TX_CLKA
P0.11 ECAT0.
P1_LINK_ACT U1C0.
SCLKOUT CCU80.
OUT31 SDMMC.
RST EBU.
BREQ ETH0.
RXERB U1C0.
DX1A ERU0.
3A2 ECAT0.
P1_RXD0A
P0.12 U1C1.
SELO0 CCU40.
OUT3 ECAT0.
MDO EBU.
HLDA ECAT0.
MDIA EBU.
HLDA U1C1.
DX2B ERU0.
2B2
P0.13 U1C1.
SCLKOUT CCU40.
OUT2 U1C1.
DX1B ERU0.
2A2
P0.14 U1C0.
SELO1 CCU40.
OUT1 U1C1.
DOUT3 U1C1.
HWIN3 CCU42.
IN3C
P0.15 U1C0.
SELO2 CCU40.
OUT0 U1C1.
DOUT2 U1C1.
HWIN2 CCU42.
IN2C
P1.0 DSD.
CGPWMN U0C0.
SELO0 CCU40.
OUT3 ERU1.
PDOUT3 U0C0.
DX2A ERU0.
3B0 CCU40.
IN3A ECAT0.
P0_TX_CLKA
P1.1 DSD.
CGPWMP U0C0.
SCLKOUT CCU40.
OUT2 ERU1.
PDOUT2 SDMMC.
SDWC U0C0.
DX1A POSIF0.
IN2A ERU0.
3A0 CCU40.
IN2A ECAT0.
P0_RX_CLKA
P1.2 ECAT0.
P0_TXD3 CCU40.
OUT1 ERU1.
PDOUT1 U0C0.
DOUT3 EBU.
AD14 U0C0.
HWIN3 EBU.
D14 POSIF0.
IN1A ERU1.
2B0 CCU40.
IN1A
P1.3 ECAT0.
P0_TX_ENA U0C0.
MCLKOUT CCU40.
OUT0 ERU1.
PDOUT0 U0C0.
DOUT2 EBU.
AD15 U0C0.
HWIN2 EBU.
D15 POSIF0.
IN0A ERU1.
2A0 CCU40.
IN0A
P1.4 WWDT.
SERVICE_OUT CAN.
N0_TXD CCU80.
OUT33 CCU81.
OUT20 U0C0.
DOUT1 U0C0.
HWIN1 U0C0.
DX0B CAN.
N1_RXDD ERU0.
2B0 CCU41.
IN0C ECAT0.
P0_RXD0A
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Data Sheet 31 V1.1, 2018-09
P1.5 CAN.
N1_TXD U0C0.
DOUT0 CCU80.
OUT23 CCU81.
OUT10 U0C0.
DOUT0 U0C0.
HWIN0 U0C0.
DX0A CAN.
N0_RXDA ERU0.
2A0 ERU1.
0A0 CCU41.
IN1C DSD.
DIN2B ECAT0.
P0_RXD1A
P1.6 ECAT0.
P0_TXD0 U0C0.
SCLKOUT SDMMC.
DATA1_OUT EBU.
AD10 SDMMC.
DATA1_IN EBU.
D10 DSD.
DIN2A
P1.7 ECAT0.
P0_TXD1 U0C0.
DOUT0 DSD.
MCLK2 U1C1.
SELO2 SDMMC.
DATA2_OUT EBU.
AD11 SDMMC.
DATA2_IN EBU.
D11 DSD.
MCLK2A DSD.
MCLK0C
P1.8 ECAT0.
P0_TXD2 U0C0.
SELO1 DSD.
MCLK1 U1C1.
SCLKOUT SDMMC.
DATA4_OUT EBU.
AD12 SDMMC.
DATA4_IN EBU.
D12 CAN.
N2_RXDA DSD.
MCLK1A DSD.
MCLK0D DSD.
MCLK2D DSD.
MCLK3D
P1.9 U0C0.
SCLKOUT CAN.
N2_TXD DSD.
MCLK0 U1C1.
DOUT0 SDMMC.
DATA5_OUT EBU.
AD13 SDMMC.
DATA5_IN EBU.
D13 DSD.
MCLK0A DSD.
MCLK1C DSD.
MCLK2C DSD.
MCLK3C ECAT0.
P0_RX_DVA
P1.10 ETH0.
MDC U0C0.
SCLKOUT CCU81.
OUT21 ECAT0.
LED_ERR SDMMC.
SDCD CCU41.
IN2C ECAT0.
P0_RXD2A
P1.11 ECAT0.
LED_STATE_RU
N
U0C0.
SELO0 CCU81.
OUT11 ECAT0.
LED_RUN ETH0.
MDO ETH0.
MDIC CCU41.
IN3C ECAT0.
P0_RXD3A
P1.12 ETH0.
TX_EN CAN.
N1_TXD CCU81.
OUT01 ECAT0.
P0_LINK_ACT SDMMC.
DATA6_OUT EBU.
AD16 SDMMC.
DATA6_IN EBU.
D16
P1.13 ETH0.
TXD0 U0C1.
SELO3 CCU81.
OUT20 ECAT0.
PHY_CLK25 SDMMC.
DATA7_OUT EBU.
AD17 SDMMC.
DATA7_IN EBU.
D17 CAN.
N1_RXDC
P1.14 ETH0.
TXD1 U0C1.
SELO2 CCU81.
OUT10 ECAT0.
SYNC0 EBU.
AD18 EBU.
D18 U1C0.
DX0E
P1.15 SCU.
EXTCLK DSD.
MCLK2 CCU81.
OUT00 U1C0.
DOUT0 EBU.
AD19 EBU.
D19 DSD.
MCLK2B ERU1.
1A0 ECAT0.
P0_LINKB
P2.0 CAN.
N0_TXD CCU81.
OUT21 DSD.
CGPWMN LEDTS0.
COL1 ETH0.
MDO EBU.
AD20 ETH0.
MDIB EBU.
D20 ERU0.
0B3 CCU40.
IN1C
P2.1 CAN.
N5_TXD CCU81.
OUT11 DSD.
CGPWMP LEDTS0.
COL0 DB.TDO/
TRACESWO EBU.
AD21 EBU.
D21 ETH0.
CLK_RMIIA ERU1.
0B0 CCU40.
IN0C ETH0.
CLKRXA
P2.2 VADC.
EMUX00 CCU81.
OUT01 CCU41.
OUT3 LEDTS0.
LINE0 LEDTS0.
EXTENDED0 EBU.
AD22 LEDTS0.
TSIN0A EBU.
D22 ETH0.
RXD0A U0C1.
DX0A ERU0.
1B2 CCU41.
IN3A
P2.3 VADC.
EMUX01 U0C1.
SELO0 CCU41.
OUT2 LEDTS0.
LINE1 LEDTS0.
EXTENDED1 EBU.
AD23 LEDTS0.
TSIN1A EBU.
D23 ETH0.
RXD1A U0C1.
DX2A ERU0.
1A2 POSIF1.
IN2A CCU41.
IN2A
P2.4 VADC.
EMUX02 U0C1.
SCLKOUT CCU41.
OUT1 LEDTS0.
LINE2 LEDTS0.
EXTENDED2 EBU.
AD24 LEDTS0.
TSIN2A EBU.
D24 ETH0.
RXERA U0C1.
DX1A ERU0.
0B2 POSIF1.
IN1A CCU41.
IN1A
P2.5 ETH0.
TX_EN U0C1.
DOUT0 CCU41.
OUT0 LEDTS0.
LINE3 LEDTS0.
EXTENDED3 EBU.
AD25 LEDTS0.
TSIN3A EBU.
D25 ETH0.
RXDVA U0C1.
DX0B ERU0.
0A2 POSIF1.
IN0A CCU41.
IN0A ETH0.
CRS_DVA
P2.6 U2C0.
SELO4 ERU1.
PDOUT3 CCU80.
OUT13 LEDTS0.
COL3 U2C0.
DOUT3 U2C0.
HWIN3 DSD.
DIN1B CAN.
N1_RXDA ERU0.
1B3 CAN.
N5_RXDB CCU40.
IN3C ECAT0.
P0_RX_ERRB
P2.7 ETH0.
MDC CAN.
N1_TXD CCU80.
OUT03 LEDTS0.
COL2 DSD.
DIN0B ERU1.
1B0 CCU40.
IN2C
P2.8 ETH0.
TXD0 ERU1.
PDOUT1 CCU80.
OUT32 LEDTS0.
LINE4 LEDTS0.
EXTENDED4 EBU.
AD26 LEDTS0.
TSIN4A EBU.
D26 DAC.
TRIGGER5 CCU40.
IN0B CCU40.
IN1B CCU40.
IN2B CCU40.
IN3B
P2.9 ETH0.
TXD1 ERU1.
PDOUT2 CCU80.
OUT22 LEDTS0.
LINE5 LEDTS0.
EXTENDED5 EBU.
AD27 LEDTS0.
TSIN5A EBU.
D27 DAC.
TRIGGER4 CCU41.
IN0B CCU41.
IN1B CCU41.
IN2B CCU41.
IN3B
P2.10 VADC.
EMUX10 ERU1.
PDOUT0 ECAT0.
PHY_RST ECAT0.
SYNC1 DB.
ETM_TRACEDA
TA3
EBU.
AD28 EBU.
D28
P2.11 ETH0.
TXER ECAT0.
P1_TXD0 CCU80.
OUT22 DB.
ETM_TRACEDA
TA2
EBU.
AD29 EBU.
D29
Table 12 Port I/O Functions (cont’d)
Function Outputs Inputs
ALT1 ALT2 ALT3 ALT4 HWO0 HWO1 HWI0 HWI1 Input Input Input Input Input Input Input Input
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Data Sheet 32 V1.1, 2018-09
P2.12 ETH0.
TXD2 ECAT0.
P1_TXD1 CCU81.
OUT33 ETH0.
TXD0 DB.
ETM_TRACEDA
TA1
EBU.
AD30 EBU.
D30 CCU43.
IN3C
P2.13 ETH0.
TXD3 ECAT0.
P1_TXD2 ETH0.
TXD1 DB.
ETM_TRACEDA
TA0
EBU.
AD31 EBU.
D31 CCU43.
IN2C
P2.14 VADC.
EMUX11 U1C0.
DOUT0 CCU80.
OUT21 CAN.
N4_TXD DB.
ETM_TRACECLK EBU.
BC0 U1C0.
DX0D CCU43.
IN0B CCU43.
IN1B CCU43.
IN2B CCU43.
IN3B
P2.15 VADC.
EMUX12 ECAT0.
P1_TXD3 CCU80.
OUT11 LEDTS0.
LINE6 LEDTS0.
EXTENDED6 EBU.
BC1 LEDTS0.
TSIN6A ETH0.
COLA U1C0.
DX0C CAN.
N4_RXDA CCU42.
IN0B CCU42.
IN1B CCU42.
IN2B CCU42.
IN3B
P3.0 U2C1.
SELO0 U0C1.
SCLKOUT CCU42.
OUT0 ECAT0.
P1_TX_ENA EBU.
RD U0C1.
DX1B CCU80.
IN2C CCU81.
IN0C
P3.1 U0C1.
SELO0 ECAT0.
P1_TXD0 EBU.
RD_WR U0C1.
DX2B ERU0.
0B1 CCU80.
IN1C
P3.2 USB.
DRIVEVBUS CAN.
N0_TXD ECAT0.
P1_TXD1 LEDTS0.
COLA EBU.
CS0 ERU0.
0A1 CCU80.
IN0C
P3.3 U1C1.
SELO1 CCU42.
OUT3 ECAT0.
MCLK SDMMC.
LED EBU.
WAIT DSD.
DIN3B CCU42.
IN3A CCU80.
IN3B
P3.4 U2C1.
MCLKOUT U1C1.
SELO2 CCU42.
OUT2 DSD.
MCLK3 SDMMC.
BUS_POWER EBU.
HOLD U2C1.
DX0B DSD.
MCLK3B CCU42.
IN2A CCU80.
IN0B ECAT0.
P1_LINKA
P3.5 U2C1.
DOUT0 U1C1.
SELO3 CCU42.
OUT1 U0C1.
DOUT0 SDMMC.
CMD_OUT EBU.
AD4 SDMMC.
CMD_IN EBU.
D4 U2C1.
DX0A ERU0.
3B1 CCU42.
IN1A ECAT0.
P1_RX_ERRA
P3.6 U2C1.
SCLKOUT U1C1.
SELO4 CCU42.
OUT0 U0C1.
SCLKOUT SDMMC.
CLK_OUT EBU.
AD5 SDMMC.
CLK_IN EBU.
D5 U2C1.
DX1B ERU0.
3A1 CCU42.
IN0A
P3.7 ECAT0.
SYNC0 CAN.
N2_TXD CCU41.
OUT3 LEDTS0.
LINE0 U2C0.
DX0C
P3.8 U2C0.
DOUT0 U0C1.
SELO3 CCU41.
OUT2 LEDTS0.
LINE1 CAN.
N2_RXDB POSIF1.
IN2B
P3.9 U2C0.
SCLKOUT CAN.
N1_TXD CCU41.
OUT1 LEDTS0.
LINE2 POSIF1.
IN1B
P3.10 U2C0.
SELO0 CAN.
N0_TXD CCU41.
OUT0 LEDTS0.
LINE3 U0C1.
DOUT3 U0C1.
HWIN3 POSIF1.
IN0B
P3.11 U2C1.
DOUT0 U0C1.
SELO2 CCU42.
OUT3 LEDTS0.
LINE4 U0C1.
DOUT2 U0C1.
HWIN2 CAN.
N1_RXDB CCU81.
IN3C
P3.12 ECAT0.
P1_LINK_ACT U0C1.
SELO1 CCU42.
OUT2 LEDTS0.
LINE5 U0C1.
DOUT1 U0C1.
HWIN1 CAN.
N0_RXDC U2C1.
DX0D CCU81.
IN2C
P3.13 U2C1.
SCLKOUT U0C1.
DOUT0 CCU42.
OUT1 LEDTS0.
LINE6 U0C1.
DOUT0 U0C1.
HWIN0 U0C1.
DX0D CCU80.
IN3C CCU81.
IN1C
P3.14 U1C0.
SELO3 U1C1.
DOUT1 U1C1.
HWIN1 U1C1.
DX0B CCU42.
IN1C
P3.15 U1C1.
DOUT0 U1C1.
DOUT0 U1C1.
HWIN0 U1C1.
DX0A CCU42.
IN0C
P4.0 CAN.
N3_TXD ECAT0.
PHY_CLK25 DSD.
MCLK1 U1C0.
SCLKOUT SDMMC.
DATA0_OUT EBU.
AD8 SDMMC.
DATA0_IN EBU.
D8 U1C1.
DX1C DSD.
MCLK1B U0C1.
DX0E U2C1.
DX0C ECAT0.
P0_RX_ERRA
P4.1 U2C1.
SELO0 U1C1.
MCLKOUT DSD.
MCLK0 U0C1.
SELO0 SDMMC.
DATA3_OUT EBU.
AD9 SDMMC.
DATA3_IN EBU.
D9 U2C1.
DX2B DSD.
MCLK0B U2C1.
DX2A DSD.
MCLK1D ECAT0.
P0_LINKA
P4.2 U2C1.
SELO1 U1C1.
DOUT0 U2C1.
SCLKOUT ECAT0.
MDO ECAT0.
MDIB U1C1.
DX0C U2C1.
DX1A CCU43.
IN1C
Table 12 Port I/O Functions (cont’d)
Function Outputs Inputs
ALT1 ALT2 ALT3 ALT4 HWO0 HWO1 HWI0 HWI1 Input Input Input Input Input Input Input Input
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Data Sheet 33 V1.1, 2018-09
P4.3 U2C1.
SELO2 U0C0.
SELO5 CCU43.
OUT3 ECAT0.
MCLK CCU43.
IN3A
P4.4 U0C0.
SELO4 CCU43.
OUT2 U2C1.
DOUT3 U2C1.
HWIN3 CCU43.
IN2A
P4.5 U0C0.
SELO3 CCU43.
OUT1 U2C1.
DOUT2 U2C1.
HWIN2 CCU43.
IN1A
P4.6 U0C0.
SELO2 CCU43.
OUT0 U2C1.
DOUT1 U2C1.
HWIN1 CAN.
N2_RXDC U2C1.
DX0E CCU43.
IN0A
P4.7 U2C1.
DOUT0 CAN.
N2_TXD U2C1.
DOUT0 U2C1.
HWIN0 U0C0.
DX0C CCU43.
IN0C
P5.0 U2C0.
DOUT0 DSD.
CGPWMN CCU81.
OUT33 ERU1.
PDOUT0 U2C0.
DOUT0 U2C0.
HWIN0 U2C0.
DX0B ETH0.
RXD0D U0C0.
DX0D ECAT0.
P0_RXD0B CCU81.
IN0A CCU81.
IN1A CCU81.
IN2A CCU81.
IN3A
P5.1 U0C0.
DOUT0 DSD.
CGPWMP CCU81.
OUT32 ERU1.
PDOUT1 U2C0.
DOUT1 U2C0.
HWIN1 U2C0.
DX0A ETH0.
RXD1D ECAT0.
P0_RXD1B CCU81.
IN0B
P5.2 U2C0.
SCLKOUT ECAT0.
P0_LINK_ACT CCU81.
OUT23 ERU1.
PDOUT2 U2C0.
DX1A ETH0.
CRS_DVD ECAT0.
P0_RXD2B CCU81.
IN1B ETH0.
RXDVD
P5.3 U2C0.
SELO0 CCU81.
OUT22 ERU1.
PDOUT3 EBU.
CKE EBU.
A20 U2C0.
DX2A ETH0.
RXERD CCU81.
IN2B
P5.4 U2C0.
SELO1 CCU81.
OUT13 EBU.
RAS EBU.
A21 ETH0.
CRSD CCU81.
IN3B ECAT0.
P0_RX_CLKB
P5.5 U2C0.
SELO2 CCU81.
OUT12 EBU.
CAS EBU.
A22 ETH0.
COLD ECAT0.
P0_TX_CLKB
P5.6 U2C0.
SELO3 CCU81.
OUT03 EBU.
BFCLKO EBU.
A23 EBU.
BFCLKI ECAT0.
P0_RX_DVB
P5.7 ECAT0.
SYNC0 CCU81.
OUT02 LEDTS0.
COLA U2C0.
DOUT2 U2C0.
HWIN2 ECAT0.
P0_RXD3B
P5.8 ECAT0.
P1_TX_ENA U1C0.
SCLKOUT CCU80.
OUT01 CAN.
N4_TXD EBU.
SDCLKO EBU.
CS2 ETH0.
RXD2A U1C0.
DX1B
P5.9 U1C0.
SELO0 CCU80.
OUT20 ETH0.
TX_EN EBU.
BFCLKO EBU.
CS3 ETH0.
RXD3A U1C0.
DX2B ECAT0.
P1_TX_CLKB
P5.10 U1C0.
MCLKOUT CCU80.
OUT10 LEDTS0.
LINE7 LEDTS0.
EXTENDED7 LEDTS0.
TSIN7A ETH0.
CLK_TXA CAN.
N5_RXDA
P5.11 U1C0.
SELO1 CCU80.
OUT00 CAN.
N5_TXD ETH0.
CRSA
P6.0 ETH0.
TXD2 U0C1.
SELO1 CCU81.
OUT31 ECAT0.
PHY_CLK25 DB.
ETM_TRACECLK EBU.
A16
P6.1 ETH0.
TXD3 U0C1.
SELO0 CCU81.
OUT30 ECAT0.
P0_TX_ENA DB.
ETM_TRACEDA
TA3
EBU.
A17 U0C1.
DX2C
P6.2 ETH0.
TXER U0C1.
SCLKOUT CCU43.
OUT3 ECAT0.
P0_TXD0 DB.
ETM_TRACEDA
TA2
EBU.
A18 U0C1.
DX1C
P6.3 CCU43.
OUT2 ECAT0.
P0_LINK_ACT U0C1.
DX0C ETH0.
RXD3B
P6.4 U0C1.
DOUT0 CCU43.
OUT1 ECAT0.
P0_TXD1 EBU.
SDCLKO EBU.
A19 EBU.
SDCLKI ETH0.
RXD2B
P6.5 CAN.
N3_TXD U0C1.
MCLKOUT CCU43.
OUT0 ECAT0.
P0_TXD2 DB.
ETM_TRACEDA
TA1
EBU.
BC2 DSD.
DIN3A ETH0.
CLK_RMIID U2C0.
DX0D ETH0.
CLKRXD
Table 12 Port I/O Functions (cont’d)
Function Outputs Inputs
ALT1 ALT2 ALT3 ALT4 HWO0 HWO1 HWI0 HWI1 Input Input Input Input Input Input Input Input
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Data Sheet 34 V1.1, 2018-09
P6.6 U2C0.
DOUT0 DSD.
MCLK3 ECAT0.
P0_TXD3 DB.
ETM_TRACEDA
TA0
EBU.
BC3 DSD.
MCLK3A ETH0.
CLK_TXB CAN.
N3_RXDB
P7.0 CAN.
N3_TXD ECAT0.
P0_TXD0 EBU.
A19
P7.1 ECAT0.
P0_TXD1 EBU.
A20 CAN.
N3_RXDC
P7.2 CAN.
N4_TXD ECAT0.
P0_TXD2 EBU.
A21
P7.3 ECAT0.
P0_TXD3 EBU.
A22 CAN.
N4_RXDC
P7.4 CCU42.
OUT0 ECAT0.
P0_RXD0C
P7.5 CCU42.
OUT1 ECAT0.
P0_RXD1C
P7.6 CCU42.
OUT2 ECAT0.
P0_RXD2C
P7.7 CCU42.
OUT3 ECAT0.
P0_RXD3C
P7.8 CAN.
N5_TXD ECAT0.
P0_TX_ENA DB.
ETM_TRACECLK
P7.9 CCU80.
OUT22 ECAT0.
P0_RX_ERRC
P7.10 CCU80.
OUT32 ECAT0.
P0_RX_CLKC
P7.11 CCU80.
OUT33 ECAT0.
P0_RX_DVC
P8.0 ECAT0.
P1_TXD0 DB.
ETM_TRACEDA
TA0
CAN.
N5_RXDC
P8.1 ECAT0.
P1_TXD1 DB.
ETM_TRACEDA
TA1
U0C0.
DX2C
P8.2 ECAT0.
P1_TXD2 DB.
ETM_TRACEDA
TA2
P8.3 ECAT0.
P1_TXD3 DB.
ETM_TRACEDA
TA3
U0C0.
DX1C
P8.4 U0C0.
SELO1 ECAT0.
P1_RXD0C
P8.5 U0C0.
SCLKOUT ECAT0.
P1_RXD1C
P8.6 U0C0.
SELO0 ECAT0.
P1_RXD2C
P8.7 U0C0.
DOUT0 ECAT0.
P1_RXD3C
P8.8 ECAT0.
P1_TX_ENA U0C0.
DX0E
Table 12 Port I/O Functions (cont’d)
Function Outputs Inputs
ALT1 ALT2 ALT3 ALT4 HWO0 HWO1 HWI0 HWI1 Input Input Input Input Input Input Input Input
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Data Sheet 35 V1.1, 2018-09
P8.9 CCU81.
OUT33 ECAT0.
P1_RX_ERRC
P8.10 CCU81.
OUT21 ECAT0.
P1_RX_CLKC
P8.11 CCU81.
OUT11 ECAT0.
P1_RX_DVC
P9.0 U2C0.
SELO0 ECAT0.
SYNC0 ECAT0.
LATCH0B U2C0.
DX2C ECAT0.
P1_TX_CLKC
P9.1 U2C0.
SCLKOUT ECAT0.
SYNC1 ECAT0.
LATCH1B U2C0.
DX1C ECAT0.
P0_TX_CLKC
P9.2 U2C0.
SELO1 ECAT0.
PHY_RST ETH0.
COLC
P9.3 U2C0.
DOUT0 ECAT0.
PHY_CLK25 ETH0.
CRSC
P9.4 ECAT0.
LED_STATE_RU
N
ECAT0.
LED_RUN U2C0.
DX0E
P9.5 U2C0.
SELO2 ECAT0.
LED_ERR ETH0.
RXD2C
P9.6 U2C0.
SELO3 ECAT0.
MCLK ETH0.
RXD3C
P9.7 U2C0.
SELO4 ECAT0.
MDO ECAT0.
MDIC ETH0.
RXERC
P9.8 ECAT0.
P0_LINK_ACT U2C1.
DX2C
P9.9 ECAT0.
P1_LINK_ACT U2C1.
DX1C
P9.10 U2C1.
DOUT0 ECAT0.
P0_LINKC
P9.11 U2C1.
SELO3 ECAT0.
P1_LINKC
P14.0 VADC.
G0CH0
P14.1 VADC.
G0CH1
P14.2 VADC.
G0CH2 VADC.
G1CH2
P14.3 VADC.
G0CH3 VADC.
G1CH3 CAN.
N0_RXDB
P14.4 VADC.
G0CH4 VADC.
G2CH0 CAN.
N4_RXDB ECAT0.
LATCH1A
P14.5 VADC.
G0CH5 VADC.
G2CH1 POSIF0.
IN2B ECAT0.
LATCH0A
P14.6 VADC.
G0CH6 POSIF0.
IN1B G0ORC6 ECAT0.
P1_RX_CLKB
P14.7 VADC.
G0CH7 POSIF0.
IN0B G0ORC7 ECAT0.
P1_RXD0B
Table 12 Port I/O Functions (cont’d)
Function Outputs Inputs
ALT1 ALT2 ALT3 ALT4 HWO0 HWO1 HWI0 HWI1 Input Input Input Input Input Input Input Input
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Data Sheet 36 V1.1, 2018-09
P14.8 DAC.
OUT_0 VADC.
G1CH0 VADC.
G3CH2 ETH0.
RXD0C
P14.9 DAC.
OUT_1 VADC.
G1CH1 VADC.
G3CH3 ETH0.
RXD1C
P14.12 VADC.
G1CH4 ECAT0.
P1_RXD1B
P14.13 VADC.
G1CH5 ECAT0.
P1_RXD2B
P14.14 VADC.
G1CH6 G1ORC6 ECAT0.
P1_RXD3B
P14.15 VADC.
G1CH7 G1ORC7 ECAT0.
P1_RX_DVB
P15.2 VADC.
G2CH2 ECAT0.
P1_RX_ERRB
P15.3 VADC.
G2CH3 ECAT0.
P1_LINKB
P15.4 VADC.
G2CH4
P15.5 VADC.
G2CH5
P15.6 VADC.
G2CH6
P15.7 VADC.
G2CH7
P15.8 VADC.
G3CH0 ETH0.
CLK_RMIIC ETH0.
CLKRXC
P15.9 VADC.
G3CH1 ETH0.
CRS_DVC ETH0.
RXDVC
P15.12 VADC.
G3CH4
P15.13 VADC.
G3CH5
P15.14 VADC.
G3CH6
P15.15 VADC.
G3CH7
HIB_IO_0 HIBOUT WWDT.
SERVICE_OUT WAKEUPA
HIB_IO_1 HIBOUT WWDT.
SERVICE_OUT WAKEUPB
USB_DP
USB_DM
TCK DB.TCK/
SWCLK
TMS DB.TMS/
SWDIO
PORST
Table 12 Port I/O Functions (cont’d)
Function Outputs Inputs
ALT1 ALT2 ALT3 ALT4 HWO0 HWO1 HWI0 HWI1 Input Input Input Input Input Input Input Input
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Data Sheet 37 V1.1, 2018-09
XTAL1 U0C0.
DX0F U0C1.
DX0F U1C0.
DX0F U1C1.
DX0F U2C0.
DX0F U2C1.
DX0F
XTAL2
RTC_XTAL1 ERU0.
1B1
RTC_XTAL2
Table 12 Port I/O Functions (cont’d)
Function Outputs Inputs
ALT1 ALT2 ALT3 ALT4 HWO0 HWO1 HWI0 HWI1 Input Input Input Input Input Input Input Input
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Data Sheet 38 V1.1, 2018-09
2.3 Power Connection Scheme
Figure 9. shows a reference power connection scheme for the XMC4[78]00.
Figure 9 Power Connection Scheme
Every power supply pin needs to b e connected. Different pins of the same supp ly need
also to be externally connected. As example, all VDDP pins must be connected externally
to one VDDP net. In this reference scheme one 100 nF capacitor is connected at each
supply pin against VSS. An additional 10 µF capacitor is connected to the VDDP nets and
an additional 10 uF capacitor to the VDDC nets.
VBAT
M x VDDC
N x VDDP
VSS
VDDA
VAREF
VAGND
Hibernate domain
RTC Hibernate
control
Retention
Memory
32 kHz
Clock
Core Domain
CPU
Dig.
Peripherals
Analog Do ma i n
ADC DAC
GPIOs
Out- of-rang e comparat or
PAD Doma in
Level
shift.
FLASH
RAMs
100 nF x M
10 µF x 1
100 nF
Reference
100 nF
3.3V
XMC4000
EVR
VSSA
Exp. Die Pad
VSS
GND
GND
GND
GND
AGND
100 nF x N
10 µF x 1
3.3V
2.1...3.6 V
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Data Sheet 39 V1.1, 2018-09
The XMC4[78]00 has a common ground concep t, all VSS, VSSA and VSSO pins share the
same ground potential. In packages with an exposed die pad it must be connected to the
common ground as well.
VAGND is the low potential to the analog reference VAREF. Depending on the application it
can share the common ground or have a different potential. In devices with shared
VDDA/VAREF and VSSA/VAGND pins the reference is tied to the supply. Some analog
channels can optionally serve as “Alternate Reference”; further details on this operating
mode are described in the Reference Manual.
When VDDP is supplied, VBAT must be supplied as well. If no other supply source (e.g.
battery) is connected to VBAT, the VBAT pin can also be connecte d directly to VDDP.
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 40 V1.1, 2018-09
3 Electrical Parameters
Attention: All parameters in this chapter are preliminary target values and may
change based on char acterization results.
3.1 General Parameters
3.1.1 Parameter Interpretation
The parameters listed in this section partly represent the characteristics of the
XMC4[78]00 and partly its requirements on the system. To aid interpreting the
parameters easily when evaluating them for a design , they are marked with a two-letter
abbreviation in column “Symbol”:
•CC
Such parameters indicate Controller Characte ristics, which are a distinctive fe ature
of the XMC4[78]00 and must be regarded for system design.
•SR
Such parameters indicate System Requirements, which must be provided by the
application system in which the XMC4[78]00 is designed in.
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 41 V1.1, 2018-09
3.1.2 Absolute Maximum Ratings
Stresses above the values listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Figure 10 explai ns the input voltage ranges of VIN an d VAIN and its dependency to the
supply level of VDDP.The input voltage must not exceed 4.3 V, and it must n ot be more
than 1.0 V above VDDP. For the range up to VDDP + 1.0 V also see the definition of the
overload conditions in Section 3.1.3.
Table 13 Absolute Maximum Rating Parameters
Parameter Symbol Values Unit Note /
Test Con
dition
Min. Typ. Max.
Storage temperature TST SR -65 – 150 °C–
Junction temperature TJ SR -40 −150 °C –
Voltage at 3.3 V power supply
pins with respect to VSS
VDDP SR – – 4.3 V –
Voltage on any Class A and
dedicated input pin with
respect to VSS
VIN SR -1.0 – VDDP + 1.0
or max. 4.3 V whichever
is lower
Voltage on any analog input
pin with respect to VAGND
VAIN
VAREF SR -1.0 – VDDP + 1.0
or max. 4.3 V whichever
is lower
Input current on any pin
during overload condition IIN SR -10 – +10 mA
Absolute maximum sum of all
input circuit currents for one
port group during overload
condition1)
1) The port groups are defined in Table 17.
ΣIIN SR -25 – +25 mA
Absolute maximum sum of all
input circuit currents during
overload condition
ΣIIN SR -100 – +100 mA
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 42 V1.1, 2018-09
Figure 10 Absolute Maximum Input Voltage Ranges
3.1.3 Pin Reliability in Overload
When receiving signals from higher voltage devices, low-voltage devices experience
overload currents and voltages that go beyond their own IO power supplies specification.
Table 14 defines overload conditions that will not cause any negative reliability impact if
all the following conditions are met:
• full operation life-time is not exceeded
•Operating Co nditions are met for
– pad supply levels (VDDP or VDDA)
– temperature
If a pin current is outside of the Operating Conditions but within the overload
conditions, then the parameters of this pin as stated in the Operating Conditions can no
longer be guaranteed. Operation is still possible in most cases but with relaxed
parameters.
Note: An overload condition on one or more pins does not require a reset.
Note: A series resistor at the pin to limit the current to the maximum permitted overload
current is sufficient to handle failure situations li ke short to battery.
V
4.3
V
SS
-1.0
A
A
B
Abs. max. input voltage V
IN
with V
DDP
> 3.3 V
Abs. max. input voltage V
IN
with V
DDP
≤ 3.3 V
V
V
DDP
+ 1.0
V
SS
-1.0
V
DDP
B
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 43 V1.1, 2018-09
Figure 11 shows th e path of the input currents during overload via the ESD protection
structures. The diodes against VDDP and ground are a simplified representation of these
ESD protection structures.
Figure 11 Input Overload Current via ESD structures
Table 15 and Table 16 list input voltages that can be reached under overload conditions.
Note that the absolute maximum input voltages as de fined in the Absolute Maximum
Ratings must not be exceeded during overload.
Table 14 Overload Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input current on any port pin
during overload condition IOV SR -5 – 5 mA
Absolute sum of all input
circuit currents for one port
group during overload
condition1)
1) The port groups are defined in Table 17.
IOVG SR – – 20 mA Σ|IOVx|, for all
IOVx <0mA
––20mAΣ|IOVx|, for all
IOVx >0mA
Absolute sum of all input
circuit currents during
overload condition
IOVS SR – – 80 mA ΣIOVG
Pn.y IOVx
GND
ESD Pad
GND
VDDP
VDDP
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 44 V1.1, 2018-09
Table 15 PN-Junction Characterisitics for positive Overload
Pad Type IOV =5mA, TJ=-40°C IOV =5mA, TJ=150°C
A1 / A1+ VIN =VDDP +1.0V VIN =VDDP +0.75V
A2 VIN =VDDP +0.7V VIN =VDDP +0.6V
AN/DIG_IN VIN =VDDP +1.0V VIN =VDDP +0.75V
Table 16 PN-Junction Characterisitics for negati ve Overload
Pad Type IOV =5mA, TJ=-40°C IOV =5mA, TJ=150°C
A1 / A1+ VIN =VSS -1.0V VIN =VSS -0.75V
A2 VIN =VSS -0.7V VIN =VSS -0.6V
AN/DIG_IN VIN =VDDP -1.0V VIN =VDDP -0.75V
Table 17 Port Groups for Overload and Short-Circuit Current Sum
Parameters
Group Pins
1 P0.[15:0], P3.[15:0], P8.[11:0 ]
2 P14.[15:0], P15.[15:0]
3 P2.[15:0], P5.[11:0], P7[11:0]
4 P1.[15:0], P4.[7:0], P6.[6:0], P9.[11:0]
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 45 V1.1, 2018-09
3.1.4 Pad Driver and Pad Classes Summary
This section gives an overview on the different pad driver classes and their basic
characteristics.
Figure 12 Output Slopes with different Pad Driver Modes
Figure 12 is a qualitative display of the resulting output slope performance with
different output driver modes. The detailed input and output characteristics are listed in
Section 3.2.1.
Table 18 Pad Driver and Pad Classes Overv iew
Class Power
Supply Type Sub-Class Speed
Grade Load Termination
A3.3 V LVTTL
I/O A1
(e.g. GPIO) 6 MHz 100 pF No
A1+
(e.g. serial I/Os) 25 MHz 50 pF Series termination
recommended
A2
(e.g. ext. Bus) 80 MHz 15 pF Series termination
recommended
V
VDDP
VSS
VOH
VOL
t
A
B
CDEF
A
B
C
D
E
F
Output High Voltage
Output Low Voltage
Weak drive strength
Medium drive strength
Strong – slow drive strength
Strong – soft drive strength
Strong – medium drive strength
Strong – sharp drive strength
ABCE
FClass A2 Pads
CDEFClass A1+ Pads
EFClass A1 Pads
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 46 V1.1, 2018-09
3.1.5 Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation and reliability of the XMC4[78]00. All parameters specified in the following
sections refer to these operating conditions, unless noted otherw ise.
Table 19 Operating Conditions Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Ambient Temperature TA SR -40 −85 °C Temp. Range F
-40 −125 °C Temp. Rang e K
Digital supply voltage VDDP SR 3.131)
1) See also the Supply Monitoring thresholds, Section 3.3.2.
3.3 3.63 2)
2) Voltage overshoot to 4.0 V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 μs and the cumulated sum of the pulses does not exceed 1 h over lifetime.
V
Core Supply Voltage VDDC
CC −1) 1.3 −V Generated
internally
Digital ground voltage VSS SR 0 −−V
ADC analog supply
voltage VDDA SR 3.0 3.3 3.62) V
Analog ground voltage for
VDDA
VSSA SR -0.1 0 0.1 V
Battery Supply Voltage for
Hibernate Domain VBAT SR 1.953)
3) To start the hibernate domain it is required that VBAT ≥2.1 V, for a reliable start of th e oscillation of RTC_XTAL
in crystal mode it is required that VBAT ≥3.0 V.
−3.63 V When VDDP is
supplied VBAT
has to be
supplied as
well.
System Frequency fSYS SR −−144 MHz
Short circuit current of
digital outputs ISC SR -5 −5mA
Absolute sum of short
circuit currents per pin
group4)
4) The port groups are defined in Table 17.
ΣISC_PG
SR −−20 mA
Absolute sum of short
circuit currents of the
device
ΣISC_D
SR −−100 mA
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 47 V1.1, 2018-09
3.2 DC Parameters
3.2.1 Input/Output Pins
The digital input stage of the shared analog/digital input pins is identical to the input
stage of the standard digital input/output pins.
The Pull-up on the PORST pin is identical to the Pull-up on the standard digital
input/ou tput pins.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 20 Standar d Pad Parameters
Parameter Symbol Values Unit Note / Test Condition
Min. Max.
Pin capacitance (digital
inputs/outputs) CIO CC −10 pF
Pull-down current |IPDL|
SR 150 −μA1)VIN ≥0.6 × VDDP
1) Current required to override the pull device with the opposite logic level (“force curr ent”).
With active pull device, at load currents between force and keep current the input state is undefined.
−10 μA2)VIN ≤0.36 × VDDP
2) Load current at which the pull device still maintains the valid logic level (“keep current”).
With active pull device, at load currents between force and keep current the input state is undefined.
Pull-Up current |IPUH|
SR −10 μA2)VIN ≥0.6 × VDDP
100 −μA1)VIN ≤0.36 × VDDP
Input Hysteresis for
pads of all A classes3)
3) Hysteresis is implemented to avoid metastable stat es and swit ch ing due to intern al g roun d bo unce. I t can n ot
be guaranteed that it suppresses switching due to external system noise.
HYSA
CC 0.1 ×
VDDP
−V
PORST spike filter
always blocked pulse
duration
tSF1 CC −10 ns
PORST spike filter
pass-through pulse
duration
tSF2 CC 100 −ns
PORST pull-down
current |IPPD|
CC 13 −mA VIN =1.0 V
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 48 V1.1, 2018-09
Figure 13 Pull Device Input Characteristics
Figure 13 visualizes the input characteristics with an active internal pull device:
• in the cases “A” the internal pull device is overridden by a strong external driver;
• in the cases “B” the internal pull device defines the input logical state against a weak
external load.
XMC4000 IN
I
PDL
AI
PDL
≥150 μA
BI
PDL
≤10 μA
V
DDP
GND
V
V
DDP
V
SS
0.6 x V
DDP
A
0.36 x V
DDP
B
Va lid High
Va lid Low
Inva lid di gi tal i nput
XMC4000
IN
I
PUH
AI
PUH
≥ 100 μA
BI
PUH
≤10 μA
V
V
DDP
V
SS
0.6 x V
DDP
B
0.36 x V
DDP
A
Va lid High
Va lid Low
Inva lid di gi tal i nput
Pull -down active
Pull-up active
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 49 V1.1, 2018-09
Table 21 Standard Pads Class_A1
Parameter Symbol Values Unit Note /
Test Condition
Min. Max.
Input leakage current IOZA1 CC -500 500 nA 0 V ≤VIN ≤VDDP
Input high voltage VIHA1 SR 0.6 × VDDP VDDP + 0.3 V max. 3.6 V
Input low voltage VILA1 SR -0.3 0.36 × VDDP V
Output high voltage,
POD1) = weak VOHA1
CC VDDP - 0.4 −VIOH ≥-400 μA
2.4 −VIOH ≥-500 μA
Output high voltage,
POD1) = medium VDDP - 0.4 −VIOH ≥-1.4 mA
2.4 −VIOH ≥-2 mA
Output low voltage VOLA1
CC −0.4 V IOL ≤500 μA;
POD1) = weak
−0.4 V IOL ≤2mA;
POD1) = medium
Fall time tFA1 CC −150 ns CL=20pF;
POD1) = weak
1) POD = Pin Out Driver
−50 ns CL=50pF;
POD1) = medium
Rise time tRA1 CC −150 ns CL=20pF;
POD1) = weak
−50 ns CL=50pF;
POD1) = medium
Table 22 Standard Pads Class_A1+
Parameter Symbol Values Unit Note /
Test Condition
Min. Max.
Input leakage current IOZA1+ CC -1 1 μA0V≤VIN ≤VDDP
Input high voltage VIHA1+ SR 0.6 × VDDP VDDP + 0.3 V max. 3.6 V
Input low voltage VILA1+ SR -0.3 0.36 × VDDP V
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 50 V1.1, 2018-09
Output high voltage,
POD1) = weak VOHA1+
CC VDDP - 0.4 −VIOH ≥-400 μA
2.4 −VIOH ≥-500 μA
Output high voltage,
POD1) = medium VDDP - 0.4 −VIOH ≥-1.4 mA
2.4 −VIOH ≥-2 mA
Output high voltage,
POD1) = strong VDDP - 0.4 −VIOH ≥-1.4 mA
2.4 −VIOH ≥-2 mA
Output low voltage VOLA1+
CC −0.4 V IOL ≤500 μA;
POD1) = weak
−0.4 V IOL ≤2mA;
POD1) = medium
−0.4 V IOL ≤2mA;
POD1) = strong
Fall time tFA1+ CC −150 ns CL=20pF;
POD1) = weak
−50 ns CL=50pF;
POD1) = medium
−28 ns CL=50pF;
POD1) = strong;
edge = slow
−16 ns CL=50pF;
POD1) = strong;
edge = soft;
Rise time tRA1+ CC −150 ns CL=20pF;
POD1) = weak
−50 ns CL=50pF;
POD1) = medium
−28 ns CL=50pF;
POD1) = strong;
edge = slow
−16 ns CL=50pF;
POD1) = strong;
edge = soft
1) POD = Pin Out Driver
Table 22 Standard Pads Class_A1+
Parameter Symbol Values Unit Note /
Test Condition
Min. Max.
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 51 V1.1, 2018-09
Table 23 Standard Pads Class_A2
Parameter Symbol Values Unit Note /
Test Condition
Min. Max.
Input Leakage current IOZA2
CC -6 6 μA0V≤VIN <
0.5*VDDP -1V;
0.5*VDDP +1V
<VIN ≤VDDP
-3 3 μA0.5*VDDP -1V <
VIN <0.5*VDDP
+1V
Input high voltage VIHA2
SR 0.6 × VDDP VDDP + 0.3 V max. 3.6 V
Input low voltage VILA2 SR -0.3 0.36 ×
VDDP
V
Output high voltage,
POD = weak VOHA2
CC VDDP - 0.4 −VIOH ≥-400 μA
2.4 −VIOH ≥-500 μA
Output high voltage,
POD = medium VDDP - 0.4 −VIOH ≥-1.4 mA
2.4 −VIOH ≥-2 mA
Output high voltage,
POD = strong VDDP - 0.4 −VIOH ≥-1.4 mA
2.4 −VIOH ≥-2 mA
Output low voltage,
POD = weak VOLA2
CC −0.4 V IOL ≤500 μA
Output low voltage,
POD = medium −0.4 V IOL ≤2mA
Output low voltage,
POD = strong −0.4 V IOL ≤2mA
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 52 V1.1, 2018-09
Fall time tFA2 CC −150 ns CL=20pF;
POD = weak
−50 ns CL=50pF;
POD = medium
−3.7 ns CL=50pF;
POD = strong;
edge = sharp
−7ns
CL=50pF;
POD = strong;
edge = medium
−16 ns CL=50pF;
POD = strong;
edge = soft
Rise time tRA2 CC −150 ns CL=20pF;
POD = weak
−50 ns CL=50pF;
POD = medium
−3.7 ns CL=50pF;
POD = strong;
edge = sharp
−7.0 ns CL=50pF;
POD = strong;
edge = medium
−16 ns CL=50pF;
POD = strong;
edge = soft
Table 23 Standard Pads Class_A2
Parameter Symbol Values Unit Note /
Test Condition
Min. Max.
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 53 V1.1, 2018-09
Table 24 HIB_IO Class_A1 special Pads
Parameter Symbol Values Unit Note /
Test Condition
Min. Max.
Input leakage current IOZHIB
CC -500 500 nA 0 V ≤VIN ≤VBAT
Input high voltage VIHHIB
SR 0.6 × VBAT VBAT + 0.3 V max. 3.6 V
Input low voltage VILHIB
SR -0.3 0.36 × VBAT V
Input Hysteresis for
HIB_IO pins1)
1) Hysteresis is implemente d to avoi d meta st able stat es an d switching due to interna l gro und b ounce. I t can not
be guaranteed that it suppresses switching due to external system noise.
HYSHIB
CC 0.1 × VBAT −VVBAT ≥3.13 V
0.06 ×
VBAT
−VVBAT <3.13 V
Output high voltage,
POD1) = medium VOHHIB
CC VBAT - 0.4 −VIOH ≥-1.4 mA
Output low voltage VOLHIB
CC −0.4 V IOL ≤2mA
Fall time tFHIB CC −50 ns VBAT ≥3.13 V
CL=50pF
−100 ns VBAT <3.13 V
CL=50pF
Rise time tRHIB CC −50 ns VBAT ≥3.13 V
CL=50pF
−100 ns VBAT <3.13 V
CL=50pF
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 54 V1.1, 2018-09
3.2.2 Analog to Digital Converters (VADC)
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 25 VADC Parameters (Operating Conditions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Analog reference voltage5) VAREF
SR VAGND
+ 1 −VDDA +
0.051) V
Analog reference ground5) VAGND
SR VSSM -
0.05 −VAREF -
1V
Analog reference voltage
range2)5) VAREF -
VAGND
SR
1−VDDA +
0.1 V
Analog input voltage VAIN SR VAGND −VDDA V
Input leakage at analog
inputs3) IOZ1 CC -100 −200 nA 0.03 × VDDA <
VAIN <0.97 × VDDA
-500 −100 nA 0 V ≤VAIN ≤ 0.03
× VDDA
-100 −500 nA 0.97 × VDDA
≤VAIN ≤VDDA
Input leakage current at
VAREF IOZ2 CC -1 −1μA0V≤ VAREF
≤VDDA
Input leakage current at
VAGND IOZ3 CC -1 −1μA0V≤VAGND
≤VDDA
Internal ADC clock fADCI CC 2 −36 MHz VDDA = 3.3 V
Switched capacitance at
the analog voltage inputs4) CAINSW
CC −46.5pF
Total capacitance of an
analog input CAINTOT
CC −12 20 pF
Switched capacitance at
the positive reference
voltage input5)6)
CAREFSW
CC −15 30 pF
Total capacitance of the
voltage reference inputs 5) CAREFTOT
CC −20 40 pF
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 55 V1.1, 2018-09
Total Unadjusted Error TUE CC -4 −4 LSB 12-bit resolution;
VDDA = 3.3 V;
VAREF = VDDA7)
Differential Non-Linearity
Error8) EADNL
CC -3 −3LSB
Gain Error8) EAGAIN
CC -4 −4LSB
Integral Non-Linearity8) EAINLCC -3 −3LSB
Offset Error8) EAOFF
CC -4 −4LSB
RMS Noise9) ENRMS
CC −12
10)11) LSB
Worst case ADC VDDA
power supply current per
active converter
IDDAA
CC −1.5 2 mA during conversion
VDDP =3.6V,
TJ= 150 oC
Charge consumption on
VAREF per conversion5) QCONV
CC −30 −pC 0 V ≤VAREF
≤VDDA12)
ON resistance of the
analog input path RAIN CC −600 1 200 Ohm
ON resistance for the ADC
test (pull down for AIN7) RAIN7T
CC 180 550 900 Ohm
Resistance of the
reference vol t age input
path
RAREF
CC −700 1 700 Ohm
1) A running conversion may become imprecise in case the normal conditions are violated (voltage overshoot).
2) If the analog refer ence voltage is below VDDA, then t he ADC converte r errors increase. I f the referen ce voltage
is reduced by the factor k (k<1), TUE, DNL, INL, Gain, and Offset err ors increase also by the factor 1/k.
3) The leakage current defin iti on is a con tinuous fun ction , as shown in figure ADCx Analog Input s Leakage. The
numerical values defined determine the characteristic points of the given continuous linear approximation -
they do not define step funct i on (see Figure 16).
4) The sampling capacity of the conversion C-network is pre-charged to VAREF/2 before the sampling moment.
Because of the parasitic elements, the voltage measured at AINx can deviate from VAREF/2.
5) Applies to AINx, when used as alternate reference input.
6) This represents an equivalent switched capacitance. This capacitance is not switched to the re ference voltage
at once. Instead, smaller capacitances are successively switched to the reference voltage.
7) For 10-bit conversions, the errors are reduced to 1/4; for 8-bit conversions, the errors are reduced to 1/16.
Never less than ±1 LSB.
8) The sum of DNL/INL/GAIN/OFF errors does not exceed the related total unadjusted error TUE.
Table 25 VADC Parameters (Operating Conditions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 56 V1.1, 2018-09
Figure 14 VADC Reference Voltage Range
The power-up calibration of the VADC requires a maximum number of 4 352 fADCI cycles.
9) This parameter is valid for soldered devices and requires careful analog board design.
10)Resulting worst case combined error is arithmetic combination of TUE and ENRMS.
11)Value is defined for one sigma Gauss distribution.
12)The resulting current for a conver sion can be calculated with IAREF =QCONV /tc.
The fastest 12-bit post-calibrated conversion of tc= 459 ns results in a typical average current of
IAREF = 65.4 µA.
Minimum VAREF - VAGND is 1 V
V
VDDA + 0.05
VAGND + 1
VAGND
Valid VAREF
VDDA
e.g. VAREF = 4/5 of VDDA
Conversion error
increases by 5/4
Precise co nversion range ( 12 bit)
t
VAREF
VSSA
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XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 57 V1.1, 2018-09
Figure 15 VADC Input Circuits
Figure 16 VADC Analog Input Leakage Current
Reference Voltage Input Circuitry
Analog Input Circuitry
Analog_InpRefDiag
REXT
=
VAIN CEXT
RAIN, On
CAINTOT - CAINSW
CAINSW
ANx
VAREF
RAREF, On
CAREFTOT - CAREFSW CAREFSW
VAGNDx
VAREFx
RAIN7T
VAGNDx
ADC-Leakage.vsd
V
IN
[% V
DDA
]
200 nA
500 nA
3% 100%97%
I
OZ1
100 nA
-500 nA
-100 nA
Si ngl e AD C Input
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XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 58 V1.1, 2018-09
Conversion Ti me
• STC defines additional clock cycles to extend the sample time
• PC adds two cycles if post-calibration is enabled
• DM adds one cycle for an extended conversion time of the MSB
Conversion Ti me Examples
System assumptions:
fADC = 144 MHz i.e. tADC = 6.9 ns, DIVA = 3, fADCI = 36 MHz i.e. tADCI = 27.8 ns
According to the given formulas the following minimum conversion times can be
achieved (STC = 0, DM = 0):
12-bit post-calibrated conversion (PC = 2):
tCN12C = (2 + 12 + 2) × tADCI + 2 × tADC = 16 × 27.8 ns + 2 × 6.9 ns = 459 ns
12-bit uncalibrated conversion:
tCN12 = (2 + 12) × tADCI + 2 × tADC = 14 × 27.8 ns + 2 × 6.9 ns = 403 ns
10-bit uncalibrated conversion:
tCN10 = (2 + 10) × tADCI + 2 × tADC = 12 × 27.8 ns + 2 × 6.9 ns = 348 ns
8-bit uncalibrated:
tCN8 = (2 + 8) × tADCI + 2 × tADC = 10 × 27.8 ns + 2 × 6.9 ns = 292 ns
3.2.3 Digital to Analog Converters (DAC)
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 26 Conve rsion Time (Operating Conditions apply)
Parameter Symbol Values Unit Note
Conversion
time tCCC 2 ×TADC +
(2+N+STC+PC+DM)× TADCI
μs N = 8, 10, 12 for
N-bit conversion
TADC =1/fPERIPH
TADCI =1/fADCI
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XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 59 V1.1, 2018-09
Table 27 DAC Parameters (Operating Conditions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
RMS supply current IDD CC −2.5 4 mA per active DAC
channel,
without load
currents of DAC
outputs
Resolution RES CC −12 −Bit
Update rate fURATE_ACC −2 Msam
ple/s data rate, where
DAC can follow
64 LSB code jumps
to ± 1LSB accuracy
Update rate fURATE_F CC −5 Msam
ple/s data rate, where
DAC can follow
64 LSB code jumps
to ± 4 LSB accuracy
Settling time tSETTLE CC −12 μs at full scale jump,
output voltage
reaches target
value ± 20 LSB
Slew rate SR CC 2 5 −V/μs
Minimum output
voltage VOUT_MIN
CC −0.3 −V code value
unsigned: 000H;
signed: 800H
Maximum output
voltage VOUT_MAX
CC −2.5 −V code value
unsigned: FFFH;
signed: 7FFH
Integral non-linearity INL CC -5.5 ±2.5 5.5 LSB RL ≥ 5kOhm,
CL ≤ 50 pF
Differential non-
linearity DNL CC -2 ±1 2 LSB RL ≥ 5kOhm,
CL ≤ 50 pF
Offset error EDOFF CC ±20 mV
Gain error EDG_IN CC -6.5 -1.5 3 %
Startup time tSTARTUP CC −15 30 μs time from output
enabling till code
valid ±16 LSB
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XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 60 V1.1, 2018-09
Conversion Calculation
Unsigned:
DACxDATA = 4095 × (VOUT - VOUT_MIN) / (VOUT_MAX - VOUT_MIN)
Signed:
DACxDATA = 4095 × (VOUT - VOUT_MIN) / (VOUT_MAX - VOUT_MIN) - 2048
3dB Bandwidth of
Output Buffer fC1 CC 2.5 5 −MHz verified by design
Output sourcing
current IOUT_SOURCE
CC −-30 −mA
Output sinking
current IOUT_SINK
CC −0.6 −mA
Output resistance ROUT CC −50 −Ohm
Load resistance RL SR 5 −− kOhm
Load capacitance CL SR −−50 pF
Signal-to-Noise
Ratio SNR CC −70 −dB examination
bandwidth < 25 kHz
Total Harmonic
Distortion THD CC −70 −dB examination
bandwidth < 25 kHz
Power Supply
Rejection Ratio PSRR CC −56 −dB to VDDA
verified by desig n
Table 27 DAC Parameters (Operating Conditions apply) (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
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XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 61 V1.1, 2018-09
Figure 17 DAC Conversion Examples
DAC output
VOUT_MIN
VOUT_MAX
64 LSBs
+/- 4LSB
fURATE_F (max)
64 LSBs
+/- 1LSB
fURATE_A (max)
DAC output
VOUT_MIN
VOUT_MAX 20 LSBs
tSETTLE
20 LSB s
tSETTLE
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XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 62 V1.1, 2018-09
3.2.4 Out-of-Range Comparator (ORC)
The Out-of-Range Comparator (ORC) triggers on analog input voltages (VAIN) above the
analog reference1) (VAREF) on selected input pins (GxORCy) and generates a service
request trigger (GxORCOUTy).
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
The parameters in Table 28 apply for the maximum reference voltage
VAREF =VDDA +50mV.
1) Always the standard VA DC ref erence, alternate references do not apply to the ORC.
Table 28 ORC Parameters (Operating Conditions apply)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
DC Switching Level VODC CC 100 125 210 mV VAIN ≥ VAREF + VODC
Hysteresis VOHYS CC 50 −VODC mV
Detection Delay of a
persistent
Overvoltage
tODD CC 50 −450 ns VAIN ≥ VAREF + 210 mV
45 −105 ns VAIN ≥ VAREF + 400 mV
Always detected
Overvoltage Pulse tOPDD CC 440 −− ns VAIN ≥ VAREF + 210 mV
90 −− ns VAIN ≥ VAREF + 400 mV
Never detected
Overvoltage Pulse tOPDN CC −−45 ns VAIN ≥ VAREF + 210 mV
−−30 ns VAIN ≥ VAREF + 400 mV
Release Delay tORD CC 65 −105 ns VAIN ≤ VAREF
Enable Delay tOED CC −100 200 ns
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XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 63 V1.1, 2018-09
Figure 18 GxORC OUTy Trigger Generation
Figure 19 ORC Detection Ranges
VSS
VAREF
tORD
VODC
VOHYS
tODD
GxORCOUTy
GxORCy
VAIN (V)
VAREF + 400 mV
t
VAREF + 200 mV
Overvoltage
may be
detected
(level uncertain)
Never
detected
Overvoltage
Pulse
(Too short)
T < tOPDN tOPDN < T < tOPDD
Overvoltage
may be
detected
T > tOPDD
Always detected
Overvoltage Pulse
T < tOPDN
Never
detected
Overvoltage
Pulse
(Too short)
tOPDN < T < tOPDD T > tOPDD
Always detected
Overvoltage Pulse
VAREF + 100 mV
Overvoltage
may be
detected
T > tOPDN
Never
detected
Overvoltage
Pulse
(To o low)
VAREF
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XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 64 V1.1, 2018-09
3.2.5 Die Temperature Sensor
The Die Temperature Sensor (DTS) measures the junction temperatur e TJ.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
The following formula calculates the temperature measured by the DTS in [oC] from the
RESULT bit field of the DTSSTAT register.
Temperature TDTS = (RESULT - 605) / 2.05 [°C]
This formula and the values defined in Table 29 apply with the following calibration
values:
• DTSCON.BGTRIM = 8H
• DTSCON.REFTRIM = 4H
Table 29 Die Tem perature Sensor Para meters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Temperature sensor range TSR SR -40 −150 °C
Linearity Error
(to the below defined formul a)
Δ
TLE CC −±1 −°C per
Δ
TJ≤30 °C
Offset Error
Δ
TOE CC −±6 −°C
Δ
TOE = TJ - TDTS
VDDP ≤3.3 V1)
1) At VDDP_max = 3.63 V the typical offset error increases by an additional
Δ
TOE =±1°C.
Measurement time tMCC −−100 μs
Start-up time after reset
inactive tTSST SR −−10 μs
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XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 65 V1.1, 2018-09
3.2.6 USB OTG Interface DC Characteristics
The Universal Serial Bus (USB) Interface is compliant to the USB Rev. 2.0 Specification
and the OTG Specification Rev. 1.3. High-Speed Mode is not sup ported.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 30 USB OTG VBUS and ID Parameters (Operating Conditions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
VBUS input voltage
range VIN CC 0.0 −5.25 V
A-device VBUS valid
threshold VB1 CC 4.4 −− V
A-device session valid
threshold VB2 CC 0.8 −2.0 V
B-device session valid
threshold VB3 CC 0.8 −4.0 V
B-device session end
threshold VB4 CC 0.2 −0.8 V
VBUS input
resistance to ground RVBUS_IN
CC 40 −100 kOhm
B-device VBUS pull-
up resistor RVBUS_PU
CC 281 −− Ohm Pull-up voltage =
3.0 V
B-device VBUS pull-
down resistor RVBUS_PD
CC 656 −− Ohm
USB.ID pull-up
resistor RUID_PU
CC 14 −25 kOhm
VBUS input current IVBUS_IN
CC −−150 μA0 V ≤ VIN ≤ 5.25 V:
TAVG = 1 ms
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XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 66 V1.1, 2018-09
Table 31 USB OTG Data Line (USB_DP, USB_DM) Parameters (Operating
Conditions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input low voltage VIL SR −−0.8 V
Input high voltage
(driven) VIH SR 2.0 −− V
Input high voltage
(floating) 1)
1) Measured at A-connector with 1.5 kOhm ± 5% to 3. 3 V ± 0.3 V connected to USB_DP or USB_DM and at B-
connector with 15 kOhm ± 5% to ground connected to USB_DP and USB_DM.
VIHZ SR 2.7 −3.6 V
Differential input
sensitivity VDIS CC 0.2 −− V
Differential common
mode range VCM CC 0.8 −2.5 V
Output low voltage VOL CC 0.0 −0.3 V 1.5 kOhm pull-
up to 3.6 V
Output high voltage VOH CC 2.8 −3.6 V 15 kOhm pull-
down to 0 V
DP pull-up resistor (idle
bus) RPUI CC 900 −1 575 Ohm
DP pull-up resistor
(upstream port
receiving)
RPUA CC 1 425 −3 090 Ohm
DP, DM pull-down
resistor RPD CC 14.25 −24.8 kOhm
Input impedance DP,
DM ZINP CC 300 −− kOhm 0 V ≤ VIN ≤ VDDP
Driver output resistance
DP, DM ZDRV CC 28 −44 Ohm
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XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 67 V1.1, 2018-09
3.2.7 Oscillator Pins
Note: It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimal parameters
for the oscillator operation. Please refer to the limits specified by the crystal or
ceramic resonator supplier.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
The oscillator pins can be operated with an external crystal (see Figure 20) or in direct
input mode (s ee Figure 21).
Figure 20 Oscillator in Crystal Mode
XTAL1
XTAL2
f
OSC
Damping resistor
may be needed for
some crystals
V
PPX
V
PPX_min
≤V
PPX
≤V
PPX_max
t
V
V
PPX_min
t
OSCS
GND
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XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 68 V1.1, 2018-09
Figure 21 Oscillator in Direct Input Mode
V
VIHBX_max
VSS
t
Input High Voltage
Input Low Voltage
Input High Voltage
XTAL1
XTAL2
not connected
External Clock
Source
Direct Inpu t Mode
VIHBX_min
VILBX_max
VILBX_min
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XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 69 V1.1, 2018-09
Table 32 OSC_XTAL Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input frequency fOSC SR 4 −40 MHz Direct Input Mode
selected
4−25 MHz External Crystal
Mode selected
Oscillator start-up
time1)2)
1) tOSCS is defined from the moment the oscillator is enable d wih SCU_OSCHPCTRL.MODE until the oscillations
reach an amplitude at XTAL1 of 0.4 * VDDP.
2) The external oscillator circuitry must be optimized by the customer and checked for negative resistance and
amplitude as recommended and specified by crystal suppliers.
tOSCS
CC −−10 ms
Input voltage at XTAL1 VIX SR -0.5 −VDDP +
0.5 V
Input amplitude (peak-
to-peak) at XTAL12)3)
3) If the shaper unit is enabled and not bypassed.
VPPX SR 0.4 ×
VDDP
−VDDP +
1.0 V
Input high voltage at
XTAL14)
4) If the shaper unit is bypassed, dedicated DC-th resholds have to be met.
VIHBXSR 1.0 −VDDP +
0.5 V
Input low voltage at
XTAL14) VILBX SR -0.5 −0.4 V
Input leakage current at
XTAL1 IILX1 CC -100 −100 nA Oscillator power
down
0V ≤ VIX ≤VDDP
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XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 70 V1.1, 2018-09
Table 33 RTC_XTAL Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input frequency fOSC SR −32.768 −kHz
Oscillator start-up
time1)2)3)
1) tOSCS is defined from the moment the o scillator is enabled by t he user with SCU_OSCULCTRL.MODE until the
oscillations reach an amplitude at RTC_XTAL1 of 400 mV.
2) The external oscillator circuitry must be optimized by the customer and checked for negative resistance and
amplitude as recommended and specified by crystal suppliers.
3) For a reliable start of the oscillation in crystal mode it is required that VBAT ≥3.0 V. A running oscillation is
maintained across the full VBAT voltage range.
tOSCS
CC −−5s
Input voltage at
RTC_XTAL1 VIX SR -0.3 −VBAT +
0.3 V
Input amplitude (peak-
to-peak) at
RTC_XTAL12)4)
4) If the shaper unit is enabled and not bypassed.
VPPX SR 0.4 −−V
Input high voltage at
RTC_XTAL15)
5) If the shaper unit is bypassed, dedicated DC-th resholds have to be met.
VIHBXSR 0.6 ×
VBAT
−VBAT +
0.3 V
Input low voltage at
RTC_XTAL15) VILBX SR -0.3 −0.36 ×
VBAT
V
Input Hysteresis for
RTC_XTAL15)6)
6) Hysteresis is implemente d to avoid metastab le st ates and switching due to in te rnal groun d bo unce. It can n ot
be guaranteed that it suppresses switching due to external system noise.
VHYSX
CC 0.1 ×
VBAT
−V3.0V ≤
VBAT <3.6V
0.03 ×
VBAT
−VVBAT <3.0V
Input leakage current at
RTC_XTAL1 IILX1 CC -100 −100 nA Oscillator power
down
0V ≤ VIX ≤VBAT
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XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 71 V1.1, 2018-09
3.2.8 Power Supply Current
The total power supply current defined below consists of a leakage and a switching
component.
Application relevant values are typically low er than those given in the followi ng tables,
and depend on the custo mer's system operat ing condi tions (e.g . thermal connection or
used application configurations).
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
If not stated otherwise, the operating conditions for the parameters in the following table
are:
VDDP = 3.3 V, TA = 25 oC
Table 34 Power Supply Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Active supply current1)11)
Peripherals enabled
Frequency:
fCPU / fPERIPH / fCCU in MHz
IDDPA CC −135 −mA 144 / 144 / 144
−125 −144 / 72 / 72
−97 −72 / 72 / 144
−80 −24 / 24 / 24
−68 −1/1/1
Active supply current
Code execution from RAM
Flash in Sleep mode
IDDPA CC −108 −mA 144 / 144 / 144
−98 −144 / 72 / 72
Active supply current2)
Peripherals disabled
Frequency:
fCPU / fPERIPH / fCCU in MHz
IDDPA CC −86 −mA 144 / 144 / 144
−85 −144 / 72 / 72
−70 −72 / 72 / 144
−55 −24 / 24 / 24
−50 −1/1/1
Sleep supply current3)
Peripherals enabled
Frequency:
fCPU / fPERIPH / fCCU in MHz
IDDPS CC −127 −mA 144 / 144 / 144
−115 −144 / 72 / 72
−93 −72 / 72 / 144
−57 −24 / 24 / 24
−47 −1/1/1
fCPU / fPERIPH / fCCU in kHz −48 −100 / 100 / 100
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 72 V1.1, 2018-09
Sleep supply current4)
Peripherals disabled
Frequency:
fCPU / fPERIPH / fCCU in MHz
IDDPS CC −77 −mA 144 / 144 / 144
−76 −144 / 72 / 72
−65 −72 / 72 / 144
−53 −24 / 24 / 24
−46 −1/1/1
fCPU / fPERIPH / fCCU in kHz −47 −100 / 100 / 100
Deep Sleep supply
current5)
Flash in Sleep mode
Frequency:
fCPU / fPERIPH / fCCU in MHz
IDDPD CC −11 −mA 24 / 24 / 24
−7.0 −4/4/4
−6.6 −1/1/1
fCPU / fPERIPH / fCCU in kHz −7.6 −100 / 100 / 100
6)
Hibernate supply current
RTC on7) IDDPH CC −8.7 −μAVBAT =3.3V
−6.5 −VBAT =2.4V
−5.7 −VBAT =2.0V
Hibernate supply current
RTC off8) IDDPH CC −8.0 −μAVBAT =3.3V
−6.0 −VBAT =2.4V
−5.0 −VBAT =2.0V
Hibernate off9) IDDPH CC −4.4 −μAVBAT =3.3V
−3.5 −VBAT =2.4V
−3.1 −VBAT =2.0V
Worst case active supply
current10) IDDPA CC −−250
11) mA VDDP =3.6V,
TJ=150oC
VDDA power supply current IDDA CC −−−
12) mA
IDDP current at PORST Lo w IDDP_PORST
CC −510mAVDDP =3.3V,
TJ=25oC
−13 55 mA VDDP =3.6V,
TJ=150oC
Power Dissipation PDISS CC −−1.4 W VDDP =3.6V,
TJ=150oC
Table 34 Power Supply Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 73 V1.1, 2018-09
Wake-up time from Sleep to
Active mode tSSA CC −6−cycles
Wake-up time from Deep
Sleep to Active mode −−−ms Defined by the
wake-up of the
Flash module,
see
Section 3.2.9
Wake-up time from
Hibernate mode −−−ms Wake-up via
power-on reset
event, see
Section 3.3.2
1) CPU executing code from Flash, all peripherals idle.
2) CPU executing code from Flash.
3) CPU in sleep, all peripherals idle, Flash in Active mode.
4) CPU in sleep, Flash in Active mode.
5) CPU in sleep, peripherals disabled, after wake-up code execution from RAM.
6) To wake-up the Flash from its Sleep mode, fCPU ≥ 1 MHz is required.
7) OSC_ULP operating with external crystal on RTC_XTAL
8) OSC_ULP off, Hibernate domain operating with OSC_SI clock
9) VBAT supplied, but Hibernate domain not started; for example state after factory assembly
10)Test Power Loop: fSYS = 144 MHz, CPU executing benchmark code from Flash, all CCUs in 100kHz timer
mode, all ADC groups in continuous conversion mode, USICs as SPI in internal loop-back mode, CAN in
500kHz internal loop-back mode , interrupt triggered DMA block transfers to parity protected RAMs and FCE,
DTS measurements and FPU calculations.
The power consumption of each customer applicatio n will most probably be lower than this value, but must be
evaluated separately.
11) IDDP decreases typically by approximately 5 mA when fSYS decreases by 10 MHz, at constant TJ
12) Sum of currents of all active converter s (A DC and DAC)
Table 34 Power Supply Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 74 V1.1, 2018-09
Peripheral Idle Currents
Default test conditions:
•fsys and derived clocks at 144 MHz
•VDDP =3.3V, Ta=25 °C
• all peripherals are held in reset (see the PRSTAT registers in the Reset Control Unit
of the SCU)
• the peripheral clocks are disabled (see CGATSTAT registers in the Clock Control
Unit of the SCU
• no I/O activity
The given v alues are a result of differential measurements with asserted and deasserted
peripheral reset as well as disabled and enabled clock of the periph eral under test.
The tested peripheral is left in the state after the peripheral reset is deasserted, no further
initialisation or configuration is done. E.g. no timer is running in the CCUs, no
communication active in the USICs, etc.
Table 35 Peripheral Idle Currents
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
PORTS
FCE
WDT
POSIFx1)
1) Enabling the fCCU clock for the POSIFx/CCU4x/CCU8x modules adds approximately IPER =4.8mA,
disregarding which and how many of those periphe rals are enabled.
IPER CC −≤0.3 −mA
MultiCAN
ERU
LEDTSCU0
ETH
CCU4x1), CCU8x1)
−≤1.0 −
DAC (digital)2)
2) The current consumption of the analog components are given in the dedicated Data Sheet sections of the
respective peripheral.
−1.3 −
USICx
DMA1
SDMMC
−3.0 −
DSD, EBU
VADC (digital)2) −4.5 −
DMA0, USB, EtherCAT −6.0 −
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 75 V1.1, 2018-09
3.2.9 Flash Memory Parameters
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 36 Flash Memory Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Erase Time per 256
Kbyte Sector tERP CC −55.5s
Erase Time per 64 Kbyte
Sector tERP CC −1.2 1.4 s
Erase Time per 16 Kbyte
Logical Sector tERP CC −0.3 0.4 s
Program time per page1) tPRP CC −5.5 11 ms
Erase suspend delay tFL_ErSusp
CC −−15 ms
Wait time after margin
change tFL_Margin
Del CC 10 −−μs
Wake-up time tWU CC −−270 μs
Read access time ta CC 22 −−n s For operati on
with 1 / fCPU < ta
wait states must
be configured2)
Data Retention Time,
Physical Sector3)4) tRET CC 20 −−years M ax. 1000
erase/program
cycles
Data Retention Time,
Logical Sector3)4) tRETL CC 20 −−years Max. 100
erase/program
cycles
Data Retention Time,
User Configuration Block
(UCB)3)4)
tRTU CC 20 −−years Max. 4
erase/program
cycles per UCB
Endurance on 64 Kbyte
Physical Sector PS4 NEPS4
CC 10000 −−cycles Cycling
distributed over
life time5)
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 76 V1.1, 2018-09
1) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The
reprogramming takes an additional time of 5.5 ms.
2) The following formula applies to the wait sta te configuration: FCON.WSPFLASH × (1 / fCPU) ≥ ta.
3) Storage and inactive time included.
4) Values given are valid for an average weighted junction temp erature of TJ = 110°C.
5) Only valid with robust EEPROM e mulation al gorithm, equally cycling the logical sector s. For more details see
the Reference Manual.
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 77 V1.1, 2018-09
3.3 AC Parameters
3.3.1 Testing Waveforms
Figure 22 Rise/Fall Time Parameters
Figure 2 3 Testing Waveform, Output De lay
Figure 2 4 Testing Waveform, Output High Imp edance
AC_Rise-Fall-Times.vsd
10%
90%
V
SS
V
DDP
t
R
t
F
10%
90%
AC_TestPoints.vsd
V
DDP
/ 2 V
DDP
/ 2
V
DDP
V
SS
Test Points
AC_HighImp.vsd
V
LOAD
+ 0.1 V Tim ing
Reference
Points
V
LOAD
-0.1V
V
OH
-0.1V
V
OL
+ 0.1V
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 78 V1.1, 2018-09
3.3.2 Power-Up and Supply Monitoring
PORST is always asserted when VDDP and/or VDDC violate the respective thresholds.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Figure 25 PORST Circuit
Table 37 Supply Monitoring Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Digital supply voltage reset
threshold VPOR CC 2.791)
1) Minimum threshold for reset assertion.
−3.052) V3)
Core supply voltage reset
threshold VPV CC −−1.17 V
VDDP voltage to ensure
defined pad states VDDPPA
CC −1.0 −V
PORST rise time tPR SR −−2μs4)
Startup time from power-on
reset with code execution
from Flash
tSSW CC −2.5 3.5 ms Time to the first
user code
instruction
VDDC ramp up time tVCR CC −550 −μs Ramp up after
power-on or
after a reset
triggered by a
violation of
VPOR or VPV
VDDP
PORST
GND
PORESET
VDDP
GND
XMC4000
RPORST
(optional)
External
reset
trigger Supply
Monitoring
IPPD
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 79 V1.1, 2018-09
Figure 26 Power-Up Behavior
3.3.3 Power Sequencing
While starting up and shutting down as well as when switching power modes of the
system it is important to limit the current load steps. A typical cause for such load steps
is changing the CPU frequency fCPU. Load steps exceeding the below defined values
may cause a power on reset triggered by the supply monitor.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
2) Maximum threshold for reset deassertion.
3) The VDDP monitoring has a typical hysteresis of VPORHYS =180mV.
4) If tPR is not met, low spikes on PORST may be se en during start up (e.g. reset pulses ge nerated by th e supply
monitoring due to a sl ow ramping VDDP).
as pr ogram med
V
POR
V
PV
V
DDP
V
DDC
Pads
PORST
V
DDPPA
Undefined H i gh-im ped ance or pul l -device active
3.3 V
1.3 V
t
SSW
t
VCR
t
PR
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 80 V1.1, 2018-09
Positive Load Step Examples
System assumptions:
fCPU = fSYS, target frequen cy fCPU = 1 44 MHz, main PLL fVCO = 288 MHz, stepping done
by K2 divider, tPLSS between individual steps:
24 MHz - 48 MHz - 72 MHz - 96 MHz - 144 MHz (K2 steps 12 - 6 - 4 - 3 - 2)
24 MHz - 48 MHz - 96 MHz - 144 MHz (K2 steps 12 - 6 - 3 - 2)
24 MHz - 72 MHz - 144 MHz (K2 steps 12 - 4 - 2)
Table 38 Power Seque ncing Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Positive Load Step Current
Δ
IPLS SR - −50 mA Load increase
on VDDP
Δ
t ≤ 10 ns
Negative Load Step
Current
Δ
INLS SR - −150 mA Load decrease
on VDDP
Δ
t ≤ 10 ns
VDDC Voltage Over-
/ Undershoot from Load
Step
Δ
VLS CC - −±100 mV For maximum
positive or
negative load
step
Positive Load Step Settling
Time tPLSS SR 50 −-μs
Negative Load Step
Settling Time tNLSS SR 100 −-μs
External Buffer Capacitor
on VDDC
CEXT SR - 10 - μF In addition
C= 100 nF
capacitor on
each VDDC pin
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 81 V1.1, 2018-09
3.3.4 Phase Locked Loop (PLL) Characteristics
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Main and USB PLL
Table 39 PLL Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Accumulated Jitter DP CC −−±5 ns accumulated
over 300 cycles
fSYS =144MHz
Duty Cycle1)
1) 50% for even K2 divider values, 50±(10/K2) for odd K2 divider values.
DDC CC 46 50 54 % Low pulse to
total period,
assuming an
ideal input clock
source
PLL base frequency fPLLBASE
CC 30 −140 MHz
VCO input frequency fREF CC 4 −16 MHz
VCO frequency range fVCO CC 260 −520 MHz
PLL lock-in time tL CC −−400 μs
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 82 V1.1, 2018-09
3.3.5 Internal Clock Source Characteristics
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Fast Internal Clock Source
Table 40 Fast Internal Clock Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Nominal frequency fOFINC
CC −36.5 −MHz not calibrated
−24 −MHz calibrated
Accuracy
Δ
fOFI
CC -0.5 −0.5 % automatic
calibration1)2)
1) Error in addition to the accuracy of the reference clock.
2) Automatic calibration compensates variations of the temperature and in the VDDP supply voltage.
-15 −15 % factory
calibration,
VDDP =3.3V
-25 −25 % no calibration,
VDDP =3.3V
-7 −7 % Variation over
voltage range3)
3.13 V ≤VDDP ≤
3.63 V
3) Deviations from the nominal VDDP voltage induce an additional error to the uncalibrated and/or factory
calibrated oscillator frequency.
Start-up time tOFIS CC −50 −μs
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 83 V1.1, 2018-09
Slow Internal Clock Source
Table 41 Slow I nternal Clock Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Nominal frequency fOSI CC −32.768 −kHz
Accuracy
Δ
fOSI
CC -4 −4%VBAT = const.
0°C≤TA≤
85 °C
-5 −5%
VBAT = const.
TA<0°C or
TA>85 °C
-5 −5%2.4V≤VBAT,
TA=25°C
-10 −10 % 1.95 V ≤
VBAT <2.4V,
TA=25°C
Start-up time tOSIS CC −50 −μs
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 84 V1.1, 2018-09
3.3.6 JTAG Interface Timing
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating conditions ap ply.
Table 42 JTAG Interface Timing Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TCK clock period t1SR 25 – – ns
TCK high time t2SR 10 – – ns
TCK low time t3SR 10 – – ns
TCK clock rise time t4SR––4ns
TCK clock fall time t5SR––4ns
TDI/TMS setup
to TCK rising edge t6SR6––ns
TDI/TMS hold
after TCK rising edge t7SR6––ns
TDO valid after TCK falling
edge1) (propagation delay)
1) The falling edge on TCK is used to generate the TDO timing.
t8CC––13nsC
L=50pF
3––nsC
L=20pF
TDO hold after TCK falling
edge1) t18 CC2––ns
TDO high imped. to valid
from TCK falling edge1)2)
2) The setup time for TDO is given implicitly by the TCK cycle time.
t9CC––14nsC
L=50pF
TDO valid to high imped.
from TCK falling edge1) t10 CC – – 13.5 ns CL=50pF
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 85 V1.1, 2018-09
Figure 27 Test Clock Timing (TCK)
Figure 28 JTAG Timing
JTAG_TCK.vsd
0.9
VDDP
0.5
VDDP
TCK
t
1
t
2
0.1
VDDP
t
3
t
5
t
4
JTAG_IO.vsd
t
6
t
7
t
6
t
7
t
9
t
8
t
10
TCK
TMS
TDI
TDO t
18
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 86 V1.1, 2018-09
3.3.7 Serial Wire Debug Port (SW-DP) Timing
The following parameters are applicable for communication through the SW-DP
interface.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating conditions ap ply.
Figure 29 SWD Timing
Table 43 SWD Interfa ce Timing Parameters (Operating Conditions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
SWDCLK clock period tSC SR 25 – – ns CL=30pF
40 – – ns CL=50pF
SWDCLK high time t1 SR 10 – 500000 ns
SWDCLK low time t2 SR 10 – 500000 ns
SWDIO input setup
to SWDCLK rising edge t3 SR 6 – – ns
SWDIO input hold
after SWDCLK rising edge t4 SR 6 – – ns
SWDIO output valid time
after SWDCLK rising edge t5 CC – – 17 ns CL=50pF
– – 13 ns CL=30pF
SWDIO output hold time
from SWDCLK rising edge t6 CC 3 – – ns
SWDCLK
SWDIO
(Output)
t1t2
t6
t5
tSC
SWDIO
(Input)
t3t4
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 87 V1.1, 2018-09
3.3.8 Embedded Trace Macro Cell (ETM) Timing
The data timing refers to the active clock edge. The XMC4[78]00 ETM uses the half-rate
clocking mode. In this mode both, the rising and falling clock edges are active clock
edges.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating conditions apply, with CL
≤
15 pF.
Figure 30 ETM Clock Timing
Figure 31 ETM Data Timing
Table 44 ETM Interface Timing Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TRACECLK period t1CC 13.8 – – ns –
TRACECLK high time t2CC 2 – – ns –
TRACECLK low time t3CC 2 – – ns –
TRACECLK and
TRACEDATA rise time t4CC – – 3 ns –
TRACECLK and
TRACEDATA fall time t5CC – – 3 ns –
TRACEDATA output valid
time t6CC -2 – 3 ns –
TRACECLK
t1
t2t3t4
t5
TRACECLK
TRACEDATA
t6t6
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 88 V1.1, 2018-09
3.3.9 Peripheral Timing
3.3.9.1 Delta-Sigma Demodulator Digital Interface Timing
The following parameters are applicable for the digital interface of the Delta-Sigma
Demodulator (DSD).
The data timing is relative to the active clock edge. Depending on the operation mode of
the connected modulator that can be the rising and falling clock edge.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 45 DSD Interface Timing Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
MCLK period in master
mode t1 CC 33.3 – – ns t1≥4xtPERIPH1)
1) tPERIPH =1/fPERIPH
MCLK high time in master
mode t2 CC 9 – – ns t2>tPERIPH1)
MCLK low time in master
mode t3 CC 9 – – ns t3>tPERIPH1)
MCLK period in slave
mode t1 SR 33.3 – – ns t1≥4xtPERIPH1)
MCLK high time in slave
mode t2 SR tPERIPH ––ns
1)
MCLK low time in slave
mode t3 SR tPERIPH ––ns
1)
DIN input setup time to the
active clock edge t4 SR tPERIPH
+4 ––ns
1)
DIN input hold time from
the active clock edge t5 SR tPERIPH
+3 ––ns
1)
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 89 V1.1, 2018-09
Figure 32 DSD Data Timing
3.3.9.2 Synchronous Serial Interface (USIC SSC) Timing
The following parameters are applicable for a USIC channel operated in SSC mode.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 46 USIC SSC Master Mode Timing
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
SCLKOUT master clock
period tCLK CC 33.3 −− ns
Slave select output SELO
active to first SCLKOUT
transmit edg e
t1 CC tPB -
6.51)
1) tPB = 1 / fPB
−− ns
Slave select output SELO
inactive afte r la st
SCLKOUT receive edge
t2 CC tPB -
8.51) −− ns
Data output DOUT[3:0]
valid time t3 CC -6 −8ns
Receive data input
DX0/DX[5:3] setup time to
SCLKOUT receive edge
t4 SR 23 −− ns
Data input DX0/DX[5:3]
hold time from SCLKOU T
receive edg e
t5 SR 1 −− ns
MCLK
DIN
t2t3
t5t4
t1
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 90 V1.1, 2018-09
Table 47 USIC SSC Slave Mode Timing
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
DX1 slave clock period tCLK SR 66.6 −− ns
Select input DX2 setup to
first clock input DX1 transmit
edge1)
1) This input timing is valid for asynchronous input signal handling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
t10 SR 3 −− ns
Select input DX2 hold after
last clock input DX1 receive
edge1)
t11 SR 4 −− ns
Receive data input
DX0/DX[5:3] setup time to
shift clock receive edge1)
t12 SR 6 −− ns
Data input DX0/DX[5:3] hold
time from clock input DX1
receive edg e1)
t13 SR 4 −− ns
Data output DOUT[3:0] valid
time t14 CC 0 −24 ns
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 91 V1.1, 2018-09
Figure 33 USIC - SSC Master/Slave Mode Timing
Note: This timing diagram shows a standard configuration, for which the slave select
signal is low-active, and the serial clock signal is not shifted and not inverted.
t
2
t
1
USIC_SSC_TMGX.VSD
Clock O utput
SCLKOUT
Data Output
DOUT[3:0]
t
3
t
3
t
5
Data
valid
t
4
First Transmit
Edge
Data Input
DX0/DX[5:3]
Sel ect Ou tput
SELOx
Active
Master Mode Ti m ing
S l ave Mode Tim i ng
t
11
t
10
Clock I nput
DX1
Data Output
DOUT[3:0]
t
14
t
14
Data
valid
Data Input
DX0/DX[5:3]
Select Input
DX2
Active
t
13
t
12
Transmit Edge: with this clock edge, transmit data is shifted to transmit data output.
Receive Edge: with this clock edge, rece ive data at receive data i npu t is latched.
Receive
Edge Last Receive
Edge
InactiveInactive
Transmit
Edge
InactiveInactive
Firs t Transm it
Edge Receive
Edge Transm it
Edge Last Receive
Edge
t
5
Data
valid
t
4
Data
valid
t
12
t
13
Drawn for BRGH.SCLKCFG = 00B. Also valid for for SCLKCFG = 01B with inverted SCLKOUT s ignal.
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 92 V1.1, 2018-09
3.3.9.3 Inter-IC (IIC) Interface Timing
The following parameters are applicable for a USIC channel operated in IIC mode.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 48 USIC IIC Standard Mode Timing1)
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open -drain mode. The high level on th ese lines must be held by an external pul l-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Fall time of both SDA and
SCL t1
CC/SR --300ns
Rise time of both SDA and
SCL t2
CC/SR - - 1000 ns
Data hold time t3
CC/SR 0- - µs
Data set-up time t4
CC/SR 250 - - ns
LOW period of SCL clock t5
CC/SR 4.7 - - µs
HIGH period of SCL clock t6
CC/SR 4.0 - - µs
Hold time for (repeated)
START condition t7
CC/SR 4.0 - - µs
Set-up time for repeated
START condition t8
CC/SR 4.7 - - µs
Set-up time for STOP
condition t9
CC/SR 4.0 - - µs
Bus free time between a
STOP and START
condition
t10
CC/SR 4.7 - - µs
Capacitive load for each
bus line Cb SR - - 400 pF
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 93 V1.1, 2018-09
Table 49 USIC IIC Fast Mode Timing1)
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open -drain mode. The high level on th ese lines must be held by an external pul l-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Fall time of both SDA and
SCL t1
CC/SR 20 +
0.1*Cb
2)
2) Cb refers to the total capacitance of one bus line in pF.
- 300 ns
Rise time of both SDA and
SCL t2
CC/SR 20 +
0.1*Cb
2)
- 300 ns
Data hold time t3
CC/SR 0- - µs
Data set-up time t4
CC/SR 100 - - ns
LOW period of SCL clock t5
CC/SR 1.3 - - µs
HIGH period of SCL clock t6
CC/SR 0.6 - - µs
Hold time for (repeated)
START condition t7
CC/SR 0.6 - - µs
Set-up time for repeated
START condition t8
CC/SR 0.6 - - µs
Set-up time for STOP
condition t9
CC/SR 0.6 - - µs
Bus free time between a
STOP and START
condition
t10
CC/SR 1.3 - - µs
Capacitive load for each
bus line Cb SR - - 400 pF
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 94 V1.1, 2018-09
Figure 34 USIC IIC Stand and Fast Mode Timing
3.3.9.4 Inter-IC Sound (IIS) Interface Timing
The following parameters are applicable for a USIC channel operated in IIS mode.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 50 USIC IIS Master Tran sm itter Timing
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Clock period t1 CC 33.3 −−ns
Clock high time t2 CC 0.35 x
t1min
−−ns
Clock low time t3 CC 0.35 x
t1min
−−ns
Hold time t4 CC 0 −−ns
Clock rise time t5 CC −−0.15 x
t1min
ns
SCL
SDA
SCL
SDA
t
1
t
2
t
1
t
2
t
10
t
9
t
7
t
8
t
7
t
3
t
4
t
5
t
6
PSSr
S
70%
30%
9
th
clock
9
th
clock
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 95 V1.1, 2018-09
Figure 35 USIC IIS Mast er Tr an sm itter Timing
Figure 36 USIC IIS Slave Receiver Timing
Table 51 USIC IIS Slave Receiver Timing
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Clock period t6 SR 66.6 −−ns
Clock high time t7 SR 0.35 x
t6min
−−ns
Clock low time t8 SR 0.35 x
t6min
−−ns
Set-up time t9 SR 0.2 x
t6min
−−ns
Hold time t10 SR 0 −−ns
SCK
WA/
DOUT
t
1
t
5
t
3
t
2
t
4
SCK
WA/
DIN
t
6
t
10
t
8
t
7
t
9
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 96 V1.1, 2018-09
3.3.9.5 SDMMC Interface Timing
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating Conditions apply, tota l external capacitive load CL = 40 pF.
AC Timing Specifications (Full-Speed Mode)
Table 52 SDMMC Timing for Full-Speed Mode
Parameter Symbol Values Unit Note/ Test
Condition
Min. Max.
Clock frequency in full speed
transfer mode (1/tpp)fpp CC 0 24 MHz
Clock cycle in full speed
transfer mode tpp CC 40 −ns
Clock low time tWL CC 10 −ns
Clock high time tWH CC 10 −ns
Clock rise time tTLH CC −10 ns
Clock fall time tTHL CC −10 ns
Inputs setup to clock rising
edge tISU_F SR 2 −ns
Inputs hold after clock rising
edge tIH_F SR 2 −ns
Outputs valid time in full speed
mode tODLY_F CC −10 ns
Outputs hold time in full speed
mode tOH_F CC 0 −ns
Table 53 SD Card Bus Timing for Full-Speed Mode1)
Parameter Symbol Values Unit Note/ Test
Condition
Min. Max.
SD card input setup time tISU 5−ns
SD card input hold time tIH 5−ns
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 97 V1.1, 2018-09
Full-Speed Output Path (Write)
Figure 37 Full-Speed Output Path
Full-Speed Write Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed skew range between the
SD_CLK and SD_DAT/CMD signals on the PCB.
No clock delay:
(1)
SD card output valid time tODLY −14 ns
SD card output hold time tOH 0−ns
1) Reference card timing values for calculation examples. Not subject to production test and not characterized.
Table 53 SD Card Bus Timing for Full-Speed Mode1) (cont’d)
Parameter Symbol Values Unit Note/ Test
Condition
Min. Max.
SD Clock at
Host Pin
SD Clock at
Card P in
O utput at
Host Pins
O utput at
Card Pins
tpp
(Clock Cycle)
Driving
Edge
Sampling
Edge
tWL
tCLK_DELAY
Output Valid Time:
tODLY_H
O utput Hold Time:
tOH_H
tDATA_ DELAY
+ tTAP_DELAY tISU
tIH
tODLY_F tDATA_DELAY tTAP_DELAY tISU
+++tWL
<
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 98 V1.1, 2018-09
With clock delay:
(2)
(3)
The data can be delayed versus clock up to 5 ns in ideal case of tWL= 20 ns.
Full-Speed Write Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed skew range between the
SD_CLK and SD_DAT/CMD signals on the PCB.
(4)
The clock can be delayed versus data up to 18.2 ns (external delay line) in ideal case of
tWL= 20 ns, with maximum tTAP_DELAY = 3.2 ns programmed.
tODLY_F tDATA_DELAY tTAP_DELAY tISU
+++tWL tCLK_DELAY
+<
tDATA_DELAY tTAP_DELAY tWL
++tPP tCLK_DELAY tISU
–tODLY_F
–+<
tDATA_DELAY tTAP_DELAY 20++40tCLK_DELAY 5–10–+<
tDATA_DELAY 5tCLK_DELAY tTAP_DELAY
–+<
tCLK_DELAY tWL tOH_F tDATA_DELAY tTAP_DELAY tIH
–++ +<
tCLK_DELAY 20 tDATA_DELAY tTAP_DELAY 5–++<
tDATA_DELAY 15 tCLK_DELAY tTAP_DELAY
++<
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 99 V1.1, 2018-09
Full-Speed Input Path (Read)
Figure 38 Full-Speed Input Path
Full-Speed Read Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed combined propagation delay
range of the SD_CLK and SD_DAT/CMD signals on the PCB.
(5)
The data + clock delay can be up to 4 ns for a 40 ns clock cycle.
SD Clock at
Host Pin
SD Clock at
Card P in
Output at
Host Pins
Output at
Card Pins
t
pp
(Clock Cycle)
Driving
Edge
Sampling
Edge
t
CLK_DELAY
t
ODLY
t
OH
t
DATA_DELAY
+ t
TAP_DELAY
t
IH_H
t
ISU_H
tCLK_DELAY tDATA_DELAY tTAP_DELAY tODLY tISU_F
+ + + + 0,5 t×pp
<
tCLK_DELAY tDATA_DELAY
+ 0,5 t×pp tODLY tISU_F
–– tTAP_DELAY
–<
tCLK_DELAY tDATA_DELAY
+ 20142–– tTAP_DELAY
–<
tCLK_DELAY tDATA_DELAY
+4tTAP_DELAY
–<
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 100 V1.1, 2018-09
Full-Speed Read Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed combined propagation delay
range of the SD_CLK and SD_DAT/CMD signals on the PCB.
(6)
The data + clock delay must be greater than 2 ns if tTAP_DELAY is not used.
If the tTAP_DELAY is programmed to at least 2 ns, the data + clock delay must be gr eater
than 0 ns (or less). This is always fulfilled.
AC Timing Specifications (High-Speed Mode)
Table 54 SDMMC Timing for High-Speed Mode
Parameter Symbol Values Unit Note/ Test
Condition
Min. Max.
Clock frequency in high speed
transfer mode (1/tpp)fpp CC 0 48 MHz
Clock cycle in high speed
transfer mode tpp CC 20 −ns
Clock low time tWL CC 7 −ns
Clock high time tWH CC 7 −ns
Clock rise time tTLH CC −3ns
Clock fall time tTHL CC −3ns
Inputs setup to clock rising
edge tISU_H SR 2 −ns
Inputs hold after clock rising
edge tIH_H SR 2 −ns
Outputs valid time in high
speed mode tODLY_H CC −14 ns
Outputs hold time in high
speed mode tOH_H CC 2 −ns
tCLK_DELAY tOH tDATA_DELAY tTAP_DELAY tIH_F
>++ +
tCLK_DELAY tDATA_DELAY tIH_F tOH
–tTAP_DELAY
–>+
tCLK_DELAY tDATA_DELAY 2tTAP_DELAY
–>+
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 101 V1.1, 2018-09
High-Speed Output Path (Write)
Figure 39 High-Speed Output Path
High-Speed Write Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed skew range between the
SD_CLK and SD_DAT/CMD signals on the PCB.
Table 55 SD Card Bus Timi ng for High-Speed Mode1)
1) Reference card timing values for calculation examples. Not subject to production test and not characterized.
Parameter Symbol Values Unit Note/ Test
Condition
Min. Max.
SD card input setup time tISU 6−ns
SD card input hold time tIH 2−ns
SD card output valid time tODLY −14 ns
SD card output hold time tOH 2.5 −ns
SD Clock at
Host Pin
SD Clock at
Car d P in
Output at
Hos t Pi ns
Output at
Car d P ins
tpp
(Clock Cycle)
Driving
Edge
Sampling
Edge
tWL
tCLK_DELAY
Output Valid Time:
tODLY_H
O utput Hold Time:
tOH_H
tDATA_DELAY
+ tTAP_DELAY tISU
tIH
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 102 V1.1, 2018-09
No clock delay:
(7)
With clock delay:
(8)
(9)
The data delay is less than the clock delay by at least 10 ns in the ideal case where tWL=
10 ns.
High-Speed Write Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed skew range between the
SD_CLK and SD_DAT/CMD signals on the PCB.
(10)
The clock can be delayed versus data up to 13.2 ns (external delay line) in ideal case of
tWL= 10 ns, with maximum tTAP_DELAY = 3.2 ns programmed.
tODLY_H tDATA_DELAY tTAP_DELAY tISU
+++tWL
<
tODLY_H tDATA_DELAY tTAP_DELAY tISU
+++tWL tCLK_DELAY
+<
tDATA_DELAY tTAP_DELAY tCLK_DELAY
–+ tWL tISU
–tODLY_H
–<
tDATA_DELAY tCLK_DELAY
–tWL tISU
–tODLY_H
–tTAP_DELAY
–<
tDATA_DELAY tCLK_DELAY
–106–14–tTAP_DELAY
–<
tDATA_DELAY tCLK_DELAY
–10–tTAP_DELAY
–<
tCLK_DELAY tWL tOH_H tDATA_DELAY tTAP_DELAY tIH
–++ +<
tCLK_DELAY tDATA_DELAY
–tWL tOH_H tTAP_DELAY tIH
–++<
tCLK_DELAY tDATA_DELAY
–102tTAP_DELAY 2–++<
tCLK_DELAY tDATA_DELAY
–10tTAP_DELAY
+<
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 103 V1.1, 2018-09
High-Speed Input Path (Read)
Figure 40 High-Speed Input Path
High-Speed Read Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed combined propagation delay
range of the SD_CLK and SD_DAT/CMD signals on the PCB.
(11)
The data + clock delay can be up to 4 ns for a 20 ns clock cycle.
SD Cloc k at
Host Pin
SD Cloc k at
Car d P in
Output at
Host Pins
Output at
Car d Pins
t
pp
(Clo ck Cycle)
Driving
Edge
Sampling
Edge
t
CLK_DELAY
t
ODLY
t
OH
t
DATA_DELAY
+ t
TAP_DELAY
t
IH_H
t
ISU_H
tCLK_DELAY tDATA_DELAY tTAP_DELAY tODLY tISU_H
++++tpp
<
tCLK_DELAY tDATA_DELAY
+tpp tODLY tISU_H
–– tTAP_DELAY
–<
tCLK_DELAY tDATA_DELAY
+ 20142–– tTAP_DELAY
–<
tCLK_DELAY tDATA_DELAY
+4tTAP_DELAY
–<
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 104 V1.1, 2018-09
High-Speed Read Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed combined propagation delay
range of the SD_CLK and SD_DAT/CMD signals on the PCB.
(12)
The data + clock delay must be greater than -0.5 ns for a 20 ns clock cycle. This is always
fulfilled.
3.3.10 EBU Timing
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating Conditions apply, with Class A2 pins and CL = 16 pF.
3.3.10.1 EBU Asynchronous Timing
Note: For each timing, the accumulated PLL jitter must be added separately.
Table 56 Common Timing Parameters for all Asynchronous Timings
Parameter Sym
bol Limit Values Unit Edge
Setting
Min. Max.
Pulse width deviation from the ideal
programmed width due to the A2 pad
asymmetry, strong driver mode,
rise delay - fall delay. CL = 16 pF.
CC ta-1 1.5 ns sharp
-2 1 medium
AD(24:16) output delay to ADV rising
edge, multiplexed
read / write
CC t13 -5.5 2 –
AD(24:16) output delay CC t14 -5.5 2 –
tCLK_DELAY tOH tDATA_DELAY tTAP_DELAY tIH_H
>++ +
tCLK_DELAY tDATA_DELAY tIH_H tOH
–tTAP_DELAY
–>+
tCLK_DELAY tDATA_DELAY 2 2,5– tTAP_DELAY
–>+
tCLK_DELAY tDATA_DELAY 0,5– tTAP_DELAY
–>+
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 105 V1.1, 2018-09
Read Timing
Table 57 Asynchronous Read Timing, Multiplexed and Demultiplexed
Parameter Symbol Limit Values Unit
Min. Max.
A(24:16) output delay to RD rising edge,
deviation from the
ideal programmed
value.
CC t0-2.5 2.5 ns
A(24:16) output delay CC t1-2.5 2.5
CS rising edge CC t2-2 2.5
ADV rising edge CC t3-1.5 4.5
BC rising edge CC t4-2.5 2.5
WAIT input setup SR t512 –
WAIT input hold SR t60–
Data input setup SR t712 –
Data input hold SR t80–
RD / WR output delay C C t9-2.5 1.5
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 106 V1.1, 2018-09
Multiplexed Read Timing
Figure 4 1 Multiplexed Read Access
t8
Next
Addr.
EBU_MuxRD_Async.vsd
AD[31:0]2) Data In
A[max:16]1)
t2
ta
ta
ta
tat4
t5t6
ta
t13
t14 t7
t9
EBU
STATE Address
Phase Address Hold
Phase (opt.) Command
Phase Recovery
Phase (opt.) New Addr.
Phase
1...15 0...15
Duration Limits in
EBU_CLK Cycles 1...31 0...15 1...15
t1
t0
pv + pv +
pv +
pv + pv + t3
pv +
pv + pv +
pv +
pv + pv +
pv +
pv = programmed v alu e,
TEBU_CLK * sum (corresponding bitfield values)
Command
Delay Phase
0...7
1) For 16-bit MUX and Twin 16-bit MUX only
2)* 16-bit MUX: - Address A[15:0], Data D[15:0] on pins AD[15:0] only
* Twin 16-Bit MUX: - Address A[15:0] on pins AD[15:0] and AD[31:16] in parallel
- Data D[31:0] on pins AD[31:0]
* 32-bit MUX: - Address A[24:0] on pins AD[24:0]
- Data D[31:0] on pins AD[31:0]
Address Out
Valid Address
RD/WR
BC[3:0]
WAIT
RD
ADV
CS[3:0]
CSCOMB
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 107 V1.1, 2018-09
Demultiplexed Read Timing
Figure 42 Demultiplexed Read Access
t8
Next
Addr.
EBU_DeMuxRD_Async.vsd
D[15:0]2) Data In
A[max:0]1)
t2
ta
ta
ta
tat4
t5t6
ta
t7
t9
EBU
STATE Address
Phase Address Hold
Phase (opt.) Command
Phase Recovery
Phase (opt.) New Addr.
Phase
1...15 0...15
Duration Limits in
EBU_CLK Cycles 1...31 0...15 1...15
t1
t0
pv + pv +
pv +
pv + pv + t3
pv +
pv + pv +
pv +
pv +
pv = programmed value,
TEBU_CLK * sum (corresp on di n g bi t f i el d va lu e s)
1) Address A[max:16] on pins A[max:16], Address A[15:0] on pins AD[31:16]
2) Data D[15:0] on pins AD[15:0]
Valid Address
RD/WR
BC[3:0]
WAIT
RD
ADV
CS[3:0]
CSCOMB
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 108 V1.1, 2018-09
Write Timing
Table 58 Asynchronous Write Timi ng, Multiplexed and De mu ltiplexed
Parameter Symbol Limit Values Unit
Min. Max.
A(24:0) output delay to RD/WR rising
edge, deviation from
the ideal programmed
value.
CC t30 -2.5 2.5 ns
A(24:0) output delay CC t31 -2.5 2.5
CS rising edge CC t32 -2 2
ADV rising edge CC t33 -2 4.5
BC rising edge CC t34 -2.5 2
WAIT input setup SR t35 12 –
WAIT input hold SR t36 0–
Data output delay CC t37 -5.5 2
Data output delay CC t38 -5.5 2
RD / WR output delay CC t39 -2.5 1.5
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 109 V1.1, 2018-09
Multiplexed Write Timing
Figure 4 3 Multiplexed Write Access
t34
Next
Addr.
EBU_MuxWR_Async.vsd
AD[31:0]2) Data Out
A[max:16]1)
ta
ta
ta
ta
t35 t36
ta
t13
t14 pv + t37
EBU
STATE Address
Phase Address Hold
Phase (opt.) Command
Phase Recovery
Phase (opt.) New Addr.
Phase
1...15 0...15
Duration Limits in
EBU_CLK Cycles 0...15 1...15
t31
t30
pv + pv +
pv +
pv + pv +t33
pv +
pv + pv +
pv + pv +
pv = programmed v alu e,
TEBU_CLK * sum (corresponding bitfield values)
Data Hold
Phase
1...31
1) For 16-bit MUX and Twin 16-bit MUX only
2)* 16-bit MUX: - Address A[15:0], Data D[15:0] on pins AD[15:0] only
* Twin 16-Bit MUX: - Address A[15:0] on pins AD[15:0] and AD[31:16] in parallel
- Data D[31:0] on pins AD[31:0]
* 32-bit MUX: - Address A[24:0] on pins AD[24:0]
- Data D[31:0] on pins AD[31:0]
t32
pv +
t38
pv +
Address Out
0...15
RD/WR
BC[3:0]
WAIT
RD
ADV
CS[3:0]
CSCOMB
Valid Address
t39
pv +
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 110 V1.1, 2018-09
Demultiplexed Write Timing
Figure 44 Demultiplexed Write Access
t34
Next
Addr.
EBU_DeMuxWR_Async.vsd
D[15:0]2) Data Out
A[max:0]1)
ta
ta
ta
ta
t35 t36
ta
pv + t37
t39
EBU
STATE Address
Phase Address Hold
Phase (opt.) Command
Phase Recovery
Phase (opt.) New Addr.
Phase
1...15 0...15
Duration Limits in
EBU_CLK Cycles 0...15 1...15
t31
t30
pv + pv +
pv +
pv + pv + t33
pv +
pv + pv +
pv +
pv = programmed value,
TEBU_CLK * sum (corresp ond i ng bi t f i el d v al u es)
Data Hold
Phase
1...31
t32
pv +
t38
pv +
0...15
1) Address A[m ax:16 ] on pin s A[max:16] , Addres s A[15 :0] on pin s AD[31: 1 6]
2) Data D[15:0] on pins AD[15:0]
RD/WR
BC[3:0]
WAIT
RD
ADV
CS[3:0]
CSCOMB
Valid Address
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 111 V1.1, 2018-09
3.3.10.2 EBU Burst Mode Access Timing
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating Conditions apply, with Class A2 pins and CL = 16 pF.
Table 59 EBU Burst Mode Read / Write Access Timing Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Output delay from BFCLKO
rising edge t10 CC -2 – 2 ns –
RD and RD/WR
active/inactive after
BFCLKO active edge1)
1) An active edge can be a rising or falling edge, depending on the settings of bits BFCON.EBSE / ECSE and
the clock divider ratio.
Negative minimum values for these parameters mean th at the last data read during a burst may be corrupted.
However, with clock feedback enabled, this value is an oversampling not required for the internal bus
transaction, and will be discarded.
t12 CC -2 – 2 ns –
CSx output delay from
BFCLKO active edge1) t21 CC -2.5 – 1.5 ns –
ADV active/inactive after
BFCLKO active edge2)
2) This parameter is valid for BUSCONx.EBSE = 1 and BUSAPx.EXTCLK = 00B.
For BUSCONx.EBSE = 1 and other values of BUSAPx.EXTCL K, ADV and BAA will be delayed by 1/2 of the
internal bus clock period TCPU = 1 / fCPU.
For BUSCONx. EBSE = 0 and BUSAPx.EXTCLK = 11B, add 2 internal bus clock periods.
For BUSCONx. EBSE = 0 and other values of BUSAPx.EXTCLK, add 1 internal bus clock period.
t22 CC -2 – 2 ns –
BAA active/inactive after
BFCLKO active edge2) t22a CC -2.5 – 1.5 ns –
Data setup to BFCLKI rising
edge3) t23 SR 3 – – ns –
Data hold from BFCLKI
rising edge3) t24 SR 0 – – ns –
WAIT setup (low or high) to
BFCLKI rising edge3) t25 SR 3 – – ns –
WAIT hold (low or high) from
BFCLKI rising edge3) t26 SR 0 – – ns –
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 112 V1.1, 2018-09
Figure 45 EBU Burst Mode Read / Write Access Timing
3) If the clock feedback is not enabled, the inp ut signals are latched using the internal clock in the same way as
for asynchronous access. Thus, t5, t6, t7 and t8 from the asynchronous timing app ly.
EBU_BurstRDWR.vsd
t
10
BFCLKI
BFCLKO1)
A[max:0]
t
22
Address
Phase(s) Comma n d
Phase(s) Burst
Phase(s) Recovery
Phase(s) Next Addr.
Phase(s)
t
22
t
21
Next
Addr.
D[31:0]
(32-Bit)
t
12
t
12
t
24
D[15:0]
(16-Bit)
t
22a
Burst
Phase(s)
t
22a
t
10
t
22
t
23
t
24
t
23
t
26
t
25
Output del ays are al w ays r eferenced to BC LKO . The r eference c l ock for i np ut
characteristics depends on bit EBU _BFCON.FDBKEN.
EBU_BFCON.FDBKEN = 0: BFCLKO is the input reference clock.
EBU_BFCON.FDBKEN = 1: BFCLKI is the input reference clock (EBU clock
fe edback en abl e d ).
1)
Burst Start Address
t
21
t
21
Data (Addr+0) Data ( Addr+4)
Data (Addr+2)Data (Addr+0)
ADV
RD
RD/WR
CS[3:0]
CSCOMB
BAA
WAIT
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 113 V1.1, 2018-09
3.3.10.3 EBU Arbitration Signal Timing
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating Conditions apply.
Figure 46 EBU Arbitration Signal Timing
Table 60 EBU Arbitration Signal Timing Parameters
Parameter Symbol Values Unit Note /
Test Cond
ition
Min. Typ. Max.
Output delay from BFCLKO
rising edge t1CC – – 16 ns CL = 50 pF
Data setup to BFCLKO
falling edge t2SR 11 – – ns –
Data hold from BFCLKO
falling edge t3SR 2 – – ns –
t
2
t
2
EBU_Arb.vsd
BFCLKO
t
3
t
1
t
1
t
1
t
1
HLDA Out put
BREQ Output
BFCLKO
t
3
H OLD Input
HLDA Input
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 114 V1.1, 2018-09
3.3.10.4 EBU SDRAM Access Timing
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating Conditions apply, with Class A2 pins and CL = 16 pF.
Note: With EBU_CLC.SYNC = 1B frequency must be limited to fCPU = 120 MHz.
Figure 47 EBU SDRAM Access CLKOUT Timing
Table 61 EBU SDRAM Access SDCLKO Signal Timing Parameters
Parameter Symbol Values Unit Note /
Test Con
dition
Min. Typ. Max.
SDCLKO period t1CC 12.5 – – ns –
SDCLKO high time t2SR 5.5 – – ns –
SDCLKO low time t3SR 3.75 – – ns –
SDCLKO rise time t4SR – – 3.0 ns –
SDCLKO fall time t5SR – – 3.0 ns –
EBU_SDCLKO.vsd
0.9
V
DDP
0.5
V
DDP
SDCLKO
t
1
t
2
0.1
V
DDP
t
3
t
5
t
4
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 115 V1.1, 2018-09
Table 62 EBU SDRAM Access Signal Timing Parameters
Parameter Symbol Limit Values Unit
Min. Max.
A(15:0) output valid from SDCLKO
low-to-high
transition
CC t6–9ns
A(15:0) output hold CC t73–
CS(3:0) low CC t8–9
CS(3:0) high CC t93–
RAS low CC t10 –9
RAS high SR t11 3–
CAS low SR t12 –9
CAS high CC t13 3–
RD/WR low CC t14 –9
RD/WR high CC t15 3–
BC(3:0) low CC t16 –9
BC(3:0) high CC t17 3–
D(15:0) output valid CC t18 –9
D(15:0) output hold CC t19 3–
CKE output valid1)
1) Not depicted in the read and write access timing figures below.
CC t22 –7
CKE output hold1) CC t23 2–
D(15:0) input hold SR t21 3–
D(15:0) input setup to SDCLKO low-to-high
transition SR t20 4–
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 116 V1.1, 2018-09
Figure 48 EBU SDRAM Read Access Timing
t
21
Row
EBU_SDRAM-RD.vsd
t
6
Column
t
7
t
12
t
13
t
16
t
17
t
20
Da ta ( 0 ) Data ( n -1)
D[15:0]
2)
A[15:0]
1)
RD/WR
BC[1:0]
CS[3:0]
CSCOMB
RAS
CAS
1)
Address A[15:0] on pin s AD[ 31:16]
2)
Data D[15:0] on pins AD[15:0]
SDCLKO
t
9
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 117 V1.1, 2018-09
Figure 49 EBU SDRAM Write Access Timing
Column
t
19
Row
EBU_SDRAM-WR.vsd
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
Data
(0) Data
(n-1)
D[15:0]
2)
A[15:0]
1)
RD/WR
BC[1:0]
CS[3:0]
CSCOMB
RAS
CAS
1)
Address A[15:0] on pin s AD[ 31:16]
2)
Data D[15:0] on pins AD[15:0]
SDCLKO
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 118 V1.1, 2018-09
3.3.11 USB Interface Characteristics
The Universal Serial Bus (USB) Interface is compliant to the USB Rev. 2.0 Specification
and the OTG Specification Rev. 1.3. High-Speed Mode is not sup ported.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Figure 50 USB Signal Timi ng
Table 63 USB Timing Parameters (operating conditions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Rise time tRCC 4 – 20 ns CL=50pF
Fall time tFCC 4 – 20 ns CL=50pF
Rise/Fall time matching tR/tFCC 90 – 111.11 % CL=50pF
Crossover voltage VCRS CC 1.3 – 2.0 V CL=50pF
USB_Rise-Fall-Times.vsd
10%
90%
D-
D+
t
R
t
F
10%
90%
V
CRS
V
SS
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 119 V1.1, 2018-09
3.3.12 Ethernet Interface (ETH) Characteristics
For proper operation of the Ethernet Interface it is required that fSYS ≥100 MHz.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
3.3.12.1 ETH Measurement Reference Points
Figure 51 ETH Measurement Reference Points
ETH_Testpoints.vsd
ETH Clock 1.4
V
1.4
V
2.0
V
0.8
V
2.0
V
0.8
V
t
R
t
F
ETH I/O
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 120 V1.1, 2018-09
3.3.12.2 ETH Management Signal Parameters (ETH_MDC, ETH_MDIO)
Figure 52 ETH Management Signal Timing
Table 64 ETH Management Signal Timing Parameters
Parameter Symbol Values Unit Note /
Test Conditi
on
Min. Typ. Max.
ETH_MDC period t1CC 400 – – ns CL=25pF
ETH_MDC high time t2CC 160 – – ns
ETH_MDC low time t3CC 160 – – ns
ETH_MDIO setup time (output ) t4CC 10 – – ns
ETH_MDIO hold time (output) t5CC 10 – – ns
ETH_MDIO data valid (input) t6SR 0 – 300 ns
ETH_Timing-Mgmt.vsd
ETH_MDC
ETH_MDIO
(output)
t
5
Valid Data
t
4
Valid Data
t
6
ETH_MDIO
(input)
ETH_MDC
ET H_MD IO s our ced by ST A:
ET H_MD IO s our ced by PH Y:
ETH_MDC
t
1
t
3
t
2
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 121 V1.1, 2018-09
3.3.12.3 ETH MII Parameters
In the following, the parameters of the MII (Media Independent Interface) are described.
Figure 53 ETH MII Signal Timing
Table 65 ETH MII Signa l T iming Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Clock period, 10 Mbps t7SR 400 – – ns CL=25pF
Clock high time, 10 Mbps t8SR 140 – 260 ns
Clock low time, 10 Mbps t9SR 140 – 260 ns
Clock period, 100 Mbps t7SR 40 – – ns
Clock high time, 10 0 Mbps t8SR 14 – 26 ns
Clock low time, 100 Mbps t9SR 14 – 26 ns
Input setup time t10 SR 10 – – ns
Input hold time t11 SR 10 – – ns
Output valid time t12 CC 0 – 25 ns
ETH_Timing-MII.vsd
ETH_MII_RX_CLK
ETH_MII _TXD[3:0]
ETH_MII_TXEN
ETH_MII_RXD[3:0]
ETH_MII_RX_DV
ETH_MII _RX_ER
ETH_MII_TX_CLK
t
11
Valid Data
t
10
Valid Data
t
12
(sour ced by ST A)
(sourced by PH Y )
t
7
t
9
t
8
ETH_MII_RX_CLK
ETH_MII_TX_CLK
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 122 V1.1, 2018-09
3.3.12.4 ETH RMII Parameters
In the following, the parameters of the RMII (Reduced Media Independent Interface) are
described.
Figure 54 ETH RMII Signal Timing
Table 66 ETH RMII Signal Timing Parameters
Parameter Symbol Values Unit Note /
Test Condit
ion
Min. Typ. Max.
ETH_RMII_REF_CL clock period t13 SR 20 – – ns CL=25pF;
50 ppm
ETH_RMII_REF_CL clock high time t14 SR 7 – 13 ns CL=25pF
ETH_RMII_REF_CL clock low time t15 SR 7 – 13 ns
ETH_RMII_RXD[1:0],
ETH_RMII_C RS se tu p ti me t16 SR 4 – – ns
ETH_RMII_RXD[1:0],
ETH_RMII_C RS h ol d time t17 SR 2 – – ns
ETH_RMII_TXD[1:0],
ETH_RMII_TXEN data valid t18 CC 4 – 15 ns
ETH_Timing-RMII.vsd
ETH_RMII_REF_CL
t17
Valid Data
t16
Valid Data
t18
t13
t15 t14
ETH_RMII_REF_CL
ETH_RMII_REF_CL
ETH_RMII _RXD[1:0]
ETH_RMII _CRS
ETH_RMII _TXD[1:0]
ETH_RMII _TXEN
(sourced by STA )
(sourced by PH Y )
Valid Data
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 123 V1.1, 2018-09
3.3.13 EtherCAT (ECAT) Characteristics
3.3.13.1 ECAT Measurement Referenc e Poi nt s
Figure 55 Measurement Reference Points
3.3.13.2 ETH Management Signal Parameters (MCLK, MDIO)
Table 67 ECAT Management Signal Timing Parameters
Parameter Symbol Values Unit Note /
Test Conditi
on
Min. Typ. Max.
ECAT_MCLK period tMCLKCC – 400 – ns IEEE802.3
requirement
(2.5 MHz)
CL=25pF
ECAT_MCLK high time tMCLK_h
CC 160 – – ns
ECAT_MCLK low time tMCLK_l
CC 160 – – ns
ECAT_MDIO setup time
(output) tD_setup
CC 10 – – ns
ECAT_MDIO hold time (output) tD_hold
CC 10 – – ns
ECAT_MDIO data valid (input) tD_valid
SR 0 – 300 ns
ECAT_Testpoints.vsd
ECAT Clock 1.4 V1.4 V
2.0 V
0.8 V2.0 V
0.8 V
tRtF
ECAT I/O
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 124 V1.1, 2018-09
Figure 56 ECAT Management Signal Timing
3.3.13.3 MII Timing TX Characteristics
Table 68 ETH MII TX Signal Timing Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
PHY_CLK25, TX_CLK
period tTX_CLK
SR –40–ns
Delay between PHY clock
source PHY_CLK25 and
TX_CLK output of the PHY
tPHY_delay
SR – – – ns PHY dependent
ECAT_Timing-Mgmt.vsd
ECAT_MCLK
ECAT_MDIO
(output) Valid Data
tD_setup
Valid Data
tD_valid
ECAT_MDIO
(input)
ECAT_MCLK
ECAT_MDIO sourced by STA:
ECAT_MDIO sourced by PHY:
ECAT_MCLK
tMCLK
tMCLK_l tMCLK_h
tD_hold
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 125 V1.1, 2018-09
Note: ECAT0_CONPx.TX_SHIFT can be adjusted by displaying TX_CLK of a PHY and
TXEN/TXD[3:0] on an oscilloscope. TXEN/TXD[3:0] is allowed to change between
0 ns and 25 ns after a rising edge of TX_CLK (according to IEEE802.3 – check
your PHY’s documentation). Configure TX_SHIFT so that TXEN/TXD[3:0] change
near the middle of this range. It is sufficient to check just one of the TXEN/TXD[3:0]
signals, because they are nearly generat ed at the same time.
Figure 57 MII TX Characteristics
PHY setup requirement:
TXEN/TXD[3:0] with respect
to TX_CLK
tTX_setup
SR 15 – 0 ns PHY dependent
IEEE802.3 limit
is 15 ns
PHY hold requirement:
TXEN/TXD[3:0] with respect
to TX_CLK
tTX_hold
CC 0 – 25 ns PHY dependent
IEEE802.3 limit
is 0 ns
Table 68 ETH MII TX Signal Timing Parameters (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
tPHY_delady
ECAT_MII_TXD[3:0]
ECAT_MII_TXEN Valid Data
ECAT_MII_TX_CLK
PHY_CLK25
tPHY_TX_Setup tPHY_TX_Hold
TX_Shift[1:0]=00
Valid Data
Valid Data
10ns
20ns
30ns
ECAT_MII_TXD[3:0]
ECAT_MII_TXEN
TX_Shift[1:0]=01
ECAT_MII_TXD[3:0]
ECAT_MII_TXEN
TX_Shift[1:0]=10
ECAT_MII_TXD[3:0]
ECAT_MII_TXEN
TX_Shift[1:0]=11 Valid Data
FAIL:Setup/HoldTimingviolated
tTX_CLK
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 126 V1.1, 2018-09
3.3.13.4 MII Timing RX Characterist ic s
Figure 5 8 MII RX characteristics
Table 69 ETH MII RX Si gnal Timing Parame ters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
RX_CLK perio d tRX_CLK
SR –40–nsC
L=25pF,
IEEE802.3
requirement
RX_DV/RX_DV/RXD[3:0]
valid before rising
edge of RX_CLK
tRX_setup
SR 10 – – ns
RX_DV/RX_DV/RXD[3:0]
valid after rising
edge of RX_CLK
tRX_hold
SR 10 – – ns
ECAT_MII_RX_CLK
tRX_hold
tRX_setup
Valid Data
ECAT_MII_RXD[3:0]
ECAT_MII_RX_DV
ECAT_MII_RX_ER
tRX_CLK
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
Data Sheet 127 V1.1, 2018-09
3.3.13.5 Sync/Latch Timings
Note: SYNC0/1 pulse length are initially loaded by EEPROM content ADR 0x0002. The
actual used value can be read back from Register DC_PULSE_LEN.
Figure 59 Sync/Latch Ti mings
Table 70 Sync/ Latch Timings
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
SYNC0/1 tDC_SYNC_
Jitter SR – – 11 +
m1)
1) additional delay form logic and pad, number is added after characterization
ns
LATCH0/1 tDC_LATCH
SR 12 +
n2)
2) additional shaping delay, number is add ed after characterization
–– ns
tDC_SYNC_Jiiter
SYNC0/1
LATCH0/1
tDC_LATCH tDC_LATCH
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Package and Reliability
Data Sheet 128 V1.1, 2018-09
4 Package and Reliability
The XMC4[78]00 is a member of the XMC4000 Family of microcontrollers. It is also
compatible to a certain extent with members of similar families or subfamilies.
Each package is optimized for the device it houses. Therefore, there may be slight
differences between packages of the same pin-count but for different device types. In
particular, the size of the Exposed Die Pad may vary.
If different device types are considered or planned for an application, it must be ensured
that the board layout fits all packages under consideration.
4.1 Package Parameters
Table 71 provides the thermal characteristics of the packages used in XMC4[78]00.
Note: For electrical reasons, it is required to connect the exposed pad to the board
ground VSS, independent of EMC and thermal requirements.
4.1.1 Thermal Considerations
When operating the XMC4[78]00 in a system, the total heat generated in the chip must
be dissipated to the ambient environment to prevent overheating and the resulting
thermal damage.
The maximum heat that can be dissipated depend s on the package and its integration
into the target board. The “Thermal resistance RΘJA” quantifies these parameters. The
power dissipation must be limited so that the average junction temperature does not
exceed 150 °C.
Table 71 Thermal Characteristics of the Packages
Parameter Symbol Limit Values Unit Package Types
Min. Max.
Exposed Die Pad
dimensions including U-
Groove
Ex × Ey
CC -7.0×7.0 mm PG-LQFP-144-24
-7.0×7.0 mm PG-LQFP-100-25
Exposed Die Pad
dimensions excluding U-
Groove
Ax × Ay
CC -6.2×6.2 mm PG-LQFP-144-24
-6.2×6.2 mm PG-LQFP-100-25
Thermal resistance
Junction-Ambient
TJ≤150 °C
RΘJA
CC - 27.0 K/W PG-LFBGA-196-2
- 19.5 K/W PG-LQFP-144-241)
1) Device mounted on a 4-layer JEDEC board (JESD 51-7) with thermal vias; exposed pad soldered.
- 22.5 K/W PG-LQFP-100-251)
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Package and Reliability
Data Sheet 129 V1.1, 2018-09
The difference between junction temperature and ambient temperature is determined by
ΔT = (PINT + PIOSTAT + PIODYN) × RΘJA
The internal power consumption is defined as
PINT = VDDP × IDDP (switching current and leakage curren t).
The static external power consumption caused by the output drivers is defined as
PIOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL)
The dynamic external power consumption caused by the output drivers (PIODYN) depends
on the capacitive load connected to the respective pins and their switching frequencies.
If the total power dissipation for a given system configuration exceeds the defined limit,
countermeasures must be taken to ensure proper system operation:
• Reduce VDDP, if possible in the system
• Reduce the system frequency
• Reduce the number of output pins
• Reduce the load on active output drivers
4.2 Package Outlines
The availability of different packages for different devices types is listed in Table 1.
The exposed die pad dimensions are listed in Table 71.
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Package and Reliability
Data Sheet 130 V1.1, 2018-09
Figure 60 PG-LQFP-144-24 (Plastic Green Low Profile Quad Flat Package)
1) Does not include plastic or metal protrusion of 0.25 max. per side
2) Does not include dambar protrusion
3) Refer table for exposed pad dimension
Bottom View
0.5
35 x 0.5 = 17.5
+0.07
-0.03
0.2 144x
CDA-B
M
0.08
C
0.08
1.6 MAX.
1.4 ±0.05
0.1±0.05
D
20 1)
2)
3)
3)
3)
3)
A-B0.2 DH4x
22 A-B0.2 DC
C
144x
BA
20 1)
22
1
144
Ex
Ax
Ay
Index Marking Index Marking
1
Exposed Diepad
144
144x
±0.15
0.6
H
0.127
-0.037
+0.073
PG-LQFP-144-22-PO V04
0°...7°
SEATING PLANE
COPLANARITY
STAND OFF
Ey
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Package and Reliability
Data Sheet 131 V1.1, 2018-09
Figure 61 PG-LQFP-100-25 (Plastic Green Low Profile Quad Flat Package)
PG-LQFP-100-24, -25-PO V04
0.5
24 x 0.5 = 12
0.2 A-B0.08 MC
C
D100x
100x
-0.03
+0.07 2)
1.6 MAX.
±0.05
±0.05
C
0.1
0.08
1.4
±0.15
0.6
H
A B
Index Marking
1
100
D
14 1)
16
0.2 C A-B D
0.2 H A-B D
100x
4x
14
1)
16
Bottom View
100
1
Exposed Diepad
SEATING
PLANE
COPLANARITY
STAND OFF
-0.037
+0.073
0.127
0°...7°
3)
Ex
3)
Ax
3)
Ey
3)
Ay
1) Does not include plastic or metal protrusion of 0.25 max. per side
2) Does not include dambar protrusion of 0.08 max. per side
3) Refer table for exposed pad dimension details
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Package and Reliability
Data Sheet 132 V1.1, 2018-09
Figure 62 PG-LFBGA-196-2 (Plastic Green Low Pro file Fine Pitch Ball Grid Array)
All dimensions in mm.
You can find complete information about Infineon packages, packing and marking in our
Infineon Internet Page “Packages”: http://www.infineon.com/packages
Subject to Agreement on the Use of Product Information
XMC4700 / XMC4800
XMC4000 Family
Quality Declarations
Data Sheet 133 V1.1, 2018-09
5 Quality Declarations
The qualification of the XMC4[78]00 is executed according to the JEDEC standard
JESD47I.
Note: For automotive applications refer to the Infineon automotive microcontrol lers.
Table 72 Quality Parameters
Parameter Sy mb ol Values Unit Note /
Test Condition
Min. Typ. Max.
Operation lifetime tOP CC 20 −− aTJ ≤ 109°C,
device permanent
on
ESD susceptibility
according to Human Body
Model (HBM)
VHBM
SR −−3 000 V EIA/JESD22-
A114-B
ESD susceptibility
according to Charged
Device Model (CDM)
VCDM
SR −−1 000 V Conforming to
JESD22-C101-C
Moisture sensitivity level MSL
CC −−3−JEDEC
J-STD-020D
Soldering te mp erature TSDR
SR −−260 °C Profile according
to JEDEC
J-STD-020D
Subject to Agreement on the Use of Product Information
www.infineon.com
Published by Infineon Technologies AG