DC to 50 MHz, Quad I/Q Demodulator and Phase Shifter AD8339 FEATURES APPLICATIONS Medical imaging (CW ultrasound beamforming) Phased array systems Radar Adaptive antennas Communication receivers FUNCTIONAL BLOCK DIAGRAM RF1N RF1P AD8339 RSTS SCLK SDI SDO SERIAL INTERFACE CSB I1OP Q1OP I2OP Q2OP I3OP Q3OP I4OP Q4OP RF2P RF2N 4LOP 4LON 0 /4 90 RF3P RF3N VPOS BIAS VNEG RF4N RF4P 06587-001 Quad integrated I/Q demodulator 16 phase select on each output (22.5 per step) Quadrature demodulation accuracy Phase accuracy: 1 Amplitude imbalance: 0.05 dB Bandwidth 4LO: LF to 200 MHz RF: LF to 50 MHz Baseband: determined by external filtering Output dynamic range: 160 dB/Hz LO drive: >0 dBm (50 ), single-ended sine wave Supply: 5 V Power consumption: 73 mW/channel (290 mW total) Power-down via SPI (each channel and complete chip) Figure 1. GENERAL DESCRIPTION The AD8339 is a quad I/Q demodulator configured to be driven by a low noise preamplifier with differential outputs. It is optimized for the LNA in the AD8332/AD8334/AD8335 family of VGAs. The part consists of four identical I/Q demodulators with a 4x local oscillator (LO) input that divides the signal and generates the necessary 0 and 90 phases of the internal LO that drive the mixers. The four I/Q demodulators can be used independently of each other (assuming that a common LO is acceptable) because each has a separate RF input. Continuous wave (CW) analog beamforming (ABF) and I/Q demodulation are combined in a single 40-lead, ultracompact chip scale device, making the AD8339 particularly applicable in high density ultrasound scanners. In an ABF system, time domain coherency is achieved following the appropriate phase alignment and summation of multiple receiver channels. A reset pin synchronizes multiple ICs to start each LO divider in the same quadrant. Sixteen programmable 22.5 phase increments are available for each channel. For example, if Channel 1 is used as a reference and Channel 2 has an I/Q phase lead of 45, the user can phase align Channel 2 with Channel 1 by choosing the appropriate phase select code. The mixer outputs are in current form for convenient summation. The independent I and Q mixer output currents are summed and converted to a voltage by a low noise, high dynamic range, current-to-voltage (I-V) transimpedance amplifier, such as the AD8021 or the AD829. Following the current summation, the combined signal is applied to a high resolution analog-to-digital converter (ADC), such as the AD7665 (16-bit, 570 kSPS). An SPI-compatible serial interface port is provided to easily program the phase of each channel; the interface allows daisy chaining by shifting the data through each chip from SDI to SDO. The SPI also allows for power-down of each individual channel and the complete chip. During power-down, the serial interface remains active so that the device can be programmed again. The dynamic range is typically 160 dB/Hz at the I and Q outputs. The AD8339 is available in a 6 mm x 6 mm, 40-lead LFCSP and is specified over the industrial temperature range of -40C to +85C. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007-2009 Analog Devices, Inc. All rights reserved. AD8339 TABLE OF CONTENTS Features .............................................................................................. 1 Dynamic Range and Noise ........................................................ 19 Applications ....................................................................................... 1 Multichannel Summation ......................................................... 20 Functional Block Diagram .............................................................. 1 Serial Interface ................................................................................ 23 General Description ......................................................................... 1 ENBL Bits .................................................................................... 23 Revision History ............................................................................... 2 Applications Information .............................................................. 24 Specifications..................................................................................... 3 Logic Inputs and Interfaces ....................................................... 24 Absolute Maximum Ratings............................................................ 5 Reset Input .................................................................................. 24 ESD Caution .................................................................................. 5 LO Input ...................................................................................... 24 Pin Configuration and Function Descriptions ............................. 6 Evaluation Board ............................................................................ 25 Equivalent Input Circuits ................................................................ 7 Connections to the Board ......................................................... 26 Typical Performance Characteristics ............................................. 8 Test Configurations .................................................................... 26 Test Circuits ..................................................................................... 14 AD8339-EVALZ Artwork ......................................................... 33 Theory of Operation ...................................................................... 18 Outline Dimensions ....................................................................... 35 Quadrature Generation ............................................................. 19 Ordering Guide .......................................................................... 35 I/Q Demodulator and Phase Shifter ........................................ 19 REVISION HISTORY 2/09--Rev. 0 to Rev. A Change to Figure 1 ........................................................................... 1 Change to Table 2 ............................................................................. 5 Added Exposed Pad Notation to Figure 2; Changes to Table 3 ............................................................................ 6 Changes to Figure 3; Added Figure 4; Renumbered Sequentially................................................................ 7 Changes to Theory of Operation Section .................................... 18 Changes to Dynamic Range and Noise Section, ........................ 20 Changes to Channel Summing Section ....................................... 21 Added Figure 55.............................................................................. 22 Changes to Serial Interface Section, ENBL Bits Section, Figure 56, and Figure 57 ................................................................ 23 Changes to Evaluation Board Section and Figure 58................. 25 Changes to Connections to the Board Section and Table 5 ...... 26 Changes to Figure 60 ...................................................................... 27 Changes to Figure 61 ...................................................................... 28 Changes to Table 7 .......................................................................... 29 Changes to Figure 63 ...................................................................... 30 Changes to Figure 64 ...................................................................... 31 Changes to Figure 65 ...................................................................... 32 Changes to Figure 66 and Figure 67 ............................................. 33 Changes to Figure 68 and Figure 69 ............................................. 34 Deleted Table 8 ................................................................................ 35 Updated Outline Dimensions ....................................................... 35 8/07--Revision 0: Initial Version Rev. A | Page 2 of 36 AD8339 SPECIFICATIONS VS = 5 V, TA = 25C, 4fLO = 20 MHz, fRF = 5.01 MHz, fBB = 10 kHz, PLO 0 dBm, per channel performance, dBm (50 ), unless otherwise noted. Single-channel AD8021 LPF values: RFILT = 787 and CFILT = 2.2 nF (see Figure 53). Table 1. Parameter OPERATING CONDITIONS Local Oscillator (LO) Frequency Range RF Frequency Range Baseband Bandwidth LO Input Level Supply Voltage (VS) Temperature Range DEMODULATOR PERFORMANCE Input Impedance Transconductance Dynamic Range Maximum Input Swing Peak Output Current (No Filtering) Input P1dB Third-Order Intermodulation (IM3) Equal Input Levels Unequal Input Levels Third-Order Input Intercept (IIP3) LO Leakage Conversion Gain Input Referred Noise Output Current Noise Noise Figure Bias Current LO Common-Mode Range RF Common-Mode Voltage Output Compliance Range PHASE ROTATION PERFORMANCE Phase Increment Quadrature Phase Error I/Q Amplitude Imbalance Channel-to-Channel Matching Test Conditions/Comments Min 4x internal LO at Pin 4LOP and Pin 4LON, square wave drive via LVDS (see Figure 64) Mixing Limited by external filtering Max Unit 0.01 200 MHz DC DC 50 50 13 5.5 +85 MHz MHz dBm V C 4.5 -40 RF, differential LO, differential Demodulated IOUT/VIN; each Ix or Qx output after low-pass filtering measured from RF inputs, all phases IP1dB - input referred noise (dBm) Differential; inputs biased at 2.5 V; Pin RFxP, Pin RFxN 0 phase shift 45 phase shift Ref = 50 Ref = 1 V rms fRF1 = 5.010 MHz, fRF2 = 5.015 MHz, fLO = 5.023 MHz Baseband tones: 0 dBm @ 8 kHz and 13 kHz Baseband tones: -1 dBm @ 8 kHz and -31 dBm @ 13 kHz fRF1 = 5.010 MHz, fRF2 = 5.015 MHz, fLO = 5.023 MHz Measured at RF inputs, worst phase, measured into 50 Measured at baseband outputs, worst phase, AD8021 disabled, measured into 50 All codes, see Figure 42 Output noise/conversion gain (see Figure 47) Output noise/RFILT With AD8334 LNA RS = 50 , RFB = RS = 50 , RFB = 1.1 k RS = 50 , RFB = 274 Pin 4LOP and Pin 4LON Pin RFxP and Pin RFxN Pin 4LOP and Pin 4LON (each pin) For maximum differential swing; Pin RFxP and Pin RFxN (dc-coupled to AD8334 LNA output) Pin IxOP and Pin QxOP One channel is reference; others are stepped 16 phase steps per channel Ix to Qx; all phases, 1 Ix to Qx; all phases, 1 Phase match I-to-I and Q-to-Q; -40C < TA < +85C Amplitude match I-to-I and Q-to-Q; -40C < TA < +85C Rev. A | Page 3 of 36 Typ 0 5.0 25||10 100||4 1.15 k||pF k||pF mS 160 2.8 2.4 3.1 14.8 1.85 dB/Hz V p-p mA mA dBm dBV -60 -66 31 -118 -68 dBc dBc dBm dBm dBm -1.3 11.8 12.9 dB nV/Hz pA/Hz 8.4 9.1 11.5 -3 -45 dB dB dB A A V V 0.2 3.8 2.5 -1.5 -2 +0.7 22.5 1 0.05 1 0.1 +2 V Degrees Degrees dB Degrees dB AD8339 Parameter LOGIC INTERFACES Pin SDI, Pin CSB, Pin SCLK, Pin RSET Logic Level High Logic Level Low Pin RSTS Logic Level High Logic Level Low Bias Current Input Resistance LO Divider RSET Setup Time LO Divider RSET High Pulse Width LO Divider RSET Response Time Phase Response Time Enable Response Time Output Logic Level High Logic Level Low SPI TIMING CHARACTERISTICS SCLK Frequency CSB Fall to SCLK Setup Time SCLK High Pulse Width SCLK Low Pulse Width Data Access Time (SDO) After SCLK Rising Edge Data Setup Time Before SCLK Rising Edge Data Hold Time After SCLK Rising Edge SCLK Rise to CSB Rise Hold Time CSB Rise to SCLK Rise Hold Time POWER SUPPLY Supply Voltage Current Over Temperature, -40C < TA < +85C Quiescent Power Disable Current PSRR Test Conditions/Comments Min Typ Max Unit 0.9 V V 1.5 1.8 1.2 Logic high (pulled to 5 V) Logic low (pulled to GND) RSET rising or falling edge to 4LOP or 4LON (differential) rising edge 0.5 0 4 5 20 200 5 12 Measured from CSB going high Measured from CSB going high (with 0.1 F capacitor on Pin LODC); no channel enabled At least one channel enabled Pin SDO loaded with 5 pF and next SDI input 500 1.7 Pin SDI, Pin SDO, Pin CSB, Pin SCLK, Pin RSTS fCLK t1 t2 t3 t4 15 1.9 0.2 V V A A M ns ns ns s s ns 0.5 10 0 10 10 100 V V MHz ns ns ns ns t5 2 ns t6 2 ns t7 t8 Pin VPOS, Pin VNEG 15 0 ns ns 4.5 VPOS, all phase bits = 0 VNEG, all phase bits = 0 VPOS, all phase bits = 0 VNEG, all phase bits = 0 Per channel, all phase bits = 0 Per channel maximum (depends on phase bits) All channels disabled; SPI stays on VPOS to Ix/Qx outputs, @ 10 kHz VNEG to Ix/Qx outputs, @ 10 kHz Rev. A | Page 4 of 36 5.0 35 -18 33 5.5 36 -19 -17 66 88 2.75 -85 -85 V mA mA mA mA mW mW mA dB dB AD8339 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Voltages Supply Voltage (VS) RF Inputs 4LO Inputs Outputs (IxOP, QxOP) Digital Inputs SDO Output LODC Pin Thermal Data (4-Layer JEDEC Board, No Airflow, Exposed Pad Soldered to PCB) JA JB JC JT JB Maximum Junction Temperature Maximum Power Dissipation (Exposed Pad Soldered to PCB) Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 60 sec) Rating 6 V 6 V to GND 6 V to GND +0.7 V to -6 V +6 V to -1.4 V 6 V to GND VPOS - 1.5 V to +6 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 32.2C/W 17.8C/W 2.7C/W 0.3C/W 16.7C/W 150C 2W -40C to +85C -65C to +150C 300C Rev. A | Page 5 of 36 AD8339 RSTS SDI RF1P RF1N COMM VPOS RSET I1OP Q1OP VNEG PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 40 39 38 37 36 35 34 33 32 31 RF2N 1 RF2P COMM 2 COMM 3 4 SCLK 5 CSB VPOS VPOS 6 7 RF3P 9 10 RF3N PIN 1 INDICATOR AD8339 TOP VIEW (Not to Scale) 8 30 Q2OP 29 28 I2OP VPOS 27 26 VPOS 25 24 4LON 23 22 VNEG I3OP 21 Q3OP 4LOP VNEG 06587-002 VPOS SDO RF4P RF4N COMM VPOS LODC I4OP Q4OP VNEG 11 12 13 14 15 16 17 18 19 20 NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE. Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 2, 9, 10, 13, 14, 37, 38 3, 4, 15, 36 5 6 7, 8, 11, 16, 27, 28, 35 Mnemonic RF1P to RF4P, RF1N to RF4N COMM SCLK CSB VPOS 12 17 SDO LODC 18, 19, 21, 22, 29, 30, 32, 33 I1OP to I4OP, Q1OP to Q4OP 20, 23, 24, 31 VNEG 25, 26 4LON, 4LOP 34 39 RSET SDI 40 RSTS EP Description RF Inputs. Require external 2.5 V bias for optimum symmetrical input differential swing if 5 V supplies are used. Ground. Serial Interface Clock. Serial Interface Chip Select Bar. Active low. Positive Supply. These pins should be decoupled with a ferrite bead in series with the supply and a 0.1 F capacitor between the VPOS pins and ground. Because the VPOS pins are internally connected, one set of supply decoupling components on each side of the chip should be sufficient. Serial Interface Data Output. Normally connected to the SDI pin of the next chip or left open. Decoupling Pin for LO. A 0.1 F capacitor should be connected between this pin and ground. The value of this capacitor affects the chip enable/disable times. I/Q Outputs. These outputs provide a bidirectional current that can be converted back to a voltage via a transimpedance amplifier. Multiple outputs can be summed by simply connecting them (wire-OR). The bias voltage should be set to 0 V or less by the transimpedance amplifier (see Figure 53). Negative Supply. These pins should be decoupled with a ferrite bead in series with the supply and a 0.1 F capacitor between the VNEG pins and ground. Because the VNEG pins are internally connected, one set of supply decoupling components for the chip should be sufficient. LO Inputs. No internal bias; optimally biased by an LVDS driver. For best performance, these inputs should be driven differentially. If driven by a single-ended sine wave at 4LOP or 4LON, the signal level should be >0 dBm (50 ) with external bias resistors. Reset for LO Interface. Logic threshold is at ~1.3 V and therefore can be driven by >1.8 V CMOS logic. Serial Interface Data Input. Logic threshold is at ~1.3 V and therefore can be driven by >1.8 V CMOS logic. Reset for SPI Interface. Logic threshold is at ~1.5 V with 0.3 V hysteresis and should be driven by >3.3 V CMOS logic. For quick testing without the need to program the SPI, the voltage on the RSTS pin should be pulled to -1.4 V; this enables all four channels in the phase (I = 1, Q = 0) state. Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the ground plane. Rev. A | Page 6 of 36 AD8339 EQUIVALENT INPUT CIRCUITS VPOS VPOS LODC SCLK CSB SDI RSET COMM 06587-005 06587-003 LOGIC INTERFACE COMM Figure 3. SCLK, CSB, SDI, and RSET Logic Inputs Figure 6. LO Decoupling Pin VPOS VPOS RFxP LOGIC INTERFACE RSTS 06587-006 COMM 06587-104 RFxN COMM Figure 4. RSTS Logic Input Figure 7. RF Inputs COMM VPOS IxOP QxOP 4LOP VNEG Figure 8. Output Drivers Figure 5. Local Oscillator Inputs Rev. A | Page 7 of 36 06587-007 COMM 06587-004 4LON AD8339 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25C, 4fLO = 20 MHz, fLO = 5 MHz, fRF = 5.01 MHz, fBB = 10 kHz, 4fLO - LVDS drive; per channel performance shown is typical of all channels, differential voltages, dBm (50 ), phase select code = 0000, unless otherwise noted (see Figure 42). 1.5 2 f = 1MHz CODE 0100 CODE 0011 CODE 0010 0 PHASE ERROR (Degrees) CODE 0001 Q 0.5 CODE 1000 CODE 0000 0 I -0.5 -1 CHANNEL 3 CHANNEL 4 -2 2 f = 1MHz 1 0 06587-008 -1.0 CODE 1100 -1.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 -1 CHANNEL 3 CHANNEL 4 -2 0000 0010 0100 2.0 REAL (Normalized) 06587-011 IMAGINARY (Normalized) 1.0 f = 5MHz 1 0110 1000 1010 1100 1110 1111 CODE (Binary) Figure 9. Normalized Vector Plot of Phase, Ch 2, Ch 3, and Ch 4 vs. Ch 1; Ch 1 Fixed at 0; Ch 2, Ch 3, and Ch 4 Stepped 22.5/Step; All Codes Displayed Figure 12. Representative Phase Error vs. Binary Phase Select Code at 1 MHz and 5 MHz; Ch 3 and Ch 4 Are Displayed with Respect to Ch 1 360 270 5MHz 225 1 2 180 1MHz 135 90 0 0000 06587-009 45 06587-012 PHASE DELAY (Degrees) 315 0010 0100 0110 1000 1010 1100 1110 C2 500mV C4 500mV 1111 CODE (Binary) Figure 10. Representative Phase Delay vs. Binary Phase Select Code at 1 MHz and 5 MHz; Ch 3 and Ch 4 Are Displayed with Respect to Ch 1 R1 500mV 20s R2 500mV 20s 20.0s/DIV 2.5MS/s 400ns/PT A C2 30.0mV Figure 13. Representative Phase Delays of the I or Q Outputs; Ch 2 Is Displayed with Respect to Ch 1, for Delays of 22.5, 45, 67.5, and 90 1 1.0 I OUTPUT OF CHANNEL 1 SHOWN f = 5MHz 0.5 CHANNEL 3 CHANNEL 4 -1.0 1.0 f = 1MHz 0.5 0 CHANNEL 3 CHANNEL 4 -1.0 0000 0010 0100 0110 1000 1010 1100 1110 -1 -2 CODE 0000 CODE 0001 CODE 0010 CODE 0011 06587-010 -0.5 0 -3 1M 1111 06587-013 -0.5 CONVERSION GAIN (dB) AMPLITUDE ERROR (dB) 0 10M 50M RF FREQUENCY (Hz) CODE (Binary) Figure 11. Representative Amplitude Error vs. Binary Phase Select Code at 1 MHz and 5 MHz; Ch 3 and Ch 4 Are Displayed with Respect to Ch 1 Rev. A | Page 8 of 36 Figure 14. Conversion Gain vs. RF Frequency, First Quadrant, Baseband Frequency = 10 kHz AD8339 0.5 0.4 4 2 0 -2 -4 -6 -8 1M 10M 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 06587-017 I/Q AMPLITUDE IMBALANCE (dB) 6 06587-014 QUADRATURE PHASE ERROR (Degrees) 8 -0.4 -0.5 100 50M 1k RF FREQUENCY (Hz) 10k 100k BASEBAND FREQUENCY (Hz) Figure 15. Representative Range of Quadrature Phase Error vs. RF Frequency for All Channels and Codes Figure 18. Representative Range of I/Q Amplitude Imbalance vs. Baseband Frequency for All Channels and Codes (See Figure 44) 2.0 3 2 AMPLITUDE MATCH (dB) 1.0 0.5 0 -0.5 -1.0 0 -1 1k 10k 06587-018 -2.0 100 1 -2 -1.5 06587-015 -3 1M 100k 10M BASEBAND FREQUENCY (Hz) Figure 16. Representative Range of Quadrature Phase Error vs. Baseband Frequency for All Channels and Codes (See Figure 44) Figure 19. Typical Channel-to-Channel Amplitude Match vs. RF Frequency, First Quadrant, over the Range of Operating Temperatures 0.5 8 fBB = 10kHz 0.4 6 PHASE ERROR (Degrees) 0.3 0.2 0.1 0 -0.1 -0.2 4 2 0 -2 -4 -0.3 -0.4 -0.5 1M -6 06587-016 I/Q AMPLITUDE IMBALANCE (dB) 50M RF FREQUENCY (Hz) 10M -8 1M 50M RF FREQUENCY (Hz) Figure 17. Representative Range of I/Q Amplitude Imbalance vs. RF Frequency for All Channels and Codes 06587-019 QUADRATURE PHASE ERROR (Degrees) fBB = 10kHz 1.5 10M 50M RF FREQUENCY (Hz) Figure 20. Typical Channel-to-Channel Phase Error vs. RF Frequency, First Quadrant, over the Range of Operating Temperatures Rev. A | Page 9 of 36 AD8339 1.4 0 I OUTPUT OF CHANNEL 1 SHOWN TRANSCONDUCTANCE = [(VBB/787)/V RF] -10 -20 IM3 (dBc) 1.2 1.1 -30 3 8 13 18 IM3 PRODUCTS LO = 5.023MHz RF1 = 5.015MHz RF2 = 5.010MHz -40 -50 -60 0.8 1M 10M -70 1M 50M RF FREQUENCY (Hz) 10M 50M RF FREQUENCY (Hz) Figure 21. Transconductance vs. RF Frequency for First Quadrant Phase Delays Figure 24. Representative Range of IM3 vs. RF Frequency, First Quadrant (See Figure 49) 10 35 +85C +25C -40C 0 30 -10 25 OIP3 (dBm) -20 -30 -40 20 15 10 -50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 06587-024 5 06587-021 -60 -70 06587-023 PHASE DELAY = 0 PHASE DELAY = 22.5 PHASE DELAY = 45 PHASE DELAY = 67.5 0.9 CONVERSION GAIN (dB) 0dBm 1.0 06587-020 TRANSCONDUCTANCE (mS) 1.3 0 1M 5.0 COMMON-MODE VOLTAGE (V) 10M 50M RF FREQUENCY (Hz) Figure 22. LO Common-Mode Range at Three Temperatures Figure 25. Representative Range of OIP3 vs. RF Frequency, First Quadrant (See Figure 49) 20 35 18 30 16 25 OIP3 (dBm) 12 10 8 6 20 15 10 4 10M 0 1k 50M RF FREQUENCY (Hz) 06587-025 2 0 1M 5 06587-022 IP1dB (dBm) 14 10k 100k BASEBAND FREQUENCY (Hz) Figure 23. Representative Range of IP1dB vs. RF Frequency, Baseband Frequency = 10 kHz, First Quadrant (See Figure 43) Figure 26. Representative Range of OIP3 vs. Baseband Frequency (See Figure 48) Rev. A | Page 10 of 36 AD8339 20 LO LEVEL = 0dBm 18 -10 16 NOISE FIGURE (dB) LO LEAKAGE (dBm) -20 -30 -40 -50 -60 -70 14 12 10 8 6 4 06587-026 -80 -90 1M 10M 06587-029 0 2 0 1M 50M 10M RF FREQUENCY (Hz) Figure 27. Representative Range of LO Leakage vs. RF Frequency at I and Q Outputs 0 50M RF FREQUENCY (Hz) Figure 30. Noise Figure vs. RF Frequency (When Driven by AD8334 LNA) 172 LO LEVEL = 0dBm 170 -20 -60 -80 -100 166 164 162 160 Q1 Q2 Q3 Q4 I1 + I2 I3 + I4 Q1 + Q2 Q3 + Q4 I1 + I2 + I3 + I4 Q1 + Q2 + Q3 + Q4 158 156 06587-027 -120 10M 152 1M 50M 10M RF FREQUENCY (Hz) Figure 31. Dynamic Range vs. RF Frequency, IP1dB Minus Noise Level -142.9 0 14 -144.1 -2 12 -145.4 -4 10 -147.0 -6 8 -148.9 6 -151.4 4 -154.9 -12 2 -161.0 -14 10M GAIN (dB) NOISE (dBm) 16 GAIN = VBB/VRF -8 -10 06587-028 NOISE (nV/Hz) Figure 28. Representative Range of LO Leakage vs. RF Frequency at RF Inputs 0 1M 50M RF FREQUENCY (Hz) -16 -3.5 50M RF FREQUENCY (Hz) DELAY = 0 DELAY = 22.5 DELAY = 45 DELAY = 67.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 06587-031 -140 1M 154 06587-030 DYNAMIC RANGE (dB) LO LEAKAGE (dBm) 168 -40 0 0.5 1.0 VOLTAGE (V) Figure 29. Representative Range of Input Referred Noise vs. RF Frequency Figure 32. Output Compliance Range for Four Values of Phase Delay (See Figure 50) Rev. A | Page 11 of 36 AD8339 T CH3 AMPL 3.18V CH3 AMPL 5.04V 3 3 CH2 AMPL 790mV CH2 AMPL 370mV 2 CH2 500mV CH3 1.00V M200ns A CH3 T 608.000ns 06587-035 06587-032 2 600mV CH3 2.00V CH2 500mV Figure 33. Enable Response vs. CSB (Filter Disabled to Show Response) with a Previously Enabled Channel (See Figure 44) 3 M200s A CH3 T -175.200ns 2.52mV Figure 36. LO Reset Response (see Figure 45) 3 2 CH2 AMPL 1.82V CH3 1.00V CH2 500mV M2.00s A CH3 T 7.840s 06587-036 06587-033 2 780mV CH3 1.00V CH2 1.00V CH4 1.00V Figure 34. Enable Response vs. CSB (Filter Disabled to Show Response) with No Channels Previously Enabled (See Figure 44) M40.0s A CH3 T 46.4000s 640mV Figure 37. Phase Switching Response at 45 (Top: CSB) CH3 AMPL 3.18V 3 3 CH2 AMPL 210mV 06587-034 CH3 1.00V CH2 500mV M200s A CH3 T -492.00ns 06587-037 2 2 600mV CH3 1.00V CH2 1.00V CH4 1.00V Figure 35. Disable Response vs. CSB (Top: CSB) (See Figure 44) M40.0s A CH3 T 46.4000s 640mV Figure 38. Phase Switching Response at 90 (Top: CSB) Rev. A | Page 12 of 36 AD8339 60 SUPPLY CURRENT (mA) 50 3 2 VPOS 30 20 VNEG M40.0s A CH3 T 46.4000s 0 -50 640mV -10 -20 -30 -40 VNEG VPOS -70 06587-039 -80 -90 -100 10k 100k 1M 10M -10 10 30 50 Figure 41. Supply Current vs. Temperature 0 -60 -30 TEMPERATURE (C) Figure 39. Phase Switching Response at 180 (Top: CSB) -50 06587-040 06587-038 10 CH3 1.00V CH2 1.00V CH4 1.00V PSRR (dB) 40 50M FREQUENCY (Hz) Figure 40. PSRR vs. Frequency (see Figure 51) Rev. A | Page 13 of 36 70 90 AD8339 TEST CIRCUITS AD8021 120nH FB 0.1F 787 AD8334 LNA 20 LPF 50 2.2nF RFxP IxOP AD8339 0.1F 20 RFxN QxOP 4LOP SIGNAL GENERATOR OSCILLOSCOPE 2.2nF 787 50 AD8021 06587-041 SIGNAL GENERATOR Figure 42. Default Test Circuit AD8021 120nH FB 0.1F 100 AD8334 LNA 20 LPF 50 10nF RFxP IxOP AD8339 0.1F 20 RFxN QxOP 4LOP SIGNAL GENERATOR OSCILLOSCOPE 10nF 100 50 AD8021 06587-042 SIGNAL GENERATOR Figure 43. P1dB Test Circuit AD8021 120nH FB 0.1F AD8334 LNA 20 LPF 50 RFxP IxOP 787 OSCILLOSCOPE AD8339 0.1F 20 RFxN QxOP 4LOP 787 SIGNAL GENERATOR 50 AD8021 Figure 44. Phase and Amplitude vs. Baseband Frequency Rev. A | Page 14 of 36 06587-043 SIGNAL GENERATOR AD8339 AD8021 120nH FB 0.1F AD8334 LNA 20 RFxP LPF 787 IxOP OSCILLOSCOPE AD8339 50 0.1F RFxN RSET 20 787 QxOP 4LOP SIGNAL GENERATOR 50 50 SIGNAL GENERATOR 06587-044 SIGNAL GENERATOR AD8021 Figure 45. LO Reset Response 120nH FB 0.1F AD8334 LNA OSCILLOSCOPE 20 RFxP LPF 50 IxOP AD8339 0.1F RFxN 20 50 50 QxOP 4LOP SIGNAL GENERATOR 50 06587-045 SIGNAL GENERATOR Figure 46. RF Input Range AD829 6.98k AD8334 LNA 270pF 20 RFxP 0.1F 0.1F 20 IxOP AD8339 RFxN QxOP 4LOP SPECTRUM ANALYZER 270pF 6.98k 50 SIGNAL GENERATOR Figure 47. Noise Rev. A | Page 15 of 36 AD829 06587-046 120nH FB 0.1F AD8339 AD8021 SPLITTER AD8334 -9.5dB LNA 120nH 20 FB 0.1F 50 787 100pF RFxP IxOP AD8339 SIGNAL GENERATOR 50 0.1F RFxN 20 SPECTRUM ANALYZER 100pF QxOP 4LOP 787 SIGNAL GENERATOR 50 AD8021 06587-047 SIGNAL GENERATOR Figure 48. OIP3 vs. Baseband Frequency AD8021 SPLITTER AD8334 -9.5dB LNA 120nH 20 FB 0.1F 50 787 2.2nF RFxP IxOP AD8339 SIGNAL GENERATOR 50 0.1F RFxN 20 SPECTRUM ANALYZER 2.2nF QxOP 4LOP 787 SIGNAL GENERATOR 50 AD8021 06587-048 SIGNAL GENERATOR Figure 49. OIP3 and IM3 vs. RF Frequency AD8021 787 AD8334 LNA 20 LPF 50 2.2nF RFxP IxOP AD8339 0.1F 20 RFxN QxOP 4LOP SIGNAL GENERATOR OSCILLOSCOPE 2.2nF 787 50 SIGNAL GENERATOR AD8021 Figure 50. Output Compliance Range Rev. A | Page 16 of 36 06587-049 120nH FB 0.1F AD8339 SIGNAL GENERATOR VPOS VPOS RFxP 0.1F SPECTRUM ANALYZER AD8339 RFxN QxOP 4LOP SIGNAL GENERATOR 06587-050 VPOS IxOP Figure 51. PSRR Rev. A | Page 17 of 36 AD8339 THEORY OF OPERATION RF2N 1 RF2P 2 COMM 3 COMM 4 SCLK 5 RSTS SDI RF1P RF1N 40 39 38 37 COMM VPOS 36 RSET I1OP Q1OP VNEG 34 33 32 31 35 0 CURRENT MIRROR 30 Q2OP CURRENT MIRROR 29 I2OP CURRENT MIRROR 28 VPOS CURRENT MIRROR 27 VPOS 26 4LOP 25 4LON V TO I V TO I SERIAL INTERFACE (SPI) 0 LOCAL OSCILLATOR DIVIDE BY 4 90 CSB 6 VPOS 7 CURRENT MIRROR 24 VNEG CURRENT MIRROR 23 VNEG CURRENT MIRROR 22 I3OP CURRENT MIRROR 21 Q3OP V TO I VPOS 8 RF3P 9 BIAS V TO I RF3N 10 11 12 13 14 VPOS SDO RF4P RF4N 15 16 COMM VPOS 17 18 19 20 LODC I4OP Q4OP VNEG 06587-051 AD8339 Figure 52. AD8339 Block Diagram The AD8339 is a quad I/Q demodulator with a programmable phase shifter for each channel. The primary application is phased array beamforming in medical ultrasound. Other potential applications include phased array radar and smart antennas for mobile communications. The AD8339 can also be used in applications that require multiple well-matched I/Q demodulators. The AD8339 is architecturally very similar to its predecessor, the AD8333. The major differences are * * The addition of a serial (SPI) interface that allows daisy chaining of multiple devices Reduced power per channel Figure 52 shows the block diagram and pinout of the AD8339. The analog inputs include the four RF inputs, which accept signals from the RF sources, and a local oscillator (applied to differential input pins marked 4LOP and 4LON) common to all channels. Each channel can be shifted up to 347.5 in 16 increments, or 22.5 per increment, via the SPI port. The AD8339 has two reset inputs: RSET synchronizes the LO dividers when multiple AD8339s are used in arrays; RSTS sets all the SPI port control bits to 0. RSTS is used for testing or to disable the AD8339 without the need to program it via the SPI port. The I and Q outputs are current-formatted and summed together for beamforming applications. A transimpedance amplifier using an AD8021 op amp is a nearly ideal method for summing multiple channels and current-to-voltage conversion because each of the AD8339 outputs is terminated by a virtual ground. A further advantage of the transimpedance amplifier is the simple implementation of high-pass filtering and the flexible number of channels accommodated. Rev. A | Page 18 of 36 AD8339 QUADRATURE GENERATION The internal 0 and 90 LO phases are digitally generated by a divide-by-4 logic circuit. The divider is dc-coupled and inherently broadband; the maximum LO frequency is limited only by its switching speed. The duty cycle of the quadrature LO signals is intrinsically 50% and is unaffected by the asymmetry of the externally connected 4LO input. Furthermore, the divider is implemented such that the 4LO signal reclocks the final flipflops that generate the internal LO signals and thereby minimizes noise introduced by the divide circuitry. For optimum performance, the 4LO input is driven differentially, but it can also be driven single-ended. A good choice for a drive is an LVDS device as is done on the AD8339 evaluation board. The common-mode range on each pin is approximately 0.2 V to 3.8 V with the nominal 5 V supplies. The minimum 4LO level is frequency dependent when driven by a sine wave. For optimum noise performance, it is important to ensure that the LO source has very low phase noise (jitter) and adequate input level to ensure stable mixer core switching. The gain through the divider determines the LO signal level vs. RF frequency. The AD8339 can be operated at very low frequencies at the LO inputs if a square wave is used to drive the LO, as is done with the LVDS driver on the evaluation board. Beamforming applications require a precise channel-to-channel phase relationship for coherence among multiple channels. A reset pin is provided to synchronize the LO divider circuits in different AD8339s when they are used in arrays. The RSET pin resets the dividers to a known state after power is applied to multiple AD8339s. A logic input must be provided to the RSET pin when using more than one AD8339. Note that at least one channel must be enabled for the LO interface to also be enabled and the LO reset to work. See the Reset Input section for more information. I/Q DEMODULATOR AND PHASE SHIFTER The I/Q demodulators consist of double-balanced Gilbert cell mixers. The RF input signals are converted into currents by transconductance stages that have a maximum differential input signal capability of 2.8 V p-p. These currents are then presented to the mixers, which convert them to baseband (RF - LO) and twice RF (RF + LO). The signals are phase shifted according to the codes programmed into the SPI latch (see Table 4); the phase bits are labeled PHx0 through PHx3, where 0 indicates LSB and 3 indicates MSB. The phase shift function is an integral part of the overall circuit. The phase shift listed in Column 1 of Table 4 is defined as being between the baseband I or Q channel outputs. As an example, for a common signal applied to a pair of RF inputs to an AD8339, the baseband outputs are in phase for matching phase codes. However, if the phase code for Channel 1 is 0000 and that of Channel 2 is 0001, then Channel 2 leads Channel 1 by 22.5. Following the phase shift circuitry, the differential current signal is converted from differential to single-ended via a current mirror. An external transimpedance amplifier is needed to convert the I and Q outputs to voltages. Table 4. Phase Select Code for Channel-to-Channel Phase Shift Shift 0 22.5 45 67.5 90 112.5 135 157.5 180 202.5 225 247.5 270 292.5 315 337.5 PHx3 (MSB) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PHx2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PHx1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PHx0 (LSB) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DYNAMIC RANGE AND NOISE Figure 53 is an interconnection block diagram of all four channels of the AD8339. More channels are easily added to the summation (up to 16 when using an AD8021 as the summation amplifier) by wire-OR connecting the outputs as shown for four channels. For optimum system noise performance, the RF input signal is provided by a very low noise amplifier, such as the LNA of the AD8332, AD8334, or AD8335. In beamforming applications, the I and Q outputs of a number of receiver channels are summed (for example, the four channels illustrated in Figure 53). The dynamic range of the system increases by the factor 10 log10(N), where N is the number of channels (assuming random uncorrelated noise). The noise in the 4-channel example of Figure 53 is increased by 6 dB while the signal quadruples (12 dB), yielding an aggregate SNR improvement of 6 dB (12 - 6). Judicious selection of the RF amplifier ensures the least degradation in dynamic range. The input referred spectral voltage noise density (en) of the AD8339 is nominally ~11 nV/Hz. For the noise of the AD8339 to degrade the system noise figure (NF) by 1 dB, the combined noise of the source and the LNA should be approximately twice that of the AD8339, or 22 nV/Hz. If the noise of the circuitry before the AD8339 is less than 22 nV/Hz, the system NF degrades more than 1 dB. For example, if the noise contribution of the LNA and source is equal to the AD8339, or 11 nV/Hz, the degradation is 3 dB. If the circuit noise preceding the AD8339 is 1.3x as large as that of the AD8339 (or ~14 nV/Hz), the degradation is 2 dB. For a circuit noise 1.45x that of the AD8339 (16 nV/Hz), the degradation is 1.5 dB. Rev. A | Page 19 of 36 AD8339 maintaining the corner frequency, thereby increasing the gain. The factor limiting the magnitude of the gain is the output swing and drive capability of the op amp selected for the I-to-V converter, in this example, the AD8021. To determine the input referred noise, it is important to know the active low-pass filter (LPF) values RFILT and CFILT, shown in Figure 53. Typical filter values for a single channel are 1.58 k for RFILT and 1 nF for CFILT; these values implement a 100 kHz single-pole LPF. If two channels are summed, as is done on the AD8339 evaluation board, the resistor value is halved (787 ) and the capacitor value is doubled (2.2 nF), maintaining the same pole frequency at twice the AD8339 current. The limitation on the number of channels summed is the drive capability of the amplifier, as explained in detail in the Channel Summing section. MULTICHANNEL SUMMATION If the RF and LO are offset by 10 kHz, the demodulated signal is 10 kHz and is passed by the LPF. The single-channel mixing gain from the RF input to the AD8021 output (for example, I1, Q1) is approximately 1.7x (4.7 dB) for 1.58 k and 1 nF, or 6 dB less for filter values of 787 and 2.2 nF (0.85x or -1.3 dB). The noise contributed by the AD8339 is then 11 nV/Hz x 1.7 or ~18.7 nV/Hz at the AD8021 output. The combined noise of the AD8021 and the 1.58 k feedback resistor is 6.3 nV/Hz, so the total output referred noise is approximately 19.7 nV/Hz. This value can be adjusted by increasing the filter resistor while AD8332, AD8334 LNA OR AD8335 PREAMP TRANSMITTER Analog Beamforming Beamforming, as applied to medical ultrasound, is defined as the phase alignment and summation of signals generated from a common source, but received at different times by a multielement ultrasound transducer. Beamforming has two functions: it imparts directivity to the transducer, enhancing its gain, and it defines a focal point within the body from which the location of the returning echo is derived. The primary application for the AD8339 is in analog beamforming circuits for ultrasound. AD8339 RFB 2 2 2 2 I1 2 T/R SW TRANSDUCER RFB 2 2 Q1 CFILT I2 RFILT AD7665 OR AD7686 I 2 T/R SW 2 2 16-BIT ADC I DATA Q2 AD8021 RFB 2 I3 CFILT AD7665 OR AD7686 2 RFB 2 2 2 2 2 2 Q3 I4 RFILT Q 16-BIT ADC Q DATA AD8021 2 0 90 QUADRATURE DIVIDER Q4 SDI CONTROLLER CLOCK DATA SYSTEM TIMING Figure 53. Interconnection Block Diagram for the AD8339 Rev. A | Page 20 of 36 06587-052 T/R SW T/R SW 2 AD8339 Combining Phase Compensation and Analog Beamforming The AD8339 integrates the phase shifter, frequency conversion, and I/Q demodulation into a single package and directly yields the baseband signal. Figure 54 is a simplified diagram showing the concept for all four channels. The ultrasound wave (US wave) is received by four transducer elements, TE1 through TE4, in an ultrasound probe and generates signals E1 through E4. In this example, the phase at TE1 leads the phase at TE2 by 45. Modern ultrasound machines used for medical applications employ an array of receivers for beamforming, with typical CW Doppler array sizes of up to 64 receiver channels that are phase shifted and summed together to extract coherent information. When used in multiples, the desired signals from each of the channels can be summed to yield a larger signal (increased by a factor N, where N is the number of channels), and the noise is increased by the square root of the number of channels. This technique enhances the signal-to-noise performance of the machine. The critical elements in a beamformer design are the means to align the incoming signals in the time domain and the means to sum the individual signals into a composite whole. Channel Summing Figure 55 shows a 16-channel beamformer using AD8339s, AD8021s, and an AD797. The number of channels summed is limited by the current drive capability of the amplifier used to implement the active low-pass filter and current-to-voltage converter. An AD8021 sums up to 16 AD8339 outputs. In an ultrasound application, the instantaneous phase difference between echo signals is influenced by the transducer-element spacing, the wavelength (), the speed of sound in the media, the angle of incidence of the probe to the target, and other factors. In Figure 54, the signals E1 through E4 are amplified 19 dB by the low noise amplifiers in the AD8334; for lower power portable ultrasound applications, the AD8335 can be used instead of the AD8334 for the lowest power per channel. For optimum signalto-noise performance, the output of the LNA is applied directly to the input of the AD8339. To sum the signals E1 through E4, E2 is shifted 45 relative to E1 by setting the phase code in Channel 2 to 0010, E3 is shifted 90 (0100), and E4 is shifted 135 (0110). The phase aligned current signals at the output of the AD8339 are summed in an I-to-V converter to provide the combined output signal with a theoretical improvement in dynamic range of 6 dB for the four channels. In traditional analog beamformers incorporating Doppler, a V-to-I converter per channel and a crosspoint switch precede passive delay lines used as a combined phase shifter and summing circuit. The system operates at the carrier frequency (RF) through the delay line, which also sums the signals from the various channels, and then the combined signal is downconverted by a very large dynamic range I/Q demodulator. The resultant I and Q signals are filtered and then sampled by two high resolution analog-to-digital converters. The sampled signals are processed to extract the relevant Doppler information. Alternatively, the RF signal can be processed by downconversion on each channel individually, phase shifting the downconverted signal, and then combining all channels. The AD8333 and the AD8339 implement this architecture. The downconversion is done by an I/Q demodulator on each channel, and the summed current output is the same as in the delay line approach. The subsequent filters after the I-to-V conversion and the ADCs are similar. TRANSDUCER ELEMENTS TE1 THROUGH TE4 CONVERT US TO ELECTRICAL SIGNALS AD8334 CH 1 PHASE SET FOR 135 LAG S1 19dB LNA 19dB LNA CH 2 PHASE SET FOR 90 LAG S2 E2 CH 3 PHASE SET FOR 45 LAG S3 19dB LNA CH 4 PHASE SET FOR 0 LAG S4 19dB LNA 45 E3 135 SUMMED OUTPUT S1 + S2 + S3 + S4 E4 Figure 54. Simplified Example of the AD8339 Phase Shifter Rev. A | Page 21 of 36 06587-053 90 S1 THROUGH S4 ARE NOW IN PHASE E1 0 4 US WAVES ARE DELAYED 45 EACH WITH RESPECT TO EACH OTHER AD8339 PHASE BIT SETTINGS AD8339 FIRST ORDER SUMMING AMPLIFIER(S) R1 100 +5V UP TO 16 AD8339 I OR Q OUTPUTS AT 3.1mA PEAK EACH WHEN PHASE SHIFT IS SET FOR 45 2 3 FROM OTHER AD8021 SUMMING AMPLIFIERS LPF1 88kHz +2.8V BASEBAND SIGNAL R4 0.1F HPF 1100Hz C2 1F - + SECOND ORDER SUMMING AMPLIFIER R2 698 AD8021 LPF2 81kHz R3 698 C3 5.6nF 0.1F -5V Figure 55. 16-Channel Beamformer Using the AD8339 Rev. A | Page 22 of 36 +10V 2 0.1F - 3 + AD797 -10V 0.1F 06587-155 C1 18nF AD8339 SERIAL INTERFACE The AD8339 contains a 4-wire, SPI-compatible digital interface (SDI, SCLK, CSB, and SDO). The interface comprises a 20-bit shift register plus a latch. The shift register is loaded MSB first. Phase selection and channel enabling information are contained in the 20-bit word. Figure 56 is a bit map of the data-word, and Figure 57 is the timing diagram. ENBL BITS When all four ENBL bits are low, only the SPI port is powered up. This feature allows for low power consumption (~13 mW per AD8339 or 3.25 mW per channel) when the CW Doppler function is not needed. Because the SPI port stays alive even with the rest of the chip powered down, the part can be awakened again by simply programming the port. As soon as the CSB signal goes high, the part turns on again. Note that this takes a fair amount of time because of the external capacitor on the LODC pin. It takes ~10 s to 15 s with the recommended 0.1 F decoupling capacitor. The decoupling capacitor on this pin is intended to reduce bias noise contribution in the LO divider chain. The user can experiment with the value of this decoupling capacitor to determine the smallest value without degrading the dynamic range within the frequency band of interest. The shift direction is to the right with MSB first. Because the latch is implemented with D-flip-flops (DFF) and CSB acts as the clock to the latch, any time that CSB is low, the latch flipflops monitor the shift register outputs. As soon as CSB goes high, the data present in the register is latched. New data can be loaded into the shift register at any time. Twenty bits are required to program each AD8339; the data is transferred from the register to the latch when CSB goes high. Depending on the data, the corresponding channels are enabled, and the phases are selected. Figure 57 illustrates the timing for two sequentially programmed devices. The SPI also has an additional pin that can be used in a test mode or as a quick way to reset the SPI and depower the chip. All bits in both the shift register and the latch are reset low when the RSTS pin is pulled above ~1.5 V. For quick testing without the need to program the SPI, the voltage on the RSTS pin should be first pulled high and then pulled to -1.4 V. This enables all four channels in the phase (I = 1, Q = 0) state (all phase bits are 0000); the channel enable bits are all set to 1. This is an untested threshold not intended for continuous operation. Note that the data is latched into the register flip-flops on the rising edge of SCLK. SDO also transitions on the rising edge of SCLK. TO PHASE SELECT AND BIAS BLOCKS FOR TO CHANNEL 1 PHASE TO CHANNEL 2 PHASE TO CHANNEL 3 PHASE TO CHANNEL 4 PHASE CHANNEL ENABLES SELECT BLOCK SELECT BLOCK SELECT BLOCK SELECT BLOCK PH SEL CH 1 PH SEL CH 2 PH SEL CH 3 PH SEL CH 4 LATCH LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB CH 1 CH 2 CH 3 CH 4 CH 1 CH 1 CH 1 CH 1 CH 2 CH 2 CH 2 CH 2 CH 3 CH 3 CH 3 CH 3 CH 4 CH 4 CH 4 CH 4 SHIFT REGISTER MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB CH 1 CH 2 CH 3 CH 4 CH 1 CH 1 CH 1 CH 1 CH 2 CH 2 CH 2 CH 2 CH 3 CH 3 CH 3 CH 3 CH 4 CH 4 CH 4 CH 4 SDO TO NEXT AD8339 SDI TO OTHER AD8339s SCLK 06587-054 TO OTHER AD8339s ENABLE BITS CSB RSTS Figure 56. Serial Interface Showing the 20-Bit Shift Register and Latch t8 t1 CSB t2 t7 SCLK t3 t5 t6 SDI t4 DATA FOR AD8339 #2 DATA FOR AD8339 #1 Figure 57. Timing Diagram Rev. A | Page 23 of 36 06587-055 SDO AD8339 APPLICATIONS INFORMATION The AD8339 is the key component of a phase shifter system that aligns time-skewed information contained in RF signals. Combined with a variable gain amplifier (VGA) and a low noise amplifier (LNA) as in the AD8332/AD8334/AD8335 VGA family, the AD8339 forms a complete analog receiver for a high performance ultrasound CW Doppler system. LOGIC INPUTS AND INTERFACES The SDI, SCLK, SDO, CSB, and RSET pins are CMOS compatible to 1.8 V. The threshold of the RSTS pin is 1.5 V with a hysteresis of 0.3 V. Each logic input pin is Schmitt trigger activated, with a threshold centered at ~1.3 V and a hysteresis of 0.1 V around this value. The only logic output, SDO, generates a signal that has a logic low level of ~0.2 V and a logic high level of ~1.9 V to allow for easy interfacing to the next AD8339 SDI input. Note that the capacitive loading for the SDO pin should be kept as small as possible (<5 pF), ideally only a short trace to the SDI pin of the next chip. The output slew is limited to approximately 500 A, which limits the speed when a large capacitor is connected. Excessive values of parasitic capacitance on the SDO pin can affect the timing and loading of data into the SDI input of the next chip. RESET INPUT The RSET pin is used to synchronize the LO dividers in AD8339 arrays. Because they are driven by the same internal LO, the four channels in any AD8339 are inherently synchronous. However, when multiple AD8339s are used, it is possible that their dividers wake up in different phase states. The function of the RSET pin is to phase align all the LO signals in multiple AD8339s. The 4LO divider of each AD8339 can be initiated in one of four possible states: 0, 90, 180, or 270 relative to other AD8339s. The internally generated I/Q signals of each AD8339 LO are always at a 90 angle relative to each other, but a phase shift can occur during power-up between the dividers of multiple AD8339s used in a common array. The LO divider reset function has been improved in the AD8339 compared with the AD8333. The RSET pin still provides an asynchronous reset of the LO dividers by forcing the internal LO to hang; however, in the AD8339, the LO reset function is fast and does not require a shutdown of the 4LO input signal. The RSET mechanism also allows the measurement of nonmixing gain from the RF input to the output. The rising edge of the active high RSET pulse can occur at any time; however, the duration should be 20 ns minimum. When the RSET pulse transitions from high to low, the LO dividers are reactivated on the next rising edge of the 4LO clock. To guarantee synchronous operation of an array of AD8339s, the RSET pulse must go low on all devices before the next rising edge of the 4LO clock. Therefore, it is best to have the RSET pulse go low on the falling edge of the 4LO clock; at the very least, the tSETUP should be 5 ns. An optimal timing setup is for the RSET pulse to go high on a 4LO falling edge and to go low on a 4LO falling edge; this gives 10 ns of setup time even at a 4LO frequency of 50 MHz (12.5 MHz internal LO). Check the synchronization of multiple AD8339s using the following procedure: 1. 2. 3. 4. 5. Activate at least one channel per AD8339 by setting the appropriate channel enable bit in the serial interface. Set the phase code of all AD8339 channels to the same logic state, for example, 0000. Apply the same test signal to all devices to generate a sine wave in the baseband output and measure the output of one channel per device. Apply an RSET pulse to all AD8339s. Because all the phase codes of the AD8339s should be the same, the combined signal of multiple devices should be N times greater than a single channel. If the combined signal is less than N times one channel, one or more of the LO phases of the individual AD8339s is in error. LO INPUT The LO input is a high speed, fully differential analog input that responds to differences in the input levels (and not logic levels). The LO inputs can be driven with a low common-mode voltage amplifier, such as the National Semiconductor(R) DS90C401 LVDS driver. The graph in Figure 22 shows the range of common-mode voltages. Logic families such as TTL or CMOS are unsuitable for direct coupling to the LO input. Rev. A | Page 24 of 36 AD8339 EVALUATION BOARD The AD8339-EVALZ requires bipolar 5 V power supplies. A 3.3 V on-board regulator provides power for the USB and EEPROM devices. The AD8339 is configured using the software provided on the CD included with the evaluation board, or using an external digital pattern generator via the 20-pin flat-cable connector P1. 06587-157 Figure 58 is a photograph of the AD8339 evaluation board; the schematic diagrams are shown in Figure 63, Figure 64, and Figure 65. Four single-ended RF inputs can be phase aligned using the LNA inputs of an AD8334 and the 16 phase adjustment options of the AD8339. The RF input signals can be derived from three sources, user selectable by jumpers. Test points enable signal tracing at various circuit nodes. Figure 58. AD8339 Evaluation Board Rev. A | Page 25 of 36 AD8339 CONNECTIONS TO THE BOARD Table 5 is a list of equipment required to activate the board with suggested test equipment, and Figure 61 shows a typical setup. A green LED glows (signifying that the 5 V power through the USB is present) when the computer is connected via the USB. However, the LED does not signify that the program is running. Selecting the frequency of the generators is quite simple. As an example, select an RF frequency of interest, for example, 5 MHz. Then select the 4LO frequency, which is four times the RF frequency, in this example, 20 MHz. The output frequency is 0 Hz. Note that the AD8021 outputs are at either a positive or negative dc voltage under this condition of perfect RF and 4LO frequency lock; it is more likely that the signal is slowly varying if the lock is not perfect. To detect an output, advance or retard the RF frequency by the desired baseband frequency. A baseband frequency of 10 kHz at the output results from an RF frequency of 5.01 MHz or 4.99 MHz. Table 5. Recommended Equipment List Description PC with Windows(R) XP Signal Generators (2) with Synchronizing Connectors 4-Channel Oscilloscope Power Supplies Scope Probes (4) Suggested Equipment Any recent laptop Rohde & Schwarz SMT03 or equivalent Tektronix DPO7104 or equivalent Agilent E3631A or equivalent Tektronix P6104 or equivalent TEST CONFIGURATIONS The three test configuration options for the AD8339-EVALZ are common input, independent input, and AD9271 drive. Common Input Signal Drive Figure 59 is a block diagram showing the simplest way to use the evaluation board, with a common signal applied to all four AD8339 inputs in parallel. Boards are configured this way as shipped. The inputs of each of the channels are connected in common by means of jumpers, as shown in Table 6, although they can just as easily be connected to any of the AD8334 LNA outputs. As shown in Figure 64, two pairs of summing amplifiers provide the I and Q outputs so that Channel 1 and Channel 2 can be observed independently of Channel 3 and Channel 4. Using a common input signal source as shown in Figure 61, the same input is applied to all four channels of the AD8339. To observe an output at the I or Q connectors, simply enable the appropriate channel or channels using the menu shown in Figure 62. For example, if only Channel 1 is enabled and the phases are set to 0, a waveform is seen at the I1 + I2 and Q1 + Q2 outputs. If Channel 2 is enabled with the phase also set to 0, the amplitude of the waveforms doubles. If the Channel 1 phase is 0 and the Channel 2 phase is set to 180, the output becomes zero, because the phases of the two channels cancel each other out. When using the common input drive mode, it is important that only the top two positions of P4A and P4B be used to avoid shorting the LNA outputs together. Independent Channel Drive Independent input mode means that each channel is driven by an LNA. The LNA inputs of the AD8334 can be driven by up to four independent signal generators or from a single generator. If the user chooses this mode, it is important not to connect the LNA inputs in parallel because of the active matching feature. Any standard splitter can be used. AD9271 Input Drive Connectors P3A, P3B, P4A, and P4B are configured to route input signals from the AD8334 LNA outputs or from an AD9271 evaluation board. The AD9271 is an octal ultrasound front end with a 12-bit ADC for each channel. When using an AD9271 as an input drive, consult the AD9271 data sheet for setup details. The AD9271 evaluation board is attached to the AD8339 by inserting the three plastic standoffs into the three guide holes in the AD8339-EVALZ board; all the jumpers in P3 and P4 are removed. The bottom connectors of the AD9271 board engage P3 and P4 and route the LNA outputs of the AD9271 to the AD8339. Figure 60 is a photograph of the two boards attached. Table 6. P3, P4 Input Jumper Configuration Common Input P4A-1 to P4B-1, top two positions (2) RF12N, RF12P, RF23N, RF23P, RF34N, RF34P Rev. A | Page 26 of 36 Independent Input P3A-1 to P3B-1, P4A-1 to P4B-1 P3A-1 to P3B-1, P4A-1 to P4B-1, all positions (8) AD8339 AD8334 LNA AD8339 I1 CH 1 RF Q1 Q1 + Q2 I TO V I1 + I2 I2 CH 2 RF Q2 I TO V I3 CH 3 RF Q3 I TO V I3 + I4 I4 CH 4 RF Q4 Q3 + Q4 I TO V 06587-057 Figure 59. AD8339 Test Configuration--Common Input Signal Drive 06587-159 COMMON SIGNAL PATH Figure 60. AD8339-EVALZ with AD9271 Evaluation Board Attached as Input Source Rev. A | Page 27 of 36 AD8339 TOP: SIGNAL GENERATOR FOR 4LO INPUT (FOR EXAMPLE, 20MHz, 1Vp-p) BOTTOM: SIGNAL GENERATOR FOR RF INPUT (FOR EXAMPLE, 5.01MHz) POWER SUPPLY PERSONAL COMPUTER SYNCHRONIZE GENERATORS USB CABLE +5V -5V 4LO INPUT 06587-059 OUTPUTS Figure 61. AD8339-EVALZ Typical Test Setup Rev. A | Page 28 of 36 AD8339 Using the SPI Port The menu consists of an array of options that are self-explanatory. Channels are enabled or disabled by selecting the channels in the Channel Enable list, and the 16 phase options are selected from the list box for each of the channels. Channel and phase selection are accessed via the SPI port on the AD8339, and the evaluation board provides two means of access. If it is desired to exercise the SPI input with custom waveforms, the SDI, SCLK, and CSB pins are available at the auxiliary connector P1. A digital pattern generator can be programmed in conformance with the timing diagram shown in Figure 57. Hardwired Jumpers The most convenient way to select channels and phase delays is through the USB port of a PC using the executable program provided on the CD or at the Analog Devices, Inc., website. Copy the .EXE and .MSI files into the same folder on the PC. Double-click the .EXE file to install the program and place a shortcut on the desktop. Double-clicking the desktop icon opens the control menu, as shown in Figure 62. As shipped, the evaluation board is configured to connect all the AD8339 RF inputs to a single LNA output. In this configuration, the phases of the four channels can be shifted throughout the full range and the outputs can be viewed on a multichannel scope using one of the channels as a reference. To operate all the LNA channels independently, it is only necessary to move the input shorting jumpers to the channel RF outputs. 06587-060 Hardwired jumpers provide for interconnection of channels and as a means for measuring output voltages at various strategic nodes (see Table 7). Figure 62. SPI Software Control Menu Table 7. Jumper and Header List Jumper, Header CSB CSBG EN12, EN34 I1234 Q1234 RF1 to RF4 RSTS RSET SCLK SDI SLKG 4LO Description Connects the chip select input to the connector or the USB inputs--normally connected to USB (test) Grounds the CSB input--shipped omitted Enables or disables Channel 1 through Channel 4--boards shipped enabled Sums all four I-channel current outputs together--shipped omitted Sums all four Q-channel current outputs together--shipped omitted Test points for the LNA outputs--a differential probe fits these Resets the SPI input--shipped omitted Resets the local oscillator input--shipped omitted Connects the serial clock input to the connector or to the USB inputs--normally connected to USB (test) Connects the serial data input to the connector or to the USB input--normally connected to USB (test) Grounds the serial clock input--shipped omitted Test pins for the 4LO level shifter output--a differential probe fits these Rev. A | Page 29 of 36 AD8339 LOP1 LON1 RF1 C67 0.1F 49 50 VCM1 51 EN34 52 EN12 53 CLMP12 54 GAIN12 55 VPS1 VOL3 37 VPS34 36 COM3X VOL4 35 NC LMD3 VOH4 34 NC C62 0.1F IN4 IN4S C12 22pF CFB4 18nF C63 0.1F C50 0.1F RFB4 274 R47 20 R48 20 L12 120nH C64 0.1F 5V 33 NC VCM3 L15 120nH C56 0.1F C85 0.1F RF4 5V LON4 LOP4 Figure 63. Schematic--LNA Section Rev. A | Page 30 of 36 06587-061 L9 120nH COM34 5V C65 0.1F C57 0.1F R64 0 C49 0.1F 31 INH3 VCM4 LON3 L14 120nH 32 LOP3 C55 0.1F IN3 56 38 NC IN3S L8 120nH VIN1 58 LON1 LOP1 59 60 COM1X 61 LMD1 62 VOH3 C10 22pF C61 0.1F INH1 VIP3 30 16 39 HILO 15 C48 0.1F COM34 17 COM3 CFB3 18nF 45 VIN3 29 RFB3 274 VPS12 40 CLMP34 14 46 NC NC VPS3 28 LON3 13 VOL1 41 U1 AD8334 GAIN34 RF3 12 47 NC MODE VPS2 27 R45 20 VOH1 42 VPS4 LOP3 11 C47 0.1F 48 COM12 26 R46 20 10 COM12 VIN2 VIN4 C46 0.1F 9 VCM2 43 NC 25 C88 0.1F C59 0.1F VOH2 VIP4 8 C87 0.1F L17 120nH R63 0 VIP2 24 5V 7 C58 0.1F 44 NC LOP4 L16 120 nH 6 C66 0.1F VOL2 23 C45 0.1F EN34 LOP2 LON4 5 C44 0.1F 22 LOP2 COM4X R43 20 RF2 DIS LON2 21 4 EN12 DIS COM2X LMD4 LON2 3 EN PIN 1 IDENTIFIER INH4 R44 20 LMD2 19 C43 0.1F COM4 2 RFB2 274 INH2 18 CFB2 18nF 63 COM2 1 COM1 64 C8 22pF L13 120nH C53 0.1F C54 0.1F C68 0.1F C60 0.1F IN2S 5V EN C86 0.1F C6 22pF L7 120nH IN2 RFB1 274 57 IN1S CFB1 18nF R49 20 VIP1 L10 120nH 20 IN1 5V R50 20 AD8339 5V R1 1k R3 1k R4 1k CSB CSBG CSB SDO SCLK SLKG SCLK SDI SDI RSTS RF2N C16 0.1F R69 2.8k 5V 9 8 10 1 R62 0 R59 0 R60 0 R58 0 TP_RF1N TP_RF2P TP_RF2N TP_RF3P 6 R61 0 TP_RF1P 5 VNEG 31 Q1OP 32 I1OP 33 RSET 34 VPOS 35 C23 VA 0.1F U4 1 AD8021 8 R18 0 3 4 C30 0.1F 4LO 4LON 25 VNEG 20 I4OP Q4OP 19 LODC 18 VNEG C29 0.1F I3OP 22 R8 0 21 R7 0 Q3OP + R6 0 C20 0.1F 5V I1234 7 4 1 10 7 4 C21 VA 0.1F 2 7 1 U5 6 AD8021 8 5 C51 0.1F 2 7 1 U6 8 AD8021 COMPONENTS SHOWN IN GRAY ARE NOT INSTALLED ENGAGES WITH CONNECTOR ON AD9271 EVAL BOARD 2 + 3 4 6 5 R38 Q3 + Q4 0 C33 5PF -VA U7 1 DS90C401M 7 8 6 5 3 06587-062 PROUTN4 6 PROUTP4 9 PROUTN3 12 PROUTP3 3 PROUTN2 PROUTP2 6 PROUTN1 PROUTP1 9 R42 787 C32 2. 2nF R2 0 P3 12 R11 0 I3 + I4 C80 5PF -VA C22 0.1F VA R54 49. 9 C79 2. 2nF R9 0 I4OP LOP C52 0.1F 1 2 P4 C82 5PF -VA R10 787 C34 5V 0.1 F 10 5 + 3 4 VNEG R14 0 I1 + I2 VPOS U7 DS90C401M R28 C28 3 3.48k 0.1F R27 4 100 R37 1.5k 2 Q4OP R30 4.22k P5 11 COMMON 1 LNA 12 TO 4 RF INPUTS R57 R56 R51 0 0 0 6 C24 0.1F R5 0 C19 0.1F R36 5.23k 2 7 R19 0 4LOP 26 17 16 VPOS COMM RF4N 14 15 VPOS R33 2.8k C84 5PF C81 2. 2nF R12 0 TP_RF4N RF23P TP_RF4P 7 RF3N RF3P RF23N 3 R34 2.8k SDO C18 0.1F RF34P RF2P RF1N RF2N 2 13 SDO SDO RF34N 11 12 VPOS 4 RF4P RF3N SDO-TP RF12N COMM 36 DUT AD8339 VNEG 23 C17 0.1F RF1P RF1N 37 VPOS 27 R17 Q1 + Q2 0 5 - Q2OP 30 8 VPOS VPOS RF12P C27 R20 0.1F 0 VNEG 24 RF3N R65 4.22k R21 0 6 -VA C26 0.1F R13 787 Q1OP VNEG 7 VPOS 10 + 3 4 VNIS 9 RF3P RF3P - 7 1 U3 AD8021 8 -5V VPOS VPOS 28 Q1234 SCLK 2 L1 120nH I2OP 29 6 CSB CSBG VPOS R70 2.8k PIN 1 IDENTIFIER C83 2. 2nF I1OP R15 0 COMM 5 SLKG R67 5.23k 17 19 3 COMM 4 5V 18 20 R16 787 C25 0.1F VA 2 RF2P RF2P R66 4.22k RF1P 38 1 RF2 N SDI RSTS R71 2.8k R72 2.8k 39 40 R68 5.23k 11 13 15 C1 0.1F R31 2.8k R30 4.22k 5V 12 14 16 C31 0.1F RSET VPOS RF1P RF1N R32 2.8k TP_RF3N 5V 1 3 5 7 9 L2 120nH 5V VPIS R36 5.23k P1 2 4 6 8 10 FROM AD8334 LNAS Figure 64. Schematic--IQ Demodulator and Phase Shifter Rev. A | Page 31 of 36 AD8339 5VS -5VS VAS GRN -VAS ORG GND1 BLUE PLUS C77 0.1F C13 10F + 25V + C11 10F 25V C15 10F + 25V C38 0.1F C37 0.1F C36 0.1F C35 0.1F L6 120nH TAB ADP3339AKCZ-3.3 GND6 + C14 10F 25V L5 120nH 5V 3.3V L4 120nH VA -5V GND7 L3 120nH GND8 3.3V R41 100k -VA C72 0.1F 1 Z1 24LC00/P 2 A0 A1 VCC 8 WP 7 SCL 6 3 A2 4 VSS SDA 5 PD1/FD9 PD2/FD10 PD3/FD11 PD4/FD12 PD5/FD13 PD7/FD15 PA1/INT1# AGND PA0/INT0# VCC VCC GND CTL2/FLAGC IFCLK/PE0/TOUT CTL1/FLAGB R52 22.1k R53 22.1k 16 17 18 19 C73 0.1F 20 21 22 23 R22 0 24 PB7/FD7 25 26 27 R40 100k 42 C4 22pF 41 40 CSB (SHT2) 39 SCLK (SHT2) 38 37 SDI (SHT2) NC 36 NC 35 NC 34 33 NC NC 32 31 NC 3.3V C75 0.1F 30 NC 29 NC GND CTL0/FLAGA RESERVED 15 3.3V GND DMINUS SCL R39 10k PA2/SLOE NC 14 U2 CY7C68013A-56LFXC DPLUS PB6/FD6 13 NC RESET# PA3/WU2 NC 12 3. 3V AVCC PB5/FD5 11 43 PA4/FIFOADR0 NC 10 44 AGND PB4/FD4 9 D- VBUS 5V 1 R55 3.3V 499 C71 0.1F CR1 NC 45 PA5/FIFOADR1 NC 2 NC 46 XTALIN PB3/FD3 GND 4 8 47 PA6/PKTEND NC 3 C70 0.1F NC NC 48 XTALOUT PB2/FD2 D+ 7 NC 49 PA7/FLAGD/SLCS NC 3.3V 6 NC 50 C76 0.1F GND PB1/FD1 A7 USB TYPE B C2 12pF NC 51 NC C3 12 pF 52 PB0/FD0 5 AVCC NC 53 NC 4 CLKOUT/PE1/T1OUT 3 C69 0.1F VCC 3.3V RDY0/SLRD RDY1/SLWR 3.3V Y1 24MHz 2 SDA NC VCC GND NC 1 54 PD6/FD14 NC 55 BLK TEST LOOP (9) C5 22pF C7 0.1 F 56 GND9 VCC OUT GND5 WAKEUP A6 GND4 -5VS 5VS VCC 2 1 IN OUT GND -VAS VAS 28 C74 0.1F 3.3V 3 GND3 3.3V GND + C78 0.1F P2 PD0/FD8 C9 1F L11 10V 120nH W3 GND2 MINUS R23 0 R24 0 R25 0 R26 0 Figure 65. Schematic--USB Rev. A | Page 32 of 36 06587-063 RED 5V AD8339 AD8339-EVALZ ARTWORK 06587-064 Figure 66 through Figure 69 show the artwork for the AD8339-EVALZ. 06587-065 Figure 66. AD8339-EVALZ Component Side Copper Figure 67. AD8339-EVALZ Wiring Side Copper Rev. A | Page 33 of 36 06587-066 AD8339 06587-067 Figure 68. AD8339-EVALZ Component Side Silkscreen Figure 69. AD8339-EVALZ Assembly Rev. A | Page 34 of 36 AD8339 OUTLINE DIMENSIONS 6.00 BSC SQ 0.60 MAX 0.60 MAX 31 30 TOP VIEW 0.50 BSC 5.75 BSC SQ 0.50 0.40 0.30 12 MAX 0.80 MAX 0.65 TYP 0.30 0.23 0.18 1 4.25 4.10 SQ 3.95 EXPOSED PAD (BOT TOM VIEW) 21 20 11 10 0.25 MIN 4.50 REF 0.05 MAX 0.02 NOM SEATING PLANE 40 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 072108-A PIN 1 INDICATOR 1.00 0.85 0.80 PIN 1 INDICATOR Figure 70. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm x 6 mm Body, Very Thin Quad (CP-40-1) Dimensions shown in millimeters ORDERING GUIDE Model AD8339ACPZ 1 AD8339ACPZ-R71 AD8339ACPZ-RL1 AD8339-EVALZ1 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Z = RoHS Compliant Part. Rev. A | Page 35 of 36 Package Option CP-40-1 CP-40-1 CP-40-1 AD8339 NOTES (c)2007-2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06587-0-2/09(A) Rev. A | Page 36 of 36