CS43L21 Low Power, Stereo Digital to Analog Converter FEATURES SYSTEM FEATURES 98 dB Dynamic Range (A-wtd) 24-bit Conversion -86 dB THD+N 4 kHz to 96 kHz Sample Rate Headphone Amplifier - GND Centered Multi-bit Delta Sigma Architecture - - - - - On-Chip Charge Pump Provides -VA_HP No DC-Blocking Capacitor Required 46 mW Power Into Stereo 16 @ 1.8 V 88 mW Power Into Stereo 16 @ 2.5 V -75 dB THD+N Low Power Operation - Variable Power Supplies - - Digital Signal Processing Engine - - - - Software Mode (IC(R) & SPITM Control) Hardware Mode (Stand-Alone Control) Digital Routing/Mixes: - Beep Generator - Tone Selections Across Two Octaves - Separate Volume Control - Programmable On & Off Time Intervals - Continuous, Periodic or One-Shot Beep Selections - - - Pop and Click Suppression Master or Slave Operation High-Impedance Digital Output Option (for easy MUXing between DAC and Other Data Sources) Quarter-Speed Mode - (i.e. Allows 8 kHz Fs while maintaining a flat noise floor up to 16 kHz) 1.8 V to 2.5 V PCM Serial Interface 1.8 V to 3.3 V Level Translator Mono Mixes Flexible Clocking Options Programmable Peak-Detect and Limiter Hardware Mode or I2C & SPI Software Mode Control Data 1.8 V to 2.5 V Digital & Analog 1.8 V to 3.3 V Interface Logic Power Down Management Bass & Treble Tone Control, De-Emphasis PCM Mix w/Independent Vol Control Master Digital Volume Control and Limiter Soft Ramp & Zero Cross Transitions Serial Audio Input Stereo Playback: 12.93 mW @ 1.8 V MUX Beep Generator Digital Signal Processing Engine Multibit Modulator MUX 1.8 V to 2.5 V Switched Capacitor DAC and Filter Headphone Amp - GND Centered Left HP Out Switched Capacitor DAC and Filter Headphone Amp - GND Centered Right HP Out Reset Charge Pump Register Configuration Advance Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright (c) Cirrus Logic, Inc. 2006 (All Rights Reserved) JULY '06 DS723A1 CS43L21 APPLICATIONS Portable Audio Players MD Players PDAs Personal Media Players Portable Game Consoles Smart Phones Wireless Headsets GENERAL DESCRIPTION The CS43L21 is a highly integrated, 24-bit, 96 kHz, low power stereo DAC. Based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment between 4 kHz and 96 kHz. The DAC offers many features suitable for low power, portable system applications. The DAC output path includes a digital signal processing engine. Tone Control provides bass and treble adjustment of four selectable corner frequencies. The Mixer allows independent volume control for PCM mix, as well as a master digital volume control for the analog output. All volume level changes may be configured to occur on soft ramp and zero cross transitions. The DAC also includes de-emphasis, limiting functions and a beep generator delivering tones selectable across a range of two full octaves. The stereo headphone amplifier is powered from a separate positive supply and the integrated charge pump provides a negative supply. This allows a ground-centered analog output with a wide signal swing and eliminates external DC-blocking capacitors. In addition to its many features, the CS43L21 operates from a low-voltage analog and digital core, making this DAC ideal for portable systems that require extremely low power consumption in a minimal amount of space. The CS43L21 is available in a 32-pin QFN package in both Commercial (-10 to +70 C) and Automotive grades (-40 to +85 C). The CS43L21 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please see "Ordering Information" on page 63 for complete details. 2 DS723A1 CS43L21 TABLE OF CONTENTS 1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE .................................................................. 6 1.1 Digital I/O Pin Characteristics ........................................................................................................... 8 2. TYPICAL CONNECTION DIAGRAMS ................................................................................................... 9 3. CHARACTERISTIC AND SPECIFICATION TABLES ......................................................................... 11 SPECIFIED OPERATING CONDITIONS ............................................................................................. 11 ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 11 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ) ...................................................... 12 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) ...................................................... 13 LINE OUTPUT VOLTAGE CHARACTERISTICS ................................................................................. 14 HEADPHONE OUTPUT POWER CHARACTERISTICS ...................................................................... 15 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .............................. 16 SWITCHING SPECIFICATIONS - SERIAL PORT ............................................................................... 16 SWITCHING SPECIFICATIONS - IC(R) CONTROL PORT .................................................................. 18 SWITCHING CHARACTERISTICS - SPITM CONTROL PORT ............................................................ 19 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 20 DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 20 POWER CONSUMPTION .................................................................................................................... 21 4. APPLICATIONS ................................................................................................................................... 22 4.1 Overview ......................................................................................................................................... 22 4.1.1 Architecture ........................................................................................................................... 22 4.1.2 Line & Headphone Outputs ................................................................................................... 22 4.1.3 Signal Processing Engine ..................................................................................................... 22 4.1.4 Beep Generator ..................................................................................................................... 22 4.1.5 Device Control (Hardware or Software Mode) ...................................................................... 22 4.1.6 Power Management .............................................................................................................. 22 4.2 Hardware Mode .............................................................................................................................. 23 4.3 Analog Outputs ............................................................................................................................... 24 4.3.1 De-Emphasis Filter ................................................................................................................ 24 4.3.2 Volume Controls .................................................................................................................... 25 4.3.3 Mono Channel Mixer ............................................................................................................. 25 4.3.4 Beep Generator ..................................................................................................................... 25 4.3.5 Tone Control .......................................................................................................................... 26 4.3.6 Limiter .................................................................................................................................... 26 4.3.7 Line-Level Outputs and Filtering ........................................................................................... 27 4.3.8 On-Chip Charge Pump .......................................................................................................... 28 4.4 Serial Port Clocking ........................................................................................................................ 28 4.4.1 Slave ..................................................................................................................................... 29 4.4.2 Master ................................................................................................................................... 29 4.4.3 High-Impedance Digital Output ............................................................................................. 30 4.4.4 Quarter- and Half-Speed Mode ............................................................................................. 30 4.5 Digital Interface Formats ................................................................................................................ 30 4.6 Initialization ..................................................................................................................................... 31 4.7 Recommended Power-Up Sequence ............................................................................................. 31 4.8 Recommended Power-Down Sequence ........................................................................................ 32 4.9 Software Mode ............................................................................................................................... 33 4.9.1 SPI Control ............................................................................................................................ 33 4.9.2 IC Control ............................................................................................................................. 33 4.9.3 Memory Address Pointer (MAP) ............................................................................................ 35 4.9.3.1 Map Increment (INCR) ............................................................................................... 35 5. REGISTER QUICK REFERENCE ........................................................................................................ 36 6. REGISTER DESCRIPTION .................................................................................................................. 39 6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 39 DS723A1 3 CS43L21 6.2 Power Control 1 (Address 02h) ...................................................................................................... 39 6.3 Speed Control (Address 03h) ......................................................................................................... 40 6.4 Interface Control (Address 04h) ..................................................................................................... 41 6.5 DAC Output Control (Address 08h) ................................................................................................ 41 6.6 DAC Control (Address 09h) ............................................................................................................ 42 6.7 PCMX Mixer Volume Control: PCMA (Address 10h) & PCMB (Address 11h) ..................................................................................... 44 6.8 Beep Frequency & Timing Configuration (Address 12h) ................................................................ 45 6.9 Beep Off Time & Volume (Address 13h) ........................................................................................ 46 6.10 Beep Configuration & Tone Configuration (Address 14h) ............................................................ 47 6.11 Tone Control (Address 15h) ......................................................................................................... 48 6.12 AOUTx Volume Control: AOUTA (Address 16h) & AOUTB (Address 17h) ................................................................................. 49 6.13 PCM Channel Mixer (Address 18h) .............................................................................................. 49 6.14 Limiter Threshold SZC Disable (Address 19h) ............................................................................. 50 6.15 Limiter Release Rate Register (Address 1Ah) .............................................................................. 51 6.16 Limiter Attack Rate Register (Address 1Bh) ................................................................................. 52 6.17 Status (Address 20h) (Read Only) ............................................................................................... 52 6.18 Charge Pump Frequency (Address 21h) ...................................................................................... 53 7. ANALOG PERFORMANCE PLOTS .................................................................................................... 54 7.1 Headphone THD+N versus Output Power Plots ............................................................................ 54 7.2 Headphone Amplifier Efficiency ...................................................................................................... 56 8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 57 8.1 Auto Detect Enabled ....................................................................................................................... 57 8.2 Auto Detect Disabled ...................................................................................................................... 58 9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 59 9.1 Power Supply, Grounding ............................................................................................................... 59 9.2 QFN Thermal Pad .......................................................................................................................... 59 10. DIGITAL FILTERS .............................................................................................................................. 60 11. PARAMETER DEFINITIONS .............................................................................................................. 61 12. PACKAGE DIMENSIONS ................................................................................................................. 62 THERMAL CHARACTERISTICS ........................................................................................................ 62 13. ORDERING INFORMATION ............................................................................................................. 63 14. REFERENCES .................................................................................................................................... 63 15. REVISION HISTORY ......................................................................................................................... 63 4 DS723A1 CS43L21 LIST OF FIGURES Figure 1.Typical Connection Diagram (Software Mode) ............................................................................. 9 Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 10 Figure 3.Headphone Output Test Load ..................................................................................................... 15 Figure 4.Serial Audio Interface Slave Mode Timing .................................................................................. 17 Figure 5.Serial Audio Interface Master Mode Timing ................................................................................ 17 Figure 6.Control Port Timing - IC ............................................................................................................. 18 Figure 7.Control Port Timing - SPI Format ................................................................................................ 19 Figure 8.Output Architecture ..................................................................................................................... 24 Figure 9.De-Emphasis Curve .................................................................................................................... 25 Figure 10.Beep Configuration Options ...................................................................................................... 26 Figure 11.Peak Detect & Limiter ............................................................................................................... 27 Figure 12.Master Mode Timing ................................................................................................................. 29 Figure 13.Tri-State SCLK/LRCK ............................................................................................................... 30 Figure 14.IS Format ................................................................................................................................. 30 Figure 15.Left-Justified Format ................................................................................................................. 31 Figure 16.Right-Justified Format (DAC only) ............................................................................................ 31 Figure 17.Initialization Flow Chart ............................................................................................................. 32 Figure 18.Control Port Timing in SPI Mode .............................................................................................. 33 Figure 19.Control Port Timing, IC Write ................................................................................................... 34 Figure 20.Control Port Timing, IC Read ................................................................................................... 34 Figure 21.THD+N vs. Output Power per Channel at 1.8 V (16 load) .................................................... 54 Figure 22.THD+N vs. Output Power per Channel at 2.5 V (16 load) .................................................... 54 Figure 23.THD+N vs. Output Power per Channel at 1.8 V (32 load) .................................................... 55 Figure 24.THD+N vs. Output Power per Channel at 2.5 V (32 load) .................................................... 55 Figure 25.Power Dissipation vs. Output Power into Stereo 16 ......................................................................56 Figure 26.Power Dissipation vs. Output Power into Stereo 16 (Log Detail) .......................................... 56 Figure 27.Passband Ripple ....................................................................................................................... 60 Figure 28.Stopband ................................................................................................................................... 60 Figure 29.Transition Band ......................................................................................................................... 60 Figure 30.Transition Band (Detail) ............................................................................................................ 60 LIST OF TABLES Table 1. I/O Power Rails ............................................................................................................................. 8 Table 2. Hardware Mode Feature Summary ............................................................................................. 23 Table 3. MCLK/LRCK Ratios .................................................................................................................... 29 DS723A1 5 CS43L21 Pin Name # SDIN SCLK MCLK TSTO(M/S) DGND VD VL RESET 1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE 32 31 30 29 28 27 26 25 LRCK 1 24 TSTO SDA/CDIN (MCLKDIV2) 2 23 TSTO SCL/CCLK (IS/LJ) 3 22 TSTO ADO/CS (DEM) 4 21 TSTO VA_HP 5 20 TSTO FLYP 6 19 TSTO GND_HP 7 18 TSTO FLYN 8 17 TSTO 9 10 11 12 13 14 15 16 VSS_HP AOUTB AOUTA VA AGND FILT+ VQ NIC CS43L21 Pin Description Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line. LRCK 1 SDA/CDIN (MCLKDIV2) 2 SCL/CCLK (IS/LJ) 3 AD0/CS (DEM) 4 VA_HP 5 Analog Power For Headphone (Input) - Positive power for the internal analog headphone section. FLYP 6 Charge Pump Cap Positive Node (Input) - Positive node for the external charge pump capacitor. GND_HP 7 Analog Ground (Input) - Ground reference for the internal headphone/charge pump section. FLYN 8 Charge Pump Cap Negative Node (Input) - Negative node for the external charge pump capacitor. VSS_HP 9 Negative Voltage From Charge Pump (Output) - Negative voltage rail for the internal analog headphone section. 6 Serial Control Data (Input/Output) - SDA is a data I/O in IC Mode. CDIN is the input data line for the control port interface in SPI Mode. MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry. Serial Control Port Clock (Input) - Serial clock for the serial control port. Interface Format Selection (Input) - Hardware Mode: Selects between IS & Left-Justified interface formats for the DAC. Address Bit 0 (IC) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in IC Mode; CS is the chip-select signal for SPI format. De-Emphasis (Input) - Hardware Mode: Enables/disables the de-emphasis filter. DS723A1 CS43L21 AOUTB AOUTA 10 11 Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteristics specification table VA 12 Analog Power (Input) - Positive power for the internal analog section. AGND 13 Analog Ground (Input) - Ground reference for the internal analog section. FILT+ 14 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. VQ 15 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. NIC 16 Not Internally Connected - This pin is not connected internal to the device and may be connected to ground or left "floating". No other external connection should be made to this pin. TSTO 17 Test Out (Output) - This pin is an output used for test purposes only and must be left "floating" (no connection external to the pin). TSTO 18 Test Out (Output) - This pin is an output used for test purposes only and must be left "floating" (no connection external to the pin). TSTO 19 Test Out (Output) - This pin is an output used for test purposes only and must be left "floating" (no connection external to the pin). TSTO 20 Test Out (Output) - This pin is an output used for test purposes only and must be left "floating" (no connection external to the pin). TSTO 21 22 Test Out (Output) - This pin is an output used for test purposes only and must be left "floating" (no connection external to the pin). TSTO 23 24 Test Out (Output) - This pin is an output used for test purposes only and must be left "floating" (no connection external to the pin). RESET 25 Reset (Input) - The device enters a low power mode when this pin is driven low. VL 26 Digital Interface Power (Input) - Determines the required signal level for the serial audio interface and host control port. Refer to the Recommended Operating Conditions for appropriate voltages. VD 27 Digital Power (Input) - Positive power for the internal digital section. DGND 28 Digital Ground (Input) - Ground reference for the internal digital section. Test Out (Output) - This pin is an output used for test purposes only and must be left "floating" (no connection external to the pin). TSTO (M/S) 29 MCLK 30 SCLK 31 Serial Clock (Input/Output) - Serial clock for the serial audio interface. SDIN 32 Serial Audio Data Input (Input) - Input for two's complement serial audio data. Thermal Pad DS723A1 Serial Port Master/Slave (Input/Output) - Hardware Mode Startup Option: Selects between Master and Slave Mode for the serial port. - Master Clock (Input) - Clock source for the delta-sigma modulators. Thermal relief pad for optimized heat dissipation. See "QFN Thermal Pad" on page 59. 7 CS43L21 1.1 Digital I/O Pin Characteristics The logic level for each input should not exceed the maximum ratings for the VL power supply. Pin Name SW/(HW) I/O Driver Receiver RESET Input - 1.8 V - 3.3 V SCL/CCLK (IS/LJ) Input - 1.8 V - 3.3 V, with Hysteresis SDA/CDIN (MCLKDIV2) Input/Output 1.8 V - 3.3 V, CMOS/Open Drain 1.8 V - 3.3 V, with Hysteresis AD0/CS (DEM) Input - 1.8 V - 3.3 V MCLK Input - 1.8 V - 3.3 V LRCK Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V SCLK Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V TSTO (M/S) Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V SDIN Input - 1.8 V - 3.3 V Table 1. I/O Power Rails 8 DS723A1 CS43L21 2. TYPICAL CONNECTION DIAGRAMS See Note 3 +1.8 V or +2.5 V 1 F 0.1 F 0.1 F VD VA 0.1 F +1.8 V or +2.5 V 1 F Note 3: Series resistance in the path of the power supplies must be avoided. Any voltage drop on VA_HP will directly impact the negative charge pump supply (VSS_HP) and result in clipping on the audio output . VA_HP AOUTB ** 1.5 F 1 F ** AOUTA FLYN 0.022 F See Note 4 VSS_HP 1.5 F ** 51.1 ** 1 F Headphone Out Left & Right FLYP GND_HP 470 * *Use low ESR ceramic capacitors. C CS43L21 C Rext Line Level Out Left & Right See Note 2 Rext 470 Speaker Driver Note 4 : Larger capacitors, such as 1.5 F, improves the charge pump performance (and subsequent THD+N) at the full scale output power achieved with gain (G) settings greater than default. Note 2 : For best response to Fs/2 : C= MCLK This circuitry is intended for applications where the CS43L21 connects directly to an unbalanced output of the device. For internal routing applications please see the DAC Analog Output Characteristics section for loading limitations. SCLK LRCK SDIN Digital Audio Processor Rext + 470 4Fs(Rext x 470 ) RESET SCL/CCLK SDA/CDIN AD0/CS 2k +1.8 V, +2.5 V or +3.3 V 2k See Note 1 VL 0.1 F Note 1: Resistors are required for IC control port operation FILT+ 1 F AGND 1 F VQ DGND Figure 1. Typical Connection Diagram (Software Mode) DS723A1 9 CS43L21 See Note 1 +1.8V or +2.5V 1 F 0.1 F 0.1 F VD VA 0.1 F +1.8V or +2.5V 1 F Note 1: Series resistance in the path of the power supplies (typically used for added filtering) must be avoided. Any voltage drop on VA_HP will directly impact the negative charge pump supply (VSS_HP) and result in clipping on the audio output . VA_HP AOUTB 1 F AOUTA FLYN 1 F Headphone Out Left & Right FLYP ** 0.022 F 51.1 VSS_HP ** GND_HP 470 C * *Use low ESR ceramic capacitors. CS43L21 C Rext Line Level Out Left & Right See Note 2 Rext 470 Speaker Driver MCLK SCLK LRCK SDIN VL or DGND Digital Audio Processor 47 k See Note 3 TSTO/M/S RESET IS/LJ MCLKDIV2 FILT+ DEM AGND 1 F 1 F +1.8V, 2.5 V or +3.3V VL VQ 0.1 F DGND k Note 3: Pull-up to VL (47 k for Master Mode. Pulldown to DGND for Slave Mode. Note 2 : This circuitry is intended for applications where the CS 43L21 connects directly to an unbalanced output of the device . For internal routing applications please see the DAC Analog Output Characteristics section for loading limitations . For best response to Fs/2 : C= Rext + 470 4Fs (Rext x 470 ) Figure 2. Typical Connection Diagram (Hardware Mode) 10 DS723A1 CS43L21 3. CHARACTERISTIC AND SPECIFICATION TABLES (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25 C.) SPECIFIED OPERATING CONDITIONS (AGND=DGND=0 V, all voltages with respect to ground.) Parameters Symbol Min Nom Max Units 1.65 2.37 1.65 2.37 1.65 2.37 1.65 2.37 3.14 1.8 2.5 1.8 2.5 1.8 2.5 1.8 2.5 3.3 1.89 2.63 1.89 2.63 1.89 2.63 1.89 2.63 3.47 V V V V V V V V V -10 -40 - +70 +85 C C DC Power Supply (Note 1) VA Analog Core VA_HP Headphone Amplifier Digital Core VD Serial/Control Port Interface VL Ambient Temperature Commercial - CNZ Automotive - DNZ TA ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V; all voltages with respect to ground.) Parameters Min Max Units -0.3 -0.3 -0.3 3.0 3.0 4.0 V V V Iin - 10 mA VIND -0.3 VL+ 0.4 V Ambient Operating Temperature (power applied) TA -50 +115 C Storage Temperature Tstg -65 +150 C DC Power Supply Symbol Analog VA, VA_HP VD Digital VL Serial/Control Port Interface Input Current Digital Input Voltage (Note 3) (Note 2) WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. The device will operate properly over the full range of the analog, headphone amplifier, digital core and serial/control port interface supplies. 2. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up. 3. The maximum over/under voltage is limited by the input current. DS723A1 11 CS43L21 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ) (Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 10 k, CL = 10 pF for the line output (see Figure 3), and test load RL = 16 , CL = 10 pF (see Figure 3) for the headphone output. HP_GAIN[2:0] = 011.) VA = 2.5V (nominal) VA = 1.8V (nominal) Min Typ Max Min Typ Max Parameter (Note 4) Unit RL = 10 k Dynamic Range 18 to 24-Bit A-weighted unweighted A-weighted unweighted 16-Bit 92 89 - 98 95 96 93 - 89 86 - 95 92 93 90 - dB dB dB dB - -86 -75 -35 -86 -73 -33 -78 - - -88 -72 -32 -88 -70 -30 -82 - dB dB dB dB dB dB 92 89 - 98 95 96 93 - 89 86 - 95 92 93 90 - dB dB dB dB - -75 -75 -35 -75 -73 -33 -69 - - -75 -72 -32 -75 -70 -30 -69 - dB dB dB dB dB dB Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB 16-Bit RL = 16 Dynamic Range 18 to 24-Bit A-weighted unweighted A-weighted unweighted 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB 16-Bit Other Characteristics for RL = 16 or 10 k Output Parameters (Note 5) Modulation Index (MI) Analog Gain Multiplier (G) Full-scale Output Voltage (2*G*MI*VA) (Note 5) Full-scale Output Power (Note 5) Interchannel Isolation (1 kHz) 16 10 k 0.6787 0.6787 0.6047 0.6047 Refer to Table "Line Output Voltage Characteristics" on page 14 Refer to Table "Headphone Output Power Characteristics" on page 15 80 80 95 93 - Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 Gain Drift - 100 - - 100 - Vpp mW dB dB dB ppm/ C AC-Load Resistance (RL) (Note 6) 16 - - 16 - - Load Capacitance (CL) (Note 6) - - 150 - - 150 pF 12 DS723A1 CS43L21 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) (Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz and 96 kHz; test load RL = 10 k, CL = 10 pF for the line output (see Figure 3), and test load RL = 16 , CL = 10 pF (see Figure 3) for the headphone output. HP_GAIN[2:0] = 011.) VA = 2.5V (nominal) Min Typ Max Parameter (Note 4) VA = 1.8V (nominal) Min Typ Max Unit RL = 10 k Dynamic Range 18 to 24-Bit A-weighted unweighted A-weighted unweighted 16-Bit 90 87 - 98 95 96 93 - 87 84 - 95 92 93 90 - dB dB dB dB - -86 -75 -35 -86 -73 -33 -73 - - -88 -72 -32 -88 -70 -30 -80 - dB dB dB dB dB dB 90 87 - 98 95 96 93 - 87 84 - 95 92 93 90 - dB dB dB dB - -75 -75 -35 -75 -73 -33 -67 - - -75 -72 -32 -75 -70 -30 -67 - dB dB dB dB dB dB Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB 16-Bit RL = 16 Dynamic Range 18 to 24-Bit A-weighted unweighted A-weighted unweighted 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB 16-Bit Other Characteristics for RL = 16 or 10 k Output Parameters (Note 5) Modulation Index (MI) Analog Gain Multiplier (G) Full-scale Output Voltage (2*G*MI*VA) (Note 5) Full-scale Output Power (Note 5) Interchannel Isolation (1 kHz) 16 10 k 0.6787 0.6787 0.6047 0.6047 Refer to Table "Line Output Voltage Characteristics" on page 14 Refer to Table "Headphone Output Power Characteristics" on page 15 80 80 95 93 - Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 Gain Drift - 100 - - 100 - Vpp mW dB dB dB ppm/ C AC-Load Resistance (RL) (Note 6) 16 - - 16 - - Load Capacitance (CL) (Note 6) - - 150 - - 150 pF DS723A1 13 CS43L21 LINE OUTPUT VOLTAGE CHARACTERISTICS Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 10 k, CL = 10 pF (see Figure 3). Parameter VA = 2.5V (nominal) Min Typ Max VA = 1.8V (nominal) Min Typ Max 1.95 - 2.15 - 1.41 - - - Unit AOUTx Voltage Into RL = 10 k HP_GAIN[2:0] Analog Gain (G) 000 0.3959 001 0.4571 010 0.5111 011 (default) 0.6047 100 0.7099 101 0.8399 110 1.0000 111 1.1430 14 VA_HP 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V - 1.34 1.34 1.55 1.55 1.73 1.73 2.05 2.05 2.41 2.41 2.85 2.85 3.39 3.39 (See (Note 7) 3.88 - 0.97 0.97 1.12 1.12 1.25 1.25 1.48 1.48 1.73 1.73 2.05 2.05 2.44 2.44 2.79 2.79 1.55 - Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp Vpp DS723A1 CS43L21 HEADPHONE OUTPUT POWER CHARACTERISTICS Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 16 , CL = 10 pF (see Figure 3). VA = 2.5V (nominal) Min Typ Max Parameter VA = 1.8V (nominal) Min Typ Max Unit AOUTx Power Into RL = 16 HP_GAIN[2:0] Analog Gain (G) 000 0.3959 001 0.4571 010 0.5111 011 (default) 0.6047 100 0.7099 101 0.8399 110 1.0000 111 1.1430 VA_HP 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V 1.8 V 2.5 V - 14 14 19 19 23 23 (Note 7) 32 (Note 7) 44 - - - - (Note 5, 7) 7 7 10 10 12 12 17 17 23 23 (Note 5) 32 - mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms mWrms 4. One-half LSB of triangular PDF dither is added to data. 5. Full-scale output voltage and power is determined by the gain setting, G, in register "Headphone Analog Gain (HP_GAIN[2:0])" on page 41. High gain settings at certain VA and VA_HP supply levels may cause clipping when the audio signal approaches full-scale, maximum power output, as shown in Figures 21 - 24 on page 55. 6. See Figure 3. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit topology, CL will effectively move the band-limiting pole of the amp in the output stage. Increasing this value beyond the recommended 150 pF can cause the internal op-amp to become unstable. 7. VA_HP settings lower than VA reduces the headroom of the headphone amplifier. As a result, the DAC may not achieve the full THD+N performance at full-scale output voltage and power. AOUTx 51 0.022 F C L R L AGND Figure 3. Headphone Output Test Load DS723A1 15 CS43L21 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE Parameter (Note 8) Frequency Response 10 Hz to 20 kHz Passband to -0.05 dB corner to -3 dB corner StopBand StopBand Attenuation (Note 9) Group Delay De-emphasis Error Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz Min Typ Max Unit -0.01 - +0.08 dB 0 0 - 0.4780 0.4996 Fs Fs 0.5465 - - Fs 50 - - dB - 10.4/Fs - s - - +1.5/+0 +0.05/-0.25 -0.2/-0.4 dB dB dB Notes: 8. Response is clock dependent and will scale with Fs. Note that the response plots (Figure 27 to Figure 30 on page 60) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 9. Measurement Bandwidth is from Stopband to 3 Fs. SWITCHING SPECIFICATIONS - SERIAL PORT (Inputs: Logic 0 = DGND, Logic 1 = VL.) Parameters RESET pin Low Pulse Width Symbol (Note 10) MCLK Frequency MCLK Duty Cycle (Note 11) Min Max Units 1 - ms 1.024 38.4 MHz 45 55 % 4 8 4 50 12.5 25 50 100 kHz kHz kHz kHz 45 55 % - 64*Fs Hz 45 55 % Slave Mode Input Sample Rate (LRCK) Quarter-Speed Mode Half-Speed Mode Single-Speed Mode Double-Speed Mode Fs Fs Fs Fs LRCK Duty Cycle SCLK Frequency 1/tP SCLK Duty Cycle LRCK Setup Time Before SCLK Rising Edge ts(LK-SK) 40 - ns SDIN Setup Time Before SCLK Rising Edge ts(SD-SK) 20 - ns th 20 - ns SDIN Hold Time After SCLK Rising Edge 16 DS723A1 CS43L21 // LRCK ts(LK-SK) // tP // SCLK // ts(SD-SK) SDIN // MSB // th MSB-1 Figure 4. Serial Audio Interface Slave Mode Timing Parameters Symbol Min Fs - Max Units Master Mode (Note 12) Output Sample Rate (LRCK) All Speed Modes LRCK Duty Cycle 1/tP SCLK Frequency SCLK Duty Cycle MCLK ----------------128 45 55 % - 64*Fs Hz 45 55 % 52 ns td(MSB) LRCK Edge to SDIN MSB Rising Edge SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge Hz ts(SD-SK) 20 - ns th 20 - ns 10. After powering up the CS43L21, RESET should be held low after the power supplies and clocks are settled. 11. See "Example System Clock Frequencies" on page 57 for typical MCLK frequencies. 12. See "Master" on page 29 // LRCK // tP // SCLK // td(MSB) ts(SD-SK) SDIN // MSB // th MSB-1 Figure 5. Serial Audio Interface Master Mode Timing DS723A1 17 CS43L21 SWITCHING SPECIFICATIONS - IC(R) CONTROL PORT (Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL = 30 pF) Parameter Symbol Min Max Unit SCL Clock Frequency fscl - 100 kHz RESET Rising Edge to Start tirs 500 - ns Bus Free Time Between Transmissions tbuf 4.7 - s Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - s Clock Low time tlow 4.7 - s Clock High Time thigh 4.0 - s Setup Time for Repeated Start Condition tsust 4.7 - s thdd 0 - s tsud 250 - ns Rise Time of SCL and SDA trc - 1 s Fall Time SCL and SDA tfc - 300 ns Setup Time for Stop Condition tsusp 4.7 - s Acknowledge Delay from SCL Falling tack 300 3450 ns SDA Hold Time from SCL Falling (Note 13) SDA Setup time to SCL Rising 13. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. RST t irs Stop Repeated Start Start Stop SDA t buf t t high t hdst tf hdst t susp SCL t low t hdd t sud t sust tr Figure 6. Control Port Timing - IC 18 DS723A1 CS43L21 SWITCHING CHARACTERISTICS - SPITM CONTROL PORT (Inputs: Logic 0 = DGND, Logic 1 = VL) Parameter Symbol Min Max Units CCLK Clock Frequency fsck 0 6.0 MHz RESET Rising Edge to CS Falling tsrs 20 - ns CS Falling to CCLK Edge tcss 20 - ns CS High Time Between Transmissions tcsh 1.0 - s CCLK Low Time tscl 66 - ns CCLK High Time tsch 66 - ns CDIN to CCLK Rising Setup Time tdsu 40 - ns CCLK Rising to DATA Hold Time (Note 14) tdh 15 - ns Rise Time of CCLK and CDIN (Note 15) tr2 - 100 ns Fall Time of CCLK and CDIN (Note 15) tf2 - 100 ns 14. Data must be held for sufficient time to bridge the transition time of CCLK. 15. For fsck <1 MHz. RST tsrs CS tcsh tcss tsch tscl tr2 CCLK tf2 tdsu tdh CDIN Figure 7. Control Port Timing - SPI Format DS723A1 19 CS43L21 DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to ground.) Parameters Min Typ Max Units Nominal Voltage Output Impedance DC Current Source/Sink (Note 16) - 0.5*VA 23 - 10 V k A FILT+ - VA - V - -0.8*(VA_HP) 10 V A - 60 - dB VQ Characteristics VSS_HP Characteristics Nominal Voltage DC Current Source Power Supply Rejection Ratio (PSRR) (Note 17) 1 kHz 16. The DC current draw represents the allowed current draw from the VQ pin due to typical leakage through electrolytic de-coupling capacitors. 17. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also increase the PSRR. DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS Parameters (Note 18) Input Leakage Current Symbol Min Max Units Iin - 10 A - 10 pF Input Capacitance 1.8 V - 3.3 V Logic High-Level Output Voltage (IOH = -100 A) VOH VL - 0.2 - V Low-Level Output Voltage (IOL = 100 A) VOL - 0.2 V High-Level Input Voltage VIH 0.68*VL - V Low-Level Input Voltage VIL - 0.32*VL V 18. See "Digital I/O Pin Characteristics" on page 8 for serial and control port power rails. 20 DS723A1 CS43L21 POWER CONSUMPTION See (Note 19) Operation PDN_DACB PDN_DACA BIT 4 BIT 3 BIT 2 BIT 1 PDN BIT 3 BIT 2 BIT 1 Power Ctl. Registers 02h 03h Typical Current (mA) iVA_HP iVA iVD iVL (Note 22) Total Power (mWrms) V 1 x x x x x x x x x x 1.8 2.5 0 0 0 0 0 Off (Note 20) 0 0 0 0 0 2 Standby (Note 21) x x x x x x 1 x x x 1.8 2.5 0 0.01 0.02 0 0.05 0 0.01 0.03 0 0.10 5 Mono Playback 1 0 1 1 1 1 0 1 1 1 1.8 2.5 1.66 1.40 2.35 0.01 9.74 2.03 1.71 3.48 0.02 18.08 0 0 1 1 1 1 0 1 1 1 1.8 2.5 2.77 2.05 2.35 0.01 12.93 3.21 2.50 3.49 0.02 23.02 6 Stereo Playback 19. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample rate = 48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode and master/slave operation. 20. RESET pin 25 held LO, all clocks and data lines are held LO. 21. RESET pin 25 held HI, all clocks and data lines are held HI. 22. VL current will slightly increase in master mode. DS723A1 21 CS43L21 4. APPLICATIONS 4.1 4.1.1 Overview Architecture The CS43L21 is a highly integrated, low power, 24-bit audio D/A comprised of stereo digital-to-analog converters (DAC) designed using multi-bit delta-sigma techniques. The DAC operates at an oversampling ratio of 128Fs. The D/A operates in one of four sample rate speed modes: Quarter, Half, Single and Double. It accepts and is capable of generating serial port clocks (SCLK, LRCK) derived from an input Master Clock (MCLK). 4.1.2 Line & Headphone Outputs The analog output portion of the D/A includes a headphone amplifier capable of driving headphone and line-level loads. An on-chip charge pump creates a negative headphone supply allowing a full-scale output swing centered around ground. This eliminates the need for large DC-Blocking capacitors and allows the amplifier to deliver more power to headphone loads at lower supply voltages. Eight gain settings for the headphone amplifier are available. 4.1.3 Signal Processing Engine A signal processing engine is available to process serial input D/A data before output to the DAC. The D/A data has independent volume controls and mixing functions such as mono mixes and left/right channel swaps. A Tone Control provides bass and treble at four selectable corner frequencies. An automatic level control provides limiting capabilities at programmable attack and release rates, maximum thresholds and soft ramping. A 15/50 s de-emphasis filter is also available at a 44.1 kHz sample rate. 4.1.4 Beep Generator A beep may be generated internally at select frequencies across approximately two octave major scales and configured to occur continuously, periodically or at single time intervals controlled by the user. Volume may be controlled independently. 4.1.5 Device Control (Hardware or Software Mode) In Software Mode, all functions and features may be controlled via a two-wire IC or three-wire SPI control port interface. In Hardware Mode, a limited feature set may be controlled via stand-alone control pins. 4.1.6 Power Management Two Software Mode control registers provide independent power-down control of the DAC, allowing operation in select applications with minimal power consumption. 22 DS723A1 CS43L21 4.2 Hardware Mode A limited feature-set is available when the D/A powers up in Hardware Mode (see "Recommended PowerUp Sequence" section on page 31) and may be controlled via stand-alone control pins. Table 2 shows a list of functions/features, the default configuration and the associated stand-alone control available. Hardware Mode Feature/Function Summary Feature/Function Default Configuration Stand-Alone Control Note Powered Up Powered Up - - Enabled - - Auto-Detect Speed Mode Single-Speed Mode - - MCLK Divide (Selectable) "MCLKDIV2" pin 2 Serial Port Master / Slave Selection (Selectable) "M/S" pin 29 DAC (Selectable) "IS/LJ" pin 3 HP Gain AOUTx Volume Invert Soft Ramp Zero Cross G = 0.6047 0 dB Disabled Enabled Disabled - - (Selectable) "DEM" pin 4 see Section on page 24 Disabled Disabled Disabled Disabled - - Data Input (PCM) to DAC - - PCMA = L; PCMB = R - - (64xFs)/7 - - Power Control Device DACx Auto-Detect Speed Mode Serial Port Slave Serial Port Master Interface Control DAC Volume & Gain DAC De-Emphasis Signal Processing Engine (SPE) Mix Beep Tone Control Peak Detect and Limiter Data Selection Channel Mix Charge Pump Frequency DAC see Section 4.4 on page 28 see Section 4.4 on page 28 see Section 4.5 on page 30 Table 2. Hardware Mode Feature Summary DS723A1 23 CS43L21 4.3 Analog Outputs AOUTA and AOUTB are the ground-centered line or headphone outputs. Various signal processing options are available, including an internal Beep Generator. The desired path to the DAC must be selected using the DATA_SEL[1:0] bits. Software Controls: "DAC Control (Address 09h)" on page 42. ARATE[7:0] RRATE[7:0] MAX[2:0] MIN[2:0] LIM_SRDIS LIM_ZCDIS LIMIT_EN SIGNAL PROCESSING ENGINE (SPE) OUTA_VOL[7:0] OUTB_VOL[7:0] +12dB/-102dB 0.5dB steps PCM Serial Interface Chnl Vol. Settings DEEMPH MUTE_PCMMIXA MUTE_PCMMIXB PCMMIXA_VOL[6:0] PCMMIXB_VOL[6:0] PCMA[1:0] PCMB[1:0] +12dB/-51.5dB 0.5dB steps Demph Limiter VOL TC_EN Channel Swap VOL DAC_SZC[1:0] DACA_MUTE DACB_MUTE INV_DACA INV_DACB DAC_SNGVOL AMUTE BPVOL[4:0] 0dB/-50dB 2.0dB steps Peak Detect Bass/ Treble/ Control DATA_SEL[1:0] 01 PDN_DACA PDN_DACB Switched Capacitor DAC and Filter HP_GAIN[2:0] Headphone Amp - GND Centered Left/Right HP Out 00 BASS_CF[1:0] TREB_CF[1:0] Charge Pump BASS[3:0] TREB[3:0] +12.0dB/-10.5dB 1.5dB steps CHRG_FREQ[3:0] VOL OFFTIME[2:0] ONTIME[3:0] FREQ[3:0] REPEAT BEEP Beep Generator Figure 8. Output Architecture 4.3.1 De-Emphasis Filter The CODEC includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter response is shown in Figure 9. The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 s pre-emphasis equalization as a means of noise reduction. De-emphasis is only available in Single-Speed Mode. Software Controls: "DAC Control (Address 09h)" on page 42. Pin Hardware Control: 24 Setting "DEM" pin 4. LO HI Selection No De-Emphasis De-Emphasis Applied DS723A1 CS43L21 Gain dB T1=50 s 0dB T2 = 15 s -10dB F1 3.183 kHz F2 Frequency 10.61 kHz Figure 9. De-Emphasis Curve 4.3.2 Volume Controls Two digital volume control functions offer independent control of the SDIN signal path into the mixer as well as a combined control of the mixed signals. The volume controls are programmable to ramp in increments of 0.125 dB at a rate controlled by the soft ramp/zero cross settings. The signal paths may also be muted via mute control bits. When enabled, each bit attenuates the signal to its maximum value. When the mute bit is disabled, the signal returns to the attenuation level set in the respective volume control register. The attenuation is ramped up and down at the rate specified by the DAC_SZC[1:0] bits. Software Controls: 4.3.3 "PCMX Mixer Volume Control: PCMA (Address 10h) & PCMB (Address 11h)" on page 44"AOUTx Volume Control: AOUTA (Address 16h) & AOUTB (Address 17h)" on page 49"DAC Output Control (Address 08h)" on page 41 Mono Channel Mixer A channel mixer may be used to create a mix of the left and right channels for the SDIN data. This mix allows the user to produce a MONO signal from a stereo source. The mixer may also be used to implement a left/right channel swap. Software Controls: 4.3.4 "PCM Channel Mixer (Address 18h)" on page 49. Beep Generator The Beep Generator generates audio frequencies across approximately two octave major scales. It offers three modes of operation: Continuous, multiple and single (one-shot) beeps. Sixteen on and eight off times are available. Note: The Beep is generated before the limiter and may affect desired limiting performance. If the limiter function is used, it may be required to set the Beep volume sufficiently below the threshold to prevent the peak detect from triggering. Since the master volume control, AOUTx_VOL[7:0], will affect the Beep volume, DAC volume may alternatively be controlled using the PCMMIXx_VOL[6:0] bits. Software Controls: DS723A1 "Beep Frequency & Timing Configuration (Address 12h)" on page 45, "Beep Off Time & Volume (Address 13h)" on page 46, "Beep Configuration & Tone Configuration (Address 14h)" on page 47 25 CS43L21 REPEAT = '1' BEEP = '1' CONTINUOUS BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) and remains on until REPEAT is cleared. REPEAT = '1' BEEP = '0' MULTI-BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) for the duration of ONTIME and turns off for the duration of OFFTIME. On and off cycles are repeated until REPEAT is cleared. REPEAT = '0' BEEP = '1' SINGLE-BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) for the duration of ONTIME. BEEP must be cleared and set for additional beeps. ... BPVOL[4:0] FREQ[3:0] ONTIME[3:0] OFFTIME[2:0] Figure 10. Beep Configuration Options 4.3.5 Tone Control Shelving filters are used to implement bass and treble (boost and cut) with four selectable corner frequencies. Boosting will affect peak detect and limiting when levels exceed the maximum threshold settings. Software Controls: 4.3.6 "Tone Control (Address 15h)" on page 48. Limiter When enabled, the limiter monitors the digital input signal before the DAC modulator, detects when levels exceed the maximum threshold settings and lowers the AOUT volume at a programmable attack rate below the maximum threshold. When the input signal level falls below the maximum threshold, the AOUT volume returns to its original level set in the Volume Control register at a programmable release rate. Attack and release rates are affected by the DAC soft ramp/zero cross settings and sample rate, Fs. Limiter soft ramp and zero cross dependency may be independently enabled/disabled. Recommended settings: Best limiting performance may be realized with the fastest attack and slowest release setting with soft ramp enabled in the control registers. The "cushion" bits allow the user to set a threshold slightly below the maximum threshold for hysteresis control - this cushions the sound as the limiter attacks and releases. Note: 1. When the Limiter is enabled, the AOUT Volume is automatically controlled and should not be adjusted manually. Alternative volume control may be realized using the PCMMIXx_VOL[6:0] bits. 2. The Limiter maintains the output signal between the CUSH and MAX thresholds. As the digital input signal level changes, the level-controlled output may not always be the same but will always fall within the thresholds. Software Controls: 26 "Limiter Release Rate Register (Address 1Ah)" on page 51, "Limiter Attack Rate Register (Address 1Bh)" on page 52, "DAC Control (Address 09h)" on page 42 DS723A1 CS43L21 Input MAX[2:0] Limiter AOUTx_VOL[7:0] volume control should NOT be adjusted manually when Limiter is enabled. ATTACK/RELEASE SOUND CUSHION Volume Output (after Limiter) CUSH[2:0] MAX[2:0] ARATE[5:0] RRATE[5:0] Figure 11. Peak Detect & Limiter 4.3.7 Line-Level Outputs and Filtering The CODEC contains on-chip buffer amplifiers capable of producing line level single-ended outputs on AOUTA and AOUTB. These amplifiers are ground centered and do not have any DC offset. A load stabilizer circuit, shown in the "Typical Connection Diagram (Software Mode)" on page 9 and the "Typical Connection Diagram (Hardware Mode)" on page 10, is required on the analog outputs. This allows the DAC amplifiers to drive line or headphone outputs. Also shown in the Typical Connection diagrams is the recommended passive output filter to support higher impedances such as those found on the inputs to operational amplifiers. "Rext", shown in the typical connection diagrams, is the input impedance of the receiving device. The invert and digital gain controls may be used to provide phase and/or amplitude compensation for an external filter. The delta-sigma conversion process produces high frequency noise beyond the audio passband, most of which is removed by the on-chip analog filters. The remaining out-of-band noise can be attenuated using an off-chip low pass filter. Software Controls: DS723A1 "DAC Output Control (Address 08h)" on page 41, "AOUTx Volume Control: AOUTA (Address 16h) & AOUTB (Address 17h)" on page 49. 27 CS43L21 4.3.8 On-Chip Charge Pump An on-chip charge pump derives a negative supply voltage from the VA_HP supply. This provides dual rail supplies allowing a full-scale output swing centered around ground and eliminates the need for large, DC-blocking capacitors. Added benefits include greater pop suppression and improved low frequency (bass) response. Note: Series resistance in the path of the power supplies must be avoided. Any voltage drop on the VA_HP supply will directly impact the derived negative voltage on the charge pump supply, VSS_HP, and may result in clipping. The FLYN and FLYP pins connect to internal switches that charges and discharges the external capacitor attached, at a default switching frequency. This frequency may be adjusted in the control port registers. Increasing the charge-pumping capacitor will slightly decease the pumping frequency. The capacitor connected to VSS_HP acts as a charge reservoir for the negative supply as well as a filter for the ripple induced by the charge pump. Increasing this capacitor will decrease the ripple on VSS_HP. Refer to the typical connection diagrams in Figure 1 on page 9 or Figure 2 on page 10 for the recommended capacitor values for the charge pump circuitry. Software Controls: 4.4 "Charge Pump Frequency (Address 21h)" on page 53. Serial Port Clocking The D/A serial audio interface port operates either as a slave or master. It accepts externally generated clocks in slave mode and will generate synchronous clocks derived from an input master clock (MCLK) in master mode. The frequency of the MCLK must be an integer multiple of, and synchronous with, the system sample rate, Fs. The LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked into or out of the device. The SPEED and MCLKDIV2 software control bits or the M/S and MCLKDIV2 stand-alone control pins, configure the device to generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode. The value on the M/S pin is latched immediately after powering up in Hardware Mode. Software Control: , "DAC Control (Address 09h)" on page 42. Pin Hardware Control: "M/S" pin 29 "MCLKDIV2" pin 2 28 Setting Selection 47 k Pull-down Slave 47 k Pull-up Master LO No Divide HI MCLK is divided by 2 prior to all internal circuitry. DS723A1 CS43L21 4.4.1 Slave LRCK and SCLK are inputs in Slave Mode. The speed of the D/A is automatically determined based on the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will then require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 stand-alone control pin. Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed mode must be selected using the SPEED[1:0] bits. Auto-Detect QSM HSM SSM DSM Disabled (Software Mode only) 512, 768, 1024, 1536, 2048, 3072 256, 384, 512, 768, 1024, 1536 128, 192, 256, 384, 512, 768 128, 192, 256, 384 512, 768, 1024*, 1536* 256, 384, 512*, 768* 128, 192, 256*, 384* 1024, 1536, 2048*, 3072* *MCLKDIV2 must be enabled. Enabled Table 3. MCLK/LRCK Ratios 4.4.2 Master LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled). In Hardware Mode the D/A operates in single-speed only. In Software Mode, the D/A operates in either quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits. /1 0 /2 1 / 128 Double Speed 00 / 128 Single Speed 01 / 256 Half Speed 10 / 512 Quarter Speed 11 MCLK LRCK Output (Equal to Fs) SPEED[1:0] MCLKDIV2 /2 Double Speed 00 /2 Single Speed 01 /4 Half Speed 10 /8 Quarter Speed 11 SCLK Output Figure 12. Master Mode Timing DS723A1 29 CS43L21 4.4.3 High-Impedance Digital Output The serial port may be placed on a clock/data bus that allows multiple masters for the SCLK/LRCK I/O without the need for external buffers. The 3ST_SP bit places the internal buffers for these I/O in a highimpedance state, allowing another device to transmit clocks without bus contention. CS42L51 Transmitting Device #2 Transmitting Device #1 3ST_SP SCLK/LRCK Receiving Device Figure 13. Tri-State SCLK/LRCK 4.4.4 Quarter- and Half-Speed Mode Quarter-Speed Mode (QSM) and Half-Speed Mode (HSM) allow lower sample rates while maintaining a relatively flat noise floor in the typical audio band of 20 Hz - 20 kHz. Single-Speed Mode (SSM) will allow lower frequency sample rates; however, the DAC's noise floor, that normally rises out-of-band, will scale with the lower sample rate and begin to rise within the audio band. QSM and HSM corrects for most of this scaling, effectively increasing the dynamic range of the CODEC at lower sample rates, relative to SSM. 4.5 Digital Interface Formats The serial port operates in standard IS, Left-Justified or Right-Justifieddigital interface formats with varying bit depths from 16 to 24. Data is clocked into the DAC on the rising edge of SCLK. Figures 14-17 illustrate the general structure of each format. Refer to "Switching Specifications - Serial Port" on page 16 for exact timing relationship between clocks and data. Software Control: "Interface Control (Address 04h)" on page 41. Pin Hardware Control: LRCK "IS/LJ" pin 3 Setting Selection LO Left-Justified Interface HI IS Interface L eft C h a n n e l R ig ht C h a n n el SCLK SDIN MSB LSB MSB AOUTA / AINxA LSB MSB AOUTB / AINxB Figure 14. IS Format 30 DS723A1 CS43L21 LRCK L eft C h a n n e l R ig ht C h a n n e l SCLK SDIN MSB LS B MSB LSB MSB AOUTB / AINxB AOUTA / AINxA Figure 15. Left-Justified Format LRCK L eft C h a n n el R ig ht C h a n n el SCLK MSB SDIN M SB LSB AOUTA LS B AOUTB Figure 16. Right-Justified Format (DAC only) 4.6 Initialization The initialization and Power-Down sequence flowchart is shown in Figure 17 on page 32. The CODEC enters a Power-Down state upon initial power-up. The interpolation and decimation filters, delta-sigma modulators and control port registers are reset. The internal voltage reference, multi-bit DAC and switchedcapacitor low-pass filters are powered down. The device will remain in the Power-Down state until the RESET pin is brought high. The control port is accessible once RESET is high and the desired register settings can be loaded per the interface descriptions in "Software Mode" on page 33. If a valid write sequence to the control port is not made within approximately 10 ms, the will enter Hardware Mode. Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage references, FILT+ will begin powering up to normal operation. The charge pump slowly powers up and charges the capacitors. Power is then applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a muted state. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequency ratio and normal operation begins. 4.7 Recommended Power-Up Sequence 1. Hold RESET low until the power supplies are stable. 2. Bring RESET high. After approximately 10 ms, the device will enter Hardware Mode. 3. For Software Mode operation, set the PDN bit to `1'b in under 10 ms. This will place the device in "standby". 4. Load the desired register settings while keeping the PDN bit set to `1'b. 5. Start MCLK to the appropriate frequency, as discussed in Section 4.4. 6. Set the PDN bit to `0'b. 7. Apply LRCKSCLK and SDIN for normal operation to begin. 8. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues. DS723A1 31 CS43L21 4.8 Recommended Power-Down Sequence To minimize audible pops when turning off or placing the D/A in standby, 1. Mute the DAC's. 2. Set the PDN bit in the power control register to `1'b. The D/A will not power down until it reaches a fully muted sate. Do not remove MCLK until after the part has fully muted. Note that it may be necessary to disable the soft ramp and/or zero cross volume transitions to achieve faster muting/power down. 3. Bring RESET low. No Power 1. No audio signal generated. Off Mode (Power Applied) 1. No audio signal generated. 2. Control Port Registers reset to default. PDN bit = '1'b? Standby Mode 1. No audio signal generated. 2. Control Port Registers retain settings. Yes No No RESET = Low? Valid MCLK Applied? Yes No 20 ms delay Control Port Active Charge Caps 1. VQ Charged to quiescent voltage. 2. Filtx+ Charged. Initialization 50 ms delay No Control Port Valid Write Seq. within 10 ms? Yes Digital/Analog Output Muted Charge Pump Powered Up Headphone Amp Powered Down Hardware Mode Minimal feature set support. Power Off Transition 1. Audible pops. Software Mode Registers setup to desired settings. Sub-Clocks Applied 1. LRCK valid. 2. SCLK valid. 3. Audio samples processed. 20 s delay 20 s delay Headphone Amp Powered Up Stand-By Transition 1. Pops suppressed. No Reset Transition 1. Pops suppressed. Valid MCLK/LRCK Ratio? Yes RESET = Low ERROR: MCLK/LRCK ratio change ERROR: Power removed Normal Operation Audio signal generated per control port or standalone settings. PDN bit set to '1'b (software mode only) ERROR: MCLK removed Analog Output Freeze 1. Aout bias = last audio sample. 2. DAC Modulators stop operation. 3. Audible pops. Figure 17. Initialization Flow Chart 32 DS723A1 CS43L21 4.9 Software Mode The control port is used to access the registers allowing the D/A to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port operates in two modes: SPI and IC, with the D/A acting as a slave device. Software Mode is selected if there is a high-to-low transition on the AD0/CS pin after the RESET pin has been brought high. IC Mode is selected by connecting the AD0/CS pin through a resistor to VL or DGND, thereby permanently selecting the desired AD0 bit address state. 4.9.1 SPI Control In Software Mode, CS is the CS43L21 chip-select signal, CCLK is the control port bit clock (input into the from the microcontroller), CDIN is the input data line from the microcontroller. Data is clocked in on the rising edge of CCLK. The D/A will only support write operations. Read request will be ignored. Figure 18 shows the operation of the control port in Software Mode. To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be 1001010. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are the data which will be placed into the register designated by the MAP. There is MAP auto-increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-increment after each byte is read or written, allowing block reads or writes of successive registers. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CCLK CHIP ADDRESS (WRITE) CDIN 1 0 0 1 0 1 0 MAP BYTE 0 INCR 6 5 4 3 DATA +n DATA 2 1 0 7 6 1 0 7 6 1 0 Figure 18. Control Port Timing in SPI Mode 4.9.2 IC Control In IC Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There is no CS pin. Pin AD0 forms the least significant bit of the chip address and should be connected through a resistor to VL or DGND as desired. The state of the pin is sensed while the CS43L21 is being reset. The signal timings for a read and write cycle are shown in Figure 19 and Figure 20. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS43L21 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper 6 bits of the 7-bit address field are fixed at 100101. To communicate with a CS43L21, the chip address field, which is the first byte sent to the CS43L21, should match 100101 followed by the setting of the AD0 pin. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto-incre- DS723A1 33 CS43L21 ment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS43L21 after each input byte is read and is input to the CS43L21 from the microcontroller after each transmitted byte. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 24 25 26 27 28 19 SCL CHIP ADDRESS (WRITE) 1 SDA 0 0 1 0 1 AD0 MAP BYTE 0 INCR 6 5 4 3 1 0 ACK 7 6 1 ACK DATA +n DATA +1 DATA 2 0 7 6 1 0 7 6 1 ACK 0 ACK STOP START Figure 19. Control Port Timing, IC Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SCL CHIP ADDRESS (WRITE) SDA 1 0 0 1 STOP MAP BYTE 0 1 AD0 0 INCR 6 5 4 3 2 1 0 ACK CHIP ADDRESS (READ) 1 0 0 1 0 ACK START DATA 1 AD0 1 START 7 ACK DATA +1 0 7 ACK 0 DATA + n 7 0 NO ACK STOP Figure 20. Control Port Timing, IC Read Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown in Figure 20, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation. Send start condition. Send 100101x0 (chip address & write operation). Receive acknowledge bit. Send MAP byte, auto-increment off. Receive acknowledge bit. Send stop condition, aborting write. Send start condition. Send 100101x1 (chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. 34 DS723A1 CS43L21 4.9.3 Memory Address Pointer (MAP) The MAP byte comes after the address byte and selects the register to be read or written. Refer to the pseudo code above for implementation details. 4.9.3.1 Map Increment (INCR) The device has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive IC writes or reads and SPI writes. If INCR is set to 1, MAP will auto-increment after each byte is read or written, allowing block reads or writes of successive registers. DS723A1 35 CS43L21 5. REGISTER QUICK REFERENCE Software mode register defaults are as shown. "Reserved" registers must maintain their default state. Addr 01h Function ID p 39 default 02h Power Ctl. 1 p 39 7 6 5 4 3 2 1 0 Chip_ID4 Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID2 Rev_ID1 Rev_ID0 1 1 0 1 1 0 0 1 Reserved Reserved Reserved Reserved PDN Reserved PDN_DACB PDN_DACA Speed Ctl. & Power Ctl. 2 p 40 default 04h Interface Ctl. p 41 default 05h Reserved 0 0 0 AUTO SPEED1 SPEED0 3-ST_SP Reserved Reserved Reserved MCLKDIV2 1 0 1 0 1 1 1 0 Reserved M/S DAC_DIF2 DAC_DIF1 DAC_DIF0 Reserved Reserved Reserved 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1 0 1 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 HP_GAIN2 HP_GAIN1 HP_GAIN0 DAC_SNG VOL INV_PCMB INV_PCMA DACB_ MUTE DACA_ MUTE 0 1 1 0 0 0 0 0 DATA_SEL1 DATA_SEL0 FREEZE Reserved DEEMPH AMUTE DAC_SZC1 DAC_SZC0 0 0 0 0 0 1 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1 0 0 0 0 0 0 0 default 03h 1(See Note 1(See Note 1(See Note 1(See Note 2 on page 2 on page 2 on page 2 on page 39) 39) 39) 39) 0 default 06h Reserved default 07h Reserved default 08h DAC Output Control p 41 default 09h DAC Control p 42 default 0Ah Reserved default 0Bh Reserved default 0Ch Reserved default 0Dh Reserved default 0Eh Reserved default 36 DS723A1 CS43L21 Addr 0Fh Function Reserved 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1 0 0 0 0 0 0 0 MUTE_PCM MIXA PCMMIXA VOL6 PCMMIXA VOL5 PCMMIXA VOL4 PCMMIXA VOL3 PCMMIXA VOL2 PCMMIXA VOL1 PCMMIXA VOL0 1 0 0 0 0 0 0 0 MUTE_PCM MIXB PCMMIXB VOL6 PCMMIXB VOL5 PCMMIXB VOL4 PCMMIXB VOL3 PCMMIXB VOL2 PCMMIXB VOL1 PCMMIXB VOL0 1 0 0 0 0 0 0 0 FREQ3 FREQ2 FREQ1 FREQ0 ONTIME3 ONTIME2 ONTIME1 ONTIME0 0 0 0 0 0 0 0 0 OFFTIME2 OFFTIME1 OFFTIME0 BPVOL4 BPVOL3 BPVOL2 BPVOL1 BPVOL0 0 0 0 0 0 0 0 0 REPEAT BEEP Reserved TREB_CF1 TREB_CF0 BASS_CF1 BASS_CF0 TC_EN 0 0 0 0 0 0 0 0 TREB3 TREB2 TREB1 TREB0 BASS3 BASS2 BASS1 BASS0 1 0 0 0 1 0 0 0 AOUTA_ VOL7 AOUTA_ VOL6 AOUTA_ VOL5 OUTA_ VOL4 AOUTA_ VOL3 AOUTA_ VOL2 AOUTA_ VOL1 AOUTA_ VOL0 0 0 0 0 0 0 0 0 AOUTB_ VOL7 AOUTB_ VOL6 AOUTB_ VOL5 AOUTB_ VOL4 AOUTB_ VOL3 AOUTB_ VOL2 AOUTB_ VOL1 AOUTB_ VOL0 0 0 0 0 0 0 0 0 PCMA1 PCMA0 PCMB1 PCMB0 Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 MAX2 MAX1 MAX0 CUSH2 CUSH1 CUSH0 LIM_SRDIS LIM_ZCDIS 0 0 0 0 0 0 0 0 LIMIT_EN LIMIT_ALL LIM_RRATE 5 LIM_RRATE 4 LIM_RRATE 3 LIM_RRATE 2 LIM_RRATE 1 LIM_RRATE 0 0 1 1 1 1 1 1 1 Reserved Reserved 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved default 10h Vol. Control PCMMIXA p 44 default 11h Vol. Control PCMMIXB p 44 default 12h BEEP Freq. & OnTime p 45 default 13h BEEP Off Time & Vol p 46 default 14h BEEP Control & Tone Config p 47 default 15h Tone Control p 48 default 16h Vol. Control AOUTA p 49 default 17h Vol. Control AOUTB p 49 default 18h PCM Channel Mixer p 49 default 19h Limiter Threshold & SZC Disable p 50 default 1Ah Limiter Config & Release Rate p 51 default 1Bh Limiter Attack Rate p 52 default 1Ch Reserved DS723A1 LIM_ARATE5 LIM_ARATE4 LIM_ARATE3 LIM_ARATE2 LIM_ARATE1 LIM_ARATE0 37 CS43L21 Addr Function 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 1 1 1 1 1 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 Reserved Reserved default 1Dh Reserved default 1Eh Reserved default 1Fh Reserved default 20h Status Reserved p 52 default 0 0 0 0 0 0 0 0 CHRG_ FREQ3 CHRG_ FREQ2 CHRG_ FREQ1 CHRG_ FREQ0 Reserved Reserved Reserved Reserved 0 1 0 1 0 0 0 0 21h p 53 default 38 SP_CLKER SPEB_OVFL SPEA_OVFL PCMA_OVFL PCMB_OVFL R DS723A1 CS43L21 6. REGISTER DESCRIPTION All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are read only. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is listed in each bit description. All "Reserved" registers must maintain their default state. 6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) 7 Chip_ID4 6 Chip_ID3 5 Chip_ID2 4 Chip_ID1 3 Chip_ID0 2 Rev_ID2 1 Rev_ID1 0 Rev_ID0 Chip I.D. (Chip_ID[4:0]) Default: 11011 Function: I.D. code for the CS43L21. Permanently set to 11011. Chip Revision (Rev_ID[2:0]) Default: 001 Function: CS43L21 revision level. Revision B is coded as 001. Revision A is coded as 000. 6.2 Power Control 1 (Address 02h) 7 Reserved 6 PDN_DACB 5 PDN_DACA 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 PDN Notes: 1. To activate the power-down sequence for individual channels (A or B,) both channels must first be powered down either by enabling the PDN bit or by enabling the power-down bits for both channels. Enabling the power-down bit on an individual channel basis after the D/A has fully powered up will mute the selected channel without achieving any power savings. 2. Reserved bits 1 - 4 should always be set "high" by the user to minimize power consumption during normal operation. Recommended channel power-down sequence: 1.) Enable the PDN bit, 2.) enable power-down for the select channels, 3.) disable the PDN bit. Power Down DAC X (PDN_DACX) Default: 0 0 - Disable 1 - Enable Function: DAC channel x will either enter a power-down or muted state when this bit is enabled. See Note 1 above. DS723A1 39 CS43L21 Power Down (PDN) Default: 0 0 - Disable 1 - Enable Function: The entire D/A will enter a low-power state when this function is enabled. The contents of the control port registers are retained in this mode. 6.3 Speed Control (Address 03h) 7 AUTO 6 SPEED1 5 SPEED0 4 3-ST_SP 3 Reserved 2 Reserved 1 Reserved 0 MCLKDIV2 Auto-Detect Speed Mode (AUTO) Default: 1 0 - Disable 1 - Enable Function: Enables the auto-detect circuitry for detecting the speed mode of the D/A when operating as a slave. When AUTO is enabled, the MCLK/LRCK ratio must be implemented according to Table 3 on page 29. The SPEED[1:0] bits are ignored when this bit is enabled. Speed is determined by the MCLK/LRCK ratio. Speed Mode (SPEED[1:0]) Default: 01 11 - Quarter-Speed Mode (QSM) - 4 to 12.5 kHz sample rates 10 - Half-Speed Mode (HSM) - 12.5 to 25 kHz sample rates 01 - Single-Speed Mode (SSM) - 4 to 50 kHz sample rates 00 - Double-Speed Mode (DSM) - 50 to 100 kHz sample rates Function: Sets the appropriate speed mode for the D/A in Master or Slave Mode. QSM is optimized for 8 kHz sample rate and HSM is optimized for 16 kHz sample rate. These bits are ignored when the AUTO bit is enabled (see Auto-Detect Speed Mode (AUTO) above). Tri-State Serial Port Interface (3ST_SP) Default: 0 0 - Disable 1 - Enable Function: When enabled and the device is configured as a master, the SCLK/LRCK signals are placed in a high-impedance output state. If the serial port is configured as a slave, SCLK/LRCK are configured as inputs. MCLK Divide By 2 (MCLKDIV2) Default: 0 0 - Disabled 1 - Divide by 2 40 DS723A1 CS43L21 Function: Divides the input MCLK by 2 prior to all internal circuitry. This bit is ignored when the AUTO bit is disabled in Slave Mode. 6.4 Interface Control (Address 04h) 7 Reserved 6 M/S 5 DAC_DIF2 4 DAC_DIF1 3 DAC_DIF0 2 Reserved 1 Reserved 0 Reserved Master/Slave Mode (M/S) Default: 0 0 - Slave 1 - Master Function: Selects either master or slave operation for the serial port. DAC Digital Interface Format (DAC_DIF[2:0]) Default = 000 DAC_DIF[2:0] 000 001 010 011 100 101 110 100 Description Left-Justified, up to 24-bit data IS, up to 24-bit data Right-Justified, 24-bit data Right-Justified, 20-bit data Right-Justified, 18-bit data Right-Justified, 16-bit data Reserved Reserved Figure 15 on page 31 14 on page 30 17 on page 3217 on page 32 17 on page 3217 on page 32 17 on page 3217 on page 32 17 on page 3217 on page 32 - Function: Selects the digital interface format used for the data in on SDIN. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in the section "Digital Interface Formats" on page 30. 6.5 DAC Output Control (Address 08h) 7 6 5 HP_GAIN2 HP_GAIN1 HP_GAIN0 4 DAC_ SNGVOL 3 2 INV_PCMB INV_PCMA 1 0 DACB_MUTE DACA_MUTE Headphone Analog Gain (HP_GAIN[2:0]) Default: 011 DS723A1 HP_GAIN[2:0] Gain Setting 000 001 010 011 100 101 110 111 0.3959 0.4571 0.5111 0.6047 0.7099 0.8399 1.0000 1.1430 41 CS43L21 Function: These bits select the gain multiplier for the headphone/line outputs. See "Line Output Voltage Characteristics" on page 14 and "Headphone Output Power Characteristics" on page 15. DAC Single Volume Control (DAC_SNGVOL) Default: 0 Function: The individual channel volume levels are independently controlled by their respective Volume Control registers when this function is disabled. When enabled, the volume on all channels is determined by the AOUTA Volume Control register and the AOUTB Volume Control register is ignored. PCMX Invert Signal Polarity (INV_PCMX) Default: 0 0 - Disabled 1 - Enabled Function: When enabled, this bit will invert the signal polarity of the PCM x channel. DACX Channel Mute (DACX_MUTE) Default: 0 0 - Disabled 1 - Enabled Function: The output of channel x DAC will mute when enabled. The muting function is affected by the DACx Soft and Zero Cross bits (DACx_SZC[1:0]). 6.6 DAC Control (Address 09h) 7 DATA_SEL1 6 DATA_SEL0 5 FREEZE 4 Reserved 3 DEEMPH 2 AMUTE 1 DAC_SZC1 0 DAC_SZC0 DAC Data Selection (DATA_SEL[1:0]) Default: 00 00 - PCM Serial Port to DAC 01 - Signal Processing Engine to DAC 10 - Reserved 11 - Reserved Function: Selects the digital signal source for the DAC. Note: Certain functions are only available when the "Signal Processing Engine to DAC" option is selected using these bits. 42 DS723A1 CS43L21 Freeze Controls (FREEZE) Default: 0 Function: This function will freeze the previous settings of, and allow modifications to be made to all control port registers without the changes taking effect until the FREEZE is disabled. To have multiple changes in the control port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit. DAC De-Emphasis Control (DEEMPH) Default: 0 0 - No De-Emphasis 1 - De-Emphasis Enabled Function: Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control. Enables the digital filter to apply the standard 15s/50s digital de-emphasis filter response for a sample rate of 44.1 kHz. Analog Output Auto MUTE (AMUTE) Default: 0 0 - Auto Mute Disabled 1 - Auto Mute Enabled Function: Enables (or disables) Automatic Mute of the analog outputs after 8192 "0" samples on each digital input channel. DAC Soft Ramp and Zero Cross Control (DAC_SZC[1:0]) Default = 10 00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings Function: Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control Immediate Change When Immediate Change is selected all volume-level changes will take effect immediately in one step. Zero Cross This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Note: The LIM_SRDIS bit is ignored. DS723A1 43 CS43L21 Soft Ramp Soft Ramp allows level changes, either by gain changes, attenuation changes or muting, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 0.5 dB per 4 left/right clock periods. Soft Ramp on Zero Crossing This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Note: The LIM_SRDIS bit is ignored. 6.7 PCMX Mixer Volume Control: PCMA (Address 10h) & PCMB (Address 11h) 7 MUTE_ PCMMIXx 6 PCMMIXx_ VOL6 5 PCMMIXx_ VOL5 4 PCMMIXx_ VOL4 3 PCMMIXx_ VOL3 2 PCMMIXx_ VOL2 1 PCMMIXx_ VOL1 0 PCMMIXx_ VOL0 Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. PCMX Mixer Channel Mute (MUTE_PCMMIXX) Default = 1 0 - Disabled 1 - Enabled Function: The PCM channel X input to the output mixer will mute when enabled. The muting function is affected by the DACX Soft and Zero Cross bits (DACX_SZC[1:0]). PCMX Mixer Volume Control (PCMMIXX_VOL[6:0]) Default: 000 0000 Binary Code Volume Setting 001 1000 *** 000 0000 111 1111 111 1110 *** 001 1001 +12.0 dB *** 0 dB -0.5 dB -1.0 dB *** -51.5 dB Function: The level of the PCMX input to the output mixer can be adjusted in 0.5 dB increments as dictated by the DACX Soft and Zero Cross bits (DACX_SZC[1:0]) from +12 to -51.5 dB. Levels are decoded as described in the table above. 44 DS723A1 CS43L21 6.8 Beep Frequency & Timing Configuration (Address 12h) 7 FREQ3 6 FREQ2 5 FREQ1 4 FREQ0 3 ONTIME3 2 ONTIME2 1 ONTIME1 0 ONTIME0 Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Beep Frequency (FREQ[3:0]) Default: 0000 FREQ[3:0] Frequency Pitch Fs = 12, 24, 48 or 96 kHz 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 260.87 Hz 521.74 Hz 585.37 Hz 666.67 Hz 705.88 Hz 774.19 Hz 888.89 Hz 1000.00 Hz 1043.48 Hz 1200.00 Hz 1333.33 Hz 1411.76 Hz 1600.00 Hz 1714.29 Hz 2000.00 Hz 2181.82 Hz C4 C5 D5 E5 F5 G5 A5 B5 C6 D6 E6 F6 G6 A6 B6 C7 Function: The frequency of the beep signal can be adjusted from 260.87 Hz to 2181.82 Hz. Beep frequency will scale directly with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. Refer to Figure 10 on page 26 for single, multiple and continuous beep configurations using the REPEAT and BEEP bits. Beep On Time Duration (ONTIME[3:0]) Default: 0000 TIME[3:0] On Time Fs = 12, 24, 48 or 96 kHz 0000 *** 1111 86 ms *** 5.2 s Function: The on-duration of the beep signal can be adjusted from approximately 86 ms to 5.2 s. The on-duration will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. Refer to Figure 10 on page 26 for single-, multiple- and continuous-beep configurations using the REPEAT and BEEP bits. DS723A1 45 CS43L21 6.9 Beep Off Time & Volume (Address 13h) 7 OFFTIME2 6 OFFTIME1 5 OFFTIME0 4 BPVOL4 3 BPVOL3 2 BPVOL2 1 BPVOL1 0 BPVOL0 Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Beep Off Time (OFFTIME[2:0]) Default: 000 OFFTIME[2:0] Off Time Fs = 12, 24, 48 or 96 kHz 000 001 010 011 100 101 110 111 1.23 s 2.58 s 3.90 s 5.20 s 6.60 s 8.05 s 9.35 s 10.80 s Function: The off-duration of the beep signal can be adjusted from approximately 75 ms to 680 ms. The off-duration will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. Refer to Figure 10 on page 26 for single-, multiple- and continuous-beep configurations using the REPEAT and BEEP bits. Beep Volume (BPVOL[4:0]) Default: 00000 Binary Code Volume Setting 00110 *** 00000 11111 11110 *** 00111 +12.0 dB *** 0 dB -2 dB -4 dB *** -50 dB Function: The level of the beep into the output mixer can be adjusted in 2.0 dB increments from +12 dB to -50 dB. Refer to Figure 10 on page 26 for single-, multiple- and continuous-beep configurations using the REPEAT and BEEP bits. Levels are decoded as described in the table above. 46 DS723A1 CS43L21 6.10 Beep Configuration & Tone Configuration (Address 14h) 7 REPEAT 6 BEEP 5 Reserved 4 TREB_CF1 3 TREB_CF0 2 BASS_CF1 1 BASS_CF0 0 TC_EN Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Repeat Beep (REPEAT) Default: 0 0 - Disabled 1 - Enabled Function: This bit is used in conjunction with the BEEP bit to mix a continuous or periodic beep with the analog output. Refer to Figure 10 on page 26 for a description of each configuration option. Beep (BEEP) Default: 0 0 - Disabled 1 - Enabled Function: This bit is used in conjunction with the REPEAT bit to mix a continuous or periodic beep with the analog output. Note: Re-engaging the beep before it has completed its initial cycle will cause the beep signal to remain ON for the maximum ONTIME duration. Refer to Figure 10 on page 26 for a description of each configuration option. Treble Corner Frequency (TREB_CF[1:0]) Default: 00 00 - 5 kHz 01 - 7 kHz 10 - 10 kHz 11 - 15 kHz Function: The treble corner frequency is user selectable as shown above. Bass Corner Frequency (BASS_CF[1:0]) Default: 00 00 - 50 Hz 01 - 100 Hz 10 - 200 Hz 11 - 250 Hz Function: The bass corner frequency is user-selectable as shown above. DS723A1 47 CS43L21 Tone Control Enable (TC_EN) Default = 0 0 - Disabled 1 - Enabled Function: The Bass and Treble tone control features are active when this bit is enabled. 6.11 Tone Control (Address 15h) 7 TREB3 6 TREB2 5 TREB1 4 TREB0 3 BASS3 2 BASS2 1 BASS1 0 BASS0 Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Treble Gain Level (TREB[3:0]) Default: 1000 dB (No Treble Gain) Binary Code Gain Setting 0000 *** 0111 1000 1001 *** 1111 +12.0 dB *** +1.5 dB 0 dB -1.5 dB *** -10.5 dB Function: The level of the shelving treble gain filter is set by Treble Gain Level. The level can be adjusted in 1.5 dB increments from +12.0 to -10.5 dB. Bass Gain Level (BASS[3:0]) Default: 1000 dB (No Bass Gain) Binary Code Gain Setting 0000 *** 0111 1000 1001 *** 1111 +12.0 dB *** +1.5 dB 0 dB -1.5 dB *** -10.5 dB Function: The level of the shelving bass gain filter is set by Bass Gain Level. The level can be adjusted in 1.5 dB increments from +10.5 to -10.5 dB. 48 DS723A1 CS43L21 6.12 AOUTx Volume Control: AOUTA (Address 16h) & AOUTB (Address 17h) 7 6 5 4 3 2 1 0 AOUTx_VOL7 AOUTx_VOL6 AOUTx_VOL5 AOUTx_VOL4 AOUTx_VOL3 AOUTx_VOL2 AOUTx_VOL1 AOUTx_VOL0 Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. AOUTX Volume Control (AOUTX_VOL[7:0]) Default = 00h Binary Code Volume Setting 0001 1000 *** 0000 0000 1111 1111 1111 1110 *** 0011 0100 *** 0001 1001 +12.0 dB *** 0 dB -0.5 dB -1.0 dB *** -102 dB *** -102 dB Function: The analog output levels can be adjusted in 0.5 dB increments from +12 to -102 dB as dictated by the DAC Soft and Zero Cross bits (DACX_SZC[1:0]). Levels are decoded in unsigned binary as described in the table above. Note: 6.13 When the limiter is enabled, the AOUT Volume is automatically controlled and should not be adjusted manually. Alternative volume control may be achieved using the PCMMIXx_VOL[6:0] bits. PCM Channel Mixer (Address 18h) 7 PCMA1 6 PCMA0 5 PCMB1 4 PCMB0 3 Reserved 2 Reserved 1 Reserved 0 Reserved Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Channel Mixer (PCMx[1:0]) Default: 00 PCMA[1:0] AOUTA PCMB[1:0] AOUTB 00 L 00 R 01 10 11 L+R -----------2 R 01 10 11 L+R -----------2 L Function: Implements mono mixes of the left and right channels as well as a left/right channel swap. DS723A1 49 CS43L21 6.14 Limiter Threshold SZC Disable (Address 19h) 7 MAX2 6 MAX1 5 MAX0 4 CUSH2 3 CUSH1 2 CUSH0 1 LIM_SRDIS 0 LIM_ZCDIS Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Maximum Threshold (MAX[2:0]) Default: 000 MAX[2:0] Threshold Setting (dB) 000 0 001 -3 010 -6 011 -9 101 -12 101 -18 110 -24 111 -30 Function: Sets the maximum level, below full scale, at which to limit and attenuate the output signal at the attack rate. Bass, Treble and digital gain settings that boost the signal beyond the maximum threshold may trigger an attack. Cushion Threshold (CUSH[2:0]) Default: 000 CUSH[2:0] Threshold Setting (dB) 000 0 001 -3 010 -6 011 -9 101 -12 101 -18 110 -24 111 -30 Function: Sets a cushion level below full scale. This setting is usually set slightly below the maximum (MAX[2:0]) threshold. The Limiter uses this cushion as a hysteresis point for the input signal as it maintains the signal below the maximum as well as below the cushion setting. This provides a more natural sound as the limiter attacks and releases. 50 DS723A1 CS43L21 Limiter Soft Ramp Disable (LIM_SRDIS) Default: 0 0 - Off 1 - On Function: Overrides the DAC_SZC setting. When this bit is set, the Limiter attack and release rate will not be dictated by the soft ramp setting. Note: This bit is ignored when the zero-cross function is enabled (i.e. when DAC_SZC[1:0] = `01'b or `11'b.) Limiter Zero Cross Disable (LIM_ZCDIS) Default: 0 0 - Off 1 - On Function: Overrides the DAC_SZC setting. When this bit is set, the Limiter attack and release rate will not be dictated by the zero-cross setting. 6.15 Limiter Release Rate Register (Address 1Ah) 7 LIMIT_EN 6 LIMIT_ALL 5 RRATE5 4 RRATE4 3 RRATE3 2 RRATE2 1 RRATE1 0 RRATE0 Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Peak Detect and Limiter Enable (LIMIT_EN) Default: 0 0 - Disabled 1 - Enabled Function: Limits the maximum signal amplitude to prevent clipping when this function is enabled. Peak Signal Limiting is performed by digital attenuation. Note: When the limiter is enabled, the AOUT Volume is automatically controlled and should not be adjusted manually. Alternative volume control may be realized using the PCMMIXx_VOL[6:0] bits. Peak Signal Limit All Channels (LIMIT_ALL) Default: 1 0 - Individual Channel 1 - Both channel A & B Function: When set to 0, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on the specific channel indicating clipping. The other channels will not be affected. When set to 1, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on both channels in response to any single channel indicating clipping. DS723A1 51 CS43L21 Limiter RELEASE Rate (RRATE[5:0]) Default: 111111 Binary Code Release Time 000000 *** 111111 Fastest Release *** Slowest Release Function: Sets the rate at which the limiter releases the digital attenuation from levels below the minimum setting in the limiter threshold register, and returns the analog output level to the AOUTx_VOL[7:0] setting. The limiter release rate is user selectable but is also a function of the sampling frequency, Fs, and the DAC_SZC setting unless the disable bit is enabled. 6.16 Limiter Attack Rate Register (Address 1Bh) 7 Reserved 6 Reserved 5 ARATE5 4 ARATE4 3 ARATE3 2 ARATE2 1 ARATE1 0 ARATE0 Note: The DATA_SEL[1:0] bits in reg09h must be set to `01'b to enable function control in this register. Limiter Attack Rate (ARATE[5:0]) Default: 000000 Binary Code Attack Time 000000 *** 111111 Fastest Attack *** Slowest Attack Function: Sets the rate at which the limiter attenuates the analog output from levels above the maximum setting in the limiter threshold register. The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and the DAC_SZC setting unless the disable bit is enabled. 6.17 Status (Address 20h) (Read Only) 7 Reserved 6 SP_CLKERR 5 SPEA_OVFL 4 SPEB_OVFL 3 2 PCMA_OVFL PCMB_OVFL 1 Reserved 0 Reserved For all bits in this register, a "1" means the associated error condition has occurred at least once since the register was last read. A "0" means the associated error condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0. Serial Port Clock Error (SP_CLK Error) Default: 0 Function: Indicates an invalid MCLK to LRCK ratio. See "Serial Port Clocking" section on page 28"Serial Port Clocking" on page 28 for valid clock ratios. Note: 52 On initial power up and application of clocks, this bit will be high as the serial port re-synchronizes. DS723A1 CS43L21 Signal Processing Engine Overflow (SPEX_OVFL) Default: 0 Function: Indicates a digital overflow condition within the data path after the signal processing engine. PCMX Overflow (PCMX_OVFL) Default: 0 Function: Indicates a digital overflow condition within the data path of the PCM mix. 6.18 Charge Pump Frequency (Address 21h) 7 6 5 4 CHRG_FREQ CHRG_FREQ CHRG_FREQ CHRG_FREQ 3 2 1 0 3 2 1 0 Reserved Reserved Reserved Reserved Charge Pump Frequency (CHRG_FREQ[3:0]) Default: 0101 N CHRG_FREQ[3:0] 0 ... 15 0000 ... 1111 Frequency 64xFs ----------------N+2 Function: Alters the clocking frequency of the charge pump in 1/(N+2) fractions of the DAC oversampling rate, 128Fs, should the switching frequency interfere with other system frequencies such as those in the AM radio band. Note: DS723A1 Distortion performance may be affected. 53 CS43L21 7. ANALOG PERFORMANCE PLOTS 7.1 Headphone THD+N versus Output Power Plots Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Fs = 48 kHz. Plots were taken from the CDB43L21 using an Audio Precision analyzer. -10 G = 0.6047 -15 VA_HP = VA = 1.8 V G = 0.7099 -20 G = 0.8399 -25 -30 G = 1.0000 -35 G = 1.1430 -40 Legend -45 d B r A -50 NOTE: Graph shows the output power per channel (i.e. Output Power = 23 mW into single 16 and 46 mW into stereo 16 with THD+N = 75 dB). -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 0 10m 20m 30m 40m 50m 60m 70m 80m W Figure 21. THD+N vs. Output Power per Channel at 1.8 V (16 load) -10 -15 G = 0.6047 VA_HP = VA = 2.5 V G = 0.7099 -20 -25 G = 0.8399 -30 G = 1.0000 -35 G = 1.1430 -40 Legend -45 d B r A NOTE: Graph shows the output power per channel (i.e. Output Power = 44 mW into single 16 and 88 mW into stereo 16 with THD+N = 75 dB). -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 0 10m 20m 30m 40m 50m 60m 70m 80m W Figure 22. THD+N vs. Output Power per Channel at 2.5 V (16 load) 54 DS723A1 CS43L21 G = 0.6047 VA_HP = VA = 1.8 G = 0.7099 -20 -30 G = 0.8399 -35 G = 1.0000 -40 G = 1.1430 -45 Legend -50 NOTE: Graph shows the output power per channel (i.e. Output Power = 22 mW into single 32 and 44 mW into stereo 32 with THD+N = 75 dB). -55 d B r -60 A -65 -70 -75 -80 -85 -90 -95 -100 0 6m 12m 18m 24m 30m 36m 42m 48m 54m 60m W Figure 23. THD+N vs. Output Power per Channel at 1.8 V (32 load) G = 0.6047 -20 VA_HP = VA = 2.5 V -25 G = 0.7099 -30 G = 0.8399 -35 G = 1.0000 -40 G = 1.1430 -45 Legend -50 -55 d B r NOTE: Graph shows the output power per channel (i.e. Output Power = 42 mW into single 32 and 84 mW into stereo 32 with THD+N = 75 dB). -60 A -65 -70 -75 -80 -85 -90 -95 -100 0 5m 10m 15m 20m 25m 30m 35m 40m 45m 50m 55m 60m W Figure 24. THD+N vs. Output Power per Channel at 2.5 V (32 load) DS723A1 55 CS43L21 7.2 Headphone Amplifier Efficiency The architecture of the headphone amplifier is that of typical class AB amplifiers. Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave; Power Consumption Mode 6 - Stereo Playback w/16 load. HP_GAIN = 1.1430. Best efficiency is realized when the amplifier outputs maximum power. VA_HP = VA = 1.8 V Figure 25. Power Dissipation vs. Output Power into Stereo 16 VA_HP = VA = 1.8 V Figure 26. Power Dissipation vs. Output Power into Stereo 16 (Log Detail) 56 DS723A1 CS43L21 8. EXAMPLE SYSTEM CLOCK FREQUENCIES 8.1 Auto Detect Enabled Sample Rate LRCK (kHz) 1024x MCLK (MHz) 1536x 2048x* 8 11.025 12 3072x* 8.1920 11.2896 12.2880 12.2880 16.9344 18.4320 24.5760 33.8688 36.8640 Sample Rate LRCK (kHz) 512x MCLK (MHz) 768x 1024x* 16 22.05 24 8.1920 11.2896 12.2880 12.2880 16.9344 18.4320 16.3840 22.5792 24.5760 16.3840 22.5792 24.5760 Sample Rate LRCK (kHz) MCLK (MHz) 384x 512x* 256x 32 44.1 48 8.1920 11.2896 12.2880 12.2880 16.9344 18.4320 Sample Rate LRCK (kHz) 128x 192x 64 88.2 96 8.1920 11.2896 12.2880 12.2880 16.9344 18.4320 16.3840 22.5792 24.5760 MCLK (MHz) 256x* 16.3840 22.5792 24.5760 1536x* 24.5760 33.8688 36.8640 768x* 24.5760 33.8688 36.8640 384x* 24.5760 33.8688 36.8640 *The"MCLKDIV2" pin 4 must be set HI. DS723A1 57 CS43L21 8.2 58 Auto Detect Disabled Sample Rate LRCK (kHz) 512x 8 11.025 12 6.1440 768x MCLK (MHz) 1024x 1536x 2048x 3072x 6.1440 8.4672 9.2160 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 24.5760 33.8688 36.8640 Sample Rate LRCK (kHz) 256x 384x 512x 16 22.05 24 6.1440 6.1440 8.4672 9.2160 8.1920 11.2896 12.2880 12.2880 16.9344 18.4320 MCLK (MHz) 768x 12.2880 16.9344 18.4320 Sample Rate LRCK (kHz) 256x 32 44.1 48 8.1920 11.2896 12.2880 12.2880 16.9344 18.4320 Sample Rate LRCK (kHz) 128x 192x 64 88.2 96 8.1920 11.2896 12.2880 12.2880 16.9344 18.4320 1024x 1536x 16.3840 22.5792 24.5760 24.5760 33.8688 36.8640 MCLK (MHz) 384x 512x 16.3840 22.5792 24.5760 MCLK (MHz) 256x 16.3840 22.5792 24.5760 768x 24.5760 33.8688 36.8640 384x 24.5760 33.8688 36.8640 DS723A1 CS43L21 9. PCB LAYOUT CONSIDERATIONS 9.1 Power Supply, Grounding As with any high-resolution converter, the CS43L21 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 on page 9 shows the recommended power arrangements, with VA and VA_HP connected to clean supplies. VD, which powers the digital circuitry, may be run from the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite bead. In this case, no additional devices should be powered from VD. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS43L21 as possible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same side of the board as the CS43L21 to minimize inductance effects. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from FILT+ and AGND. The CS43L21 evaluation board demonstrates the optimum layout and power supply arrangements. 9.2 QFN Thermal Pad The CS43L21 is available in a compact QFN package. The under side of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers. In split ground systems, it is recommended that this thermal pad be connected to AGND for best performance. The CS43L21 evaluation board demonstrates the optimum thermal pad and via configuration. DS723A1 59 CS43L21 10.DIGITAL FILTERS 60 Figure 27. Passband Ripple Figure 28. Stopband Figure 29. Transition Band Figure 30. Transition Band (Detail) DS723A1 CS43L21 11.PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channel pairs. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channel pairs. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. DS723A1 61 CS43L21 12.PACKAGE DIMENSIONS 32L QFN (5 X 5 mm BODY) PACKAGE DRAWING e b D Pin #1 Corner Pin #1 Corner E2 E A1 L D2 A Top View DIM MIN A A1 b D D2 E E2 e L -0.0000 0.0071 0.1280 0.1280 0.0118 Bottom View Side View INCHES NOM --0.0091 0.1969 BSC 0.1299 0.1969 BSC 0.1299 0.0197 BSC 0.0157 MAX MIN 0.0394 0.0020 0.0110 -0.00 0.18 0.1319 3.25 0.1319 3.25 0.0197 0.30 MILLIMETERS NOM --0.23 5.00 BSC 3.30 5.00 BSC 3.30 0.50 BSC 0.40 NOTE MAX 1.00 0.05 0.28 3.35 3.35 0.50 1 1 1,2 1 1 1 1 1 1 JEDEC #: MO-220 Controlling Dimension is Millimeters. 1. Dimensioning and tolerance per ASME Y 14.5M-1995. 2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip. THERMAL CHARACTERISTICS Parameter Junction to Ambient Thermal Impedance 62 2 Layer Board 4 Layer Board Symbol Min Typ Max Units JA - 52 38 - C/Watt DS723A1 CS43L21 13.ORDERING INFORMATION Product CS43L21 CDB43L21 Description Package Pb-Free Grade Temp Range Commercial -10 to +70 C Low-Power Stereo D/A with HP Amp for Portable Apps 32L-QFN CS43L21 Evaluation Board - Yes No Automotive -40 to +85 C - - Container Order # Rail CS43L21-CNZ Tape & Reel CS43L21-CNZR Rail CS43L21-DNZ Tape & Reel CS43L21-DNZR - CDB43L21 14.REFERENCES 1. Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices, Version 6.0, February 1998. 2. Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters, by Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992. 3. Cirrus Logic, A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori, K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 4. Philips Semiconductor, The IC-Bus Specification: Version 2.1, January 2000. http://www.semiconductors.philips.com 15.REVISION HISTORY Revision A1 Changes Initial Release Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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