Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
http://www.cirrus.com
Advance Product Information This document contains informatio n for a new product.
Cirrus Logic reserves the right to modify this product without notice.
JULY '06
DS723A1
Low Power, Stereo Digital to Analog Converter
FEATURES
98 dB Dynamic Range (A-wtd)
-86 dB THD+N
Headphone Amplifier - GND Centered
– On-Chip Charge Pump Provides -VA_HP
– No DC-Blocking Capacitor Required
– 46 mW Power Into Stereo 16 Ω @ 1.8 V
– 88 mW Power Into Stereo 16 Ω @ 2.5 V
– -75 dB THD+N
Digital Signal Processing Engine
– Bass & Treble Tone Control, De-Emphasis
– PCM Mix w/Independent Vol Control
– Master Digital Volume Control and Limiter
– Soft Ramp & Zero Cross Transitions
Beep Generator
– Tone Selections Across Two Octaves
– Separate Volume Control
– Programmable On & Off Time Intervals
– Continuous, Periodic or One-Shot Beep
Selections
Programmable Peak-Detect and Limiter
Pop and Click Suppression
SYSTEM FEATURES
24-bit Conversion
4 kHz to 96 kHz Sample Rate
Multi-bit Delta Sigma Architecture
Low Power Operation
– Stereo Playback: 12.93 mW @ 1.8 V
Variable Power Supplies
– 1.8 V to 2.5 V Digital & Analog
– 1.8 V to 3.3 V Interface Logic
Power Down Management
Software Mode (I²C® & SPI™ Control)
Hardware Mode (Stand-Alone Control)
Digital Routing/Mixes:
– Mono Mixes
Flexible Clocking Options
– Master or Slave Operation
– High-Impedance Digital Output Option (for
easy MUXing between DAC and Other
Data Sources)
– Quarter-Speed Mode - (i.e. Allows 8 kHz Fs
while maintaining a flat noise floor up to
16 kHz)
1.8 V to 3.3 V
Multibit
∆Σ Modulator
Charge
Pump
Left HP Out
Right HP Out
Serial Audio
Input
1.8 V to 2.5 V
PCM Serial Interface
Register
Configuration
Level Translator
Reset
Hardware
Mode or I2C &
SPI Software
Mode
Control Data
Beep
Generator
MUX
MUX
Headphone
Amp - GND
Centered
Headphone
Amp - GND
Centered
1.8 V to 2.5 V
Switched
Capacitor DAC
and Filter
Switched
Capacitor DAC
and Filter
Digital
Signal
Processing
Engine
CS43L21
2DS723A1
CS43L21
APPLICATIONS
Portable Audio Players
MD Players
PDAs
Personal Media Players
Portable Game Consoles
Smart Phones
Wireless Headse ts
GENERAL DESCRIPTION
The CS43L21 is a highly integr ated , 24-b it, 96 kHz, low
power stereo DAC. Based on multi-bit, delta-sigma
modulation, it allows infinite sample rate adjustment be-
tween 4 kHz and 96 kHz. The DAC offers many features
suitable for low power, portable system applications.
The DAC output pa th includes a digital signal pr ocess-
ing engine. Tone Control provides bass and treble
adjustment of four selectable corner frequencies. The
Mixer allows independent volume control for PCM mix,
as well as a master digital volume control for the analog
output. All volume level changes may be configured to
occur on soft ramp and zero cross transitions. The DAC
also includes de-emphasis, limiting functions and a
beep generator delivering tones selectable across a
range of two full octaves.
The stereo headphon e amplifier is powered from a sep-
arate positive supply and the integrated charge pump
provides a negative supply. This allows a ground-cen-
tered analog output with a wide signal swing and
eliminates external DC-blocking capacitors.
In addition to its many features, the CS43L21 operates
from a low-voltage analog and digital core, making this
DAC ideal for portable systems that require extremely
low power consumption in a minimal am ount of space.
The CS43L21 is available in a 32-pin QFN package in
both Commercial (-10 to +70° C) and Automotive
grades (-40 to +85° C). The CS43L21 Customer Dem-
onstration board is also available for device evaluation
and implementation suggestions. Please see “Ordering
Information” on page 63 for complete details.
DS723A1 3
CS43L21
TABLE OF CONTENTS
1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE .................................................................. 6
1.1 Digital I/O Pin Characteristics ........................................................................................................... 8
2. TYPICAL CONNECTION DIAGRAMS ................................................................................................... 9
3. CHARACTERISTIC AND SPECIFICATION TABLES ......................................................................... 11
SPECIFIED OPERATING CONDITIONS ............................................................................................. 11
ABSOLUTE MAXIMUM RATINGS .......................................................................................................11
ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ) ...................................................... 12
ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) ...... ... ................. ... ... ... ... .... ... ... ...... 13
LINE OUTPUT VOLTAGE CHARACTERISTICS ................................................................................. 14
HEADPHONE OUTP UT POWER CHARA CTERISTI CS ................ ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 15
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .............................. 16
SWITCHING SPECIFICATIONS - SERIAL PORT ............................................................................... 16
SWITCHING SPECIFICATIONS - I²C® CONTROL PORT .................................................................. 18
SWITCHING CHARACTERISTICS - SPI™ CONTROL PORT ............................................................ 19
DC ELECTRICAL CHARACTERISTICS .............................................................................................. 20
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 20
POWER CONSUMPTION .................................................................................................................... 21
4. APPLICATIONS ................................................................................................................................... 22
4.1 Overview ......................................................................................................................................... 22
4.1.1 Architecture ........................................................................................................................... 22
4.1.2 Line & Headphone Outputs ................................................................................................... 22
4.1.3 Signal Processing Engine ..................................................................................................... 22
4.1.4 Beep Generator ..................................................................................................................... 22
4.1.5 Device Control (Hardware or Software Mode) ...................................................................... 22
4.1.6 Power Management .............................................................................................................. 22
4.2 Hardware Mode .............................................................................................................................. 23
4.3 Analog Outputs ............................................................................................................................... 24
4.3.1 De-Emphasis Filter ................................................................................................................ 24
4.3.2 Volume Controls .................................................................................................................... 25
4.3.3 Mono Channel Mixer ............................................................................................................. 25
4.3.4 Beep Generator ..................................................................................................................... 25
4.3.5 Tone Control .......................................................................................................................... 26
4.3.6 Limiter .................................................................................................................................... 26
4.3.7 Line-Level Outputs and Filtering ........................................................................................... 27
4.3.8 On-Chip Charge Pump .......................................................................................................... 28
4.4 Serial Port Clocking ........................................................................................................................ 28
4.4.1 Slave ..................................................................................................................................... 29
4.4.2 Master ................................................................................................................................... 29
4.4.3 High-Impedance Digital Output ............................................................................................. 30
4.4.4 Quarter- and Half-Speed Mode .............................................................................................30
4.5 Digital Interface Formats ................................................................................................................ 30
4.6 Initialization ..................................................................................................................................... 31
4.7 Recommended Power-Up Sequence ............................................................................................. 31
4.8 Recommended Power-Down Sequence ........................................................................................ 32
4.9 Software Mode ............................................................................................................................... 33
4.9.1 SPI Control ............................................................................................................................ 33
4.9.2 I²C Control ............................................................................................................................. 33
4.9.3 Memory Address Pointer (MAP) .. .......... .......... ......... .......... .......... ......... .......... .......... ...... ...... 35
4.9.3.1 Map Increment (I NCR) .. ...... ....... ...... ....... ...... ....... ...... ....... ...... ... ....... ...... ....... ...... ...... 35
5. REGISTER QUICK REFERENCE ........................................................................................................ 36
6. REGISTER DESCRIPTION .................................................................................................................. 39
6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 39
4DS723A1
CS43L21
6.2 Power Control 1 (Address 02h) ...................................................................................................... 39
6.3 Speed Control (Address 03h) ......................................................................................................... 40
6.4 Interface Control (Address 04h) ..................................................................................................... 41
6.5 DAC Output Control (Address 08h) ................................................................................................ 41
6.6 DAC Control (Address 09h) ............................................................................................................ 42
6.7 PCMX Mixer Volume Contro l:
PCMA (Address 10h) & PCMB (Address 11h) ..................................................................................... 44
6.8 Beep Frequency & Timing Configuration (Address 12h) ................................................................ 45
6.9 Beep Off Time & Volume (Address 13h) ........................................................................................ 46
6.10 Beep Configuration & Tone Conf iguration (Address 14h) ............................................................ 47
6.11 Tone Control (Address 15h) ......................................................................................................... 48
6.12 AOUTx Volume Control:
AOUTA (Address 16h) & AOUTB (Address 17h) ................................................................................. 49
6.13 PCM Channel Mixer (Address 18h) .............................................................................................. 49
6.14 Limiter Threshold SZC Disable (Address 19h) ............................................................................. 50
6.15 Limiter Release Rate Register (Address 1Ah) .............................................................................. 51
6.16 Limiter Attack Rate Register (Address 1Bh) ................................................................................. 52
6.17 Status (Address 20h) (Read Only) ............................................................................................... 52
6.18 Charge Pump Frequency (Address 21h) ...................................................................................... 53
7. ANALOG PERFORMANCE PLOTS .......... ... ................. ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ................ ... ...54
7.1 Headphone THD+N versus Output Power Plots ............................................................................ 54
7.2 Headphone Amplifier Efficiency ...................................................................................................... 56
8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 57
8.1 Auto Detect Enabled ....................................................................................................................... 57
8.2 Auto Detect Disabled ...................................................................................................................... 58
9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 59
9.1 Power Supply, Grounding ............................................................................................................... 59
9.2 QFN Thermal Pad .......................................................................................................................... 59
10. DIGITAL FILTERS .............................................................................................................................. 60
11. PARAMETER DEFINITIONS .............................................................................................................. 61
12. PACKAGE DIMENSIONS ................................................................................................................. 62
THERMAL CHARACTERISTICS ........ ................ ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ................ .... ... ... ... ...62
13. ORDERING INFORMATION ............................................................................................................. 63
14. REFERENCES .................................................................................................................................... 63
15. REVISION HISTORY ......................................................................................................................... 63
DS723A1 5
CS43L21
LIST OF FIGURES
Figure 1.Typical Connection Diagram (Software Mode) ............................................................................. 9
Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 10
Figure 3.Headphone Output Test Load ..................................................................................................... 15
Figure 4.Serial Audio Interface Slave Mode Timing .................................................................................. 17
Figure 5.Serial Audio Interface Master Mode Timing ................................................................................ 17
Figure 6.Control Port Timing - I²C ............................................................................................................. 18
Figure 7.Control Port Timing - SPI Format ................................................................................................ 19
Figure 8.Output Architecture ..................................................................................................................... 24
Figure 9.De-Emphasis Curve .................................................................................................................... 25
Figure 10.Beep Configuration Options ...................................................................................................... 26
Figure 11.Peak Detect & Limiter ............................................................................................................... 27
Figure 12.Master Mode Timing ................................................................................................................. 29
Figure 13.Tri-State SCLK/LRCK ............................................................................................................... 30
Figure 14.I²S Format ................................................................................................................................. 30
Figure 15.Left-Justified Format ................................................................................................................. 31
Figure 16.Right-Justified Format (DAC only) ............................................................................................ 31
Figure 17.Initialization Flow Chart ............................................................................................................. 32
Figure 18.Control Port Timing in SPI Mode . ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ................... 33
Figure 19.Control Port Timing, I²C Write ................................................................................................... 34
Figure 20.Control Port Timing, I²C Read ................................................................................................... 34
Figure 21.T HD+N vs. Output Power per Channel at 1.8 V (16 Ω load) .................................................... 54
Figure 22.T HD+N vs. Output Power per Channel at 2.5 V (16 Ω load) .................................................... 54
Figure 23.T HD+N vs. Output Power per Channel at 1.8 V (32 Ω load) .................................................... 55
Figure 24.T HD+N vs. Output Power per Channel at 2.5 V (32 Ω load) .................................................... 55
Figure 25.Power Dissipation vs. Output Power into Stereo 16 Ω ......................................................................56
Figure 26.Power Dissipation vs. Output Power into Stereo 16 Ω (Log Detail) ....... ... .... ... ... ... ... .... ... ... ... ... 56
Figure 27.Passband Ripple ....................................................................................................................... 60
Figure 28.Stopband ................................................................................................................................... 60
Figure 29.Transition Band ......................................................................................................................... 60
Figure 30.Transition Band (Detail) ............................................................................................................ 60
LIST OF TABLES
Table 1. I/O Power Rails ............................................................................................................................. 8
Table 2. Hardware Mode Feature Summary ............................................................................................. 23
Table 3. MCLK/LRCK Ratios ................................. ... ... ... .... ... ... ... ................ .... ... ... ... .... ... ... ...................... 29
6DS723A1
CS43L21
1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE
Pin Name # Pin Description
LRCK 1Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
SDA/CDIN
(MCLKDIV2) 2Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode. CDIN is the input data line for the
control port interface in SPI Mode.
MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to a ll inte rnal circuitr y.
SCL/CCLK
(I²S/LJ)3Serial Control Port Clock (Input) - Serial clock for the serial control port.
Interface Format Selection (Input) - Hardware Mode: Selects between I²S & Left-Justified interfac e for-
mats for the DAC.
AD0/CS
(DEM) 4Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode; CS
is the chip-sel ect signal for SPI format.
De-Emphasis (Input) - Hardware Mode: Enables/disables the de-emphasis filter.
VA_HP 5Analog Power For Headphone (Input) - Positive power for the internal analog headphone section.
FLYP 6Charge Pump Cap Positive Node (Input) - Positive node for the external charge pump capacitor.
GND_HP 7Analog Gr ound (Input) - Ground reference for th e internal headphone/charge pump section.
FLYN 8Charge Pump Cap Negative Node (Input) - Negative node for the external charge pump capacitor.
VSS_HP 9Negative Voltage From Charge Pump (Output) - Negative voltage rail for the internal analog head-
phone section.
109
8
7
6
5
4
3
2
1
11 12 13 14 15 16
17
18
19
20
21
22
23
24
25
262728
29
303132
CS43L21
VD
DGND
TSTO(M/S)
MCLK
SDIN
SCLK
VSS_HP
AOUTB
AOUTA
VA
AGND
FILT+
NIC
VQ
SDA/CDIN (MCLKDIV2)
SCL/CCLK (I²S/LJ)
ADO/CS (DEM)
FLYP
VL
RESET
GND_HP
FLYN
TSTO
TSTO
TSTO
TSTO
TSTO
TSTO
TSTO
TSTO
VA_HP
LRCK
DS723A1 7
CS43L21
AOUTB
AOUTA 10
11 Analog Audio Ou tput (Output) - The full-scale output level is specified in the DAC Analog Cha r acteris-
tics specification table
VA 12 Analog Power (Input) - Positive power for the internal analog section.
AGND 13 Analog Ground (Input) - Ground reference for the internal analog section.
FILT+ 14 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
VQ 15 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
NIC 16 Not Internally Connected - This pin is not connected internal to the device and may be connected to
ground or left “floating”. No other external connection should be made to this pin.
TSTO 17 Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-
nection external to the pin).
TSTO 18 Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-
nection external to the pin).
TSTO 19 Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-
nection external to the pin).
TSTO 20 Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-
nection external to the pin).
TSTO 21
22 Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-
nection external to the pin).
TSTO 23
24 Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-
nection external to the pin).
RESET 25 Reset (Input) - The device enters a low power mode when this pin is driven low.
VL 26 Digit a l In terface Pow er (Input) - Determines the required signal level for the serial audio interface and
host control port. Refer to the Recommended Operating Conditions for appropriate voltages.
VD 27 Digital Power (Input) - Positive power for the internal digital section.
DGND 28 Digital Ground (Input) - Ground reference for the internal digital secti on.
TSTO
(M/S)29
Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con-
nection external to the pin).
Serial Port Master/Slave (Input/Output) - Hardware Mode Startup Option: Selects between Master and
Slave Mode for the serial port.
MCLK 30 Master Clock (Input) - Clock source for the delta-sigma modulators.
SCLK 31 Serial Clock (Input/Output) - Serial clock for the serial audio interface.
SDIN 32 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
Thermal Pad -Thermal relief pad for optimized heat dissipation. See “QFN Thermal Pad” on page 59.
8DS723A1
CS43L21
1.1 Digital I/O Pin Characteristics
The logic level for each input should not exceed the maximum ratings for the VL power supply.
Pin Name
SW/(HW) I/O Driver Receiver
RESET Input - 1.8 V - 3.3 V
SCL/CCLK
(I²S/LJ)Input - 1.8 V - 3.3 V, with Hysteresis
SDA/CDIN
(MCLKDIV2) Input/Output 1.8 V - 3.3 V, CMOS/Open Drain 1.8 V - 3.3 V, with Hysteresis
AD0/CS
(DEM) Input - 1.8 V - 3.3 V
MCLK Input - 1.8 V - 3.3 V
LRCK Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V
SCLK Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V
TSTO
(M/S)Input/Output 1.8 V - 3.3 V, CMOS 1.8 V - 3.3 V
SDIN Input - 1.8 V - 3.3 V
Ta ble 1. I/O Power Rails
DS723A1 9
CS43L21
2. TYPICAL CONNECTION DIAGRAMS
1 µF
+1.8 V or +2.5 V
1 µF
VQ
FILT+
0.1 µF
1 µF
DGND
VL
0.1 µF
+1.8 V, +2 .5 V
or +3.3 V
SCL/CCLK
SDA/CDIN
RESET
2 k Ω
See Note 1
LRCK
AGND
AD0/CS
MCLK
SCLK
0.1 µF
VA_HP
VD
SDIN
CS43L21
2 k Ω
1 µF
+1.8 V or +2.5 V
AOUTB
AOUTA
470 Ω
470 Ω
C
CRext
Rext
See Note 2
Note 1:
Resistors are required for I²C
control port operation
For best response to Fs/2 :
()
4704470
×
+
=
ext
ext
RFs
R
C
π
This circuitry is intended for applications where the
CS43L21 connects directly to an unbalanced output of the
device. For internal routing applications pleas e see the
DAC Analog Output Characteristics section for loading
limitations.
Note 2 :
Digital Audio
Processor
0.1 µF
VA
Headph on e Out
Left & Right
Line Le vel Out
Left & Right
Speaker Driver
FLYP
FLYN
VSS_HP
GND_HP
1 µF
51.1 Ω
0.022 µF
1 µF **
**
* *Use low ESR ceramic capacitors.
See Note 3
Note 3:
Series resistance in the path of the power supplies must
be avoided. Any voltage drop on VA_HP will directly
impact the negative charge pump supply (VSS_HP) and
result in clipping on the audio output.
1.5 µF
1.5 µF
See Note 4
Note 4 :
Larger capacitors, such as 1 .5 µF, improves the char ge
pump performance (and subsequent THD+N) at the full
scale output power achieved with gain (G) settings
greater than default.
**
**
Figure 1. Typical Connection Diagram (Software Mode)
10 DS723A1
CS43L21
+1.8V or +2.5V
1 µF
VQ
FILT+
0.1 µF
1 µF
DGND
VL
0.1 µF
+1.8V, 2.5 V
or +3.3V
I²S/LJ
MCLKDIV2
RESET
LRCK
AGND
DEM
MCLK
SCLK
0.1 µF
VA_HP
VD
SDIN
CS43L21
1 µF
+1.8V or +2.5V
AOUTB
AOUTA
470Ω
470Ω
C
CRext
Rext
See Note 2
For best response to Fs/2 :
()
4704470
×
+
=
ext
ext
RFs
R
C
π
This circuitry is intended for applications where the CS43L21 connects directly to an unbalanced output of the device. For
internal routing applications please see the DAC Analog Output Characteristics section for loading limitations .
Note 2 :
Digital Audio
Processor
0.1 µF
VA
Headphone Out
Left & Right
Line Level Out
Left & Right
Speaker Driver
FLYP
FLYN
VSS_HP
GND_HP
51.1 Ω
0.022 µF
1 µF See Note 1
Note 1:
Series resistance in the path of the power supplies (typically
used for added filtering) must be avoided. Any voltage drop
on VA_HP will directly impact the negative charge pump
supply (VSS_HP) and result in clipping on the audio output.
1 µF
1 µF **
**
* *Use low ESR ceramic capacitors.
See Note 3
Note 3:
Pull-up to VL (47 kΩfor Master Mode. Pull-
down to DGND for Slave Mode.
47kΩTSTO/M/S
VL or DGND
kΩ
Figure 2. Typical Conn ection Diagram (Hardware Mode)
DS723A1 11
CS43L21
3. CHARACTERISTIC AND SPECIFICATION TABLES
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per-
formance characteristics and specifications are derived from measurements taken at nominal supply voltages and
TA = 25° C.)
SPECIFIED OPERATING CONDITIONS
(AGND=DGND=0 V, all voltages with respect to ground.)
ABSOLUTE MAXIMUM RATINGS
(AGND = DGND = 0 V; all voltages with respect to ground.)
WARNING:Op eration at or beyo nd these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
Notes: 1. The device will operate properly over the full range of the analog, headphone amplifier, digital core and
serial/control port interface supplies.
2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
3. The maximum over/under voltage is limited by the input current.
Parameters Symbol Min Nom Max Units
DC Power Supply (Note 1)
Analog Core VA 1.65
2.37 1.8
2.5 1.89
2.63 V
V
Headphone Amplifier VA_HP 1.65
2.37 1.8
2.5 1.89
2.63 V
V
Digital Core VD 1.65
2.37 1.8
2.5 1.89
2.63 V
V
Serial/Control Port Interface VL 1.65
2.37
3.14
1.8
2.5
3.3
1.89
2.63
3.47
V
V
V
Ambient Temperature Commercial - CNZ
Automotive - DNZ TA-10
-40 -
-+70
+85 °C
°C
Parameters Symbol Min Max Units
DC Power Supply Analog
Digital
Serial/Control Port Interface
VA, VA_HP
VD
VL
-0.3
-0.3
-0.3
3.0
3.0
4.0
V
V
V
Input Current (Note 2) Iin -±10mA
Digital Input Voltage
(Note 3) VIND -0.3 VL+ 0.4 V
Ambient Operating Temperature (pow er applied) TA-50 +115 °C
Stor age Tempera tu re Tstg -65 +150 °C
12 DS723A1
CS43L21
ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ)
(Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement
bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 10 kΩ, CL = 10 pF for the line output
(see Figure 3), and test load RL = 16 Ω, CL = 10 pF (see Figure 3) for the headphone o utput. HP_GAIN[2:0] = 011.)
Parameter (Note 4) VA = 2.5V (nominal)
Min Typ Max VA = 1.8V (nominal)
Min Typ Max Unit
RL = 10 kΩ
Dynamic Range
18 to 24-Bit A-weighted
unweighted
16-Bit A-weighted
unweighted
92
89
-
-
98
95
96
93
-
-
-
-
89
86
-
-
95
92
93
90
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-86
-75
-35
-86
-73
-33
-78
-
-
-
-
-
-
-
-
-
-
-
-88
-72
-32
-88
-70
-30
-82
-
-
-
-
-
dB
dB
dB
dB
dB
dB
RL = 16 Ω
Dynamic Range
18 to 24-Bit A-weighted
unweighted
16-Bit A-weighted
unweighted
92
89
-
-
98
95
96
93
-
-
-
-
89
86
-
-
95
92
93
90
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-75
-75
-35
-75
-73
-33
-69
-
-
-
-
-
-
-
-
-
-
-
-75
-72
-32
-75
-70
-30
-69
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Other Characteristics for RL = 16
Ω
or 10 k
Ω
Output Parameters Modulation Index (MI)
(Note 5) Analog Gain Multiplier (G) -0.6787
0.6047 --
0.6787
0.6047 -
Full-scale Output Voltage (2•G•MI•VA) (Note 5) Refer to Table “Line Output Voltage Characteristics” on
page 14 Vpp
Full-scale Outpu t Power (Note 5) Refer to Table “Headphone Output Power Characteristics”
on page 15 mW
Interchannel Isolation (1 kHz) 16 Ω
10 kΩ
-
-80
95 -
--
-80
93 -
-dB
dB
Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB
Gain Drift - ±100 - - ±100 - ppm/°
C
AC-Load Resistance (RL)(Note 6) 16 - - 16 - - Ω
Load Capacitance (CL)(Note 6) - - 150 - - 150 pF
DS723A1 13
CS43L21
ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ)
(Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement
bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz and 96 kHz; test load RL = 10 kΩ, CL = 10 pF for the
line output (see Figure 3), and test load RL = 16 Ω, CL = 10 pF (see Figure 3) for the headphone output.
HP_GAIN[2:0] = 011.)
Parameter (Note 4) VA = 2.5V (nominal)
Min Typ Max VA = 1.8V (nominal)
Min Typ Max Unit
RL = 10 kΩ
Dynamic Range
18 to 24-Bit A-weighted
unweighted
16-Bit A-weighted
unweighted
90
87
-
-
98
95
96
93
-
-
-
-
87
84
-
-
95
92
93
90
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-86
-75
-35
-86
-73
-33
-73
-
-
-
-
-
-
-
-
-
-
-
-88
-72
-32
-88
-70
-30
-80
-
-
-
-
-
dB
dB
dB
dB
dB
dB
RL = 16
Ω
Dynamic Range
18 to 24-Bit A-weighted
unweighted
16-Bit A-weighted
unweighted
90
87
-
-
98
95
96
93
-
-
-
-
87
84
-
-
95
92
93
90
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise
18 to 24-Bit 0 dB
-20 dB
-60 dB
16-Bit 0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-75
-75
-35
-75
-73
-33
-67
-
-
-
-
-
-
-
-
-
-
-
-75
-72
-32
-75
-70
-30
-67
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Other Characteristics for RL = 16
Ω
or 10 k
Ω
Output Parameters Modulation Index (MI)
(Note 5) Analog Gain Multiplier (G) -0.6787
0.6047 --
0.6787
0.6047 -
Full-scale Output Voltage (2•G•MI•VA) (Note 5) Refer to Table “Line Output Voltage Characteristics” on
page 14 Vpp
Full-scale Output Power (Note 5) Refer to Table “Headphone Output Power Characteristics”
on page 15 mW
Interchannel Isolation (1 kHz) 16 Ω
10 kΩ
-
-80
95 -
--
-80
93 -
-dB
dB
Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB
Gain Drift - ±100 - - ±100 - ppm/°
C
AC-Load Resistance (RL)(Note 6) 16 - - 16 - - Ω
Load Capacitance (CL)(Note 6) - - 150 - - 150 pF
14 DS723A1
CS43L21
LINE OUTPUT VOLTAGE CHARACTERISTICS
Test conditions (u nless otherwise specified) : Inp ut test signal is a fu ll-scale 997 Hz sine wave; measureme nt band-
width is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 10 kΩ, CL = 10 pF (see Figure 3).
Parameter VA = 2.5V (nominal)
Min Typ Max VA = 1.8V (nominal)
Min Typ Max Unit
AOUTx Voltage Into RL = 10 k
Ω
HP_GAIN[2:0] Analog
Gain (G) VA_HP
000 0.3959 1.8 V - 1.34 - - 0.97 - Vpp
2.5 V - 1.34 - - 0.97 - Vpp
001 0.4571 1.8 V - 1.55 - - 1.12 - Vpp
2.5 V - 1.55 - - 1.12 - Vpp
010 0.5111 1.8 V - 1.73 - - 1.25 - Vpp
2.5 V - 1.73 - - 1.25 - Vpp
011 (default) 0.6047 1.8 V - 2.05 - 1.41 1.48 1.55 Vpp
2.5 V 1.95 2.05 2.15 - 1.48 - Vpp
100 0.7099 1.8 V - 2.41 - - 1.73 - Vpp
2.5 V - 2.41 - - 1.73 - Vpp
101 0.8399 1.8 V - 2.85 - 2.05 Vpp
2.5 V - 2.85 - - 2.05 - Vpp
110 1.0000 1.8 V - 3.39 - - 2.44 - Vpp
2.5 V - 3.39 - - 2.44 - Vpp
111 1.1430 1.8 V (See (Note 7) 2.79 Vpp
2.5 V - 3.88 - - 2.79 - Vpp
DS723A1 15
CS43L21
HEADPHONE OUTPUT POWER CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement band-
width is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 16 Ω, CL = 10 pF (see Figure 3).
4. One-half LSB of triangular PDF dither is added to data.
5. Full-scale output voltage and power is determined by the gain setting, G, in register “Headphone Analog
Gain (HP_GAIN[2:0])” on page 41. High gain settings at certain VA and VA_HP supply levels may
cause clipping when the audio signal approaches full-scale, maximum power output, as shown in
Figures 21 - 24 on page 55.
6. See Figure 3. RL and CL reflect the recommended minimum resistance and maximum capacitance re-
quired for the internal op-amp's stability and signal integrity. In this circuit topology, CL will effectively
move the band-limiting pole of the amp in the output stage. Increasing this value beyond the recom-
mended 150 pF can cause the internal op-amp to become unstable.
7. VA_HP settings lower than VA reduces th e headroom of the hea dphone amplifier. As a resu lt, the DAC
may not achieve the full THD+N performance at full-scale output voltage and power.
Parameter VA = 2.5V (nominal)
Min Typ Max VA = 1.8V (nominal)
Min Typ Max Unit
AOUTx Power Into RL = 16
Ω
HP_GAIN[2:0] Analog
Gain (G) VA_HP
000 0.3959 1.8 V - 14 - - 7 - mWrms
2.5 V - 14 - - 7 - mWrms
001 0.4571 1.8 V - 19 - - 10 - mWrms
2.5 V - 19 - - 10 - mWrms
010 0.5111 1.8 V - 23 - - 12 - mWrms
2.5 V - 23 - - 12 - mWrms
011 (default) 0.6047 1.8 V (Note 7) -17 -mW
rms
2.5 V - 32 - - 17 - mWrms
100 0.7099 1.8 V (Note 7) -23 -mW
rms
2.5 V - 44 - - 23 - mWrms
101 0.8399 1.8 V (Note 5) mWrms
2.5 V -32 -mW
rms
110 1.0000 1.8 V (Note 5, 7)mWrms
2.5 V mWrms
111 1.1430 1.8 V mWrms
2.5 V mWrms
AOUTx
AGND
RL
CL
0.022 µF
51 Ω
Figure 3. Headphone Output Test Load
16 DS723A1
CS43L21
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Notes: 8. Response is clock dependent and will scale with Fs. Note that the response plots (Figure 27 to Figure 30
on page 60) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
9. Measurement Bandwidth is from Stopband to 3 Fs.
SWITCHING SPECIFICATIONS - SERIAL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL.)
Parameter (Note 8) Min Typ Max Unit
Frequency Response 10 Hz to 20 kHz -0.01 - +0.08 dB
Passband to -0.05 dB corner
to -3 dB corner 0
0-
-0.4780
0.4996 Fs
Fs
StopBand 0.5465 - - Fs
StopBand Attenuation (Note 9) 50 - - dB
Group Delay - 10.4/Fs - s
De-emphasis Error Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
+1.5/+0
+0.05/-0.25
-0.2/-0.4
dB
dB
dB
Parameters Symbol Min Max Units
RESET pin Low Pulse Width (Note 10) 1-ms
MCLK Frequency 1.024 38.4 MHz
MCLK Duty Cycle (Note 11) 45 55 %
Slave Mode
Input Sample Rate (LRCK) Quarter-Speed Mode
Half-Speed Mode
Single-Speed Mode
Double-Speed Mode
Fs
Fs
Fs
Fs
4
8
4
50
12.5
25
50
100
kHz
kHz
kHz
kHz
LRCK Duty Cycle 45 55 %
SCLK Frequency 1/tP-64•F
sHz
SCLK Duty Cycle 45 55 %
LRCK Setup Time Before SCLK Rising Edge ts(LK-SK) 40 - ns
SDIN Setup Time Before SCLK Rising Edge ts(SD-SK) 20 - ns
SDIN Hold Time After SCLK Rising Edge th20 - ns
DS723A1 17
CS43L21
10. After powering u p the CS43L21, RESET should be held low after the power su pplies and clocks are set-
tled.
11. See “Example System Clock Frequencies” on page 57 for typical MCLK frequencies.
12. See “Master” on page 29
Master Mode (Note 12 )
Output Sample Rate (LRCK) All Speed Modes Fs-Hz
LRCK Duty Cycle 45 55 %
SCLK Frequency 1/tP- 64•FsHz
SCLK Duty Cycle 45 55 %
LRCK Edge to SDIN MSB Rising Edge td(MSB) 52 ns
SDIN Setup Time Before SCLK Rising Edge ts(SD-SK) 20 - ns
SDIN Hold Time After SCLK Rising Edge th20 - ns
Parameters Symbol Min Max Units
//
//
//
//
//
//
ts(SD-SK)
MSB MSB-1
LRCK
SCLK
SDIN
ts(LK-SK) tP
th
Figure 4. Serial Audio Interface Slave Mode Timing
MCLK
128
-----------------
//
//
//
//
//
//
ts(SD-SK)
MSB MSB-1
LRCK
SCLK
SDIN
td(MSB)
tP
th
Figure 5. Serial Audio Interface Master Mo de Timing
18 DS723A1
CS43L21
SWITCHING SPECIFICATIONS - I²C® CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL=30pF)
13. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
Parameter Symbol Min Max Unit
SCL Clock Frequency fscl - 100 kHz
RESET Rising Edge to Start tirs 500 - ns
Bus Free Time Between Transmissions tbuf 4.7 - µs
Start Condition Hold T ime (prior to first clock pulse) thdst 4.0 - µs
Clock Low time tlow 4.7 - µs
Clock High Time thigh 4.0 - µs
Setup Time for Repeated Start Condition tsust 4.7 - µs
SDA Hold Time from SCL Falling (Note 13) thdd 0-µs
SDA Setup time to SCL Rising tsud 250 - ns
Rise Time of SCL and SDA trc -1µs
Fall T ime SCL and SDA tfc - 300 ns
Setup Time for Stop Condition tsusp 4.7 - µs
Acknowledge Delay from SCL Fallin g tack 300 3450 ns
tbuf thdst thdst
tlow tr
tf
thdd
thigh
tsud tsust
tsusp
Stop Start Start Stop
Repeated
SDA
SCL
tirs
RST
Figure 6. Control Port Timing - I²C
DS723A1 19
CS43L21
SWITCHING CHARACTERISTICS - SPI™ CONTROL PORT
(Inputs: Logic 0 = DGND , Lo gic 1 = VL)
14. Data must be held for sufficient time to bridge the transition time of CCLK.
15. For fsck <1 MHz.
Parameter Symbol Min Max Units
CCLK Clock Frequency fsck 06.0MHz
RESET Rising Edge to CS Falling tsrs 20 - ns
CS Falling to CCLK Edge tcss 20 - ns
CS High Time Between Transmissions tcsh 1.0 - µs
CCLK Low Time tscl 66 - ns
CCLK High Time tsch 66 - ns
CDIN to CCLK Rising Setup T ime tdsu 40 - ns
CCLK Rising to DATA Hold Time (Note 14) tdh 15 - ns
Rise T ime of CCLK and CDIN (Note 15) tr2 -100ns
Fall Time of CCLK and CDIN (Note 15) tf2 -100ns
CS
CCLK
CDIN
RST tsrs
tscl
tsch
tcss tr2
tf2
tcsh
tdsu tdh
Figure 7. Control Port Timing - SPI Format
20 DS723A1
CS43L21
DC ELECTRICAL CHARACTERISTICS
(AGND = 0 V; all voltages with respect to ground.)
16. The DC current draw represents the allowed current draw from the VQ pin due to typical leakage
through electrolytic de-coupling capacitors.
17. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also
increase the PSRR.
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS
18. See “Digital I/O Pin Characteristics” on page 8 for serial and contr ol port power rails.
Parameters Min Typ Max Units
VQ Characteristics
Nominal Voltage
Output Impedance
DC Current Source/Sink (Note 16 )
-
-
-
0.5•VA
23
-
-
-
10
V
kΩ
µA
FILT+ -VA-V
VSS_HP Characteristics
Nominal Voltage
DC Current Source -
--0.8•(VA_HP) -
10 V
µA
Power Supply Rejection Ratio (PSRR) (Note 17) 1 kHz -60-dB
Parameters (Note 18) Symbol Min Max Units
Input Leakage Current Iin -±10µA
Input Capacitance -10pF
1.8 V - 3.3 V Logic
High-Level Output Voltage (IOH = -100 µA) VOH VL - 0.2 - V
Low-Level Output Voltage (IOL = 100 µA) VOL -0.2V
High-Level Input Voltage VIH 0.68•VL - V
Low-Level Input Vo ltage VIL - 0.32•VL V
DS723A1 21
CS43L21
POWER CONSUMPTION
See (Note 19)
19. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample rate =
48 kHz; No load. Digital (VD) and logic (VL) supply current will vary depending on speed mode and mas-
ter/slave operation.
20. RESET pin 25 held LO, all clocks and data lines are held LO.
21. RESET pin 25 held HI, all clocks and data lines are held HI.
22. VL current will slightly increase in master mode.
Power Ctl. Registers Typical Current (mA)
Operation
02h 03h
PDN_DACB
PDN_DACA
BIT 4
BIT 3
BIT 2
BIT 1
PDN
BIT 3
BIT 2
BIT 1
V
iVA_HP iVA iVD iVL
(Note 22) Total
Power
(mWrms)
1Off (Note 20) xxxxxxxxxx1.8 0 0 0 0 0
2.5 0 0 0 0 0
2 Standby (Note 21) xxxxxx1xxx1.8 0 0.01 0.02 0 0.05
2.5 0 0.01 0.03 0 0.10
5 Mono Playback 10111101111.8 1.66 1.40 2.35 0.01 9.74
2.5 2.03 1.71 3.48 0.02 18.08
6 Stereo Playback 00111101111.8 2.77 2.05 2.35 0.01 12.93
2.5 3.21 2.50 3.49 0.02 23.02
22 DS723A1
CS43L21
4. APPLICATIONS
4.1 Overview
4.1.1 Architecture
The CS43L21 is a highly integrated, low power, 24-bit audio D/A comprised of stereo digital-to-analog
converters (DAC) designed using multi-bit delta-sigma techniques. The DAC operates at an oversampling
ratio of 128Fs. The D/A op erates in one of four sample r ate speed modes: Quarter, Half, Single a nd Dou-
ble. It accepts and is capable of generating serial por t clocks (SCLK, LRCK) derived from an input Master
Clock (MCLK).
4.1.2 Line & Headphone Outputs
The analog output portion of the D/A includes a headphone amplifier capable of driving headphone and
line-level loads. An on-chip charge pump creates a negative headphone supply allowing a full-scale out-
put swing centered around ground. This eliminates th e need for large DC- Blocking capacitors and allows
the amplifier to deliver more power to headphone loads at lower supply voltages. Eight gain settings for
the headphone amplifie r are available.
4.1.3 Signal Processing Engine
A signal processing engine is available to process serial input D/A data before output to the DAC. The
D/A data has independen t volume co ntrols and mixing functions such as mono mixes a nd left/rig ht chan-
nel swaps. A Tone Control provides bass and treble at four selectable corner frequencies. An automatic
level control provides limiting capabilities at programmable attack and release rates, maximum thresholds
and soft ramping. A 15/50 µs de-emphasis filter is also available at a 44.1 kHz sample rate.
4.1.4 Beep Generator
A beep may be generated internally at select frequencies across approximately two octave major scales
and configured to occur continuously, periodically or at single time intervals controlled by the user. Volume
may be controlled independently.
4.1.5 Device Control (Hardware or So ftware Mode)
In Software Mode, all functions and features may be controlled via a two-wire I²C or three-wire SPI control
port interface . In Hard wa re Mod e , a limited feature set may be controlled via stand-alone control pins.
4.1.6 Power Management
Two Software M ode control regist ers provide inde pendent po wer-down con trol of the DAC, allowin g op-
eration in select applications with minimal power consumption.
DS723A1 23
CS43L21
4.2 Hardware Mode
A limited feature-set is available when the D/A powers up in Hardware Mode (see “Recommended Power-
Up Sequence” section on page 31) and may be controlled via stan d-alone control pins. Table 2 shows a list
of functions/features, the default configuration and the associated stand-alone control available.
Hardware Mode Feature/Function Summary
Feature/Function Default Configuratio n Stand-Alone Control Note
Power Control Device
DACx Powered Up
Powered Up --
Auto-Detect Enabled - -
Spee d Mode Serial Port Slave
Serial Port Master Auto-Detect Speed Mode
Single-Speed Mode --
MCLK Divide (Selectable) “MCLKDIV2” pin 2 see Section
4.4 on page 28
Serial Port Master / Slave Selection (Selectable) “M/S” pin 29 see Section
4.4 on page 28
Interface Control DAC (Selectable) “I²S/LJ” pin 3 see Section
4.5 on page 30
DAC Volume & Gain HP Gain
AOUTx Volume
Invert
Soft Ramp
Zero Cross
G = 0.6047
0 dB
Disabled
Enabled
Disabled
--
DAC De-Emphasis (Selectable) “DEM” pin 4 see Section
on page 24
Signal Processing Engine (SPE) Mix
Beep
Tone Control
Peak Detect and Limiter
Disabled
Disabled
Disabled
Disabled
--
Data Selection Data Input (PCM) to DAC - -
Channel Mix DAC PCMA = L; PCMB = R - -
Charge Pump Frequency (64xFs)/7 - -
Table 2. Hardware Mode Feature Summary
24 DS723A1
CS43L21
4.3 Analog Outputs
AOUTA and AOUTB are the ground -centered line or headpho ne outputs. Various signal processing options
are available, including an internal Beep Generator. The desired path to the DAC must be selected using
the DATA_SEL[1:0] bits.
4.3.1 De-Emphasis Filter
The CODEC includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter re-
sponse is shown in Figure 9. The de-empha sis feature is included to acco mmodate audio recordings that
utilize 50/15 µs pre-emphasis equalization as a me ans of nois e r edu ction. De -e mph asis is o nly availa ble
in Single-Speed Mode.
Software
Controls: “DAC Control (Address 09h)” on page 42.
Software
Controls: “DAC Control (Address 09h)” on page 42.
Hardware
Control:
Pin Setting Selection
“DEM” pin 4. LO No De-Emphasis
HI De-Emphasis Applied
Charge
Pump
Left/Right
HP Out
Switched
Capac i to r DAC
and Filter
Headphone
Amp - GND
Centered
PDN_DACA
PDN_DACB
DATA_SEL[1:0]
00
CHRG_FREQ[3:0]
01
HP_GAIN[2:0]
Beep
Generator
Bass/
Treble/
Control
ΣVOL
Peak
Detect
Limiter
Chnl Vol.
Settings
Demph VOL
VOL
+12dB/-102dB
0.5dB steps
OUTA_VOL[7:0]
OUTB_VOL[7:0]
+12dB/-51.5dB
0.5dB steps
PCMMIXA_VOL[6:0]
PCMMIXB_VOL[6:0]
0dB/-50dB
2.0dB ste p s
BPVOL[4:0]
MUTE_PCMMIXA
MUTE_PCMMIXB
DEEMPH
BASS[3:0]
TREB[3:0]
+12.0dB/-10.5dB
1.5dB ste p s
BASS_CF[1:0]
TREB_CF[1:0]
TC_EN
SIGNAL PROCESSING ENGINE (SPE)
DAC_SZC[1:0]
DACA_MUTE
DACB_MUTE
INV_DACA
INV_DACB
DAC_SNGVOL
AMUTE
ARATE[7:0]
RRATE[7:0]
MAX[2:0]
MIN[2:0]
LIM_SRDIS
LIM_ZCDIS
LIMIT_EN
PCMA[1:0]
PCMB[1:0]
PCM Serial Interface
OFFTIME[2:0]
ONTIME[3:0]
FREQ[3:0]
REPEAT
BEEP
Channel
Swap
Figure 8. Output Architecture
DS723A1 25
CS43L21
4.3.2 Volume Controls
Two digital volume control functions offer independent control of the SDIN signal path into the mixer as
well as a combined control of the mixed signals. The volume controls are programmable to ramp in incre-
ments of 0.125 dB at a rate controlled by the soft ramp/zero cross settings.
The signal paths may also be muted via mute control bits. When enabled, each bit attenuates the signal
to its maximum value. When the mute bit is disabled, the signal returns to the attenuation level set in the
respective volume control register. The attenuation is ramped up and down at the rate specified by the
DAC_SZC[1:0] bits.
4.3.3 Mono Channel Mixer
A channel mixer may be used to create a mix of the left and right channels for the SDIN data. This mix
allows the user to produce a MONO signal from a stereo source. The mixer may also be used to imple-
ment a left/righ t ch an ne l swap .
4.3.4 Beep Generator
The Beep Generator gen erates audio frequencies across approximately two octave major scales. It offe rs
three modes of operation: Continuous, multiple and single (one-shot) beeps. Sixteen on and eight off
times are availa ble .
Note: The Be ep is gen erated b efor e the limiter an d may affe ct desire d limitin g p erforma nce. If the limiter
function is used, it may be require d to set the Beep volume sufficiently below the threshold to prevent th e
peak detect from triggering. Since the master volume control, AOUTx_VOL[7:0], will affect the Beep vol-
ume, DAC volume may alternatively be controlled using the PCMMIXx_VOL[6:0] bits.
Software
Controls:
“PCMX Mixer Volume Control: PCMA (Address 10h) & PCMB (Address 11h)” on page 44“AOUTx
Volume Control: AOUTA (Address 16h) & AOUTB (Address 17h)” on page 49“DAC Output Control
(Address 08h)” on page 41
Software
Controls: “PCM Channel Mixer (Address 18h)” on page 49.
Software
Controls: “Beep Frequency & Timing Con figuration (Address 12h)” on page 45, “Beep Off Time & Volume
(Address 13h)” on page 46, “Beep Configuration & Tone Con figuration (Address 14h)” on page 47
Gain
dB
-10dB
0dB
Frequency
T2 = 15 µs
T1=50 µs
F1 F2
3.183 kHz 10.61 kHz
Figure 9. De-Emphasis Curve
26 DS723A1
CS43L21
4.3.5 Tone Control
Shelving filters are used to implement bass and treble (boost and cut) with four selectable corner frequen-
cies. Boosting will affect peak detect and limiting when levels exceed the maximum threshold settings.
4.3.6 Limiter
When enabled, th e limiter monitors the digital inpu t signal before the DAC modulator, detects when le vels
exceed the maximum threshold settings and lowers the AOUT volume at a programmable attack rate be-
low the maximum threshold. When the input signal level falls below the maximum threshold, the AOUT
volume returns to its original level set in the Volume Control register at a programmable release rate. At-
tack and release rates ar e affected by the DAC soft ramp/zero cross settings and sample rate, Fs. Limiter
soft ramp and zero cross dependency may be independently enabled/disabled.
Recommended settings: Best limiting performance may be realized with the fastest attack and slowest
release settin g with soft ramp enab led in the control re gisters. The “c ushion” bits allow th e user to set a
threshold slightly below the maximum threshold for hysteresis control - this cushions the sound as the lim-
iter attacks and releases.
Note:
1. When the Limiter is enabled, the AOUT Volume is automatically controlled and should not be adjusted
manually. Alternative volume control may be realized using the PCMM IXx_VOL[6:0] bits.
2. The Limiter ma intains the output signal between the CUSH and MAX thresholds. As the dig ital input
signal level changes, the level-controlled output may not always be the same but will always fall within
the thresholds.
Software
Controls: “Tone Control (Address 15h)” on page 48 .
Software
Controls: “Limiter Release Rate Register (Address 1Ah)” on page 51, “Limiter Attack Rate Register (Address
1Bh)” on page 52, “DAC Control (Address 09h)” on page 42
FREQ[3:0]
...
BPVOL[4:0]
ONTIME[3:0] OFFTIME[2:0]
REPEAT = '0'
BEEP = '1'
REPEAT = '1'
BEEP = '0'
REPEAT = '1'
BEEP = '1'
SINGLE-BEEP: Beep turns on at a
configurable frequency (FREQ) and
volume (BPVOL) for the duration of
ONTIME. BEEP must be cleared
and set for additional beeps.
MULTI-BEEP: Beep turns on at a configurable frequency (FREQ)
and volume (BPVOL) for the duration of ONTIME and turns off for
the duration of OFFTIME. On and off cycles are repeated until
REPEAT is cleared.
CONTINUOUS BEEP: Beep turns on at a configurable frequency (FREQ) and volume (BPVOL) and remains
on until REPEAT is cleared.
Figure 10. Beep Configuration Options
DS723A1 27
CS43L21
4.3.7 Lin e-Level Outputs and Filtering
The CODEC contains on-chip buffer amplifiers cap able of prod ucing line level single-ended outputs on
AOUTA and AOUTB. These amp lifiers are groun d center ed and do not have any DC o ffset. A load stabi-
lizer circuit, shown in the “ Typical Connection Diagram (Software Mode)” on page 9 and the “Typical Con-
nection Diagr am (Hardw are Mo de)” on page 10, is required on the analog outputs. This allows the DAC
amplifiers to drive line or hea dphone outputs.
Also shown in the T ypical Connection diagrams is the recommended passive o utput filter to support h igh-
er impedances such as those found on the inputs to operational amplifiers. “Rext”, shown in the typical
connection diag ra m s, is the input imp e da nc e of the re ce ivin g de vice.
The invert and digital gain controls may be used to provide phase and/or amplitude compensation for an
external filter.
The delta-sigma conve rsion process produces high frequency noise beyond the audio passband, most of
which is removed by the on-chip analog filter s. The remainin g out-of-band noise can be attenu ated using
an off-chip low pass filter.
Software
Controls: “DAC Output Control (Address 08h)” on page 41, “AOUTx Volume Control: AOUTA (Address 16h)
& AOUTB (Address 17h)” on page 49.
MAX[2:0]
Output
(after Limiter)
Input
RRATE[5:0]ARATE[5:0]
Volume
Limiter
CUSH[2:0]
ATTACK/RELEASE SOUND
CUSHION
MAX[2:0]
AOUTx_VOL[7:0] volume
control should NOT be
adjusted manually when
Limiter is enabled.
Figure 11. Peak Detect & Limiter
28 DS723A1
CS43L21
4.3.8 On-Chip Charge Pump
An on-chip charge pump derives a negative supply voltage from the VA_HP supply. This provides dual
rail supplies allowing a full-scale output swing centere d around groun d and eliminates the need for large ,
DC-blocking capacitors. Added benefits include greater pop suppression and improved low frequency
(bass) response. Note: Series resistance in the path of the power supplies must be avoided. Any voltage
drop on the VA_HP supply will directly impact the derived negative voltage on the charge pump supply,
VSS_HP, and may result in clipping.
The FLYN and FLYP pins connect to internal switches that charges and dischar ges the external capacitor
attached, at a default switching frequency. This frequency may be adjusted in the control port registers.
Increasing the charge-pumping capacitor will slightly decease the pumping frequency. The capacitor con-
nected to VSS_HP acts as a charge reservoir for the negative supply as well as a filter for the ripple in-
duced by the charge pump. Increasing this capacitor will decrease the ripple on VSS_HP. Refer to the
typical connection diagrams in Figure 1 on pag e 9 or Figure 2 on page 10 for the recommended capacitor
values for the charge pump circuitry.
4.4 Serial Port Clocking
The D/A serial audio interface port operates either as a slave or master. It accepts externally generated
clocks in slave mode and will generate synchronous clocks derived from an input master clock (MCLK) in
master mode.
The frequency of the MCLK must be an integer multip le of, and synchronous with, the system sample rate,
Fs. The LRCK frequency is equa l to Fs, the frequency at which a udio samples for each channel are clocked
into or out of the device.
The SPEED and MCLKDIV2 software control bits or the M/S and MCLKDIV2 stand-alone control pins, con-
figure the device to generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode.
The value on the M/S pin is latched immediately after powering up in Hardware Mode.
Software
Controls: “Charge Pump Frequency (Address 21h)” on page 53.
Software
Control: , “DAC Control (Address 09h)” on page 42.
Hardware
Control:
Pin Setting Selection
“M/S” pin 29 47 kΩ Pull-down Slave
47 kΩ Pull-up Master
“MCLKDIV2” pi n 2 LO No Divide
HI MCLK is divided by 2 prior
to all internal circuitry.
DS723A1 29
CS43L21
4.4.1 Slave
LRCK and SCLK are inputs in Slave Mode. The speed of the D/A is automatically determined based on
the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will then
require an intern al divide-by- two of MCLK* u sing eith er th e MCLKDIV2 bit or the M CLKDIV2 stand-a lone
control pin.
Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed
mode must be selected using the SPEED[1:0] bits.
4.4.2 Master
LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled).
In Hardware Mode the D/A operates in single-speed only. In Software Mode, the D/A operates in either
quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits.
Auto-Detect QSM HSM SSM DSM
Disabled
(Software
Mode only)
512, 768, 1024, 1536,
2048, 3072 256, 384, 512, 768,
1024, 1536 128, 192, 256, 384,
512, 768 128, 192, 256, 384
Enabled 1024, 1536, 2048*,
3072* 512, 768, 1024*, 1536* 256, 384, 512*, 768* 128, 192, 256*, 384*
*MCLKDIV2 must be enabled.
Table 3. MCLK/LRCK Ratios
÷ 256
÷ 128
÷ 512
LRCK Output
(Equal to Fs)
Single
Speed
Quarter
Speed
Half
Speed
01
10
11
SCLK Output
÷ 2
÷ 1 0
1
MCLK
MCLKDIV2
÷ 128 00
÷ 4
÷ 2
÷ 8
Single
Speed
Quarter
Speed
Half
Speed
01
10
11
÷ 2 00
Double
Speed
Double
Speed
SPEED[1:0]
Figure 12. Master Mode Timing
30 DS723A1
CS43L21
4.4.3 High-Impedance Digital Output
The serial port may be placed on a clock/data bus that allows multiple masters for the SCLK/LRCK I/O
without the need for external buffers. The 3ST_SP bit places the internal buffers for these I/O in a high-
impedance state , allo win g an ot he r de vice to transmit cloc ks with ou t bu s con te nt ion .
4.4.4 Quarter- and Half-Speed Mode
Quarter-Speed Mode (QSM) and Half-Speed Mode (HSM) allow lower sample rates while maintaining a
relatively flat noise floor in the typical audio band of 20 Hz - 20 kHz. Single-Speed Mode (SSM) will allow
lower frequency sample rates; however, the DAC's noise floor, that normally rises out-of-band, will scale
with the lower sample rate and begin to rise within the audio band. QSM and HSM corrects for most of
this scaling, effectively increasing the dynamic range of the CODEC at lower sample rates, relative to
SSM.
4.5 Digital Interface Formats
The serial port opera tes in standard I²S, Left-Justified or Right-Justifieddi gital interface formats with varying
bit depths from 16 to 24. Data is clocked into the DAC on the rising edge of SCLK. Figures 14-17 illustrate
the general structure of each format. Refer to “Switching Specifications - Serial Port” on page 16 for exact
timing relationship between clocks and data.
Software
Control: “Interface Control (Address 04h)” on page 41.
Hardware
Control:
Pin Setting Selection
“I²S/LJ” pin 3 LO Left-Justified Interface
HI I²S Interface
CS42L51
Transmitting Device #1 Transmitting Device #2
Receiving Device
3ST_SP
SCLK/LRCK
Figure 13. Tri-State SCLK/LRCK
LRCK
SCLK
MSB LSB MSB LSB
AOUTA / AINxA
Left Channe l Right Channel
SDIN
AOUTB / AINxB
MSB
Figure 14. I²S Forma t
DS723A1 31
CS43L21
4.6 Initialization
The initialization and Power-Down sequence flowchart is shown in Figure 17 on page 32. The CODEC en-
ters a Power-Do wn state up on initial powe r-up. The inter polation and decima tion filters, de lta-sigma mo du-
lators and control port registers are reset. The internal voltage reference, multi-bit DAC and switched-
capacitor low-pass filters are powered down.
The device will remain in the Power-Down state until the RESET pin is brought high. The contr ol port is ac-
cessible once RESET is high and the desi red reg ister se ttings can be loaded per the inter face descriptio ns
in “Software Mode” on page 33. If a valid write sequence to the control port is not made within approximately
10 ms, the will enter Hardware Mode.
Once MCLK is valid, the quiescent voltage, VQ , and th e internal voltage references, FILT+ will begin pow-
ering up to normal oper ation. The charge pump slowly powers up and cha rges the capacitors. Pow er i s th en
applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a mut-
ed state. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the
MCLK/LRCK frequency ratio and normal operation begins.
4.7 Recommended Power-Up Sequence
1. Hold RESET low until the power supplies are stable.
2. Bring RESET high. After approximately 10 ms, the device will ente r Ha rd wa re Mode .
3. For Software Mode operation, set the PDN bit to ‘1’b in under 10 ms. This will place the device in “stand-
by”.
4. Load the desired register settings while keeping the PDN bit set to ‘1’b.
5. Start MCLK to the appropriate frequency, as discussed in Section 4.4.
6. Set the PDN bit to ‘0’b.
7. Apply LRCKSCLK and SDIN for normal operation to begin.
8. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to
prevent power glitch related issues.
LRCK
SCLK
MSB LSB MSB LSB
Left Channel Right Channel
SDIN MSB
AOUTA / AINxA AOUTB / AINxB
Figure 15. Left-J ustified Format
LRCK
SCLK
MSB LSB MSB LSB
Left Channel Right Channel
SDIN
AOUTA AOUTB
Figure 16. Right-Justified Format (DAC only)
32 DS723A1
CS43L21
4.8 Recommended Power-Down Sequence
To minimize audible pops when turning off or placing the D/A in standby,
1. Mute the DAC’s.
2. Set the PDN bit in the power control register to ‘1’b. The D/A will not power down until it reaches a fully
muted sate. Do not remove MCLK until after the part has fully muted. Note that it may be necessary to
disable the soft ramp and/or zero cross volume transitions to achieve faster muting/power down.
3. Bring RESET low.
Initialization
Software Mode
Registers setup to
desired settings.
RESET = Low?
No Power
1. No audio signal
generated.
Off Mode (Power Applied)
1. No audio signal generated.
2. Control Por t Re gi s ters re se t
to default.
Control Port
Active
Control Port Valid
Write Seq. within
10 ms?
Hardware Mode
Minimal feature
set support.
PDN bit = '1'b?
Sub-Clocks Applied
1. LRCK valid.
2. SCLK valid.
3. Audio samples
processed.
Valid
MCLK/LRCK
Ratio?
No
Yes
No
Yes
No
Yes
Yes
No
Normal Operation
Audio signal generated per control port or stand-
alone settings.
Analog Output Freeze
1. Aout bias = last audio sample.
2. DAC Modulators stop operation.
3. Audible pops.
ERROR: MCLK removed
PDN bit set to '1'b
(software mode only)
Standby Mode
1. No audio signal generated.
2. Control Port Registers retain
settings.
Reset Transition
1. Pops suppressed.
Power Off Transition
1. Audible pops.
ERROR: Power removed
Valid
MCLK Applied?
No
20 ms delay
Charge Caps
1. VQ Charged to
quiescent voltage.
2. Filtx+ Charged.
Digital/Analog
Output Muted
50 ms delay
Charge Pump
Powered U p
Headphone Amp
Powered U p
20
µ
s delay
Headphone Amp
Powered Down
20
µ
s delay
Stand-By
Transition
1. Pops suppressed.
ERROR: MCLK/LRCK ratio change
RESET = Low
Figure 17. Initialization Flow Chart
DS723A1 33
CS43L21
4.9 Software Mode
The control port is used to access the registers allowing the D/A to be configured for the de sired operational
modes and formats. The ope ration of the control port may be completely a synchronous with respect to the
audio sample rates. However, to avoid potential interference problems, the control port pins should remain
static if no operation is required.
The control port operates in two mo des: SPI and I² C, with the D/A acting as a slave device. Software Mod e
is selected if there is a high-to-lo w transition on the AD0/CS pin after the RESET pin has been brought hi gh.
I²C Mode is selected by connectin g the AD0/CS pin through a resistor to VL or DGND, thereby permanently
selecting the desired AD0 bit address state.
4.9.1 SPI Control
In Software Mod e, CS is the CS43L21 chip-sel ect signal, CCLK i s the co ntrol port bit clock (input into the
from the microcontroller), CDIN is the input data line from the microcontroller. Data is clocked in on the
rising edge of CCLK. The D/A will only support write operations. Read request will be ignored.
Figure 18 shows the operation of the control port in Software Mode. To write to a register, bring CS low.
The first seven bits on CDIN form the chip address and must be 1001010. The eighth bit is a read/write
indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to be updated. The next eight bits are the data which will
be placed into the register designated by the MAP.
There is MAP auto-increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero,
the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-increment
after each byte is read or written, allowing block reads or writes of successive registers.
4.9.2 I²C Control
In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS pin. Pin AD0 forms the least significant bit of the chip address and should be connected
through a resistor to VL or DGND as desired. The state o f the pin is sensed w hile the CS43L21 is being
reset.
The signal timings for a read and write cycle are shown in Figure 19 and Figure 20. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the
CS43L21 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low
for a write). The upper 6 bits of the 7-bit address field are fixed at 100101. To communicate with a
CS43L21, the chip address field, which is the first byte sent to the CS43L21, should match 1 00101 followed
by the setting of the AD0 pin. The eighth bit of the address is the R/W bit. If the operation is a write, the
next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the op-
eration is a read, the contents of the register pointed to by the MAP will be output. Setting the auto-incre-
4 5 6 7
CCLK
CHIP ADDRESS (WRITE) MAP BYTE DATA
1 0 0 1 0 1 0 0
CDIN INCR 6 5 4 3 2 1 0 7 6 1 0
0 1 2 3 8 9 12 16 1710 11 13 14 15
DATA +n
CS
7 6 1 0
Figure 18. Control Port Timing in SPI Mode
34 DS723A1
CS43L21
ment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an
acknowledge bit. The ACK bit is output from the CS43L21 after each input byte is read and is input to the
CS43L21 from the microcontroller after each transm itted byte.
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 20, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 100101x0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto-increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 100101x1 (chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
4 5 6 7 24 25
SCL
CHIP ADDRES S ( WRITE) MAP BYTE DATA DATA +1
START
ACK STOP
ACKACKACK
1 0 0 1 0 1 AD0 0
SDA INCR 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0
0 1 2 3 8 9 12 16 17 18 1910 11 13 14 15 27 28
26
DATA +n
Figure 19. Control Port Timing, I²C Write
SCL
CHIP ADDRESS (WRIT E) MAP BYTE DATA DATA +1
START ACK
STOP
ACK
ACK
ACK
1 0 0 1 0 1 AD0 0
SDA 1 0 0 1 0 1 AD0 1
CHIP AD DRESS ( READ)
START
INCR 6 5 4 3 2 1 0 7 0 7 0 7 0
NO
168 9 12 13 14 154 5 6 7 0 1 20 21 22 23 24 26 27 28
2 3 10 11 17 18 19 25
ACK
DATA + n
STOP
Figure 20. Control Port Timing, I²C Read
DS723A1 35
CS43L21
4.9.3 Memory Address Pointer (MAP)
The MAP byte comes after the address byte and selects the register to be read or written. Refer to the
pseudo code above for implementation details.
4.9.3.1 Map Increment (INCR)
The device has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is
set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP
will auto-increment after each byte is read or written, allowing block reads or writes of successive registers.
36 DS723A1
CS43L21
5. REGISTER QUICK REFERENCE
Software mode register defaults are as shown. “Reserved” registers must maintain their default state.
AddrFunction76543210
01h ID Chip_ID4 Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID2 Rev_ID1 Rev_ID0
p39
default 11011001
02h Power Ctl. 1 Reserved PDN_DACB PDN_DACA ReservedReserved Reserved Reserved PDN
p39
default
000
1(See Note
2 on page
39)
1(See Note
2 on page
39)
1(See Note
2 on page
39)
1(See Note
2 on page
39)
0
03h Speed Ctl. &
Power Ctl. 2 AUTO SPEED1 SPEED0 3-ST_SP Reserved Reserved Reserved MCLKDIV2
p40
default 10101110
04h Interface Ctl. Reserved M/S DAC_DIF2 DAC_DIF1 DAC_DIF0 Reserved Reserved Reserved
p41
default 00000000
05h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default 00000000
06h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default 10100000
07h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default 00000000
08h DAC Output
Control HP_GAIN2 HP_GAIN1 HP_GAIN0 DAC_SNG
VOL INV_PCMB INV_PCMA DACB_
MUTE DACA_
MUTE
p41
default 01100000
09h DAC Control DATA_SEL1 DATA_SEL0 FREEZE Reserved DEEMPH AMUTE DAC_SZC1 DAC_SZC0
p42
default 00000110
0Ah Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default 00000000
0Bh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default 00000000
0Ch Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default 00000000
0Dh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default 00000000
0Eh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default 10000000
DS723A1 37
CS43L21
0Fh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default 10000000
10h Vol. Control
PCMMIXA MUTE_PCM
MIXA PCMMIXA
VOL6 PCMMIXA
VOL5 PCMMIXA
VOL4 PCMMIXA
VOL3 PCMMIXA
VOL2 PCMMIXA
VOL1 PCMMIXA
VOL0
p44
default 10000000
11h Vol. Control
PCMMIXB MUTE_PCM
MIXB PCMMIXB
VOL6 PCMMIXB
VOL5 PCMMIXB
VOL4 PCMMIXB
VOL3 PCMMIXB
VOL2 PCMMIXB
VOL1 PCMMIXB
VOL0
p44
default 10000000
12h BEEP Freq. &
OnTime FREQ3 FREQ2 FREQ1 FREQ0 ONTIME3 ONTIME2 ONTIME1 ONTIME0
p45
default 00000000
13h BEEP Off
Time & Vol OFFTIME2 OFFTIME1 OFFTIME0 BPVOL4 BPVOL3 BPVOL2 BPVOL1 BPVOL0
p46
default 00000000
14h BEEP Con-
trol & Tone
Config
REPEAT BEEP Reserved TREB_CF1 TREB_CF0 BASS_CF1 BASS_CF0 TC_EN
p47
default 00000000
15h Tone Control TREB3 TREB2 TREB1 TREB0 BASS3 BASS2 BASS1 BASS0
p48
default 10001000
16h Vol. Control
AOUTA AOUTA_
VOL7 AOUTA_
VOL6 AOUTA_
VOL5 OUTA_ VOL4 AOUTA_
VOL3 AOUTA_
VOL2 AOUTA_
VOL1 AOUTA_
VOL0
p49
default 00000000
17h Vol. Control
AOUTB AOUTB_
VOL7 AOUTB_
VOL6 AOUTB_
VOL5 AOUTB_
VOL4 AOUTB_
VOL3 AOUTB_
VOL2 AOUTB_
VOL1 AOUTB_
VOL0
p49
default 00000000
18h PCM Channel
Mixer PCMA1 PCMA0 PCMB1 PCMB0 Reserved Reserved Reserved Reserved
p49
default 00000000
19h Limiter
Threshold &
SZC Disable
MAX2 MAX1 MAX0 CUSH2 CUSH1 CUSH0 LIM_SRDIS LIM_ZCDIS
p50
default 00000000
1Ah Limiter Con-
fig & Release
Rate
LIMIT_EN LIMIT_ALL LIM_RRATE
5LIM_RRATE
4LIM_RRATE
3LIM_RRATE
2LIM_RRATE
1LIM_RRATE
0
p51
default 01111111
1Bh Limiter Attack
Rate Reserved Reserved LIM_ARATE5 LIM_ARATE4 LIM_ARATE3 LIM_ARATE2 LIM_ARATE1 LIM_ARATE0
p52
default 00000000
1Ch Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
AddrFunction76543210
38 DS723A1
CS43L21
default 00000000
1Dh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default 00111111
1Eh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default 00000000
1Fh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
default 00000000
20h Status Reserved SP_CLKER
RSPEB_OVFL SPEA_OVFL PCMA_OVFL PCMB_OVFL Reserved Reserved
p52
default 00000000
21h CHRG_
FREQ3 CHRG_
FREQ2 CHRG_
FREQ1 CHRG_
FREQ0 Reserved Reserved Reserved Reserved
p53
default 01010000
AddrFunction76543210
DS723A1 39
CS43L21
6. REGISTER DESCRIPTION
All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are
read only. See the following bit definition tables for bit assignment information. The default state of each bit after a
power-up sequence or reset is listed in each bit description.
All “Reserved” registers must maintain their default state.
6.1 Chip I.D. and Revision Register (Address 01h) (Read Only)
Chip I.D. (Chip_ID[4:0])
Default: 11011
Function:
I.D. code for the CS43L21. Permanently set to 11011.
Chip Revision (Rev_ID[2:0])
Default: 001
Function:
CS43L21 revision level. Revision B is coded as 001. Revision A is coded as 000.
6.2 Power Control 1 (Address 02h)
Notes: 1. To activate the powe r-down sequence for individu al channels (A or B,) both channels must first be pow-
ered down either by enabling the PDN bit or by enabling the power-down bits for both channels. En-
abling the power-down bit on an individual channel basis after the D/A has fully powered up will mute
the selected channel without achieving any power savings.
2. Reserved bits 1 - 4 should always be set “h igh” by th e user to minimize power consum ption during n or-
mal operation.
Recommended ch an nel po we r- do wn sequen ce: 1.) Enable the PDN bit, 2.) enable power-down for the se-
lect channels, 3.) disable the PDN bit.
Power Down DAC X (PDN_DACX)
Default: 0
0 - Disable
1 - Enable
Function:
DAC channel x will either enter a power-down or muted state when this bit is enabled. See Note 1 above.
76543210
Chip_ID4 Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID2 Rev_ID1 Rev_ID0
76543210
Reserved PDN_DACB PDN_DACA Reserved Reserved Reserved Reserved PDN
40 DS723A1
CS43L21
Power Down (PDN)
Default: 0
0 - Disable
1 - Enable
Function:
The entire D/A will enter a low-power state when this function is enabled. The contents of the control port
registers are retained in this mode.
6.3 Speed Control (Address 03h)
Auto-Detect Speed Mode (AUTO)
Default: 1
0 - Disable
1 - Enable
Function:
Enables the auto- detect circuitry for detecting the speed mode of th e D/A when opera ting as a slave. When
AUTO is enabled, the MCLK/LRCK ratio must be implemented according to Table 3 on page 29. The
SPEED[1:0] bits are ignored when this bit is enabled. Speed is determined by the MCLK/LRCK ratio.
Speed Mode (SPEED[1:0])
Default: 01
11 - Quarter-Speed Mode (QSM) - 4 to 12.5 kHz sample rates
10 - Half-Speed Mode (HSM) - 12.5 to 25 kHz sample rates
01 - Single-Speed Mode (SSM) - 4 to 50 kHz sample rates
00 - Double-Speed Mode (DSM) - 50 to 100 kHz sample rates
Function:
Sets the appropriate speed mode for the D/A in Master or Slave Mode. QSM is optimized for 8 kHz sample
rate and HSM is optimized for 16 kHz sample rate. These bits are ignored when the AUTO bit is enabled
(see Auto-Detect Speed Mode (AUTO) above).
Tri-State Serial Port Interface (3ST_SP)
Default: 0
0 - Disable
1 - Enable
Function:
When enabled and the device is configured as a master, the SCLK/LRCK signals are placed in a high-im-
pedance output state. If the serial port is configured as a slave, SCLK/LRCK are configured as inputs.
MCLK Divide By 2 (MCLKDIV2)
Default: 0
0 - Disabled
1 - Divide by 2
76543210
AUTO SPEED1 SPEED0 3-ST_SP Reserved Reserved Reserved MCLKDIV2
DS723A1 41
CS43L21
Function:
Divides the input MCLK by 2 prior to all internal circuitry. This bit is ignored when the AUTO bit is disabled
in Slave Mode.
6.4 Interface Control (Address 04h)
Master/Slave Mode (M/S)
Default: 0
0 - Slave
1 - Master
Function:
Selects either master or slave operation for the serial port.
DAC Digital Interface Format (DAC_DIF[2:0])
Default = 000
Function:
Selects the digital interface format used for the data in on SDIN. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are
detailed in the section “Digital Interface Formats” on page 30.
6.5 DAC Output Control (Address 08h)
Headphone Analog Gain (HP_GAIN[2:0])
Default: 011
76543210
Reserved M/S DAC_DIF2 DAC_DIF1 DAC_DIF0 Reserved Reserved Reserved
DAC_DIF[2:0] Description Figure
000 Left-Justifie d, up to 24 -b it da ta 15 on page 31
001 I²S, up to 24-bit data 14 on page 30
010 Right-Justified, 24-bit data 17 on page 3217 on page 32
011 Right-Justified, 20-bit data 17 on page 3217 on page 32
100 Right-Justified, 18-bit data 17 on page 3217 on page 32
101 Right-Justified, 16-bit data 17 on page 3217 on page 32
110 Reserved -
100 Reserved -
76543210
HP_GAIN2 HP_GAIN1 HP_GAIN0 DAC_
SNGVOL INV_PCMB INV_PCMA DACB_MUTE DACA_MUTE
HP_GAIN[2:0] Gain Setting
000 0.3959
001 0.4571
010 0.5111
011 0.6047
100 0.7099
101 0.8399
110 1.0000
111 1.1430
42 DS723A1
CS43L21
Function:
These bits select the gain multiplier for the headphon e/line outputs. See “ Line Output Voltage Ch ar acteris-
tics” on page 14 and “Headphone Output Power Characteristics” on page 15.
DAC Single Volume Control (DAC_SNGVOL)
Default: 0
Function:
The individual channel volume levels are independently controlled by their respective Volume Control reg-
isters when this function is disabled . When enabled, the volume on all channels is dete rmined by the AOU-
TA Volume Control register and the AOUTB Volume Control register is ignored.
PCMX Invert Signal Polarity (INV_PCMX)
Default: 0
0 - Disabled
1 - Enabled
Function:
When enabled, this bit will invert the signal polarity of the PCM x channel.
DACX Channel Mute (DACX_MUTE)
Default: 0
0 - Disabled
1 - Enabled
Function:
The output of channel x DAC will mute when enabled. The muting function is affected by the DACx Soft and
Zero Cross bits (DACx_SZC[1:0]).
6.6 DAC Control (Address 09h)
DAC Data Selection (DATA_SEL[1:0])
Default: 00
00 - PCM Serial Port to DAC
01 - Signal Processing Engine to DAC
10 - Reserved
11 - Reserved
Function:
Selects the digital signal source for the DAC. Note: Certain functions are only available when the “Signal
Processing Engine to DAC” option is selected using these bits.
76543210
DATA_SEL1 DATA_SEL0 FREEZE Reserved DEEMPH AMUTE DAC_SZC1 DAC_SZC0
DS723A1 43
CS43L21
Freeze Controls (FREEZE)
Default: 0
Function:
This function will freeze the previous settings of, and allow modifications to be made to all control port reg-
isters without the changes taking effect until the FREEZE is disabled. To have multiple changes in the con-
trol port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then
disable the FREEZE bit.
DAC De-Emphasis Control (DEEMPH)
Default: 0
0 - No De-Emphasis
1 - De-Emphasis Enabled
Function:
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control.
Enables the digital filter to apply the standard 15µs/50µs digital de-emphasis filter response for a sample
rate of 44.1 kHz.
Analog Output Auto MUTE (AMUTE)
Default: 0
0 - Auto Mute Disabled
1 - Auto Mute Enabled
Function:
Enables (or disables) Automatic Mute of the analog outputs after 8192 “0” samples on each digital input
channel.
DAC Soft Ramp and Zero Cross Control (DAC_SZC[1:0])
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control
Immediate Change
When Immediate Change is selected all volume-level changes will take effect immediately in one step.
Zero Cross
This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a
timeout period between 1024 and 2048 sample periods (21.3 ms to 42.7 ms at 48 kHz sample rate) if the
signal does not encounter a zero crossing. The zero cross function is independently monitored and imple-
mented for each channel. Note: The LIM_SRDIS bit is ignored.
44 DS723A1
CS43L21
Soft Ramp
Soft Ramp allows level changes, either by gain change s, attenuation changes or muting, to be implemented
by incremen tally ramping, in 1/8 dB steps, from the c urrent level to the new level at a rate of 0.5 dB per 4
left/right clock periods.
Soft Ramp on Zero Crossing
This setting dictates that signal-level changes, either by gain changes, attenuation changes or muting, will
occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur
after a timeout period between 5 12 and 1024 sample period s (10.7 ms to 21.3 ms at 48 kHz sample rate ) if
the signal does n ot enco unte r a zero cr ossin g. The zero cro ss function is indep en dently mo nitor ed and im-
plemented for each channel. Note: The LIM_SRDIS bit is ignored.
6.7 PCMX Mixer Volume Control:
PCMA (Address 10h) & PCMB (Address 11h)
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
PCMX Mixer Channel Mute (MUTE_PCMMIXX)
Default = 1
0 - Disabled
1 - Enabled
Function:
The PCM channel X input to the output mixer will mute when enabled. The muting function is affected by
the DACX Soft and Zero Cross bits (DACX_SZC[1:0]).
PCMX Mixer Volume Control (PCMMIXX_VOL[6:0])
Default: 000 0000
Function:
The level of the PCMX input to the output mixe r can be adjusted in 0.5 dB increments as dictated by the
DACX Soft and Zero Cross bits (DACX_SZC[1:0]) from +12 to -51.5 dB. Levels are decoded as described
in the table above.
76543210
MUTE_
PCMMIXx PCMMIXx_
VOL6 PCMMIXx_
VOL5 PCMMIXx_
VOL4 PCMMIXx_
VOL3 PCMMIXx_
VOL2 PCMMIXx_
VOL1 PCMMIXx_
VOL0
Binary Code Volume Setting
001 1000 +12.0 dB
··· ···
000 0000 0 dB
111 1111 -0.5 dB
111 1110 -1.0 dB
··· ···
001 1001 -51.5 dB
DS723A1 45
CS43L21
6.8 Beep Frequency & Timing Configuration (Address 12h)
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Beep Frequency (FREQ[3:0])
Default: 0000
Function:
The frequency of the beep signal can be adjusted from 260.87 Hz to 2181.82 Hz. Beep frequency will scale
directly with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. Refer to Figure 10 on
page 26 for single, multiple and continuous beep configurations using the REPEAT and BEEP bits.
Beep On Time Duration (ONTIME[3:0])
Default: 0000
Function:
The on-duration of the beep signal can be adjusted from approximately 86 ms to 5.2 s. The on-duration will
scale inversely with sample rate, Fs, but is fixed at the nomina l Fs within each speed mod e. Refer to Figure
10 on page 26 for single-, multiple- and continuous-beep configurations using the REPEAT and BEEP bits.
76543210
FREQ3 FREQ2 FREQ1 FREQ0 ONTIME3 ONTIME2 ONTIME1 ONTIME0
FREQ[3:0] Frequency
Fs = 12, 24, 48 or 96
kHz
Pitch
0000 260.87 Hz C4
0001 521.74 Hz C5
0010 585.37 Hz D5
0011 666.67 Hz E5
0100 705.88 Hz F5
0101 774.19 Hz G5
0110 888.89 Hz A5
0111 1000.00 Hz B5
1000 1043.48 Hz C6
1001 1200.00 Hz D6
1010 1333.33 Hz E6
1011 1411.76 Hz F6
1100 1600.00 Hz G6
1101 1714.29 Hz A6
1110 2000.00 Hz B6
1111 2181.82 Hz C7
TIME[3:0] On Time
Fs = 12, 24, 48 or 96 kHz
0000 86 ms
··· ···
1111 5.2 s
46 DS723A1
CS43L21
6.9 Beep Off Time & Volume (Address 13h)
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Beep Off Time (OFFTIME[2:0])
Default: 000
Function:
The off-duration of the beep signal can be adjusted from approximately 75 ms to 680 ms. The off-duration
will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. Refer to
Figure 10 on page 26 for single-, multiple- and continuous-beep configurations using the REPEAT and
BEEP bits.
Beep Volume (BPVOL[4:0])
Default: 00000
Function:
The level of the beep into the output mixer can be adjusted in 2.0 dB increments from +12 dB to -50 dB.
Refer to Figure 10 on page 26 for single -, multiple- and continuous-beep co nfigurations using the REPEAT
and BEEP bits. Levels are decoded as described in the table above.
76543210
OFFTIME2 OFFTIME1 OFFTIME0 BPVOL4 BPVOL3 BPVOL2 BPVOL1 BPVOL0
OFFTIME[2:0] Off Time
Fs = 12, 24, 48 or
96 kHz
000 1.23 s
001 2.58 s
010 3.90 s
011 5.20 s
100 6.60 s
101 8.05 s
110 9.35 s
111 10.80 s
Binary Code Volume Setting
00110 +12.0 dB
··· ···
00000 0 dB
11111 -2 dB
11110 -4 dB
··· ···
00111 -50 dB
DS723A1 47
CS43L21
6.10 Beep Configuration & Tone Configuration (Address 14h)
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Repeat Beep (REPEAT)
Default: 0
0 - Disabled
1 - Enabled
Function:
This bit is used in con junction with the BEEP bit to mix a continu ous or periodic beep with the analog output.
Refer to Figure 10 on page 26 for a description of each configuration option.
Beep (BEEP)
Default: 0
0 - Disabled
1 - Enabled
Function:
This bit is used in conjunction with the REPEAT bit to mix a continuous or periodic beep with the analog
output. Note: Re-engaging the beep before it has completed its initial cycle will cause the beep signal to
remain ON for the ma ximum ONTIME duration. Refer to Figu re 10 on page 26 for a descr iption of each con-
figuration option.
Treble Corner Frequency (TREB_CF[1:0])
Default: 00
00 - 5 kHz
01 - 7 kHz
10 - 10 kHz
11 - 15 kHz
Function:
The treble corner frequency is user selectable as shown above.
Bass Corner Frequency (BASS_CF[1:0])
Default: 00
00 - 50 Hz
01 - 100 Hz
10 - 200 Hz
11 - 250 Hz
Function:
The bass corner fre qu en cy is user-selectable as shown above.
76543210
REPEAT BEEP Reserved TREB_CF1 TREB_CF0 BASS_CF1 BASS_CF0 TC_EN
48 DS723A1
CS43L21
Tone Control Enable (TC_EN)
Default = 0
0 - Disabled
1 - Enabled
Function:
The Bass and Treble tone control features are active when this bit is enabled.
6.11 Tone Control (Address 15h)
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Treble Gain Level (TREB[3:0])
Default: 1000 dB (No Treble Gain)
Function:
The level of the sh elving treble gain filte r is set by Treble Gain Level. The level can be adjusted in 1.5 dB
increments from +12.0 to -10.5 dB.
Bass Gain Level (BASS[3:0])
Default: 1000 dB (No Bass Gain)
Function:
The level of the shelving bass gain filter is set by Bass Gain Level. The level can be adjusted in 1.5 dB in-
crements from +10.5 to -10.5 dB.
76543210
TREB3 TREB2 TREB1 TREB0 BASS3 BASS2 BASS1 BASS0
Binary Code Gain Setting
0000 +12.0 dB
··· ···
0111 +1.5 dB
1000 0 dB
1001 -1.5 dB
··· ···
1111 -10.5 dB
Binary Code Gain Setting
0000 +12.0 dB
··· ···
0111 +1.5 dB
1000 0 dB
1001 -1.5 dB
··· ···
1111 -10.5 dB
DS723A1 49
CS43L21
6.12 AOUTx Volume Control:
AOUTA (Address 16h) & AOUTB (Address 17h)
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
AOUTX Volume Contro l (AOU TX _VO L[7 :0 ])
Default = 00h
Function:
The analog output levels can be adjusted in 0 .5 dB increments from +12 to -102 dB as dictated by the DAC
Soft and Zero Cross bits (DACX_SZC[1:0]). Levels are decoded in unsigned binary as described in the table
above.
Note: When the limiter is enabled, the AOUT Volume is automatically controlled and should not be ad-
justed manually. Alternative volume control may be achieved using the PCMMIXx_VOL[6:0] bits.
6.13 PCM Channel Mixer (Address 18h)
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Channel Mixer (PCMx[1:0])
Default: 00
Function:
Implements mono mixes of the left and right channels as well as a left/right channel swap.
76543210
AOUTx_VOL7 AOUTx_VOL6 AOUTx_VOL5 AOUTx_VOL4 AOUTx_VOL3 AOUTx_VOL2 AOUTx_VOL1 AOUTx_VOL0
Binary Code Volume Setting
0001 1000 +12.0 dB
··· ···
0000 0000 0 dB
1111 1111 -0.5 dB
1111 1110 -1.0 dB
··· ···
0011 0100 -102 dB
··· ···
0001 1001 -102 dB
76543210
PCMA1 PCMA0 PCMB1 PCMB0 Reserved Reserved Reserved Reserved
PCMA[1:0] AOUTA PCMB[1:0] AOUTB
00 L 00 R
01 01
10 10
11 R 11 L
LR+
2
------------ LR+
2
------------
50 DS723A1
CS43L21
6.14 Limiter Threshold SZC Disable (Address 19h)
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Maximum Threshold (MAX[2:0])
Default: 000
Function:
Sets the maximum level, below full scale, at which to limit and attenuate the output signa l at the attack rate.
Bass, Treble and digital gain settings that boost the signal beyond the maximum threshold may trigger an
attack.
Cushion Threshold (CUSH[2:0] )
Default: 000
Function:
Sets a cushion level below full scale. This setting is usually set slightly below the maximum (MAX[2:0])
threshold. The Limiter uses this cushion as a hysteresis point for the input signal as it maintains the signal
below the maximum as well as below the cushion setting. This provides a more natural sound as the limiter
attacks and releases.
76543210
MAX2 MAX1 MAX0 CUSH2 CUSH1 CUSH0 LIM_SRDIS LIM_ZCDIS
MAX[2:0] Threshold
Setting
(dB)
000 0
001 -3
010 -6
011 -9
101 -12
101 -18
110 -24
111 -30
CUSH[2:0] Threshold
Setting
(dB)
000 0
001 -3
010 -6
011 -9
101 -12
101 -18
110 -24
111 -30
DS723A1 51
CS43L21
Limiter Soft Ramp Disable (LIM_SRDIS)
Default: 0
0 - Off
1 - On
Function:
Overrides the DAC_SZC setting. When this bit is set, the Limiter attack and release rate will not be dictated
by the soft ramp setting. Note: This bit is ignored when the zero-cross function is enabled (i.e. when
DAC_SZC[1:0] = ‘01’b or ‘11’b.)
Limiter Zero Cross Disable (LIM_ZCDIS)
Default: 0
0 - Off
1 - On
Function:
Overrides the DAC_SZC setting. When this bit is set, the Limiter attack and release rate will not be dictated
by the zero-cross setting.
6.15 Limiter Release Rate Register (Address 1Ah)
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Peak Detect and Limiter Enable (LIMIT_EN)
Default: 0
0 - Disabled
1 - Enabled
Function:
Limits the maximum signal amplitude to prevent clipping when this function is enabled. Peak Signal Limiting
is performe d by digital attenu ation. Note: When the limiter is enabled, the AOUT Volume is automatically
controlled and should not be adjusted manually. Alternative volume control may be realized using the
PCMMIXx_VOL[6:0] bits.
Peak Signal Limit All Channels (LIMIT_ALL)
Default: 1
0 - Individual Channel
1 - Both channel A & B
Function:
When set to 0, the peak signal limiter will limit the ma ximum signal amplitude to prevent clipping on the spe-
cific channel indicating clipping. The other channels will not be affected.
When set to 1, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on both
channels in response to any single channel indicating clipping.
76543210
LIMIT_EN LIMIT_ALL RRATE5 RRATE4 RRATE3 RRATE2 RRATE1 RRATE0
52 DS723A1
CS43L21
Limiter RELEASE Rate (RRATE[5:0])
Default: 111111
Function:
Sets the rate at which the limiter releases the digital attenuation from levels below the minimum setting in
the limiter threshold register, and returns the analog output level to the AOUTx_VOL[7:0] setting.
The limiter release rate is user selectable but is also a function of the sampling frequency, Fs, and the
DAC_SZC setting unless the disable bit is enabled.
6.16 Limiter Attack Rate Register (Address 1Bh)
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Limiter Attack Rate (ARATE[5:0])
Default: 000000
Function:
Sets the rate at which the limiter attenu ates the analog output from levels above the maximum setting in the
limiter threshold register.
The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and the
DAC_SZC setting unless the disable bit is enabled.
6.17 Status (Address 20h) (Read Only)
For all bits in this register, a “1” means the associated error condition has occu rred at leas t once since th e
register was last read. A ”0” means the associated error condition has NOT occurr ed sin ce the la st reading
of the register. Reading the register resets all bits to 0.
Serial Port Clock Error (SP_CLK Error)
Default: 0
Function:
Indicates an invalid MCLK to LRCK ratio. See “Serial Port Clocking” section on page 28“Serial Port Clock-
ing” on page 28 for valid clock ratios.
Note: On initial power up and application of clocks, this bit will be high as the serial port re-synchronizes.
Binary Code Release Time
000000 Fastest Release
··· ···
111111 Slowest Release
76543210
Reserved Reserved ARATE5 ARATE4 ARATE3 ARATE2 ARATE1 ARATE0
Binary Code Attack Time
000000 Fastest Attack
··· ···
111111 Slowest Attack
76543210
Reserved SP_CLKERR SPEA_OVFL SPEB_OVFL PCMA_OVFL PCMB_OVFL Reserved Reserved
DS723A1 53
CS43L21
Signal Processing Engine Overflow (SPEX_OVFL)
Default: 0
Function:
Indicates a digital overflow condition within the data path after the signal processing engine.
PCMX Overflow (PCMX_OVFL)
Default: 0
Function:
Indicates a digital overflow conditio n within the data path of the PCM mix.
6.18 Charge Pump Frequency (Address 21h)
Charge Pump Frequency (CHRG_FREQ[3:0])
Default: 0101
Function:
Alters the clocking frequency of the cha rge pump in 1/(N+2) fractions of the DAC oversampling rate, 128Fs,
should the switching frequency interfere with other system frequencies such as those in the AM radio band.
Note: Distortion performance may be affected.
76543210
CHRG_FREQ
3CHRG_FREQ
2CHRG_FREQ
1CHRG_FREQ
0Reserved Reserved Reserved Reserved
N CHRG_FREQ[3:0] Frequency
0 0000
... ...
15 1111
64xFs
N2+
-----------------
54 DS723A1
CS43L21
7. ANALOG PERFORMANCE PLOTS
7.1 Headphone THD+N versus Output Power Plots
Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave; measurement band-
width is 10 Hz to 20 kHz; Fs = 48 kHz. Plots were taken from the CDB43L21 using an Audio Precision an-
alyzer.
G = 0.6047
G = 0.7099
G = 0.8399
G = 1.0000
G = 1.1430
Legend
-100
-10
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
d
B
r
A
080m10m 20m 30m 40m 50m 60m 70m
W
Figure 21. THD+N vs. Output Power pe r Chan nel at 1.8 V (16 Ω load)
VA_HP = VA = 1.8 V
NOTE: Graph shows the out-
put power per channel (i.e.
Output Power = 23 mW into
single 16 Ω and 46 mW into
stereo 16 Ω with THD+N = -
75 dB).
G = 0.6047
G = 0.7099
G = 0.8399
G = 1.0000
G = 1.1430
Legend
-100
-10
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
d
B
r
A
080m10m 20m 30m 40m 50m 60m 70m
W
Figure 22. THD+N vs. Output Power pe r Chan nel at 2.5 V (16 Ω load)
VA_HP = VA = 2.5 V
NOTE: Graph shows the out-
put power per channel (i.e.
Output Power = 44 mW into
single 16 Ω and 88 mW into
stereo 16 Ω with THD+N = -
75 dB).
DS723A1 55
CS43L21
G = 0.6047
G = 0.7099
G = 0.8399
G = 1.0000
G = 1.1430
Legend
-100
-20
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
d
B
r
A
060m6m 12m 18m 24m 30m 36m 42m 48m 54m
W
Figure 23. THD+N vs . Output Power per Channel at 1.8 V (32 Ω load)
VA_HP = VA = 1.8
NOTE: Graph shows the out-
put power per channel (i.e.
Output Power = 22 mW into
single 32 Ω and 44 mW into
stereo 32 Ω with THD+N = -
75 dB).
G = 0.6047
G = 0.7099
G = 0.8399
G = 1.0000
G = 1.1430
Legend
-100
-20
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
d
B
r
A
060m5m 10m 15m 20m 25m 30m 35m 40m 45m 50m 55m
W
Figure 24. THD+N vs. Outpu t Power per Channel at 2.5 V (32 Ω load)
VA_HP = VA = 2.5 V
NOTE: Graph shows the out-
put power per channel (i.e.
Output Power = 42 mW into
single 32 Ω and 84 mW into
stereo 32 Ω with THD+N = -
75 dB).
56 DS723A1
CS43L21
7.2 Headphone Amplifier Efficiency
The architecture of the headphone amplifier is that of typical class AB amplifiers. Test conditions (unless
otherwise specified): Input test signal is a 997 Hz sine wave; Power Consumption Mode 6 - Stereo Playback
w/16 Ω load. HP_GAIN = 1.1430. Best efficiency is realized when the amplifier outputs maximu m p ower.
Figure 25. Power Dissipation vs. Output Power into Stereo 16 Ω
VA_HP = VA = 1.8 V
Figure 26. Power Dissipation vs. Output Power into Stereo 16 Ω (Log Detail)
VA_HP = VA = 1.8 V
DS723A1 57
CS43L21
8. EXAMPLE SYSTEM CLOCK FREQUENCIES
8.1 Auto Detect Enabled
*The”MCLKDIV2” pin 4 must be set HI.
Sample Rate
LRCK (kHz) MCLK (MHz)
1024x 1536x 2048x* 3072x*
8 8.1920 12.2880 16.3840 24.5760
11.025 11.2896 16.9344 22.5792 33.8688
12 12.2880 18.4320 24.5760 36.8640
Sample Rate
LRCK (kHz) MCLK (MHz)
512x 768x 1024x* 1536x*
16 8.1920 12.2880 16.3840 24.5760
22.05 11.2896 16.9344 22.5792 33.8688
24 12.2880 18.4320 24.5760 36.8640
Sample Rate
LRCK (kHz) MCLK (MHz)
256x 384x 512x* 768x*
32 8.1920 12.2880 16.3840 24.5760
44.1 11.2896 16.9344 22.5792 33.8688
48 12.2880 18.4320 24.5760 36.8640
Sample Rate
LRCK (kHz) MCLK (MHz)
128x 192x 256x* 384x*
64 8.1920 12.2880 16.3840 24.5760
88.2 11.2896 16.9344 22.5792 33.8688
96 12.2880 18.4320 24.5760 36.8640
58 DS723A1
CS43L21
8.2 Auto Detect Disabled
Sample Rate
LRCK (kHz) MCLK (MHz)
512x 768x 1024x 1536x 2048x 3072x
8 - 6.1440 8.1920 12.2880 16.3840 24.5760
11.025 - 8.4672 11.2896 16.9344 22.5792 33.8688
12 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640
Sample Rate
LRCK (kHz) MCLK (MHz)
256x 384x 512x 768x 1024x 1536x
16 - 6.1440 8.1920 12.2880 16.3840 24.5760
22.05 - 8.4672 11.2896 16.9344 22.5792 33.8688
24 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640
Sample Rate
LRCK (kHz) MCLK (MHz)
256x 384x 512x 768x
32 8.1920 12.2880 16.3840 24.5760
44.1 11.2896 16.9344 22.5792 33.8688
48 12.2880 18.4320 24.5760 36.8640
Sample Rate
LRCK (kHz) MCLK (MHz)
128x 192x 256x 384x
64 8.1920 12.2880 16.3840 24.5760
88.2 11.2896 16.9344 22.5792 33.8688
96 12.2880 18.4320 24.5760 36.8640
DS723A1 59
CS43L21
9. PCB LAYOUT CONSIDERATIONS
9.1 Power Supply, Grounding
As with any high-reso lution co nverte r, the CS43L21 re quires ca refu l attention to power supply and gr ound-
ing arrangements if its potential performa nce is to be realized. Figure 1 on page 9 shows the recommended
power arrangements, with VA and VA_HP connected to clean su pplies. VD, which powers the digital circuit-
ry, may be run from the system logic supply. Al ternatively, VD may be powered from the analog supply via
a ferrite bead. In this case, no additional devices should be powered from VD.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS43L21 as pos-
sible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same
side of the board as the CS43L21 to minimize inductance effects. All signals, especially clocks, should be
kept away from the FILT+ a nd VQ pins in o rder to avoid unwanted coupling into the modu lators. The FILT+
and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path
from FILT+ and AGND. The CS43L21 evaluation bo ard demonstrates the optimum layout and power supply
arrangements.
9.2 QFN Thermal Pad
The CS43L21 is available in a compact QFN p ackage . The unde r side of the QFN pa ckage reveals a la rge
metal pad that serves as a thermal relief to provide for maximum h eat dissip ation. This pad must mate with
an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of
vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers.
In split ground systems, it is recommended that this thermal pad be connected to AGND for best perfor-
mance. The CS43L21 evaluation board demonstrates the optimum thermal pad and via configuration.
DS723A1 61
CS43L21
11.PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral compon ents over th e specified
bandwidth. Dynamic Range is a signal-to-noise ratio mea surement over the specified band width made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This
technique ensu res tha t the distortion co mpone nts are below the noise level and do n ot affect the m easure-
ment. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,
and the Electronic Industries Association of Japan, EIAJ CP-307 . Exp re ssed in de cib els .
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral compon ents over th e specified
band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at
1 k Hz. Units in decibels.
Interchannel Isolation
A measure of crosstalk betwe en the left and right cha nnel pairs. Measu red for each ch annel at the conver t-
er's output with no signal to the inpu t under test and a full- scale signal applied to the oth er channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channel pairs. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a fu ll-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
62 DS723A1
CS43L21
12.PACKAGE DIMENSIONS
1. Dimensioning and tolerance per ASME Y 14.5M-1995.
2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm
from the terminal tip.
THERMAL CHARACTERISTICS
INCHES MILLIMETERS NOTE
DIM MIN NOM MAX MIN NOM MAX
A----0.0394----1.001
A1 0.0000 -- 0.0020 0.00 -- 0.05 1
b 0.0071 0.0091 0.0110 0.18 0.23 0.28 1,2
D 0.1969 BSC 5.00 BSC 1
D2 0.1280 0.1299 0.1319 3.25 3.30 3.35 1
E 0.1969 BSC 5.00 BSC 1
E2 0.1280 0.1299 0.1319 3.25 3.30 3.35 1
e 0.0197 BSC 0.50 BSC 1
L 0.0118 0.0157 0.0197 0.30 0.40 0.50 1
JEDEC #: MO-220
Controlling Dimension is Millimeters.
Parameter Symbol Min Typ Max Units
Junction to Ambient Thermal Impedance 2 Layer Board
4 Layer Board θJA -
-52
38 -
-°C/Watt
Side View
A1
Bottom View
Top View
A
Pin #1 Corner
D
E
D2
L
be Pin #1 Corner
E2
32L QFN (5 X 5 mm BODY) PACKAGE DRAWING
DS723A1 63
CS43L21
13.ORDERING INFORMATION
14.REFERENCES
1. Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices,
Version 6.0, February 1998.
2. Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters, by Steven
Harris. Presented at the 93rd Conve ntion of the Audio Engineering Society, October 1992.
3. Cirrus Logic, A Fifth-Order Delta -Sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori, K. Ha-
mashita and E.J. Swanson. Paper p resented at the 93rd Convention of the Audio Engineer ing Society, Oc-
tober 1992.
4. Philips Semiconductor, The I²C-Bus Specification: Version 2.1, Ja nu ar y 20 00 .
http://www.semiconductors.philips.com
15.REVISION HISTORY
Product Description Package Pb-Free Grade Temp Range Container Order #
CS43L21 Low-Power Stereo D/A
with HP Amp for Portable
Apps 32L-QFN Yes Commercial -10 to +70° C Rail CS43L21-CNZ
Tape & Reel CS43L21-CNZR
Automotive -40 to +85° C Rail CS43L21-DNZ
Tape & Reel CS43L21-DNZR
CDB43L21 CS43L21 Evaluation
Board - No - - - CDB43L21
Revision Changes
A1 Initial Release
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
"Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and i ts subsi diaries ("Cirru s")
believe that the inform ation co ntained in this docu ment is accura te and reliable. Ho wever, the informa tion is subje ct to chan ge without notice an d is provided "AS IS"
without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that
information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment,
including those pertaining to warranty, i ndemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this in for mat i on , in cl udi n g use
of this informat ion as t he basi s for man ufact ure or sale of an y items , or f or inf ringement of pat ents or othe r right s of t hird parties. This document is the property of
Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or
other i nte l le c tu al pr op er ty r i gh ts . Ci rr us o wns t h e copy rights a ss oci at e d wi t h th e i nformati on con t ai ned he re i n and gi v es c ons e nt for copies to be made of the infor-
mation only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such
as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYST EMS, MILITA RY APPLICATI ONS, PRODUCTS SURGIC ALLY IMPLANTED I NTO THE BODY, AUTOMOTIVE SAF ETY OR SECURITY DE-
VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDER-
STOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED,
INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT
THAT IS USED IN SU CH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CU STOMER USES OR PE RMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL
APPLICATIONS, CUSTOMER AGREE S, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DI RECT ORS, EMPLOYE ES, DI STRI BUTO RS AND
OTHER AGENTS FROM ANY AND ALL LIABI LITY, INCLUDING ATTORNEYS’ FEES AN D COSTS, THAT MAY RE SULT FROM OR ARISE IN CONNECTI ON
WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be tradem ark s
or service marks of their respective owners.
I²C is a registered trademark of Philips Semiconductor.
SPI is a trademar k of M oto rola, Inc.
