PARADIGM: PDM44528 Features (Interfaces directly with the i486 , Pentium processors (80, 66, 60, 50, 40 MHz) 1 High Speed Access Times - Clock to data valid times: 8, 9, 10, 12, 14 ns - Cycle Times: 12.5, 15, 20, 25 ns High Density 32K x 18 Architecture Choice of 5V or 3V +10% Output Vee for output level compatability High Output Drive: 30 pF at Rated Taa Asynchronous Output Enable Self Timed Write Cycle Byte Writeable via Dual Write Strobes Internal interleaved burst read/write address counter Internal registers for Address, Data, Controls Packages: 52-pin PLCC OOOO0O OO OO 32K x 18 Fast CMOS Synchronous Static SRAM with Interleaved Burst Counter Description The PDM44528 is a 589,824 bit synchronous random access memory organized as 32,768 words by 18 bits. It has burst mode capability and interface controls designed to provide high-performance in secondary cache designs for i486 and Pentium microproces- sors. Addresses, write data and all control signals except output enable are controlled through positive edge triggered registers. Write cycles are self timed and are also initiated by the rising edge of the clock. Controls are provided to allow burst reads and writes of up to four words in length. A two-bit burst address counter controls the two least significant bits of the address during burst reads and writes. The interleaved burst address counter uses the 2-bit counting scheme required by the i486 and Pentium microprocessors. Individual write strobes provide byte write for the upper and lower 9-bit bytes of data. An asynchronous output enable simplifies interface to high speed buses. Separate output Vcc pins provide user controlled output levels of 5V or 3.3V, for 3.3V TTL compatibility. Functional Block Diagram Address Reg Burst Counter Control T i486, Pentium are trademarks of inte! Corp. 32Kx18 SRAM Array DQO-DQ8 +* DQ9-DQ17 Mm 6941090 00006584 340 a 6-11PARADIGM PDM44528 Pin Assignment Ola. 2i| aia << <x ews 1 Das 1 DQ7 DQG VvCCcaQ ovssaQ DAS 52 Pin PLCC 1 DOQ4 331 DQ3 DQe2 VSSQ VCCQ 1DaQ1 1 Dao Pinout Name YO | Description Name VO | Description A | Address Inputs A14-A2 Tw { Low Byte Write Enable, DQ0-DQ8 At, AO I Address Inputs A1 & AO UW I Upper Byte Write Enable, DQ8-DQ17 DQO-DQ17 VO | Read/Write Data G | Output Enable K | Clock VCC | Array Power (+5V) ADV I Burst Counter Advance vecQ | Output Power for DQs (+3.3V or +5V) ADSC I Controller Address Status vss | Array Ground ADSP I Processor Address Status VSSQ | Output Ground for DQs E I Chip Enable Asynchronous Truth Table Burst Sequence Table Operation G VO Status Sequence A14-A2 Al AO Read L Data Out Start Address AAAA B Cc Read H High-Z 1st Burst Address AAAA B c Write x High-Z: Write Data In 2nd Burst Address AAAA B c Deselected x High-Z 3rd Burst Address AMAA B c NOTE: 1. X means Dont Care. 2. For a write operation following a read operation, G must be high before the input data required setup time and held high through the input data hold time. 6-12 @ 6941090 0000699 257PARADIGM PDM44528 Synchronous Truth Table (See Notes 1 through 4) E ADSP | ADSC ADV | UWoerlW K Address Operation H x L X x T N/A Deselected L L X xX xX fT External Read Cycle, Begin Burst L H L X L T Extemal Write Cycle, Begin Burst L H L Xx H tT Extemal Read Cycle, Begin Burst x H H L L T Next Write Cycle, Continue Burst x H H L H T Next Read Cycle, Continue Burst xX H H H L tT Current Write Cycle, Suspend Burst xX H H H H tT Current Read Cycle, Suspend Burst 4 x H L L tT Next Write Cycle, Continue Burst X x H L H t Next Read Cycle, Continue Burst x x H H L t Current Write Cycle, Suspend Burst x Xx H H H Tt Current Read Cycle, Suspend Burst NOTE: X means Don't Care. All inputs except G must meet setup and hold times relative low-to-high transition of clock, K. Wait states are inserted by suspending burst. ADSP is gated by E. Both ADSP and E must be valid for ADSP to load the address register and force a read. BONS Burst Mode Operation This is a synchronous part. All activities are initiated by the positive, low-to-high edge of the clock (K). This part can perform burst reads and writes with burst lengths of up to 4 words. The 4 word burst is created by using a burst counter to drive the two least significant bits of the internal RAM address. The burst counter is loaded at the start of the burst and is incremented for each word of the burst. The burst counter uses a modified binary sequence compatible with the cache line burst reload sequence of i486 microprocessors. This sequence is given in the Burst Sequence Table. Burst transfers are initiated by the ADSC or ADSP signals. When the ADSP and E signals are sampled low, a read cycle is started (independent of W and ADSC), and prior burst activity is terminated. ADSP is gated by E, so both must be active for ADSP to load the address register and to initiate a read cycle. The address and the chip enable input (E) are sampled by the same edge that samples ADSP. Read data is valid at the output after the specified delay from the clock edge. When ADSC is sampled low and ADSP is sampled high, a read or write cycle is started depending on the state of OW or LW. If UW and LW are both sampled high, a read cycle is started, as described above. If UW or LW is sampled low, a write cycle is begun. The address, write data, and the chip enable input (E) are sampled by the same edge that sam- ples ADSC and UW or LW. The ADV line is held high for this clock edge to maintain the correct address for the internal write operation which will follow this second clock edge. After the first cycle of the write burst, The state of UW and LW determines whether the next cycle is a read or write cycle, and ADV controls the advance of the address counter. The address counter is advanced by the ADV signal. This increments the address to the next available RAM address. You write the next word in the burst by taking ADV low and presenting the write data at the positive edge of the clock. If ADV is sampled low, the burst counter advances and the write data -- which is sampled by the same clock -- is written into the internal RAM during the time following the clock edge. MB 6941090 oo00700 429 a 613PARADIGM Absolute Maximum Ratings Symbol Rating Com. Unit VIERM Terminal Voltage with Respect to GND -0.5 to +7.0 Vv Ta Operating Temperature Oto +70 C Teas Temperature Under Bias 55 to +125 C Tstg Storage Temperature 55 to +125 C lout DC Output Current 50 mA NOTE: 1. Recommended DC Operating Conditions PDM44528 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect reliability. Symbol Description Min. Typ. Max. Unit Vec Supply Voltage 4.75 5.0 5.25 Vv Veco 5V 45 5.0 5.5 Vv 3.3V 3.0 3.3 3.6 Vv GND Supply Voltage 0 0 0 Vv Industrial Ambient Temperature 40 25 85 C Commercial Ambient Temperature 0 25 70 C 6-14 6941090 oo00701 7645 aPARADIGM PDM44528 DC Electrical Characteristics (V., = 5.0V 5%, All Temperature Ranges) Symbol Description Test Conditions Min. Max. Unit Nl Input Leakage Current Vec = MAX., Vin = GND to Voc _ 1 pA IILol Output Leakage Current Voc= MAX., Vout = GND to Voc _ 1 pA Vor Output Low Voltage Vee = Min, lop = 8 MA 0 0.4 Vv Vou Output High Voltage Veco = Min., loy = ~4 MA 2.4 Veca Vv Vin Input HIGH Voltage 2.2 6 Vv | Vip Input LOW Voltage (1) 0.5 0.8 Vv | | NOTE: 1. Undershoots to -1.5 for 10 ns are allowed once per cycle. | | Power Supply Characteristics Symbol | Description Test Conditions Sns | -9ns | -10ns | -12ns | -14ns| Unit lect Active Supply Current: Voc = Max., Com'l | 380 360 360 340 320 | mA Outputs Open Inputs @ 0.0V or 3.0V F= 1/Teyc on Relk & Welk Isp Standby Current: Voc = Max., Com | 130 120 120 110 100 mA Outputs Open Inputs @ 0.0V or 3.0V . F=WTeye, E= Vin Capacitance (T, = +25C, f=1.0 MHz) Symbol Parameter Conditions Max. Unit Cin Input Capacitance Vin = OV 6 pF Cout Output Leakage Current Vout = OV 8 pF NOTES: 1. Characterized values, not currently tested. 2. With output deselected. MB 6941090 ooo0702 &TL a 6-15PARADIGM PDM44528 D.U.T. AC Test Conditions input Pulse Levels GND to 3.0V Input rise and fall times 3ns Input timing reference levels 1.5V Output reference levels 1.5V Output Load See Figures 1 and 2 +5 D.U.T. 30 p 5 pF , (Includes Jig & (Includes Jig & scope capacitance) scope capacitance) Figure 1a. Output Load Figure 1b. Output Disable Timing Load AC Electrical Characteristics (V,_ = 5V + 5%, All Temperature Ranges) Parameter Symbol 8 39 -10 -12 14 Type Units Notes Clock Cycle time teyc 13 15 15 20 25 Min. ns Clock to Data Valid (Std Load) tep 8 9 10 12 14 Max. ns 5 Clock to Data Valid (0 pF Load) tepo 7 8 9 1 13 Min. ns Output Enable toe 5 5 6 7 Max. ns Clock to Data Low-Z tict 3 3 3 3 3 Min. ns Clock to Data Hold Time lace 3 3 3 3 3 Min. ns OE to Output Low 2) torz 0 0 0 0 ) Min. ns 1 OE to Output High-2Z") tonz 2 2 2 2 2 Min ns 1,6 5 5 5 6 7 Max. ns 1,6 Clock to Data High-Z tez 6 6 6 7 8 Max. ns 1,6 Clock High/Low tw 4 4 5 6 7 Min. ns Setup Time ts 2.5 25 2.5 3 3 Min. ns 7 Hold Time ty 0.5 0.5 0.5 0.5 0.5 Min. ns 7 NOTES: 1. Values characterized and guaranteed by design, not currently tested. 2. Aread cycle is defined by UW and LW high or ADSP low for the setup and hold times. A write cycle is defined by LW or UW low and ADSP high for the set up and hold times. 3. All read and write cycle timings are referenced from K or G. 4. Gis a dont care when UW or LW is sampled low. 5. Maximum access times are guaranteed for all possible i486 external bus cycles. 6. Transition is measured +500 mV from steady-state voltage with load of Figure 1B. This parameter is sampled rather than 100% tested. At any given voltage and temperature, toyz max is less than tg; z min for a given device and from device to device. 7. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of K whenever ADSP or ADSC is low, and the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when ADSP or ADSC is low) to remain enabled. 6-16 M@@ 6941090 0000703 535PARADIGM ADSP Read Timing Diagram K \Y ONY a _ C my tw tw CYC =x LIQ EW INNS WN Address K A0-A14 Va OW, OW SEVEN tg ty ADV \N YA KA OY x t ep ~ tdc1, tde2 Read Data . i . . DQ0-DQ17 Valid Valid Vatid Valid toLz | At, Ao At, AO Ay, Ao Ay, AQ t toe OHZ G PDM44528 We 6941090 0000704 474 aPARADIGM! ADSP Write Timing Diagram PDM44528 tcyc mi LY i S SSASS home SOK - WN OW. SSS : SE ER KK mW SS SS SY) WK | UK Pay KAAQAAYL OXOY Write Data YS SS SO) DQ0-DQ17 K Valid y Ai. Ag A1,A0 SX Valid SX Valid XSK vata A1,A9 At. Ag NOTE: UW and LW are ignored for the first cycle when ADSP initiates the burst. ADSP active loads a new address into the address counter and forces the first cycle to be a read cycle. 6-18 Me 6941090 0000705 300PARADIGM ADSC Read Timing Diagrams teyc SS S SOS SS SN MOAI SOK _Yald@ QN SS tg tH ADV SSXQn INS Read Data DQ0-DQ17 | tcp et coat Valid toLz Ai, Ao toe tdc1, tdc2 Valid At, Ao Valid Ay, Ag Valid Aq, Ao toHz Van PDM44528 me 6941090 0000706 ch? 6-19PARADIGM PDM44528 ADSC Write Timing Diagram ADSP Next Burst ADSC E Address A0-A14 | ADV Write Data DQO-DQ17 At, Ag Aq, Ao Ay, Ao Ai, Ao $20 ME 6941050 c000707 183PARADIGM PDM44528 Ordering Information | 44528 32Kx18 PDM XXxxx Ss XX x x Device Power Speed Package Temp Blank Commercial (0 to 70 C) | Industrial (40 to 85 C) J 2-pin PLCC 8 Commercial Only 9 10 12 14 |__| Ss Standard Power Chip Description PDM44528 ~52-pin PLCC mm 6941090 0000708 01T 6-21