ICS9179AM-12LF - INTEGRATED DEVICE TECHNOLOGY

Integrated

Circuit

Systems, Inc.

General Description Features

ICS9179-12

0264E—12/09/08

Block Diagram

PentiumPro is a trademark of Intel Corporation

I2C is a trademark of Philips Corporation

3 DIMM Buffer

Pin Configuration

The ICS9179-12 is a buffer intended for reduced pin count

2 - chip Intel BX chipset designs

An I2C interface is included, enabling individual outputs to be

turned on or off. With 13 outputs, up to 3 DIMMs are supported.

•Thirteen high speed, low noise buffers, supports up to

three SDRAM DIMMs.

•Buffer outputs skew matched to within 250ps.

•I2C Serial Configuration interface to allow individual

OUTPUTs to be stopped low.

•Multiple VDD, VSS pins for noise reduction

•3.3V±5% supply voltage

•28-pin SOIC and SSOP package

•Propagation delay between 1 to 5.5ns

•Operation to 133MHz at 3.3V±5%

28-Pin SOIC and SSOP

* Internal pull-up resistor of 100K

Ohms to 3.3V on indicated inputs

Power Groups

VDD (0:4), GND (0:4) = Power supply for OUTPUT buffer

VDDI, GNDI = Power supply for I2C circuitry

ICS9179-12

0264E—12/09/08

Pin Descriptions

Notes:

1. At power up all thirteen OUTPUTs are enabled and active.

2. OE has a 100K Ohm internal pull-up resistor to keep all outputs active.

3. The SDATA and SCLK inputs both have internal pull-up resistors with values above 100K Ohms.

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ICS9179-12

0264E—12/09/08

VDD

This is the power supply to the internal core logic of the

device as well as the clock output buffers for OUTPUT (0:12).

This pin operates at 3.3V volts. Clocks from the listed

buffers that it supplies will have a voltage swing from Ground

to this level. For the actual guaranteed high and low voltage

levels for the Clocks, please consult the DC parameter table

in this data sheet.

GND

This is the power supply ground (common or negative) return

pin for the internal core logic and all the output buffers.

OUTPUT (0:12)

These Output Clocks are use to drive Dynamic RAM’s and

are low skew copies of the CPU Clocks. The voltage swing

of the OUTPUTs output is controlled by the supply voltage

that is applied to VDD of the device, operates at 3.3 volts.

I2C

The SDATA and SCLOCK Inputs are used to program the

device. The clock generator is a slave-receiver device in the

I2C protocol. It will allow read-back of the registers. See

configuration map for register functions. The I2C

specification in Philips I2C Peripherals Data Handbook

(1996) should be followed.

BUF_IN

Input for Fanout buffers (OUTPUT 0:12).

VDDI

This is the power supply to I2C circuitry.

Technical Pin Function Descriptions

ICS9179-12

0264E—12/09/08

Controller (Ho st) ICS (S lave /Receiver )

Start Bit

Address

D2(H) ACK

Dummy Command Code

Dummy Byte Count ACK

Byte 0 ACK

Byte 1

Byte 2 ACK

Byte 3 ACK

Byte 4

Byte 5

Byte 6 ACK

Stop Bit

How to Write:

Controller (Ho st) ICS (S lave /Receiver )

Start Bit

Address

D3(H)

Byte Count

ACK B

te 0

ACK Byte 1

ACK Byte 2

ACK B

ACK Byte

ACK Byte 5

ACK B

ACK

Stop Bit

How to Read:

1 . The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.

Read-Back will support Intel PIIX4 "Block-Read" protocol.

2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

3. The input is operating at 3.3V logic levels.

4. The data byte format is 8 bit bytes.

5. To simplify the clock generator I 2C interface, the protocol is set to use only "Block-Writes" from the controller. The

bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte

has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those

two bytes. The data is loaded until a Stop sequence is issued.

6. At power-on, all registers are set to a default condition, as shown.

General I2C serial interface information

The information in this section assumes familiarity with I2C programming.

For more information, contact ICS for an I2C programming application note.

How to Write:

• Controller (host) sends a start bit.

• Controller (host) sends the write address D2 (H)

• ICS clock will acknowledge

• Controller (host) sends a dummy command code

• ICS clock will acknowledge

• Controller (host) sends a dummy byte count

• ICS clock will acknowledge

• Controller (host) starts sending first byte (Byte 0)

through byte 5

• ICS clock will acknowledge each byte one at a time.

• Controller (host) sends a Stop bit

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the read address D3 (H)

• ICS clock will acknowledge

• ICS clock will send the byte count

• Controller (host) acknowledges

• ICS clock sends first byte (Byte 0) through byte 6

• Controller (host) will need to acknowledge each byte

• Controller (host) will send a stop bit

Notes:

ICS9179-12

0264E—12/09/08

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Byte 1: OUTPUT Clock Register

Functionality

ICS9279-12 Power Consumption

The values below are estimates of target specifications.

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Serial Configuration Command Bitmaps

Byte 0: OUTPUT Clock Register (Default=0)

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4tiB-1 devreseR

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2tiB61 2TUPTUO

1tiB31 1TUPTUO

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Byte 2: OUTPUT Clock Register

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4tiB-1 devreseR

3tiB-1 devreseR

2tiB-1 devreseR

1tiB-1 de

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0tiB-1 devreseR

Notes: 1 = Enabled; 0 = Disabled, outputs held low

Note: PWD = Power-Up Default

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ICS9179-12

0264E—12/09/08

Absolute Maximum Ratings

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V

Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are

stress specifications only and functional operation of the device at these or any other conditions above those listed in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect product reliability.

Electrical Characteristics - Input & Suppl y

TA = 0 - 70C; Supply Voltage V

DD = 3.3 V +/-5% (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input High Voltage V

IH 2V

DD+0.3 V

Input Low Voltage V

IL VSS-0.3 0.8 V

Input High Current IIH VIN = VDD 5uA

Input Low Current IIL VIN = 0 V; Inputs with no pull-up resistors -5 uA

IIL VIN = 0 V; Inputs with 100K pull-up resistors -60 uA

IDD1 CL = 0 pF; FIN @ 66MHz 120 mA

Operating IDD2 CL = 0 pF; FIN @ 100MHz 180 mA

IDD3 CL = 0 pF; FIN @ 133MHz 250 mA

Supply Current IDD4 CL = 30 pF; RS=33Ω; FIN @ 66MHz 230 mA

IDD5 CL = 30 pF; RS=33Ω; FIN @ 100MHz 360 mA

IDD6 CL = 30 pF; RS=33Ω; FIN @ 133MHz 500 mA

Input frequency Fi1VDD = 3.3 V; A ll Out puts Loaded 10 133 MHz

Input Capacitance CIN1Logic Inputs 5 pF

1Guarenteed by design, not 100% tested in production.

ICS9179-12

0264E—12/09/08

El ect rical Characterist i cs - O ut puts

TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Impedance RDSP VO = VDD*(0.5) 10 24 Ω

Output Impedance RDSN VO = VDD*(0.5) 10 24 Ω

Output High Voltage VOH IOH = -30 mA 2.6 V

Output Low Voltage VOL IOL = 23 mA 0.4 V

Output High Current IOH VOH = 2.0 V -54 mA

Output Low Current IOL VOL = 0.8 V 40 mA

Rise Time1TrVOL = 0.4 V, VOH = 2.4 V 1.33 ns

Fall Time1TfVOH = 2.4 V, VOL = 0.4 V 1.33 ns

Duty Cycle1DtVT = 1.5 V 45 55 %

Skew1Tsk VT = 1.5 V 250 ps

TPROP1 VT = 1.5 V 1 5.5 ns

TPROP2 VT = 50% BIN to 10% OUT 1 5 ns

Propagation1TPROPEN VT = 1.5 V 1 8 ns

TPROPDIS VT = 1.5 V 18ns

1Guarenteed by design, not 100% tested in production.

ICS9179-12

0264E—12/09/08

28 Pin SSOP Package

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9179yF-12LFT

XXXX y F - PPPLFT

Designation for tape and reel packaging

Annealed Lead Free (optional, RoHs compliant part)

Pattern Number (2 or 3 digit number for parts with ROM code patterns)

Package Type

F=SSOP

Revison Designator (will not correlate with datasheet revision)

Device Type (consists of 3 or 4 digit numbers)

Ordering Information

Example:

ICS9179-12

0264E—12/09/08

SOIC Package

TNUOCDAELL82

LNOISNEMID407.0

9179yM-12LFT

XXXX y M - PPPLFT

Designation for tape and reel packaging

Annealed Lead Free (optional, RoHs compliant part)

Pattern Number (2 or 3 digit number for parts with ROM code patterns)

Package Type

M=SOIC

Revison Designator (will not correlate with datasheet revision)

Device Type (consists of 3 or 4 digit numbers)

Ordering Information

Example:

ICS9179-12

0264E—12/09/08

Revision History

Rev. Issue Date Description Page #

E 12/9/2008 Removed ICS prefix from ordering information 8-9