DF6808 8-bit FAST Microcontrollers Family ver 1.04 OVERVIEW Document contains brief description of DF6808 core functionality. The DF6808 is a advanced 8-bit MCU IP Core with highly sophisticated, on chip peripheral capabilities. DF6808 soft core is binary-compatible with the industry standard 68HC08 8-bit microcontroller and can achieve a performance 45-100 million instructions per second. There are two configurations of DF6808: Harvard where data and program buses are separated, and von Neumann with common program and data bus DF6808 has FAST architecture that is 3.2 times faster compared to original implementation. Core in standard configuration has integrated on chip major peripheral function. The DF6808 Microcontroller Core contains full-duplex UART (Asynchronous serial communications interface (SCI), and Synchronous Serial Peripheral Interface SPI. The main 16-bit, free-running timer system has implemented two input capture lines and two output-compare lines. Self-monitoring circuitry is included on-chip to protect against system errors. A computer operating properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a nonmaskable interrupt if illegal opcode is detected. Two software-controlled power-saving modes, WAIT and STOP, are available to conserve additional power. These modes make the All trademarks mentioned in this document are trademarks of their respective owners. DF6808 IP Core especially attractive for automotive and battery-driven applications. DF6808 is fully customizable, which means it is delivered in the exact configuration to meet users requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow. CPU FEATURES FAST architecture, 3.2 times faster than the original implementation Software compatible with industry standard 68HC08 Configurable Harvard or Von Neumann architectures 64 bytes of System Function Registers space (SFRs) Up to 64 k bytes of Program Memory Up to 64k bytes of Data Memory De-multiplexed Address/Data Bus to allow easy connection to memory Two power saving modes: STOP, WAI Ready pin allows Core to operate with slow program and data memories Fully synthesizable, static synchronous design with no internal tri-states http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. No internal reset generator or gated clock Dedicated Interrupt vector for each interrupt source Scan test ready Technology independent HDL source code Main16-bit timer/counter system 16 bit free running counter Core can be fully customized 800 MHz virtual clock frequency compared to original implementation Timer clocked by internal source 16-bit Compare/Capture Unit Two independent input-capture functions DESIGN FEATURES ONE GLOBAL SYSTEM CLOCK SYNCHRONOUS RESET ALL ASYNCHRONOUS INPUT SIGNALS ARE Two output-compare channels Events capturing Pulses generation Digital signals generation Gated timers SYNCHRONIZED BEFORE INTERNAL USE 9 DATA MEMORY: The DF6808 can address up to 64K bytes of Data Memory. The lowest 64 Bytes is reserved for Special Function Registers area. Data Memory can be implemented as synchronous or asynchronous RAM 9 SYSTEM FUNCTION REGISTERS: Up to 64 System Function Registers(SFRs) may be implemented in the DF6808 design. 9 PROGRAM MEMORY: Up to 64kB of Program Memory may be implemented to the DF6808 design. Program Memory can be implemented as synchronous or asynchronous ROM. 9 Pulse width modulation Pulse width measuring SPI - Master and Slave Serial Peripheral Interface Supports speeds up 1/4 of system clock Software selectable polarity and phase of se- rial clock SCK System errors detection Allows operation from a wide range of system clock frequencies (build-in 5-bit timer) Interrupt generation Full-duplex UART - SCI Standard Nonreturn to Zero format (NRZ) 8 or 9 bit data transfer ALL CORE IS DESIGNED AS SYNCHRONOUS Integrated baud rate generator LOGIC WITHOUT ANY MICROCODE. Noise, Overrun and Framing error detection PERIPHERALS The peripherals listed below are implemented in standard configuration of DF6808. Sophisticated comparator DoCD TM IDLE and BREAK characters generation Wake-up block to recognize UART wake-up from IDLE condition Three SCI related interrupts on Chip Debugger Processor execution control Read, write all processor contents Hardware execution breakpoints Three wire communication interface Four 8-bit I/O Ports Interrupt Controller 7 interrupt sources 7 priority levels All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF VHDL & VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support IP Core implementation support 3 months maintenance Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support HDL Source to Netlist Single Design to Unlimited Designs CONFIGURATION The following parameters of the DF6808 core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. TM * DoCD Hardware Debugger - used unused * Architecture type - Harvard Von Neumann * Memories type - Synchronous Asynchronou * Data Memory wait-states - used unused * Power saving STOP mode - used unused * WATCHDOG Timer - used unused * Timer system - used unused * Compare Capture channels - used unused * PORTS A, B, C, D - used unused * SCI - UART Interface - used unused * SPI Interface - used unused * Support for DIV Instructions - used unused * Support for MUL Instruction - used unused * Support for DAA Instruction - used unused LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows use IP Core in single FPGA bitstream and ASIC implementation. Unlimited Designs, One Year licenses allow use IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction except One Year license where time of use is limited to 12 months. Single Design license for VHDL, Verilog source code called HDL Sour- ce Encrypted, or plain text EDIF called Netlist One Year license for Encrypted Netlist only Unlimited Designs license for HDL Source Netlist Upgrade from All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. PINS DESCRIPTION PIN ACTIVE TYPE clk - input Global system clock rst Low input Global system reset prgdata[7:0] - input Program memory bus input datai[7:0] - input Memory bus input ufrdatai[7:0] - input UFRs data bus input ready DESCRIPTION Low input Code and Data memory Ready irq * input Interrupt input portai[7:0] - input Port A input portbi[7:0] - input Port B input portci[7:0] - input Port C input portdi[7:0] - input Port D input cap1,2 Low input Capture inputs rxd Low input SCI receiver data input si High input SPI slave input mi High input SPI master input scki * input SPI clock input Low input SPI slave select clkdocd - input DoCD TM clock input docddatai - input DoCD TM serial Data input ss prgaddr[15:0] - output Program memory address bus prgoe - output Program memory output enable datao[7:0] - output Data memory & UFR bus output addr[15:0] - output Data memory address bus ramwe Low output Data memory write enable ramoe Low output Data memory output enable ufraddr[5:0] ufrwe - output UFR's address bus Low output UFRs write enable ufroe Low output UFRs output enable halt High output Halt clock system (STOP inst.) portao[7:0] - output Port A output portbo[7:0] - output Port B output portco[7:0] - output Port C output portdo[7:0] - output Port D output ddra[7:0] - output Port A data direction control ddrb[7:0] - output Port B data direction control ddrc[7:0] - output Port C data direction control ddrd[7:0] - output Port D data direction control cmp1,2 * output Compare outputs txd Low output SCI transmitter data output so High output SPI slave output mo High output SPI master output SPI clock output scko * output sckz High output Disconnect SPI clock output - output DoCD TM Serial Data Output Serial Clock Output Program Memory Write docddatao docdclk - output DoCD TM prgwe - output DoCD TM SYMBOL clk rst prgdata(7:0) prgaddr(15:0) prgoe datao(7:0) datai(7:0) ufrdatai(7:0) ready addr(15:0) ramwe ramoe ufraddr(5:0) ufrwe ufroe halt irq portai(7:0) portbi(7:0) portci(7:0) portdi(7:0) portao(7:0) portbo(7:0) portco(7:0) portdo(7:0) ddra(7:0) ddrb(7:0) ddrc(7:0) ddrd(7:0) cmp1 cmp2 cap1 cap2 rxd txd si mi scki ss so mo scko sckz clkdocd docddatai DoCD TM Interface docddatao docdclk prgwe * Kind of activity is configurable All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. BLOCK DIAGRAM Control Unit - Performs the core synchronization and data flow control. This module manages execution of all instructions. The Control Unit also manages execution of STOP instruction and wakes-up the processor from the STOP mode. become outputs, the last data written to port will be driven out the port pins. clk rst Opcode Decoder Opcode Decoder - Performs an instruction opcode decoding and the control functions for all other blocks. halt Control Unit ALU - Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (A), Condition Code Register (CCREG), Index registers (H:X) and related logic like arithmetic unit, logic unit, multiplier and divider. irq Interrupt Controller Bus Controller - Program Memory, Data Memory & SFR's (Special Function Register) interface controls access into the program and data memories and special registers. It contains Program Counter (PC), Stack Pointer (SP) register, and related logic. Interrupt Controller - DF6808 extended IC has implemented 9-level interrupt priority control. The interrupt requests may come from external pin (IRQ) as well as from particular peripherals. The DF6808 peripheral systems generate maskable interrupts, which are recognized only if the global interrupt mask bit (I) in the CCR is cleared. Maskable interrupts are prioritized according to default arrangement established during reset. When interrupt condition occurs, an interrupt status flag is set to indicate the condition. I/O Ports - All ports are 8-bit general-purpose bi-directional I/O system. The PORTA, PORTB, PORTC, PORTD data registers have their corresponding data direction registers DDRA, DDRB, DDRC, DDRD to control ports data flow. It assures that all DF6808's ports have full I/O selectable registers. Writes to any ports pins cause data to be stored in the data registers. If any port pins are configured as output then data registers are driven out of those pins. Reads from port pins configured as input causes that input pin is read. If port pins is configured as output, during read data register is read. Writes to any ports pins not configured as outputs do not cause data to be driven out of those pins, but the data is stored in the output registers. Thus, if the pins later All trademarks mentioned in this document are trademarks of their respective owners. BUS Controller ufraddr(5:0) ufrwe ufroe ALU Watchdog Timer rxd txd so si mo mi scko scki sckz ss I/O Ports SCI Unit SPI Unit ready prgdata(7:0) prgaddr(15:0) prgoe datai(7:0) datao(7:0) addr(23:0) ramwe ramoe Timer with Compare / Capture Unit TM DoCD Debugger portai(7:0) portbi(7:0) portci(7:0) portdi(7:0) portao(7:0) portbo(7:0) portco(7:0) portdo(7:0) ddra(7:0) ddrb(7:0) ddrc(7:0) ddrd(7:0) cap1 cap2 cmp1 cmp2 clkdocd docddatai docddatao docdclk prgwe Timer & Compare - The programmable timer is based on free-running 16-bit counter with a fixed divide by four prescaler. plus input capture/output compare circuitry. The timer can be used for many purposes including measuring pulse length of two input signals and generating two output signals. The timer has 16bit architecture, hence each specific functional segment is represented by two 8-bit registers. These registers contains the high and low byte of that functional block. Accessing the low byte of a specific timer function allows full control of that function, however, an access of the high byte inhibits that specific timer function until the byte is also accessed. Each of the input-capture channel has its own 16-bit time capture latch (input-capture register) and each of the output-compare channel has its own 16-bit compare register. Additional http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. control bits permit software to control the edge(s) that trigger each input-capture function and the automatic actions that result from output-compare functions. Although hardwired logic is included to automate many timer activities, this timer architecture is essentially a software-oriented system. This structure is easily adaptable to a very wide range of applications although it is not as efficient as dedicated hardware for some specific timing applications. Watchdog Timer - The Watchdog Timer consist of a free running Timer CLK/213 , plus control logic. The Watchdog Timer can be enabled by software by writing `1' to the WDOG bit in MISC register($000C). Once enabled the WDT Timer cannot be disabled by software. In addition the WDOG bit acts as a reset mechanism for the WDT timer. Writing logic one `1' to the WDOG bit clears Watchdog counter and inhibits Watchdog timeout SCI - The SCI is a full-duplex UART type asynchronous system, using standard non return to zero (NRZ) format : 1 start bit, 8 or 9 data bits and a 1 stop bit. The DF6808 resynchronizes the receiver bit clock on all one to zero transitions in the bit stream. Therefore differences in baud rate between the sending device and the SCI are not as likely to cause reception errors. Three logic samples are taken near the middle of data bit time, and majority logic decides the sense for the bit. For the start and stop bits seven logic samples are taken. Even if noise causes one of these samples to be incorrect, the bit will still be received correctly. The receiver also has the ability to enter a temporary standby mode (called receiver wakeup) to ignore messages intended for a different receiver. Logic automatically wakes up the receiver in time to see the first character of the next message. This wakeup feature greatly reduces CPU overhead in multi-drop SCI networks. The SCI transmitter can produce queued characters of idle (whole characters of all logic 1) and break (whole characters of all logic 0). In addition to the usual transmit data register empty (TDRE) status flag, this SCI also provides a transmit complete (TC) indication that can be used in applications with a modem. SPI Unit - it's a fully configurable master/slave Serial Peripheral Interface, which allows user to configure polarity and phase of All trademarks mentioned in this document are trademarks of their respective owners. serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. SPI data are simultaneously transmitted and received. SPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. SPI automatically drives slave select outputs SSO[7:0], and address SPI slave device to exchange serially shifted data. Error-detection logic is included to support interprocessor communications. A write-collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master mode-fault detector automatically disables SPI output drivers if more than one SPI devices simultaneously attempts to become bus master. DoCDTM - Debug Unit - it's a real-time hardware debugger provides debugging capability of a whole SoC system. In contrast to other on-chip debuggers DoCDTM provides nonintrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed if any write/read occurred at particular address with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off to save silicon and reduce power consumption. A special care on power consumption has been taken, and when debugger is not used it is automatically switched in power save mode. Finally whole debugger is turned off when debug option is no longer used. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. OPTIONAL PERIPHERALS There are also available an optional peripherals, not included in presented DF6808 Microcontroller Core. The optional peripherals, can be implemented in microcontroller core upon customer request. I2C bus controller - Master 7-bit and 10-bit addressing modes NORMAL, FAST, HIGH speeds Multi-master systems supported Clock arbitration and synchronization User defined timings on I2C lines Wide range of system clock frequencies Interrupt generation I2C bus controller - Slave NORMAL speed 100 kbs FAST speed 400 kbs HIGH speed 3400 kbs Wide range of system clock frequencies User defined data setup time on I2C lines Interrupt generation PWM - Pulse Width Modulation Timer Fixed-Point arithmetic coprocessor PERFORMANCE The following table gives a survey about the Core area and performance in the ALTERA(R) devices after Place & Route: Speed Logic Cells Fmax grade CYCLONE -6 2635 61 MHz CYCLONE II -6 2635 65 MHz STRATIX -5 2636 65 MHz STRATIX II -3 2124 96 MHz STRATIX GX -5 2636 66 MHz APEX20KC -7 2531 48 MHz APEX20KE -1 2531 41 MHz ACEX1K -1 2536 36 MHz FLEX10KE -1 2536 36 MHz Core performance in ALTERA(R) devices Device Area utilized by the each unit of DF6808 core in vendor specific technologies is summarized in table below. Component Area [LC] CPU* Main Timer COM/CAP Watchdog SPI Interface UART - SCI I/O Ports Total area 1 780 110 150 29 131 272 161 2 635 214 55 60 14 62 124 64 593 *CPU - consisted of ALU, Control Unit and Instruction Decoder, Bus Controller with support for 64KB RAM, External IRQ pin Interrupt Controller Core components area utilization arithmetic coprocessor Floating-Point IEEE-754 standard single precision All trademarks mentioned in this document are trademarks of their respective owners. [FFs] http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. Function IMPROVEMENT For user the most important is application speed improvement. The most commonly used arithmetic functions and theirs improvement are shown in table below. Improvement was computed as {M68HC08 clock periods} divided by {DF6808 clock periods} required to execute an identical function. More details are available in core documentation 8-bit addition (immediate data) 8-bit addition (direct addressing) 8-bit addition (indirect addressing) 8-bit subtraction (immediate data) 8-bit subtraction (direct addressing) 8-bit subtraction (indirect addressing) 16-bit addition (immediate data) 16-bit addition (direct addressing) 16-bit addition (indirect addressing 16-bit subtraction (immediate data) 16-bit subtraction (direct addressing) 16-bit subtraction (indirect addressing Multiplication Division Improvement 4 4 3,6 4 4 3,6 4 4 3,6 4 4 3,6 5 5 DF68XX FAMILY OVERVIEW + * * * + 4 4 4 + * + + * + DF68XX family of High Performance Microcontroller Cores + optional * configurable All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. Size - ASIC gates * * * DoCD Debugger + Interface for additional SFRs 1* 1* 1* + Pulse accumulator 2/2* 22* 5/3* + Watchdog Timer * * * * I\O Ports 1* 1* SPI M/S Interface - SCI (UART) 7 7 17 3 Main Timer System 7 7 20 3 Compare\Capture - READY for Pro. and Data mem. Interrupt levels 64k 64k 16M 16M Data Pointers Interrupt sources 64k 64k 64k 64k Real Time Interrupt Motorola Memory Expansion Logic DF6805 DF6808 DF6811 DF6811CPU Paged Data Memory space Design Physical Linear memory space The main features of each DF68XX family member have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. User can specify its own peripheral set (including listed below and the others) and requests the core modifications. 6 700 8 900 12 000 6 500 CONTACTS For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND n fo @ d c d .p l e-mail: iinfo@dcd.pl tel. : +48 32 282 82 66 fax : +48 32 282 74 37 Distributors: ttp://www.dcd.pl/apartn.php Please check hhttp://www.dcd.pl/apartn.php All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved.