Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. I
08/10/09
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
IS61WV5128ALL/ALS
IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
512K x 8 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM
AUGUST 2009
DESCRIPTION
The ISSI IS61WV5128Axx and IS61/64WV5128Bxx
are very high-speed, low power, 524,288-word by
8-bit CMOS static RAMs. The IS61WV5128Axx and
IS61/64WV5128Bxx are fabricated using ISSI's high-
performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques,
yields higher performance and low power consumption
devices.
When CE is HIGH (deselected), the device assumes
a standby mode at which the power dissipation can be
reduced down with CMOS input levels.
The IS61WV5128Axx and IS61/64WV5128Bxx operate
from a single power supply.
The IS61WV5128ALL and IS61/64WV5128BLL are avail-
able in 36-pin 400-mil SOJ, 36-pin mini BGA, and 44-pin
TSOP (Type II) packages.
The IS61WV5128ALS and IS61/64WV5128BLS are
available in 32-pinTSOP (Type I), 32-pin sTSOP (Type I),
32-pin SOP and 32-pin TSOP (Type II) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A18
CE
OE
WE
512K X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
FEATURES
HIGH SPEED: (IS61/64WV5128ALL/BLL)
• High-speedaccesstime:8,10,20ns
• LowActivePower:85mW(typical)
• Lowstand-bypower:7mW(typical)
CMOS standby
LOW POWER: (IS61/64WV5128ALS/BLS)
• High-speedaccesstime:25,35ns
• LowActivePower:35mW(typical)
• Lowstand-bypower:0.6mW(typical)
CMOS standby
• Singlepowersupply
— Vd d 1.65V to 2.2V (IS61WV5128Axx)
— Vd d 2.4V to 3.6V (IS61/64WV5128Bxx)
• Fullystaticoperation:noclockorrefresh
required
• Threestateoutputs
• IndustrialandAutomotivetemperaturesupport
• Lead-freeavailable
2 Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
PIN CONFIGURATION (HIGH SPEED) (61/64WV5128ALL/BLL)
36 mini BGA
PIN DESCRIPTIONS
A0-A18 Address Inputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Bidirectional Ports
Vd d Power
GND Ground
NC No Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A0
A1
A2
A3
A4
CE
I/O0
I/O1
V
DD
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
VDD
I/O5
I/O4
A14
A13
A12
A11
A10
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VDD
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
VDD
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
44
43
42
41
44-Pin TSOP (Type II)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
A0
I/O4
I/O5
GND
V
DD
I/O6
I/O7
A9
A1
A2
OE
A10
NC
WE
NC
A18
CE
A11
A3
A4
A5
A17
A16
A12
A6
A7
A15
A13
A8
I/O0
I/O1
V
DD
GND
I/O2
I/O3
A14
36-Pin SOJ
Integrated Silicon Solution, Inc. — www.issi.com 3
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
PIN CONFIGURATION (LOW POWER) (61/64WV5128ALS/BLS)
32-pin TSOP (TYPE I), (Package Code T)
32-pin sTSOP (TYPE I) (Package Code H)
32-pin SOP
32-pin TSOP (TYPE II)
(Package Code T2)
PIN DESCRIPTIONS
A0-A18 Address Inputs
CE Chip Enable 1 Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
Vd d Power
GND Ground
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
WE
A18
A15
V
DD
A17
A16
A14
A12
A7
A6
A5
A4
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
A15
A18
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
V
DD
4 Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VD D = 2.4V-3.6V
Symbol Parameter Test Conditions Min. Max. Unit
Vo h Output HIGH Voltage Vd d = Min., Io h = –1.0 mA 1.8 — V
Vo l Output LOW Voltage Vd d = Min., Io l = 1.0 mA — 0.4 V
VI h Input HIGH Voltage 2.0 Vd d + 0.3 V
VI l Input LOW Voltage(1) –0.3 0.8 V
Il I Input Leakage GND ≤ VI n ≤ Vd d –1 1 µA
Il o Output Leakage GND ≤ Vo u t ≤ Vd d , Outputs Disabled –1 1 µA
Note:
1. VI l (min.) = –0.3V DC; VI l (min.) = –2.0V AC (pulse width <10 ns). Not 100% tested.
VI h (max.) = Vd d + 0.3V dC; VI h (max.) = Vd d + 2.0V AC (pulse width <10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VD D = 3.3V + 5%
Symbol Parameter Test Conditions Min. Max. Unit
Vo h Output HIGH Voltage Vd d = Min., Io h = –4.0 mA 2.4 — V
Vo l Output LOW Voltage Vd d = Min., Io l = 8.0 mA — 0.4 V
VI h Input HIGH Voltage 2 Vd d + 0.3 V
VI l Input LOW Voltage(1) –0.3 0.8 V
Il I Input Leakage GND ≤ VI n ≤ Vd d –1 1 µA
Il o Output Leakage GND ≤ Vo u t ≤ Vd d , Outputs Disabled –1 1 µA
Note:
1. VI l (min.) = –0.3V DC; VI l (min.) = –2.0V AC (pulse width <10 ns). Not 100% tested.
VI h (max.) = Vd d + 0.3V dC; VI h (max.) = Vd d + 2.0V AC (pulse width <10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
VD D = 1.65V-2.2V
Symbol Parameter Test Conditions Min. Max. Unit
Vo h Output HIGH Voltage Vd d = Min, Io h = -0.1 mA 1.4 — V
Vo l Output LOW Voltage Vd d = Min, Io l = 0.1 mA — 0.2 V
VI h Input HIGH Voltage 1.4 Vd d + 0.2 V
VI l (1) Input LOW Voltage –0.2 0.4 V
Il I Input Leakage GND ≤ VI n ≤ Vd d –1 1 µA
Il o Output Leakage GND ≤ Vo u t ≤ Vd d , Outputs Disabled –1 1 µA
Note:
1. VI l (min.) = –0.3V DC; VI l (min.) = –2.0V AC (pulse width <10 ns). Not 100% tested.
VI h (max.) = Vd d + 0.3V dC; VI h (max.) = Vd d + 2.0V AC (pulse width <10 ns). Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com 5
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
Vt e r M Terminal Voltage with Respect to GND –0.5 to Vd d + 0.5 V
Vd d Vd d Relates to GND –0.3 to 4.0 V
ts t g Storage Temperature –65 to +150 °C
Pt Power Dissipation 1.0 W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CI n Input Capacitance VI n = 0V 6 pF
CI/o Input/Output Capacitance Vo u t = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A = 25°C, f = 1 MHz, Vd d = 3.3V.
TRUTH TABLE
Mode WE CE OE I/O Operation VD D Current
Not Selected X H X High-Z Is b 1, Is b 2
(Power-down)
Output Disabled H L H High-Z IC C
Read H L L do u t IC C
Write L L X dI n IC C
6 Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
OPERATING RANGE (VD D ) (IS61WV5128BLL)(1)
Range Ambient Temperature VD D (8 nS)1 VD D (10 nS)1
Commercial 0°C to +70°C 3.3V + 5% 2.4V-3.6V
Industrial –40°C to +85°C 3.3V + 5% 2.4V-3.6V
Note:
1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%,
the device meets 8ns.
OPERATING RANGE (VD D ) (IS64WV5128BLL)
Range Ambient Temperature VD D (10 nS)
Automotive –40°C to +125°C 2.4V-3.6V
HIGH SPEED (IS61WV5128ALL/BLL)
OPERATING RANGE (VD D ) (IS61WV5128ALL)
Range Ambient Temperature VD D Speed
Commercial 0°C to +70°C 1.65V-2.2V 20ns
Industrial –40°C to +85°C 1.65V-2.2V 20ns
Automotive –40°C to +125°C 1.65V-2.2V 20ns
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 -10 -20
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
IC C Vd d Dynamic Operating Vd d = Max., Com. — 50 — 40 — 40 mA
Supply Current Io u t = 0 mA, f = fM A x Ind. — 55 — 45 — 45
Auto. — — — 65 — 65
typ.(2) 25
IC C 1 Operating Vd d = Max., Com. — 35 — 35 — 30 mA
Supply Current Io u t = 0 mA, f = 0 Ind. — 40 — 40 — 40
Auto. — — — 60 — 60
Is b 1 TTL Standby Current Vd d = Max., Com. — 10 — 10 — 10 mA
(TTL Inputs) VI n = VI h or VI l Ind. — 15 — 15 — 15
CE ≥ VI h , f = 0 Auto. — — — 30 — 30
Is b 2 CMOS Standby Vd d = Max., Com. — 7 — 7 — 7 mA
Current (CMOS Inputs) CE ≥ Vd d – 0.2V, Ind. — 10 — 10 — 10
VI n ≥ Vd d – 0.2V, or Auto. — — — 20 — 20
VI n ≤ 0.2V
, f = 0 typ.(2) 2
Note:
1. At f = fM A x , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vd d = 3.0V, TA = 25oC and not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com 7
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-25 -35
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
IC C Vd d Dynamic Operating Vd d = Max., Com. — 20 — 20 mA
Supply Current Io u t = 0 mA, f = fM A x Ind. — 25 — 25
Auto. — 50 — 50
typ.(2) 11
IC C 1 Operating Vd d = Max., Com. — 10 — 10 mA
Supply Current Io u t = 0 mA, f = 0 Ind. — 12 — 12
Auto. — 20 — 20
Is b 1 TTL Standby Current Vd d = Max., Com. — 5 — 5 mA
(TTL Inputs) VI n = VI h or VI l Ind. — 7 — 7
CE ≥ VI h , f = 0 Auto. — 10 — 10
Is b 2 CMOS Standby Vd d = Max., Com. — 1 — 1 mA
Current (CMOS Inputs) CE ≥ Vd d – 0.2V, Ind. — 2 — 2
VI n ≥ Vd d – 0.2V, or Auto. — 10 — 10
VI n ≤ 0.2V
, f = 0 typ.(2) 0.2
Note:
1. At f = fM A x , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vd d = 3.0V, TA = 25oC and not 100% tested.
OPERATING RANGE (VD D ) (IS61WV5128BLS)(1)
Range Ambient Temperature VD D Speed
Commercial 0°C to +70°C 2.4V-3.6V 25 ns
Industrial –40°C to +85°C 2.4V-3.6V 25 ns
LOW POWER (IS61WV5128ALS/BLS)
OPERATING RANGE (VD D ) (IS61WV5128ALS)
Range Ambient Temperature VD D Speed
Commercial 0°C to +70°C 1.65V-2.2V 35ns
Industrial –40°C to +85°C 1.65V-2.2V 35ns
Automotive –40°C to +125°C 1.65V-2.2V 35ns
OPERATING RANGE (VD D ) (IS64WV5128BLS)
Range Ambient Temperature VD D Speed
Automotive –40°C to +125°C 2.4V-3.6V 35 ns
8 Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
AC TEST LOADS
Figure 1.
319 Ω
5 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
Figure 2.
ZO = 50Ω
1.5V
50Ω
OUTPUT
30pF
Including
jig and
scope
AC TEST CONDITIONS
Parameter Unit Unit Unit
(2.4V-3.6V) (3.3V + 10%) (1.65V-2.2V)
Input Pulse Level 0V to 3V 0V to 3V 0V to 1.8V
InputRiseandFallTimes 1V/ns 1V/ns 1V/ns
Input and Output Timing 1.5V 1.5V 0.9V
and Reference Level (VRef)
OutputLoad SeeFigures1and2 SeeFigures1and2 SeeFigures1and2
Integrated Silicon Solution, Inc. — www.issi.com 9
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 -10
Symbol Parameter Min. Max. Min. Max. Unit
tr C Read Cycle Time 8 — 10 — ns
tA A Address Access Time — 8 — 10 ns
to h A Output Hold Time 2.0 — 2.0 — ns
tA C e CE Access Time — 8 — 10 ns
td o e OE Access Time — 4.5 — 4.5 ns
th z o e (2) OE to High-Z Output — 3 — 4 ns
tl z o e (2) OE to Low-Z Output 0 — 0 — ns
th z C e (2 CE to High-Z Output 0 3 0 4 ns
tl z C e (2) CE to Low-Z Output 3 — 3 — ns
tP u Power Up Time 0 — 0 — ns
tP d Power Down Time — 8 — 10 ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output load-
ingspeciedinFigure1.
2. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.
10 Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-20 ns -25 ns -35 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tr C Read Cycle Time 20 — 25 — 35 — ns
tA A Address Access Time — 20 — 25 — 35 ns
to h A Output Hold Time 2.5 — 4 — 4 — ns
tA C e CE Access Time — 20 — 25 — 35 ns
td o e OE Access Time — 8 — 12 — 15 ns
th z o e (2) OE to High-Z Output 0 8 0 8 0 10 ns
tl z o e (2) OE to Low-Z Output 0 — 0 — 0 — ns
th z C e (2 CE to High-Z Output 0 8 0 8 0 10 ns
tl z C e (2) CE to Low-Z Output 3 — 10 — 10 — ns
tP u Power Up Time
0 — 0 — 0 — ns
tP d Power Down Time
— 20 — 25 — 35 ns
Notes:
1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
Vd d -0.3VandoutputloadingspeciedinFigure1a.
2. TestedwiththeloadinFigure1b.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
3. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com 11
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
READ CYCLE NO. 2(1,3) (CE and OE Controlled)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VI l .
3. Address is valid prior to or coincident with CE LOW transitions.
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VI l )
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
DOUT
ADDRESS
12 Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 -10
Symbol Parameter Min. Max. Min. Max. Unit
tw C Write Cycle Time 8 — 10 — ns
ts C e CE to Write End 6.5 — 8 — ns
tA w Address Setup Time 6.5 — 8 — ns
to Write End
th A Address Hold from Write End 0 — 0 — ns
ts A Address Setup Time 0 — 0 — ns
tP w e 1 WE Pulse Width (OE = HIGH) 6.5 — 8 — ns
tP w e 2 WE Pulse Width (OE = LOW) 8.0 — 10 — ns
ts d Data Setup to Write End 5 — 6 — ns
th d Data Hold from Write End 0 — 0 — ns
th z w e (2) WE LOW to High-Z Output — 3.5 — 5 ns
tl z w e (2) WE HIGH to Low-Z Output 2 — 2 — ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output load-
ingspeciedinFigure1.
2. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one
can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that
terminates the write. Shaded area product in development
Integrated Silicon Solution, Inc. — www.issi.com 13
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
-20 ns -25 ns -35 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tw C Write Cycle Time 20 — 25 — 35 — ns
ts C e CE to Write End 12 — 18 — 25 — ns
tA w Address Setup Time 12 — 15 — 25 — ns
to Write End
th A Address Hold from Write End 0 — 0 — 0 — ns
ts A Address Setup Time 0 — 0 — 0 — ns
tP w e 1 WE Pulse Width (OE = HIGH) 12 — 18 — 30 — ns
tP w e 2 WE Pulse Width (OE = LOW) 17 — 20 — 30 — ns
ts d Data Setup to Write End 9 — 12 — 15 — ns
th d Data Hold from Write End 0 — 0 — 0 — ns
th z w e (3) WE LOW to High-Z Output — 9 — 12 — 20 ns
tl z w e (3) WE HIGH to Low-Z Output 3 — 5 — 5 — ns
Notes:
1. Test conditions for IS61WV6416LL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse
levels of 0.4V to Vd d -0.3VandoutputloadingspeciedinFigure1a.
2. TestedwiththeloadinFigure1b.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
14 Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
DATAUNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
DOUT
DIN DATA
IN
VALID
t
LZWE
t
SD
CE_WR1.eps
Integrated Silicon Solution, Inc. — www.issi.com 15
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08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > VI h .
DATAUNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
DOUT
DIN
OE
DATAIN VALID
t
LZWE
t
SD
CE_WR2.eps
WRITE CYCLE NO. 2(1,2) (WE Controlled: OE is HIGH During Write Cycle)
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
DATAUNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA t
HZWE
ADDRESS
CE
WE
DOUT
DIN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR3.eps
16 Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
DATA RETENTION WAVEFORM (CE Controlled)
HIGH SPEED (IS61WV5128ALL/BLL)
DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V)
Symbol Parameter Test Condition Options Min. Typ.(1) Max. Unit
Vd r Vd d for Data Retention See Data Retention Waveform 2.0 — 3.6 V
Id r Data Retention Current Vd d = 2.0V, CE ≥ Vd d – 0.2V Com. — 2 6 mA
Ind. — — 8
Auto. 15
ts d r Data Retention Setup Time See Data Retention Waveform 0 — — ns
tr d r Recovery Time See Data Retention Waveform tr C — — ns
Note 1: Typical values are measured at Vd d = 3.0V, TA = 25
o
C and not 100% tested.
VDD
CE ≥ V
DD
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
Data Retention Mode
DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V)
Symbol Parameter Test Condition Options Min. Typ.(1) Max. Unit
Vd r Vd d for Data Retention See Data Retention Waveform 1.2 — 3.6 V
Id r Data Retention Current Vd d = 1.2V, CE ≥ Vd d – 0.2V Com. — 2 6 mA
Ind. — — 8
ts d r Data Retention Setup Time See Data Retention Waveform 0 — — ns
tr d r Recovery Time See Data Retention Waveform tr C — — ns
Note 1: Typical values are measured at Vd d = 1.8V, TA = 25
o
C and not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com 17
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
DATA RETENTION WAVEFORM (CE Controlled)
LOW POWER (IS61WV5128ALS/BLS)
DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V)
Symbol Parameter Test Condition Options Min. Typ.(1) Max. Unit
Vd r Vd d for Data Retention See Data Retention Waveform 2.0 — 3.6 V
Id r Data Retention Current Vd d = 2.0V, CE ≥ Vd d – 0.2V Com. — 0.2 1 mA
Ind. — — 2
Auto. 10
ts d r Data Retention Setup Time See Data Retention Waveform 0 — — ns
tr d r Recovery Time See Data Retention Waveform tr C — — ns
Note 1: Typical values are measured at Vd d = 3.0V, TA = 25
o
C and not 100% tested.
VDD
CE ≥ V
DD
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
Data Retention Mode
DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V)
Symbol Parameter Test Condition Options Min. Typ.(1) Max. Unit
Vd r Vd d for Data Retention See Data Retention Waveform 1.2 — 3.6 V
Id r Data Retention Current Vd d = 1.2V, CE ≥ Vd d – 0.2V Com. — 0.2 1 mA
Ind. — — 2
ts d r Data Retention Setup Time See Data Retention Waveform 0 — — ns
tr d r Recovery Time See Data Retention Waveform tr C — — ns
Note 1: Typical values are measured at Vd d = 1.8V, TA = 25
o
C and not 100% tested.
18 Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
ORDERING INFORMATION (HIGH SPEED)
Commercial Range: 0°C to +70°C
Voltage Range: 2.4V to 3.6V
Speed (ns) Order Part No. Package
10 (81) IS61WV5128BLL-10TL TSOP (Type II), Lead-free
Note:
1. Speed = 8ns for Vd d = 3.3V + 5%. Speed = 10ns for Vd d = 2.4V to 3.6V.
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
Speed (ns) Order Part No. Package
10 (81) IS61WV5128BLL-10BI 36-ball mini BGA (6mm x 8mm)
IS61WV5128BLL-10BLI 36-ball mini BGA (6mm x 8mm), Lead-free
IS61WV5128BLL-10TI TSOP (Type II)
IS61WV5128BLL-10TLI TSOP (Type II), Lead-free
IS61WV5128BLL-10KLI 400-mil Plastic SOJ, Lead-free
Note:
1. Speed = 8ns for Vd d = 3.3V + 5%. Speed = 10ns for Vd d = 2.4V to 3.6V.
Industrial Range: -40°C to +85°C
Voltage Range: 1.65V to 2.2V
Speed (ns) Order Part No. Package
20 IS61WV5128ALL-20BI 36-ball mini BGA (6mm x 8mm)
IS61WV5128ALL-20TI TSOP (Type II)
Automotive Range: -40°C to +125°C
Voltage Range: 2.4V to 3.6V
Speed (ns) Order Part No. Package
10 IS64WV5128BLL-10BA3 36-ball mini BGA (6mm x 8mm)
IS64WV5128BLL-10BLA3 36-ball mini BGA (6mm x 8mm), Lead-free
IS64WV5128BLL-10CTA3 TSOP (Type II), Copper Leadframe
IS64WV5128BLL-10CTLA3 TSOP (Type II), Copper Leadframe
Lead-free
Integrated Silicon Solution, Inc. — www.issi.com 19
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
ORDERING INFORMATION (LOW POWER)
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
Speed (ns) Order Part No. Package
25 IS61WV5128BLS-25TLI TSOP (Type II), Lead-free
20 Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
NOTE :
5. Reference document : JEDEC SPEC MS-027.
1. Controlling dimension : mm
at the seating plane after final test.
3. Dimension b2 does not include dambar protrusion/intrusion.
4. Formed leads shall be planar with respect to one another within 0.1mm
2. Dimension D and E1 do not include mold protrusion .
12/20/2007
Integrated Silicon Solution, Inc. — www.issi.com 21
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
NOTE :
1. CONTROLLING DIMENSION : MM .
2. Reference document : JEDEC MO-207
08/12/2008
Package Outline
22 Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
1. CONTROLLING DIMENSION : MM
NOTE :
Θ
Θ
06/04/2008
Package Outline
Integrated Silicon Solution, Inc. — www.issi.com 23
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
24 Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
Integrated Silicon Solution, Inc. — www.issi.com 25
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS