Semiconductor Components Industries, LLC, 2002
December, 2002 - Rev. 4 1Publication Order Number:
MMBTA42LT1/D
MMBTA42LT1,
MMBTA43LT1
MMBTA42LT1 is a Preferred Device
High Voltage Transistors
NPN Silicon
MAXIMUM RATINGS
Rating Symbol MMBTA42 MMBTA43 Unit
Collector- Emitter Voltage VCEO 300 200 Vdc
Collector- Base Voltage VCBO 300 200 Vdc
Emitter- Base Voltage VEBO 6.0 6.0 Vdc
Collector Current-Continuous IC500 mAdc
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation FR-5 Board (Note 1)
TA = 25°C
Derate above 25°C
PD225
1.8
mW
mW/°C
Thermal Resistance, Junction to Ambient RJA 556 °C/W
Total Device Dissipation
Alumina Substrate (Note 2)
TA = 25°C
Derate above 25°C
PD300
2.4
mW
mW/°C
Thermal Resistance, Junction to Ambient RJA 417 °C/W
Junction and Storage Temperature TJ, Tstg -55 to
+150 °C
1. FR-5 = 1.0 x 0.75 x 0.062 in.
2. Alumina = 0.4 x 0.3 x 0.024 in. 99.5% alumina.
Device Package Shipping
ORDERING INFORMATION
MMBTA42LT1 SOT-23
SOT-23 (TO-236)
CASE 318
STYLE 6
3000/Tape & Reel
2
3
1
Preferred devices are recommended choices for future use
and best overall value.
MARKING DIAGRAMS
1D X
MMBTA42LT1
M1E X
MMBTA43LT1
MMBTA43LT3 SOT-23 3000/Tape & Reel
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1D, M1E = Specific Device Code
X = Date Code
COLLECTOR
3
1
BASE
2
EMITTER
MMBTA42LT1, MMBTA43LT1
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2
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Max Unit
OFF CHARACTERISTICS
Collector- Emitter Breakdown Voltage (Note 3)
(IC = 1.0 mAdc, IB = 0) MMBTA42
MMBTA43
V(BR)CEO 300
200 -
-
Vdc
Collector- Base Breakdown Voltage
(IC = 100 Adc, IE = 0) MMBTA42
MMBTA43
V(BR)CBO 300
200 -
-
Vdc
Emitter- Base Breakdown Voltage
(IE = 100 Adc, IC = 0) V(BR)EBO 6.0 - Vdc
Collector Cutoff Current
(VCB = 200 Vdc, IE = 0) MMBTA42
(VCB = 160 Vdc, IE = 0) MMBTA43
ICBO -
-0.1
0.1
Adc
Emitter Cutoff Current
(VEB = 6.0 Vdc, IC = 0) MMBTA42
(VEB = 4.0 Vdc, IC = 0) MMBTA43
IEBO -
-0.1
0.1
Adc
ON CHARACTERISTICS (Note 3)
DC Current Gain
(IC = 1.0 mAdc, VCE = 10 Vdc) Both Types
(IC = 10 mAdc, VCE = 10 Vdc) Both Types
(IC = 30 mAdc, VCE = 10 Vdc) MMBTA42
MMBTA43
hFE 25
40
40
40
-
-
-
-
-
Collector- Emitter Saturation Voltage
(IC = 20 mAdc, IB = 2.0 mAdc) MMBTA42
MMBTA43
VCE(sat) -
-0.5
0.5
Vdc
Base-Emitter Saturation Voltage
(IC = 20 mAdc, IB = 2.0 mAdc) VBE(sat) - 0.9 Vdc
SMALL- SIGNAL CHARACTERISTICS
Current- Gain - Bandwidth Product
(IC = 10 mAdc, VCE = 20 Vdc, f = 100 MHz) fT50 - MHz
Collector-Base Capacitance
(VCB = 20 Vdc, IE = 0, f = 1.0 MHz) MMBTA42
MMBTA43
Ccb -
-3.0
4.0
pF
3. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.
MMBTA42LT1, MMBTA43LT1
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C, CAPACITANCE (pF)
Figure 1. DC Current Gain
VR, REVERSE VOLTAGE (VOLTS)
0.1
100
0.1
10
1.0 10 1000
Ceb @ 1MHz
Figure 2. Capacitance
IC, COLLECTOR CURRENT (mA)
10070503020107.05.03.02.0
80
70
50
30
20
10
TJ = 25°C
VCE = 20 V
f = 20 MHz
f, CURRENT−GAIN  BANDWIDTH (MHz)
T
1.0
IC, COLLECTOR CURRENT (mA)
Figure 3. Current-Gain - Bandwidth
V, VOLTAGE (VOLTS)
1.4
0.0
1.2
1.0
0.8
0.6
0.4
0.2
100100.1 1.0
100
1.0 Ccb @ 1MHz
60
40
VBE(on) @ 25°C, VCE = 10 V
VCE(sat) @ 25°C, IC/IB = 10
VBE(sat) @ 25°C, IC/IB = 10
VCE(sat) @ 125°C, IC/IB = 10
VCE(sat) @ −55°C, IC/IB = 10
VBE(sat) @ 125°C, IC/IB = 10
VBE(sat) @ −55°C, IC/IB = 10
VBE(on) @ 125°C, VCE = 10 V
VBE(on) @ −55°C, VCE = 10 V
Figure 4. “ON” Voltages
IC, COLLECTOR CURRENT (mA)
120
0.1 1.0 10
100
80
60
0
hFE, DC CURRENT GAIN
TJ = +125°C
25°C
−55°C
VCE = 10 Vdc
100
20
40
MMBTA42LT1, MMBTA43LT1
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4
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device which
in this case is 225 milliwatts.
INFORMATION FOR USING THE SOT-23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
SOT-23
mm
inches
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
SOT-23 POWER DISSIPATION
PD = TJ(max) - TA
RθJA
PD = 150°C - 25°C
556°C/W = 225 milliwatts
The power dissipation of the SOT-23 is a function of th e
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipa-
tion. Power dissipation for a surface mount device is deter-
mined b y T J(max), the maximum rated junction temperature
of the die, RθJA, the thermal resistance from the device
junction to ambient, and the operating temperature, TA.
Using the values provided on the data sheet for the SOT-23
package, PD can be calculated as follows:
The 556°C/W for the SOT-23 package assumes the use
of the recommended footprint on a glass epoxy printed
circuit board to achieve a power dissipation of 225 milli-
watts. There are other alternatives to achieving higher
power dissipation from the SOT-23 package. Another
alternative would be to use a ceramic substrate or an
aluminum core board such as Thermal Clad. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the
rated temperature of the device. When the entire device is
heated to a high temperature, failure to complete soldering
within a short time could result in device failure. There-
fore, the following items should always be observed in
order to minimize the thermal stress to which the devices
are subjected.
Always preheat the device.
The delta temperature between the preheat and
soldering should be 100°C or less.*
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
Mechanical stress or shock should not be applied
during cooling.
* Soldering a device without preheating can cause exces-
sive thermal shock and stress which can result in damage
to the device.
MMBTA42LT1, MMBTA43LT1
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5
PACKAGE DIMENSIONS
CASE 318-08
ISSUE AH
SOT-23 (TO-236)
DJ
K
L
A
C
BS
H
GV
3
12
DIM
A
MIN MAX MIN MAX
MILLIMETERS
0.1102 0.1197 2.80 3.04
INCHES
B0.0472 0.0551 1.20 1.40
C0.0350 0.0440 0.89 1.11
D0.0150 0.0200 0.37 0.50
G0.0701 0.0807 1.78 2.04
H0.0005 0.0040 0.013 0.100
J0.0034 0.0070 0.085 0.177
K0.0140 0.0285 0.35 0.69
L0.0350 0.0401 0.89 1.02
S0.0830 0.1039 2.10 2.64
V0.0177 0.0236 0.45 0.60
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
4. 318−03 AND −07 OBSOLETE, NEW STANDARD
318−08.
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
MMBTA42LT1, MMBTA43LT1
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6
Notes
MMBTA42LT1, MMBTA43LT1
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7
Notes
MMBTA42LT1, MMBTA43LT1
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8
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Phone: 81-3-5773-3850
Email: r14525@onsemi.com
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MMBTA42LT1/D
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