IP4254CZ16-8-TTL,132 - NXP SEMICONDUCTORS

1. General description

CBTL06DP212 is a high performance multi-channel Generation 2 multiplexer meant for

DisplayPort (DP) v1.2, v1.1a or Embe dded DisplayPort a pplications operating at dat a rate

of 1.62 Gbit/s, 2.7 Gbit/s or 5.4 Gbit/s. It is designed using NXP proprietary

high-bandwidth pass-gate technology and it can be used for 1 : 2 switching or 2 : 1

multiplexing of four high- speed dif ferential AC -coupled DP chan nels. Further, it is capable

of switching/multiplexing of Hot Plug Detect (HPD) signal as well as Auxiliary (AUX) and

Display Data Channel (DDC) signals. In order to support GPUs/CPUs that have dedicated

AUX and DDC I/Os, CBTL06DP212 provides an additional level of multiplexing of AUX

and DDC signals delivering true flexibility and choice.

A typical application of CBTL06DP212 is on motherboards where one of two GPU

DisplayPort sources needs to be selected to connect to a DisplayPort sink device or

connector. A controller chip selects which path to use by setting a select signal HIGH or

LOW. Due to the bidirectional nature of th e signal p aths, CBTL06DP212 ca n also be used

in the reverse topology, e.g., to connect one display source device to one of two display

sink devices or connectors.

2. Features and benefits

1 : 2 switching or 2 : 1 multiplexing of DisplayPort (v1.2 - 5.4 Gbit/s) signals

4 high-speed differential channels with 2 : 1 multiplexing/switching for DisplayPort

main link signals

1 channel with 4 : 1 multiplexing/switching for AUX or DDC signals

1 channel with 2 : 1 multiplexing/switching for HPD signal

High-bandwidth: 5 GHz at 3dB

Low insertion loss:

0.5 dB at 100 MHz

3dB at 5GHz

Low crosstalk: 35 dB at 3 GHz

Low off-state isolation: 30 dB at 3 GHz

Low return loss: 8dB at 3GHz

Very low intra-pair skew (5 ps typical)

Very low inter-pair skew (< 80 ps)

Switch/multiplexer position select CMOS input

DDC and AUX ports tolerant to being pulled to +5 V via 2.2 k resistor

Supports HDMI/DVI incorrect dongle connection

Single 3.3 V power supply

Operation current of 2 mA typical

CBTL06DP212

High-performance DisplayPort Gen2 2 : 1 multiplexer

Rev. 2 — 3 November 2011 Product data sheet

Product data sheet Rev. 2 — 3 November 2011 2 of 18

NXP Semiconductors CBTL06DP212

High-performance DisplayPort Gen2 2 : 1 multiplexer

ESD 8 kV HBM, 1 kV CDM

ESD 2 kV HBM, 500 V CDM for control pins

Available in 5 mm 5 mm, 0.5 mm ball pitch TFBGA48 package

3. Applications

Motherboard applications requiring DisplayPort and PCI Express

switching/multiplexing

Docking stations

Notebook computers

Chip sets requiring flexible allocation of PCI Express or DisplayPort I/O pins to board

connectors

4. Ordering information

[1] Total height including solder balls after printed circuit board mounting = 1.15 mm maximum.

5. Marking

[1] Industrial temperature range.

Table 1. Ordering information

Type number Solder process Package

Name Description Version

CBTL06DP212EE Pb-free (SnAgCu

solder compound) TFBGA48 plastic thin fine-pitch ball grid array package;

48 balls; body 5 50.8 mm[1] SOT918-1

Table 2. Package marking

Line Marking Description

A6D212

[1] basic type number

B xxxxxxx diffusion lot number

C ZPGyyww manufacturing code:

Z = diffusion site

P = assembly site

G = lead-free

yy = year code

ww = week code

Product data sheet Rev. 2 — 3 November 2011 3 of 18

NXP Semiconductors CBTL06DP212

High-performance DisplayPort Gen2 2 : 1 multiplexer

6. Functional diagram

Fig 1. Functional diagram

CBTL06DP212

VDD

IN1_n+

OUT_n−

AUX+

AUX−

AUX+ or SCL

OUT_n+

IN1_n−

002aaf878

IN2_n+

IN2_n−

AUX1+ 00

AUX1−

AUX2+

AUX2−

DDC_CLK1

DDC_DAT1

DDC_CLK2

DDC_DAT2

HPD_1

HPD_2

GPU_SEL

DDC_AUX_SEL

TST0

AUX− or SDA

HPDIN

GND

Product data sheet Rev. 2 — 3 November 2011 4 of 18

NXP Semiconductors CBTL06DP212

High-performance DisplayPort Gen2 2 : 1 multiplexer

7. Pinning information

7.1 Pinning

Fig 2. Pi n co nfi gura tio n for TFBG A4 8

Transparent top view

Fig 3. Ball mapping

002aaf879

Transparent top view

CBTL06DP212EE

246891357

ball A1

index area

002aaf943

GPU_SEL VDD IN1_0−IN1_1−IN1_2−IN1_3+ IN1_3−

23456789

BOUT_0−OUT_0+ GND IN1_0+ IN1_1+ IN1_2+ TST0 IN2_0+ IN2_0−

CDDC_AUX

_SEL GND

DOUT_1−OUT_1+ IN2_1+ IN2_1−

EOUT_2−OUT_2+ IN2_2+ IN2_2−

FOUT_3−OUT_3+ IN2_3+ IN2_3−

GGND GND

HAUX−AUX+ HPD_2 GND DDC_CLK2 AUX2+ GND DDC_CLK1 AUX1+

JHPDIN HPD_1 VDD DDC_DAT2 AUX2−DDC_DAT1 AUX1−

Product data sheet Rev. 2 — 3 November 2011 5 of 18

NXP Semiconductors CBTL06DP212

High-performance DisplayPort Gen2 2 : 1 multiplexer

7.2 Pin description

Table 3. Pin description

Symbol Ball Type Description

GPU_SEL A1 3.3 V CMOS

single-ended input Selects between two multiplexer/switch path s. When HIGH, p ath 2

left-side is connected to its corresponding right-side I/O. When

LOW, path 1 left-side is connected to its corresponding right-side

I/O.

DDC_AUX_SEL C2 3.3 V CMOS

single-ended input Selects between DDC and AUX paths. When HIGH, the CLK and

DAT I/Os are connected to their respective DDCOUT terminals.

When LOW, the AUX+ and AUX I/Os are connected to their

respective DDCOUT terminals.

TST0 B7 3.3 V CMOS

single-ended input Test pin for NXP use only. Should be tied to VDD in normal

operation.

IN1_0+ B4 differential I/O Four high-speed differential pairs for DisplayPort or PCI Express

signals, path 1, left-side.

IN1_0A4 differenti a l I/O

IN1_1+ B5 differential I/O

IN1_1A5 differenti a l I/O

IN1_2+ B6 differential I/O

IN1_2A6 differenti a l I/O

IN1_3+ A8 differential I/O

IN1_3A9 differenti a l I/O

IN2_0+ B8 differential I/O Four high-speed differential pairs for DisplayPort or PCI Express

signals, path 2, left-side.

IN2_0B9 differenti a l I/O

IN2_1+ D8 differential I/O

IN2_1D9 differentia l I/ O

IN2_2+ E8 differential I/O

IN2_2E9 differenti a l I/O

IN2_3+ F8 differential I/O

IN2_3F9 d iffer en tial I/O

OUT_0+ B2 differential I/O Four high-speed differential pairs for DisplayPort or PCI Express

signals, right-side.

OUT_0B1 differenti a l I/O

OUT_1+ D2 differential I/O

OUT_1D1 differentia l I/ O

OUT_2+ E2 differential I/O

OUT_2E1 differenti a l I/O

OUT_3+ F2 differential I/O

OUT_3F1 d iffer en tial I/O

AUX1+ H9 differential I/O High-speed differential pair for AUX signals, path 1, left-side.

AUX1J9 differentia l I/ O

AUX2+ H6 differential I/O High-speed differential pair for AUX signals, path 2, left-side.

AUX2J6 differentia l I/ O

DDC_CLK1 H8 differential I/O Pair of single-ended terminals for DDC clock and data signals,

path 1, left-side.

DDC_DAT1 J8 differential I/O

Product data sheet Rev. 2 — 3 November 2011 6 of 18

NXP Semiconductors CBTL06DP212

High-performance DisplayPort Gen2 2 : 1 multiplexer

8. Functional description

Refer to Figure 1 “Functional diagram”.

The CBTL06DP212 uses a 3.3 V power supply. All main signal paths are implemented

using high-band wid th p a ss-gate te chno logy and ar e bidir ectional. No clock or r eset signal

is needed for the multiplexer to function.

The switch position for the main channels is selected using the select signal GPU_SEL.

Additionally, the signal DDC_AUX_SEL selects between AUX and DDC positions for the

DDC / AUX channel. The detailed operation is described in Section 8.1.

8.1 Multiplexer/switch select functions

The internal multiplexer switch position is controlled by two logic inputs GPU_SEL and

DDC_AUX_SEL as de sc rib ed below.

DDC_CLK2 H5 differential I/O Pair of single-ended terminals for DDC clock and data signals,

path 2, left-side.

DDC_DAT2 J5 differential I/O

AUX+ H2 differential I/O High-speed differential pair for AUX or single-ended DDC signals,

right-side.

AUXH1 differentia l I/ O

HPD_1 J2 single-ended I/O Single ended channel fo r the HPD signal, path 1, left-side.

HPD_2 H3 single-e nded I/O Single ended channel for the HPD signal, path 2, left-side.

HPDIN J1 single-ended I/O Single ended chann el for the HPD signal, right-side.

VDD A2, J4 power supply 3.3 V power supply.

GND B3, C8,

G2, G8,

H4, H7

ground Ground.

Table 3. Pin description …continued

Symbol Ball Type Description

Table 4. Multiplexer/switch select control for INn and OUTn channels

GPU_SEL IN1_n IN2_n

0 active; connected to OUT_n high-impedance

1 high-impedance active; connected to OUT_n

Table 5. Multiplexer/switch sele ct con t rol for HPD channel

GPU_SEL HPD_1 HPD_2

0 active; connected to HPDIN high-impedance

1 high-impedance active; connected to HPDIN

Product data sheet Rev. 2 — 3 November 2011 7 of 18

NXP Semiconductors CBTL06DP212

High-performance DisplayPort Gen2 2 : 1 multiplexer

9. Limiting values

[1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model -

Component level; Electrostatic Discharge Association, Rome, NY, USA.

[2] Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device

Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.

10. Recommended operating conditions

[1] HPD input is tolerant to 5 V input, provided a 1 k series resistor between the voltage source and the pin is

placed in series. See Section 12.1 “Special considerations”.

[2] DDC/AUX inputs are tolerant to 5 V input, provided a 2.2 k series resistor between the voltage source and

the pin is placed in series. See Section 12.1 “Special considerations”.

Table 6. Multiplexer/switch select control for DDC and AUX channels

DDC_AUX_SEL GPU_SEL AUX1 AUX2 DDC_CLK1,

DDC_DAT1 DDC_CLK2,

DDC_DAT2

0 0 active;

connected to AUX high-impedance high-impedance high-impedance

0 1 high-impedance active;

connected to AUX high-impedance high-impedance

1 0 high-impedance high-impedance active;

connected to AUX high-impedance

1 1 high-impedance high-impedance high-impedance active;

connected to AUX

Table 7. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.3 +5 V

Tcase case temperature 40 +85 C

VESD electrostatic discharge

voltage HBM [1] - 8000 V

HBM; CMOS inputs [1] - 2000 V

CDM [2] - 1000 V

CDM; CMOS inputs [2] 500 V

Table 8. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3.0 3.3 3.6 V

VIinput voltage CMOS inputs 0.3 - VDD +0.3 V

HPD inputs [1] 0.3 - VDD +0.3 V

DDC/AUX inputs [2] 0.3 - VDD +0.3 V

other inputs 0.3 - +2.6 V

Tamb ambient temperature operating in free air 40 - +85 C

Product data sheet Rev. 2 — 3 November 2011 8 of 18

NXP Semiconductors CBTL06DP212

High-performance DisplayPort Gen2 2 : 1 multiplexer

11. Characteristics

11.1 General characteristics

11.2 DisplayPort channel characteristics

Table 9. General characteristics

Symbol Parameter Conditions Min Typ Max Unit

IDD supply current VDD =3.3V - 23mA

Pcons power consumption VDD =3.3V --10mW

tstartup start-up time supply voltage valid to channel specified

operating characteristics --10s

trcfg reconfiguration time GPU_SEL or DDC_AUX_SEL state change

to channel specified operating characteristics --1s

Table 10. DisplayPort channel characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIinput voltage 0.3 - +2.6 V

VIC common-mode input voltage 0 - 2.0 V

VID differential input voltage peak-to-peak - - +1.2 V

Ron ON-state resistance VDD =3.3V; V

I=2V; I

I=20mA - 6.5 - 

DDIL differential insertion loss channel is ON; f 100 MHz - 0.5 - dB

channel is ON; f = 3.0 GHz - 2.5 - dB

channel is OFF; f 3.0 GHz - 30 - dB

DDRL differential return loss f = 100 MHz - 25 - dB

f=3.0GHz - 8- dB

DDNEXT differential near-end crosstalk adjacent channels are ON

f = 100 MHz - 65 - dB

f=3.0GHz - 35 - dB

B bandwidth 3.0 dB intercept - 5 - GHz

tPD propagation delay from left-side port to right-side port

or vice versa -80-ps

tsk(dif) differential skew time intra-pair - 5 - ps

tsk skew time inter-pair - - 80 ps

Product data sheet Rev. 2 — 3 November 2011 9 of 18

NXP Semiconductors CBTL06DP212

High-performance DisplayPort Gen2 2 : 1 multiplexer

11.3 AUX and DDC ports

[1] Time from DDC/AUX input changing state to AUX output changing state. Includes DDC/AUX rise/fall time.

11.4 HPDIN input, HPD_x outputs

[1] Time from HPDIN changing state to HPD_x changing state. Includes HPD rise/fall time.

11.5 GPU_SEL and DDC_AUX_SEL inputs

Table 11. AUX and DDC port characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIinput voltage 0.3 - VDD +0.3 V

VOoutput voltage no load - - VDD V

VIC common-mode input voltage AUX 0 - 2.0 V

VID differential input voltage AUX - - +1.4 V

tPD propagation delay from left-side port to right-side

port or vice versa [1] -80- ps

Table 12. HPD input and output characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIinput voltage 0.3 - VDD +0.3 V

VOoutput voltage no load - - VDD V

tPD propagation delay from HPDIN to HPD_x or vice versa [1] -80- ps

Table 13. GPU_SEL and DDC_AUX_SEL input characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIH HIGH-level input voltage 2.0 - - V

VIL LOW-level input voltage - - 0.8 V

ILI input leakage current VDD =3.6V; 0.3VVI3.9 V - - 10 A

Product data sheet Rev. 2 — 3 November 2011 10 of 18

NXP Semiconductors CBTL06DP212

High-performance DisplayPort Gen2 2 : 1 multiplexer

12. Application information

12.1 Special considerations

Certain cable or dongle misplug scenarios make it possible for a 5 V input condition to

occur on pins AUX+ and AUX, as well as HPDIN. When AUX+ and AUX are connected

through a minimum of 2.2 k each, the CBTL06DP212 will sink current but will not be

damaged. Similarly, HPDIN may be connected to 5 V via at least a 1 k resistor. (Correct

functional operation to specification is not expected in these scenarios.) The latter also

prevents the HPDIN input from loading down the system HPD signal when power to the

CBTL06DP212 is off.

Fig 4. Application di agram

OUT_n−

HPDIN

OUT_n+

002aaf944

2 : 1

MUX

AUX−

AUX+

4 : 1

MUX

2 : 1

MUX

DDC_AUX_SEL

GPU_SEL

CBTL06DP212

DP CONNECTOR

IN1_n−

IN1_n+

GPU2_DP++ SOURCE

IN2_n−

IN2_n+

AUX1−

AUX1+

GND

100 kΩ

AUX2−

AUX2+

GND

100 kΩ

GPU1_DP++ SOURCE

+3.3 V

DDC_DAT1

DDC_CLK1

2 kΩ

DDC_DAT2

DDC_CLK2

HPD_1

HPD_2

Product data sheet Rev. 2 — 3 November 2011 11 of 18

NXP Semiconductors CBTL06DP212

High-performance DisplayPort Gen2 2 : 1 multiplexer

13. Package outline

Fig 5. Package outline TFBGA48 (SOT918-1)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT918-1 MO-195- - - - - -

SOT918-1

05-09-21

05-10-13

UNIT A

max

mm 1.15 0.25

0.15 0.90

0.75 0.35

0.25 5.1

4.9 5.1

4.9

DIMENSIONS (mm are the original dimensions)

TFBGA48: plastic thin fine-pitch ball grid array package; 48 balls; body 5 x 5 x 0.8 mm

A2b D E e2

0.5

0.15

0.05

0.08

0.1

0 2.5 5 mm

scale

ball A1

index area

246813579

AC B

∅ vMC∅ wM

ball A1

index area

B A

detail X

Product data sheet Rev. 2 — 3 November 2011 12 of 18

NXP Semiconductors CBTL06DP212

High-performance DisplayPort Gen2 2 : 1 multiplexer

14. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

14.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

14.2 Wave and reflow soldering

W ave soldering is a joinin g technology in which the joint s are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circui t board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

14.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 2 — 3 November 2011 13 of 18

NXP Semiconductors CBTL06DP212

High-performance DisplayPort Gen2 2 : 1 multiplexer

14.4 Reflow soldering

Key characteristics in reflow soldering are:

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 6) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 14 and 15

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 6.

Table 14. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350  350

< 2.5 235 220

 2.5 220 220

Table 15. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 2 — 3 November 2011 14 of 18

NXP Semiconductors CBTL06DP212

High-performance DisplayPort Gen2 2 : 1 multiplexer

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

15. Abbreviations

MSL: Moisture Sensitivity Level

Fig 6. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 16. Abbreviations

Acronym Description

AUX Auxiliary channel (in DisplayPort defini tio n)

CDM Charged-Device Model

CMOS Complementary Metal-Oxide Semiconductor

CPU Central Processing Unit

DP DisplayPort

DVI Digital Video Interface

ESD ElectroStatic Discharge

GPU Graphics Processor Unit

HBM Human Body Model

HDMI High-Definition Multimedia Interface

I/O Input/Output

PCI Peripheral Component Interconnect

Product data sheet Rev. 2 — 3 November 2011 15 of 18

NXP Semiconductors CBTL06DP212

High-performance DisplayPort Gen2 2 : 1 multiplexer

16. Revision history

Table 17. Revision history

Document ID Release date Data sheet status Change notice Supersedes

CBTL06DP212 v.2 20111103 Product data sheet - CBTL06DP212 v. 1

Modifications: •Table 2 “Package marking”: Line A marking corrected from “6DP212” to “6D212”

CBTL06DP212 v.1 20110221 Product data sheet - -

Product data sheet Rev. 2 — 3 November 2011 16 of 18

NXP Semiconductors CBTL06DP212

High-performance DisplayPort Gen2 2 : 1 multiplexer

17. Legal information

17.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

17.2 Definitions

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full information. For detailed and full informatio n see the relevant full data

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data sheet shall define the specification of the product as agr eed between

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deemed to off er functions and qualities beyond those described in the

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customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with t heir

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessa ry

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by cust omer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by cust omer.

No offer to sell or license — Not hing in this document may be interpret ed or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyri ghts, paten ts or

other industrial or intellectual property right s.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from competent authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objecti ve specification for product development .

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 2 — 3 November 2011 17 of 18

NXP Semiconductors CBTL06DP212

High-performance DisplayPort Gen2 2 : 1 multiplexer

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for aut omo tive use. It i s neit her qua lif ied nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applicati ons.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever cust omer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive appl ications beyond NXP Semi conductors’

standard warrant y and NXP Semiconductors’ product specifications.

17.4 Licenses

17.5 Trademarks

Notice: All refe renced brands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Purchase of NXP ICs with HDMI technology

Use of an NXP IC with HDMI technology in equipment that co mplies with

the HDMI standard re quires a license from HDMI Licensing LLC, 1060 E.

Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail:

admin@hdmi.org.

NXP Semiconductors CBTL06DP212

High-performance DisplayPort Gen2 2 : 1 multiplexer

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 3 November 2011

Document identifier: CBTL06DP212

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

19. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Functional description . . . . . . . . . . . . . . . . . . . 6

8.1 Multiplexer/switch select functions . . . . . . . . . . 6

9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7

10 Recommended operating conditions. . . . . . . . 7

11 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 8

11.1 General characteristics. . . . . . . . . . . . . . . . . . . 8

11.2 DisplayPort channel characteristics . . . . . . . . . 8

11.3 AUX and DDC ports . . . . . . . . . . . . . . . . . . . . . 9

11.4 HPDIN input, HPD_x outputs . . . . . . . . . . . . . . 9

11.5 GPU_SEL and DDC_AUX_SEL inputs. . . . . . . 9

12 Application information. . . . . . . . . . . . . . . . . . 10

12.1 Special considerations . . . . . . . . . . . . . . . . . . 10

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11

14 Soldering of SMD packages . . . . . . . . . . . . . . 12

14.1 Introduction to soldering . . . . . . . . . . . . . . . . . 12

14.2 Wave and reflow soldering . . . . . . . . . . . . . . . 12

14.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 12

14.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 13

15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14

16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15

17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16

17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16

17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

17.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

17.4 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

17.5 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

18 Contact information. . . . . . . . . . . . . . . . . . . . . 17

19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18