TIBPAL16L8-25C, TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16L8-30M, TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS059A − FEBRUARY 1984 − REVISED DECEMBER 2010
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DHigh-Performance Operation:
Propagation Delay
C Suffix . . . 25 ns Max
M Suffix...30 ns Max
DFunctionally Equivalent, but Faster Than
PAL16L8A, PAL16R4A, PAL16R6A, and
PAL16R8A
DPower-Up Clear on Registered Devices (All
Register Outputs Are Set High, but Voltage
Levels at the Output Pins Go Low)
DPackage Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
DDependable Texas Instruments Quality and
Reliability
DEVICE I
INPUTS
3-STATE
O
OUTPUTS
REGISTERED
Q
OUTPUTS
I/O
PORTS
PAL16L8 10 2 0 6
PAL16R4 8 0 4 (3-state
buffers) 4
PAL16R6 8 0 6 (3-state
buffers) 2
PAL16R8 8 0 8 (3-state
buffers) 0
description
These programmable array logic devices feature
high speed and functional equivalency when
compared with currently available devices. These
IMPACT™ circuits combine the latest Advanced
Low-Power Schottky technology with proven
titanium-tungsten fuses to provide reliable,
high-performance substitutes for conventional
TTL logic. Their easy programmability allows for
quick design of custom functions and typically
results in a more compact circuit board. In
addition, chip carriers are available for further
reduction in board space.
The TIBPAL16’ C series is characterized from 0°C
to 75°C. The TIBPAL16’ M series is characterized
for operation over the full military temperature
range of −55°C to 125°C.
Copyright © 2010, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
IMPACT is a trademark of Texas Instruments.
PAL is a registered trademark of Advanced Micro Devices Inc.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
I
I
I
I
I
I
I
I
I
GND
VCC
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
TIBPAL16L8’
C SUFFIX ...J OR N PACKAGE
M SUFFIX ...J OR W PACKAGE
(TOP VIEW)
4
5
6
7
8
18
17
16
15
14
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
TIBPAL16L8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
I
I
I
O
I/O O
I
GND
I
VCC
3212019
910111213
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLK
I
I
I
I
I
I
I
I
GND
VCC
I/O
I/O
Q
Q
Q
Q
I/O
I/O
OE
TIBPAL16R4’
C SUFFIX ...J OR N PACKAGE
M SUFFIX ...J OR W PACKAGE
(TOP VIEW)
CLK
I
I
I
I
I
I
I
I
GND
VCC
I/O
Q
Q
Q
Q
Q
Q
I/O
OE
TIBPAL16R6’
C SUFFIX ...J OR N PACKAGE
M SUFFIX ...J OR W PACKAGE
(TOP VIEW)
CLK
I
I
I
I
I
I
I
I
GND
VCC
Q
Q
Q
Q
Q
Q
Q
Q
OE
TIBPAL16R8’
C SUFFIX ...J OR N PACKAGE
M SUFFIX ...J OR W PACKAGE
(TOP VIEW)
I
I
CLK
I/O
I/O I/O
I
GND
VCC
OE
I/O
Q
Q
Q
Q
I
I
I
I
I
TIBPAL16R4’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
I
I
CLK
I/O
QI/O
I
GND
VCC
Q
Q
Q
Q
Q
I
I
I
I
I
OE
TIBPAL16R6’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
I
I
CLK
Q
QQ
I
GND
VCC
OE
Q
Q
Q
Q
Q
I
I
I
I
I
TIBPAL16R8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
4
5
6
7
8
18
17
16
15
14
3212019
910111213
4
5
6
7
8
18
17
16
15
14
3212019
910111213
4
5
6
7
8
18
17
16
15
14
3212019
910111213
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagrams (positive logic)
denotes fused inputs
TIBPAL16L8’
TIBPAL16R4’
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I
EN ≥1
&
32 × 64
10 16
166
7
7
7
7
7
7
7
7
6
Q
I/O
I/O
I/O
I/O
I
EN
816
164
7
7
7
8
8
8
7
4
≥1
≥1
8
Q
Q
Q
4
1D
I = 1 2
CLK C1
EN 2
OE
4
16 ×
16 ×
&
32 × 64
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagrams (positive logic)
denotes fused inputs
TIBPAL16R6’
TIBPAL16R8’
Q
I/O
I/O
I
EN
816
162
7
8
8
8
7
2
≥1
≥1
8
Q
Q
Q
6
1D
I = 1 2
CLK C1
EN 2
OE
6
8Q
8Q
Q
I816
168
8
8
8
8
8
Q
Q
Q
1D
I = 1 2
CLK C1
EN 2
8Q
8Q
≥1
OE
8Q
8Q
16 ×
16 ×
&
32 × 64
&
32 × 64
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
0 4 8 12 16 20 24 28 31
I2
I3
4
I5
I6
I7
I8
I9
O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
O
12
I
11
Increment
I1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
First
Fuse
Numbers
I
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
2016
0 4 8 12 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
I/O
19
I/O
18
Q
17
Q
16
Q
15
Q
14
I/O
13
I/O
12
11
Increment
CLK 1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
First
Fuse
Numbers
C1
1D
I = 1
C1
1D
I = 1
C1
1D
I = 1
C1
1D
I = 1
OE
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
Fuse number = First fuse number + Increment
0 4 8 12 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
I/O
19
Q
17
Q
16
Q
15
Q
14
I/O
12
11
Increment
CLK 1
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
First
Fuse
Numbers
C1
1D
I = 1
C1
1D
I = 1
C1
1D
I = 1
C1
1D
I = 1
OE
Q
18
C1
1D
I = 1
Q
13
C1
1D
I = 1
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
0 4 8 12 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
Q
17
Q
16
Q
15
Q
14
Increment
CLK 1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
First
Fuse
Numbers
C1
1D
I = 1
C1
1D
I = 1
C1
1D
I = 1
C1
1D
I = 1
OE
Q
18
C1
1D
I = 1
Q
13
C1
1D
I = 1
Q
19
C1
1D
I = 1
Q
12
C1
1D
I = 1
11
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 0°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: These ratings apply, except for programming pins, during a programming cycle.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
VIH High-level input voltage 2 5.5 V
VIL Low-level input voltage 0.8 V
IOH High-level output current −3.2 mA
IOL Low-level output current 24 mA
fclock Clock frequency 0 30 MHz
t
Pulse duration clock (see Note 2)
High 10
ns
twPulse duration, clock (see Note 2) Low 15 ns
tsu Setup time, input or feedback before clock↑20 ns
thHold time, input or feedback after clock↑0 ns
TAOperating free-air temperature 0 25 75 °C
NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, fclock. The minimum pulse durations specified are
for clock high or low only, but not for both simultaneously.
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 4.75 V, II = −18 mA −1.5 V
VOH VCC = 4.75 V, IOH = −3.2 mA 2.4 3.3 V
VOL VCC = 4.75 V, IOL = 24 mA 0.35 0.5 V
I
Outputs
V 5 25 V
V 27 V
20
A
IOZH I/O ports VCC = 5.25 V, VO = 2.7 V 100 μA
I
Outputs
V 5 25 V
V 04 V
−20
A
IOZL I/O ports VCC = 5.25 V, VO = 0.4 V −250 μA
IIVCC = 5.25 V, VI = 5.5 V 0.1 mA
IIH VCC = 5.25 V, VI = 2.7 V 20 μA
IIL VCC = 5.25 V, VI = 0.4 V −0.25 mA
IO‡VCC = 5.25 V, VO = 2.25 V −30 −125 mA
ICC VCC = 5.25 V, VI = 0, Outputs open 75 100 mA
†All typical values are at VCC = 5 V, TA = 25°C.
‡The output conditions have been chosen to produce a current that closely approximates one-half of the short-circuit output current, IOS.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER FROM
(INPUT)
TO
(OUTPUT) TEST CONDITIONS MIN TYP†MAX UNIT
fmax 30 MHz
tpd I, I/O O, I/O 15 25 ns
tpd CLK↑Q
R1
=
500 Ω,
10 15 ns
ten OE↓Q
R1
=
500 Ω
,
R2 = 500 Ω, 15 20 ns
tdis OE↑Q
R2 500 Ω,
See Figure 3 10 20 ns
ten I, I/O O, I/O 14 25 ns
tdis I, I/O O, I/O 13 25 ns
†All typical values are at VCC = 5 V, TA = 25°C.
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: These ratings apply, except for programming pins, during a programming cycle.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 5.5 V
VIL Low-level input voltage 0.8 V
IOH High-level output current −2 mA
IOL Low-level output current 12 mA
fclock Clock frequency 0 25 MHz
t
Pulse duration clock (see Note 2)
High 15
ns
twPulse duration, clock (see Note 2) Low 20 ns
tsu Setup time, input or feedback before clock↑25 ns
thHold time, input or feedback after clock↑0 ns
TAOperating free-air temperature −55 25 125 °C
NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, fclock. The minimum pulse durations specified are
for clock high or low only, but not for both simultaneously.
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 4.5 V, II = −18 mA −1.5 V
VOH VCC = 4.5 V, IOH = −2 mA 2.4 3.2 V
VOL VCC = 4.5 V, IOL = 12 mA 0.25 0.4 V
I
Outputs
V 55 V
V 27 V
20
A
IOZH I/O ports VCC = 5.5 V VO = 2.7 V 100 μA
I
Outputs
V 55 V
V 04 V
−20
A
IOZL I/O ports VCC = 5.5 V, VO = 0.4 V −250 μA
I
Pin 1, 11
V 55 V
V 55 V
0.2
mA
IIAll others VCC = 5.5 V, VI = 5.5 V 0.1 mA
Pin 1, 11 50
IIH I/O ports VCC = 5.5 V, VI = 2.7 V 100 μA
IIH
All others
VCC 5.5 V,
VI 2.7 V
20
μA
I
I/O ports
V 55 V
V 04 V
−0.25
mA
IIL All others VCC = 5.5 V, VI = 0.4 V −0.2 mA
IOS‡VCC = 5.5 V, VO = 0.5 V −30 −250 mA
ICC VCC = 5.5 V, VI = 0, Outputs open 75 105 mA
†All typical values are at VCC = 5 V, TA = 25°C.
‡Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. Set VO at 0.5 V to
avoid test-equipment degradation.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER FROM
(INPUT)
TO
(OUTPUT) TEST CONDITIONS MIN TYP†MAX UNIT
fmax 25 MHz
tpd I, I/O O, I/O 15 30 ns
tpd CLK↑Q
R1
=
390 Ω,
10 20 ns
ten OE↓Q
R1
=
390 Ω
,
R2 = 750 Ω, 15 25 ns
tdis OE↑Q
R2 750 Ω,
See Figure 4 10 25 ns
ten I, I/O O, I/O 14 30 ns
tdis I, I/O O, I/O 13 30 ns
†All typical values are at VCC = 5 V, TA = 25°C.
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic also is available, upon request, from the nearest TI field sales office or local authorized TI
distributor, by calling Texas Instruments at +1 (972) 644−5580, or by visiting the TI Semiconductor Home Page
at www.ti.com/sc.
preload procedure for registered outputs (see Figure 1 and Note 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below.
Step 1. With VCC at 5 V and Pin 1 at VIL, raise Pin 11 to VIHH.
Step 2. Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Step 3. Pulse Pin 1, clocking in preload data.
Step 4. Remove output voltage, then lower Pin 11 to VIL. Preload can be verified by observing the
voltage level at the output pin.
td
tsu
tw
td
VIHH
VIL
VIL
VOL
VOH
VIH
Pin 11
Pin 1
Registered I/O Input Output
VIH
VIL
NOTE 3: td = tsu = th = 100 ns to 1000 ns VIHH = 10.25 V to 10.75 V
Figure 1. Preload Waveforms
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
power-up reset (see Figure 2)
Following power up, all registers are set high. This feature provides extra flexibility to the system designer and
is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is important
that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not occur until
all applicable input and feedback setup times are met.
1.5 V
tsu‡
tpd†
tw
VIL
VIH
5 V
VCC
Active-Low
Registered Output
CLK
4 V
VOH
VOL
1.5 V
(600 ns TYP, 1000 ns MAX)
1.5 V
†This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
‡This is the setup time for input or feedback.
Figure 2. Power-Up Reset Waveforms
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
tdis
tdis
tsu
S1
From Output
Under Test
Test
Point
R2
CL
(see Note A)
LOAD CIRCUIT FOR 3-STATE OUTPUTS
th
Timing
Input
Data
Input
Input
In-Phase
Output
Out-of-Phase
Output
(see Note D)
tpd
tpd
tpd
tpd
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOH
VOH
VOL
VOL
tw
High-Level
Pulse
Low-Level
Pulse
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
3.5 V
0.3 V
≈3.5 V
VOL
VOH
VOH − 0.3 V
≈0 V
ten
ten
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATIONS
R1
3.5 V
0.3 V
VOL + 0.3 V
7 V
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤1 MHz, tr = tf ≤ 2 ns, duty cycle = 50%
D. When measuring propagation delay times of 3-state outputs from low to high, switch S1 is closed.
When measuring propagation delay times of 3-state outputs from high to low, switch S1 is open.
E. Equivalent loads may be used for testing.
1.3 V
1.3 V 1.3 V
3.5 V
0.3 V
3.5 V
0.3 V
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
3.5 V
0.3 V
3.5 V
0.3 V
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
1.3 V
Figure 3. Load Circuit and Voltage Waveforms
TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C
TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M
LOW-POWER HIGH-PERFORMANCE IMPACT™PAL® CIRCUITS
SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
tdis
tdis
tsu
S1
From Output
Under Test
Test
Point
R2
CL
(see Note A)
LOAD CIRCUIT FOR 3-STATE OUTPUTS
th
Timing
Input
Data
Input
Input
In-Phase
Output
Out-of-Phase
Output
(see Note D)
tpd
tpd
tpd
tpd
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOH
VOH
VOL
VOL
tw
High-Level
Pulse
Low-Level
Pulse
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
3 V
0
≈3.3 V
VOL
VOH
VOH − 0.5 V
≈0 V
ten
ten
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATIONS
R1
3 V
0
VOL + 0.5 V
5 V
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤10 MHz, tr = tf ≤ 2 ns, duty cycle = 50%
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
1.5 V
1.5 V 1.5 V
3 V
0
3 V
0
1.5 V 1.5 V
1.5 V 1.5 V
3 V
0
3 V
0
1.5 V 1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
Figure 4. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-85155052A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
85155052A
TIBPAL16
L8-30MFKB
5962-8515505RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8515505RA
TIBPAL16L8-30M
JB
5962-8515505SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8515505SA
TIBPAL16L8-30M
WB
5962-85155062A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
85155062A
TIBPAL16
R8-30MFKB
5962-8515506RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8515506RA
TIBPAL16R8-30M
JB
5962-8515506SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8515506SA
TIBPAL16R8-30M
WB
5962-85155072A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
85155072A
TIBPAL16
R6-30MFKB
5962-8515507RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8515507RA
TIBPAL16R6-30M
JB
5962-8515507SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8515507SA
TIBPAL16R6-30M
WB
5962-85155082A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
85155082A
TIBPAL16
R4-30MFKB
5962-8515508RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8515508RA
TIBPAL16R4-30M
JB
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-8515508SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8515508SA
TIBPAL16R4-30M
WB
JM38510/50605BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
50605BRA
JM38510/50606BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
50606BRA
JM38510/50607BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
50607BRA
JM38510/50608BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
50608BRA
M38510/50605BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
50605BRA
M38510/50606BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
50606BRA
M38510/50607BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
50607BRA
M38510/50608BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
50608BRA
TIBPAL16L8-25CFN ACTIVE PLCC FN 20 46 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-245C-168 HR 0 to 75 16L8-25
TIBPAL16L8-25CJ OBSOLETE CDIP J 20 TBD Call TI Call TI
TIBPAL16L8-25CN ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 75 TIBPAL16L8-25C
N
TIBPAL16L8-30MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
85155052A
TIBPAL16
L8-30MFKB
TIBPAL16L8-30MJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 TIBPAL16L8-30M
J
TIBPAL16L8-30MJB ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8515505RA
TIBPAL16L8-30M
JB
TIBPAL16L8-30MWB ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8515505SA
TIBPAL16L8-30M
WB
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TIBPAL16R4-25CFN ACTIVE PLCC FN 20 46 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-245C-168 HR 0 to 75 16R4-25
TIBPAL16R4-25CJ OBSOLETE CDIP J 20 TBD Call TI Call TI
TIBPAL16R4-25CN ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 75 TIBPAL16R4-25C
N
TIBPAL16R4-30MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
85155082A
TIBPAL16
R4-30MFKB
TIBPAL16R4-30MJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 TIBPAL16R4-30M
J
TIBPAL16R4-30MJB ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8515508RA
TIBPAL16R4-30M
JB
TIBPAL16R4-30MWB ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8515508SA
TIBPAL16R4-30M
WB
TIBPAL16R6-25CFN ACTIVE PLCC FN 20 46 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-245C-168 HR 0 to 75 16R6-25
TIBPAL16R6-25CN ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 75 TIBPAL16R6-25C
N
TIBPAL16R6-30MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
85155072A
TIBPAL16
R6-30MFKB
TIBPAL16R6-30MJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 TIBPAL16R6-30M
J
TIBPAL16R6-30MJB ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8515507RA
TIBPAL16R6-30M
JB
TIBPAL16R6-30MWB ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8515507SA
TIBPAL16R6-30M
WB
TIBPAL16R8-25CFN ACTIVE PLCC FN 20 46 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-245C-168 HR 0 to 75 16R8-25
TIBPAL16R8-25CN ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 75 TIBPAL16R8-25C
N
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 4
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TIBPAL16R8-30MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
85155062A
TIBPAL16
R8-30MFKB
TIBPAL16R8-30MJB ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8515506RA
TIBPAL16R8-30M
JB
TIBPAL16R8-30MWB ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8515506SA
TIBPAL16R8-30M
WB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 5
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.