6 GHz to 18 GHz, Front-End IC ADTR1107 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM Operates from 6 GHz to 18 GHz 25 dBm typical transmit state PSAT 22 dB typical transmit state small signal gain 18 dB typical receive state small signal gain 2.5 dB typical receive state noise figure Coupled power amplifier output for power detection VDD_LNA VGG_LNA VSS_SW CTRL_SW VDD_SW RX_OUT ADTR1107 ANT TX_IN Phased array antenna Military radar Weather radar Communication links Electronic warfare VGG_PA VDD_PA CPLR_OUT 22146-001 APPLICATIONS Figure 1. GENERAL DESCRIPTION The ADTR1107 is a compact, 6 GHz to 18 GHz, front-end IC with an integrated power amplifier, low noise amplifier (LNA), and a reflective single-pole double-throw (SPDT) switch. These integrated features make the device ideal for phased array antenna and radar applications. The front-end IC offers 25 dBm of saturated output power (PSAT) and 22 dB small signal gain in Rev. A transmit state, and 18 dB small signal gain and 2.5 dB noise figure in receive state. The device has a directional coupler for power detection. The input/outputs (I/Os) are internally matched to 50 . The ADTR1107 is supplied in a 5 mm x 5 mm, 24-terminal, land grid array (LGA) package. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADTR1107 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Transmit State................................................................................9 Applications ...................................................................................... 1 Receive State................................................................................ 16 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 23 General Description ......................................................................... 1 Applications Information ............................................................. 24 Revision History ............................................................................... 2 Recommended Bias Sequencing .............................................. 24 Specifications .................................................................................... 3 Typical Application Circuit ...................................................... 25 Absolute Maximum Ratings ........................................................... 6 Thermal Resistance ...................................................................... 6 Interfacing the ADTR1107 to the ADAR1000 X Band and KU Band Beamformer............................................................................ 26 ESD Caution.................................................................................. 6 Outline Dimensions ....................................................................... 28 Pin Configuration and Function Descriptions ............................ 7 Ordering Guide .......................................................................... 28 Interface Schematics .................................................................... 8 Typical Performance Characteristics ............................................. 9 REVISION HISTORY 4/2020--Rev. 0 to Rev. A Changes to VDD_LNA Parameter, Table 4 ................................. 5 1/2020--Revision 0: Initial Version Rev. A | Page 2 of 28 Data Sheet ADTR1107 SPECIFICATIONS Transmit state, VDD_PA = 5 V, IDQ_PA = 220 mA, VDD_SW = 3.3 V, VSS_SW = -3.3 V, CTRL_SW = 0 V, receive state off (VDD_LNA = 0 V, VGG_LNA = 0 V), TA = 25C, unless otherwise noted. Table 1. Parameter OVERALL FUNCTION Frequency Range Symbol Min Typ 6 TRANSMIT STATE Small Signal Gain 19.5 Gain Flatness Input Return Loss Output Return Loss Output 1 dB Compression (OP1dB) Saturated Output Power (PSAT) Output Third-Order Intercept (OIP3) Noise Figure Coupling Factor Isolation TX_IN to RX_OUT ANT to RX_OUT RF Settling Time 0.1 dB 0.05 dB Switching Speed Rise and Fall Time Turn On and Turn Off Time VDD_PA Quiescent Current (IDQ_PA) 21 tRISE, tFALL tON, tOFF 3.3 Max Unit 14 GHz Test Conditions/Comments 21.5 dB 0.8 13 15 23 25 31 9 23.5 dB dB dB dBm dBm dBm dB dB TX_IN to ANT output power (POUT) per tone = 8 dBm TX_IN to ANT Coupling factor = ANT POUT - CPLR_OUT POUT 40 64 dB dB Receive state off Receive state off 17 ns 50% CTRL_SW to 0.1 dB of final RF output 22 ns 50% CTRL_SW to 0.05 dB of final RF output 2 10 5.0 220 ns ns V mA 10% to 90% of RF output 50% CTRL_SW to 90% of RF output 5.5 TX_IN to ANT TX_IN to ANT TX_IN to ANT TX_IN to ANT Adjust VGG_PA voltage between -1.75 V and -0.25 V to achieve the desired IDQ_PA Transmit state, VDD_PA = 5 V, IDQ_PA = 220 mA, VDD_SW = 3.3 V, VSS_SW = -3.3 V, CTRL_SW = 0 V, receive state off, TA = 25C, unless otherwise noted. Table 2. Parameter OVERALL FUNCTION Frequency Range TRANSMIT STATE Small Signal Gain Gain Flatness Input Return Loss Output Return Loss OP1dB PSAT OIP3 Noise Figure Coupling Factor Isolation TX_IN to RX_OUT ANT to RX_OUT Symbol Min Typ 14 20 19 Max Unit 18 GHz Test Conditions/Comments 22 0.6 12 11 21.5 24 31.5 6.5 18 dB dB dB dB dBm dBm dBm dB dB TX_IN to ANT TX_IN to ANT TX_IN to ANT TX_IN to ANT TX_IN to ANT POUT per tone = 8 dBm TX_IN to ANT Coupling factor = ANT POUT - CPLR_OUT POUT 39 64 dB dB Receive state off Receive state off Rev. A | Page 3 of 28 TX_IN to ANT ADTR1107 Parameter RF Settling Time 0.1 dB 0.05 dB Switching Speed Rise and Fall Time Turn On and Turn Off Time VDD_PA IDQ_PA Data Sheet Symbol Min Typ tRISE, tFALL tON, tOFF 3.3 Max Unit Test Conditions/Comments 17 22 ns ns 50% CTRL_SW to 0.1 dB of final RF output 50% CTRL_SW to 0.05 dB of final RF output 2 10 5.0 220 ns ns V mA 10% to 90% of RF output 50% CTRL_SW to 90% of RF output 5.5 Adjust VGG_PA voltage between -1.75 V and -0.25 V to achieve the desired IDQ_PA Receive state, self biased, VDD_LNA = 3.3 V, VGG_LNA = 0 V, VDD_SW = 3.3 V, VSS_SW = -3.3 V, CTRL_SW = 3.3 V, transmit state off (VDD_PA = 0 V, VGG_PA = -1.75 V), TA = 25C, unless otherwise noted. Table 3. Parameter OVERALL FUNCTION Frequency Range RECEIVE STATE Small Signal Gain Gain Flatness Input Return Loss Output Return Loss OP1dB PSAT OIP3 Noise Figure Isolation ANT to TX_IN RX_OUT to TX_IN RF Settling Time 0.1 dB 0.05 dB Switching Speed Rise and Fall Time Turn On and Turn Off Time VDD_LNA IDQ_LNA Symbol Min Typ 6 15.5 12 tRISE, tFALL tON, tOFF 2.0 Max Unit 14 GHz Test Conditions/Comments 17.5 0.6 13 14 14 16 26 2.5 dB dB dB dB dBm dBm dBm dB ANT to RX_OUT 32 48 dB dB Transmit state off Transmit state off 17 22 ns ns 50% CTRL_SW to 0.1 dB of final RF output 50% CTRL_SW to 0.05 dB of final RF output 2 10 3.3 80 ns ns V mA 10% to 90% of RF output 50% CTRL_SW to 90% of RF output 3.6 ANT to RX_OUT ANT to RX_OUT ANT to RX_OUT ANT to RX_OUT POUT per tone = 0 dBm ANT to RX_OUT Self biased Receive state, self biased, VDD_LNA = 3.3 V, VGG_LNA = 0 V, VDD_SW = 3.3 V, VSS_SW = -3.3 V, CTRL_SW = 3.3 V, transmit state off, TA = 25C, unless otherwise noted. Table 4. Parameter OVERALL FUNCTION Frequency Range RECEIVE STATE Small Signal Gain Gain Flatness Input Return Loss Output Return Loss OP1dB PSAT Symbol Min Typ 14 16 12 18 0.9 13 18 14 16.5 Max Unit 18 GHz dB dB dB dB dBm dBm Rev. A | Page 4 of 28 Test Conditions/Comments ANT to RX_OUT ANT to RX_OUT ANT to RX_OUT ANT to RX_OUT ANT to RX_OUT Data Sheet Parameter OIP3 Noise Figure Isolation ANT to TX_IN RX_OUT to TX_IN RF Settling Time 0.1 dB 0.05 dB Switching Speed Rise and Fall Time Turn On and Turn Off Time VDD_LNA IDQ_LNA ADTR1107 Symbol Min tRISE, tFALL tON, tOFF 2.0 Typ 25.5 3 Max Unit dBm dB Test Conditions/Comments ANT to RX_OUT POUT per tone = 0 dBm ANT to RX_OUT 26 46 dB dB Transmit state off Transmit state off 17 22 ns ns 50% CTRL_SW to 0.1 dB of final RF output 50% CTRL_SW to 0.05 dB of final RF output 2 10 3.3 80 ns ns V mA 10% to 90% of RF output 50% CTRL_SW to 90% of RF output 3.6 Self biased SPDT switch bias at VDD_SW = 3.3 V, VSS_SW = -3.3 V. Table 5. Parameter SUPPLY CURRENT Positive Negative DIGITAL CONTROL INPUTS Voltage Low High Current (Low and High) Symbol Min IDD_SW ISS_SW Typ Max 14 120 Unit Test Conditions/Comments VDD_SW and VSS_SW A A CTRL_SW 0 1.2 0.8 3.3 <1 Rev. A | Page 5 of 28 V V A ADTR1107 Data Sheet ABSOLUTE MAXIMUM RATINGS Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 6. Parameter Transmit State (PA On), Receive State Off VDD_PA VGG_PA Continuous Wave (CW) RF Input Power (RFIN) at TX_IN Continuous Power Dissipation (PDISS) (TA = 85C, Derate 18.98 mW/C Above 85C) Receive State (LNA On), Transmit State Off VDD_LNA VGG_LNA CW RFIN at ANT PDISS (TA = 85C, Derate 5.04 mW/C Above 85C) Transmit and Receive States Output Load Voltage Standing Wave Ratio (VSWR) VDD_SW Range VSS_SW Range VDD_CTRL Range Channel Temperature Maximum Peak Reflow Temperature (Moisture Sensitivity Level 3, MSL3)1 Storage Temperature Range Operating Temperature Range ESD Sensitivity (Human Body Model) 1 Rating 5.5 V -2 V to +0 V 20 dBm 1.71 W THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. 4V -2 V to +0.2 V 20 dBm 0.453 W JC is the thermal resistance from the operating portion of the device to the outside surface of the package (case) closest to the device mounting area. Table 7. Thermal Resistance1 7:1 Package Type CC-24-8 -0.3 V to +3.6 V -3.6 V to +0.3 V -0.3 V to VDD + 0.3 V 175C 260C 1 JC Transmit State 52.7 Unit C/W Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board with 36 thermal vias. Refer to the JEDEC standard JESD51 for additional information. ESD CAUTION -40C to +125C -40C to +85C Class 1B (Passed 500 V) See the Ordering Guide section for more information. Table 8. Signal Path Truth Table State Transmit Receive JC Receive State 198.4 CTRL_SW Low High RF Signal Path TX_IN to ANT ANT to RX_OUT Rev. A | Page 6 of 28 Data Sheet ADTR1107 VDD_LNA VGG_LNA GND VSS_SW CTRL_SW VDD_SW 24 23 22 21 20 19 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 1 18 GND RX_OUT 2 17 ANT GND 3 16 GND GND 4 15 GND TX_IN 5 14 GND GND 6 13 GND ADTR1107 12 NOTES 1. NIC = NO INTERNAL CONNECTION. SOLDER THESE PINS TO A LOW IMPEDANCE GROUND PLANE. 2. EXPOSED PAD. MUST BE CONNECTED TO RF/DC GROUND. 22146-002 CPLR_OUT 9 NIC GND 11 8 VDD_PA NIC 10 7 VGG_PA TOP VIEW (Not to Scale) Figure 2. Pin Configuration Table 9. Pin Function Descriptions Pin No. 1, 3, 4, 6, 11, 13 to 16, 18, 22 2 5 7 8 9, 10 12 17 19 20 21 23 Mnemonic GND Description Ground. Solder these pins to a low impedance ground plane. RX_OUT TX_IN VGG_PA VDD_PA NIC CPLR_OUT ANT VDD_SW CTRL_SW VSS_SW VGG_LNA 24 VDD_LNA EPAD Receive Path Output. This pin is dc-coupled to ground and ac matched to 50 . Transmit Path Input. This pin is dc-coupled to ground and ac matched to 50 . Power Amplifier Gate Bias. This pin is used to set the desired quiescent current of the amplifier. Power Amplifier Drain Bias Voltage. No Internal Connection. Solder these pins to a low impedance ground plane. Transmit Path Coupled Port. This port is used in connection with a detector to monitor transmitted power. RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 . SPDT Switch Positive Bias Voltage. Switch Digital Control. This pin controls the state of the SPDT switch. SPDT Switch Negative Bias Voltage. LNA Gate Voltage Bias. This pin is used to set the desired quiescent current of the LNA. If this pin is supplied with 0 V or is connected to ground, the LNA runs in self bias mode at a typical current of 80 mA. LNA Drain Voltage Bias. Exposed Pad. Must be connected to RF/dc ground. Rev. A | Page 7 of 28 ADTR1107 Data Sheet INTERFACE SCHEMATICS VDD_LNA 22146-008 22146-003 GND Figure 3. GND Interface Schematic VGG_LNA Figure 9. VGG_LNA Interface Schematic Figure 4. ANT Interface Schematic VDD_SW RX_OUT VDD_SW 8k 22146-010 ANT 22146-009 22146-004 Figure 8. VDD_LNA Interface Schematic 22146-005 CTRL_SW Figure 10. RX_OUT Interface Schematic Figure 5. CTRL_SW and VDD_SW Interface Schematic VDD_PA 22146-006 2.5k Figure 11. TX_IN Interface Schematic 22146-007 Figure 6. VDD_PA Interface Schematic VGG_PA 22146-011 TX_IN Figure 7. VGG_PA Interface Schematic Rev. A | Page 8 of 28 Data Sheet ADTR1107 TYPICAL PERFORMANCE CHARACTERISTICS TRANSMIT STATE 26 25 24 20 22 10 GAIN (dB) S11 (dB) S21 (dB) S22 (dB) 15 5 0 -5 +85C +25C -40C 2 4 6 8 10 12 14 16 18 20 22 24 26 12 Figure 12. Broadband Gain and Return Loss vs. Frequency, 10 MHz to 26 GHz, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off 24 22 22 GAIN (dB) 24 5.0V 4.0V 3.3V 16 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) 12 22146-013 6 Figure 13. Gain vs. Frequency for Various VDD_PA, Transmit State, Path = TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off 10 11 12 13 14 15 16 17 18 19 20 250mA 220mA 200mA 180mA 150mA 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) Figure 16. Gain vs. Frequency for Various IDQ_PA, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, Receive State Off 0 OUTPUT RETURN LOSS (dB) +85C +25C -40C -4 -8 -12 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) Figure 14. Input Return Loss vs. Frequency for Various Temperatures, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off -8 -12 -16 -20 22146-014 -16 +85C +25C -40C -4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) 22146-017 0 -20 9 18 14 5 8 20 16 14 12 7 FREQUENCY (GHz) 26 18 6 Figure 15. Gain vs. Frequency for Various Temperatures, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off 26 20 5 22146-016 0 22146-015 14 -15 FREQUENCY (GHz) GAIN (dB) 18 -10 -20 INPUT RETURN LOSS (dB) 20 16 22146-012 BROADBAND GAIN AND RETURN LOSS (dB) 30 Figure 17. Output Return Loss vs. Frequency for Various Temperatures, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off Rev. A | Page 9 of 28 ADTR1107 Data Sheet 0 36 -20 CLRP_OUT COUPLING FACTOR (dB) -30 -40 -50 -60 -70 -80 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Figure 18. Reverse Isolation vs. Frequency for Various Temperatures,Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off 22 20 18 16 14 12 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) Figure 21. CLPR_OUT Coupling Factor vs. Frequency for Various Temperatures, Transmit State, Coupling Factor = ANT POUT - CPLR_OUT POUT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off +85C +25C -40C +85C +25C -40C -10 ANT TO RX_OUT ISOLATION (dB) -10 -20 -30 -40 -50 -60 -20 -30 -40 -50 -60 -70 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 -90 Figure 19. TX_IN to RX_OUT Isolation vs. Frequency for Various Temperatures, Transmit State, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) 22146-022 -80 22146-019 TX_IN TO RX_OUT ISOLATION (dB) 24 0 FREQUENCY (GHz) Figure 22. ANT to RX_OUT Isolation vs. Frequency for Various Temperatures, Transmit State, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off 16 16 +85C +25C -40C 5.0V 4.0V 3.3V 14 NOISE FIGURE (dB) 14 NOISE FIGURE (dB) 26 8 0 12 10 8 6 12 10 8 6 6 7 8 9 10 11 12 13 14 FREQUENCY (GHz) 15 16 17 18 4 22146-020 4 28 22146-021 5 FREQUENCY (GHz) -70 30 10 22146-018 -90 +85C +25C -40C 32 Figure 20. Noise Figure vs. Frequency for Various Temperatures, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off 6 7 8 9 10 11 12 13 14 FREQUENCY (GHz) 15 16 17 18 22146-023 REVERSE ISOLATION (dB) 34 +85C +25C -40C -10 Figure 23. Noise Figure vs. Frequency for Various VDD_PA, Transmit State, Path = TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off Rev. A | Page 10 of 28 Data Sheet ADTR1107 16 28 +85C +25C -40C 26 250mA 220mA 200mA 180mA 150mA 12 24 22 OP1dB (dBm) NOISE FIGURE (dB) 14 10 8 20 18 16 14 6 6 7 8 9 10 11 12 13 14 15 16 17 18 FREQUENCY (GHz) 10 22146-024 Figure 24. Noise Figure vs. Frequency for Various IDQ_PA, Transmit State , Path = TX_IN to ANT, VDD_PA = 5 V, Receive State Off 9 10 11 12 13 14 15 16 17 18 19 20 26 24 22 20 18 20 18 16 16 14 14 12 12 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) 10 22146-025 5 Figure 25. OP1dB vs. Frequency for Various VDD_PA, Transmit State, Path = TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off 6 28 26 26 24 24 22 22 PSAT (dBm) 30 16 8 9 10 11 12 13 14 15 16 17 18 19 20 20 5.0V 4.0V 3.3V 18 16 +85C +25C -40C 14 7 Figure 28. OP1dB vs. Frequency for Various IDQ_PA, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, Receive State Off 28 18 5 FREQUENCY (GHz) 30 20 250mA 220mA 200mA 180mA 150mA 22146-028 OP1dB (dBm) 22 OP1dB (dBm) 8 FREQUENCY (GHz) 5.0V 4.0V 3.3V 24 PSAT (dBm) 7 28 26 14 12 12 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) 10 22146-026 10 6 Figure 27. OP1dB vs. Frequency for Various Temperatures,Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off 28 10 5 Figure 26. PSAT vs. Frequency for Various Temperatures, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) 22146-029 4 22146-027 12 Figure 29. PSAT vs. Frequency for Various VDD_PA, Transmit State, Path = TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off Rev. A | Page 11 of 28 ADTR1107 Data Sheet 30 35 28 +85C +25C -40C 30 26 25 24 20 250mA 220mA 200mA 180mA 150mA 18 16 14 20 PAE (%) 15 10 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) 0 22146-030 5.0V 4.0V 3.3V 10 11 12 13 14 15 16 17 18 19 20 25 20 20 15 15 10 10 5 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0 22146-031 5 POUT (dBm), GAIN (dB), PAE (%) 10 250 5 230 -16 -12 -8 -4 INPUT POWER (dBm) 0 4 8 210 Figure 32. POUT, Gain, PAE and Power Amplifier Supply Current (IDD_PA) vs. Input Power, 6 GHz, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off 25 8 9 10 11 12 13 14 15 16 17 18 19 20 450 POUT GAIN PAE IDD_PA 410 20 370 15 330 10 290 5 250 0 -20 22146-032 270 IDD_PA (mA) 290 POUT GAIN PAE IDD_PA 7 30 310 20 6 Figure 34. PAE vs. Frequency for Various IDQ_PA, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, Receive State Off, PAE Measured at PSAT 330 25 5 FREQUENCY (GHz) Figure 31. Power Added Efficiency (PAE) vs. Frequency for Various VDD_PA, Transmit State, Path = TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off, PAE Measured at PSAT 30 250mA 220mA 200mA 180mA 150mA 22146-034 25 PAE (%) PAE (%) 9 30 FREQUENCY (GHz) POUT (dBm), GAIN (dB), PAE (%) 8 35 30 0 -20 7 Figure 33. PAE vs. Frequency for Various Temperatures, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off, PAE Measured at PSAT 35 15 6 FREQUENCY (GHz) Figure 30. PSAT vs. Frequency for Various IDQ_PA,Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, Receive State Off 0 5 -16 -12 -8 -4 INPUT POWER (dBm) 0 4 8 210 22146-035 10 22146-033 5 12 IDD_PA (mA) PSAT (dBm) 22 Figure 35. POUT, Gain, PAE and IDD_PA vs. Input Power, 10 GHz, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off Rev. A | Page 12 of 28 Data Sheet ADTR1107 30 330 410 25 310 15 330 10 290 5 250 0 -20 -15 -10 -5 0 5 10 210 INPUT POWER (dBm) Figure 36. POUT, Gain, PAE and IDD_PA vs. Input Power, 14 GHz, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off POUT GAIN PAE IDD_PA 20 15 290 270 10 250 5 230 0 -20 -15 -10 -5 0 5 IDD_PA (mA) 370 210 22146-039 20 POUT (dBm), GAIN (dB), PAE (%) 25 450 IDD_PA (mA) POUT GAIN PAE IDD_PA 22146-036 POUT (dBm), GAIN (dB), PAE (%) 30 INPUT POWER (dBm) Figure 39. POUT, Gain, PAE and IDD_PA vs. Input Power, 18 GHz, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off 2.0 40 MAX PDISS 30 OIP3 (dBm) 1.0 6GHz 8GHz 10GHz 12GHz 14GHz 16GHz 18GHz 0 -20 -15 15 5 -10 -5 0 5 10 Figure 37. Power Dissipation vs. Input Power at TA = 85C, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off 0 35 30 30 25 25 OIP3 (dBm) 35 5.0V 4.0V 3.3V 15 5 5 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) 0 22146-038 7 Figure 38. OIP3 vs. Frequency for Various VDD_PA, POUT/Tone = 8 dBm, Transmit State, Path = TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off 8 9 10 11 12 13 14 15 16 17 18 19 20 250mA 220mA 200mA 180mA 150mA 15 10 6 7 20 10 5 6 Figure 40. OIP3 vs. Frequency for Various Temperatures, POUT/Tone = 8 dBm, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off 40 20 5 FREQUENCY (GHz) 40 0 +85C +25C -40C 10 INPUT POWER (dBm) OIP3 (dBm) 20 22146-040 0.5 25 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) 22146-041 1.5 22146-037 POWER DISSIPATION (W) 35 Figure 41. OIP3 vs. Frequency for Various IDQ_PA, POUT/Tone = 8 dBm, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, Receive State Off Rev. A | Page 13 of 28 ADTR1107 Data Sheet 40 70 35 60 50 25 IM3 (dBc) 20 8dBm 6dBm 4dBm 20 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) 0 Figure 42. OIP3 vs. Frequency for Various POUT/Tone, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off 65 60 60 55 55 50 50 OIP2 (dBm) 70 35 +85C +25C -40C 30 25 35 25 15 9 10 11 12 13 14 15 16 17 18 FREQUENCY (GHz) 10 22146-043 8 Figure 43. Output Second-Order Intercept (OIP2) vs. Frequency for Various Temperatures, POUT/Tone = 8 dBm, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off 65 60 60 55 55 50 50 OIP2 (dBm) 70 40 250mA 220mA 200mA 180mA 150mA 30 25 10 11 12 13 14 FREQUENCY (GHz) 15 16 17 12 13 14 15 16 17 18 8dBm 6dBm 4dBm 25 18 10 22146-044 9 11 30 15 8 10 35 20 7 9 40 15 6 8 45 20 10 7 Figure 46. OIP2 vs. Frequency for Various VDD_PA, POUT/Tone = 8 dBm, Transmit State, Path = TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off 65 45 6 FREQUENCY (GHz) 70 35 5.0V 4.0V 3.3V 30 20 7 8 40 15 6 7 45 20 10 6 Figure 45. Third-Order Intermodulation Distortion Relative to Carrier (IM3) vs. POUT/Tone, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off 65 40 5 POUT/TONE (dBm) 70 45 4 22146-046 5 22146-042 0 22146-045 10 5 OIP2 (dBm) 6GHz 8GHz 10GHz 12GHz 14GHz 16GHz 18GHz 30 15 10 OIP2 (dBm) 40 Figure 44. OIP2 vs. Frequency for Various IDQ_PA, POUT/Tone = 8 dBm, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, Receive State Off 6 7 8 9 10 11 12 13 14 FREQUENCY (GHz) 15 16 17 18 22146-047 OIP3 (dBm) 30 Figure 47. OIP2 vs. Frequency for Various POUT/Tone, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off Rev. A | Page 14 of 28 Data Sheet ADTR1107 400 0 325 IGG_PA (mA) IDD_PA (mA) 350 0.1 300 275 -0.4 225 -10 -5 0 5 10 -0.5 -20 22146-048 -15 INPUT POWER (dBm) Figure 48. IDD_PA vs. Input Power for Various Frequencies, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off 600 IDQ_PA (mA) 500 400 300 200 100 -1.00 VGG_PA (V) -0.75 -0.50 -0.25 22146-049 0 -1.25 -15 -10 -5 0 5 10 Figure 50. Power Amplifier Gate Current (IGG_PA) vs. Input Power for Various Frequencies, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off 700 -1.50 6GHz 8GHz 10GHz 12GHz 14GHz 16GHz 18GHz INPUT POWER (dBm) 800 -100 -1.75 -0.2 -0.3 250 200 -20 -0.1 22146-050 375 0.2 6GHz 8GHz 10GHz 12GHz 14GHz 16GHz 18GHz Figure 49. IDQ_PA vs. VGG_PA, VDD_PA = 5 V, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, Receive State Off Rev. A | Page 15 of 28 ADTR1107 Data Sheet RECEIVE STATE 22 20 20 15 18 GAIN (dB) S11 (dB) S21 (dB) S22 (dB) 10 5 0 +85C +25C -40C 12 2 4 6 8 10 12 14 16 18 20 22 24 26 8 Figure 51. Broadband Gain and Return Loss vs. Frequency, 10 MHz to 26 GHz, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off 20 18 18 GAIN (dB) 20 12 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) Figure 52. Gain vs. Frequency for Various VDD_LNA, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Transmit State Off 10 11 12 13 14 15 16 17 18 19 20 14 8 50mA 100mA 85mA, SELF BIAS MODE 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) Figure 55. Gain vs. Frequency for Various IDQ_LNA, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Controlled VGG_LNA, Transmit State Off 0 -4 OUTPUT RETURN LOSS (dB) +85C +25C -40C -8 -12 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) Figure 53. Input Return Loss vs. Frequency for Various Temperatures, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off -4 -8 -12 -16 -20 22146-053 -16 +85C +25C -40C 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) 22146-056 0 -20 9 10 22146-052 8 8 16 12 2.0V 3.0V 3.3V 3.6V 10 7 FREQUENCY (GHz) 22 14 6 Figure 54. Gain vs. Frequency for Various Temperatures, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off 22 16 5 22146-055 0 22146-054 10 -15 FREQUENCY (GHz) GAIN (dB) 14 -10 -20 INPUT RETURN LOSS (dB) 16 -5 22146-051 BROADBAND GAIN AND RETURN LOSS (dB) 25 Figure 56. Output Return Loss vs. Frequency for Various Temperatures, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off Rev. A | Page 16 of 28 Data Sheet ADTR1107 0 REVERSE ISOLATION (dB) RX_OUT TO TX_IN ISOLATION (dB) +85C +25C -40C -10 -20 -30 -40 -60 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) Figure 57. Reverse Isolation vs. Frequency for Various Temperatures, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off -30 -40 -50 -60 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) Figure 60. RX_OUT to TX_IN Isolation vs. Frequency for Various Temperatures, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off 0 6.0 5.5 +85C +25C -40C -10 5.0 4.5 NOISE FIGURE (dB) ANT TO TX_IN ISOLATION (dB) -20 -70 22146-057 -50 +85C +25C -40C -10 22146-060 0 -20 -30 4.0 3.5 3.0 2.5 2.0 +85C +25C -40C 1.5 -40 1.0 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) Figure 58. ANT to TX_IN Isolation vs. Frequency for Various Temperatures, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off 6.0 5.5 5.5 5.0 5.0 4.5 4.5 3.5 3.0 2.5 2.0 2.0V 3.0V 3.3V 3.6V 1.5 1.0 8 10 12 14 16 18 20 4.0 3.5 3.0 2.5 2.0 1.5 50mA 100mA 85mA, SELF BIAS MODE 1.0 0.5 6 8 10 12 14 FREQUENCY (GHz) 16 18 20 0 22146-059 4 Figure 59. Noise Figure vs. Frequency for Various VDD_LNA, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Transmit State Off 4 6 8 10 12 14 FREQUENCY (GHz) 16 18 20 22146-062 0.5 0 6 Figure 61. Noise Figure vs. Frequency for Various Temperatures, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off 6.0 4.0 4 FREQUENCY (GHz) NOISE FIGURE (dB) NOISE FIGURE (dB) 0 22146-058 5 22146-061 0.5 -50 Figure 62. Noise Figure vs. Frequency for Various IDQ_LNA, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Controlled VGG_LNA, Transmit State Off Rev. A | Page 17 of 28 Data Sheet 22 22 20 20 18 18 16 16 14 14 OP1dB (dBm) 12 10 8 6 8 9 10 11 12 13 14 15 16 17 18 19 20 20 18 18 16 16 14 14 PSAT (dBm) 22 20 10 50mA 100mA 85mA, SELF BIAS MODE 8 4 2 2 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) Figure 64. OP1dB vs. Frequency for Various IDQ_LNA, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Controlled VGG_LNA, Transmit State Off 0 20 18 18 16 16 14 14 PSAT (dBm) 20 8 2.0V 3.0V 3.3V 3.6V 6 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 12 10 50mA 100mA 85mA, SELF BIAS MODE 8 6 4 2 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) 0 22146-065 0 +85C +25C -40C FREQUENCY (GHz) 22 10 10 11 12 13 14 15 16 17 18 19 20 Figure 67. PSAT vs. Frequency for Various Temperatures, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State = Off 22 12 9 8 6 7 8 10 4 6 7 12 6 5 6 FREQUENCY (GHz) 22 12 5 Figure 66. OP1dB vs. Frequency for Various VDD_LNA, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Transmit State Off 22146-064 OP1dB (dBm) 0 22146-066 7 22146-067 6 22146-063 5 Figure 63. OP1dB vs. Frequency for Various Temperatures, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off 0 2.0V 3.0V 3.3V 3.6V 2 FREQUENCY (GHz) PSAT (dBm) 8 4 2 0 10 6 +85C +25C -40C 4 12 Figure 65. PSAT vs. Frequency for Various VDD_LNA, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Transmit State Off 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) 22146-068 OP1dB (dBm) ADTR1107 Figure 68. PSAT vs. Frequency for Various IDQ_LNA, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Controlled VGG_LNA, Transmit State Off Rev. A | Page 18 of 28 ADTR1107 25 25 20 20 15 15 PAE (%) +85C +25C -40C 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) 0 POUT (dBm), GAIN (dB), PAE (%) 20 PAE (%) 15 10 50mA 100mA 85mA, SELF BIAS MODE 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) 9 10 11 12 13 14 15 16 17 18 19 20 110 20 105 POUT GAIN PAE IDD_LNA 15 10 100 95 5 90 0 85 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 80 INPUT POWER (dBm) Figure 70. PAE vs. Frequency for Various IDQ_LNA, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Controlled VGG_LNA, Transmit State Off, PAE Measured at PSAT Figure 73. POUT, Gain, PAE and IDD_LNA vs. Input Power, 6 GHz, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA= 0 V, Transmit State Off 110 25 110 20 105 20 105 10 POUT GAIN PAE IDD_LNA 100 95 5 90 0 85 -5 -20 -16 -12 -8 -4 INPUT POWER (dBm) 0 4 80 IDD_LNA (mA) 15 POUT (dBm), GAIN (dB), PAE (%) 25 Figure 71. POUT, Gain, PAE and IDD_LNA vs. Input Power, 10 GHz, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA= 0 V, Transmit State Off 15 10 POUT GAIN PAE IDD_LNA 100 95 5 90 0 85 -5 -20 22146-071 POUT (dBm), GAIN (dB), PAE (%) 8 25 -5 -20 22146-070 5 7 Figure 72. PAE vs. Frequency for Various VDD_LNA, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Transmit State Off, PAE Measured at PSAT 25 0 6 FREQUENCY (GHz) Figure 69. PAE vs. Frequency for Various Temperatures, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off, PAE Measured at PSAT 5 5 IDD_LNA (mA) 7 22146-073 6 -15 -10 -5 INPUT POWER (dBm) 0 5 80 IDD_LNA (mA) 5 2.0V 3.0V 3.3V 3.6V 5 22146-069 5 0 10 22146-072 10 22146-074 PAE (%) Data Sheet Figure 74. POUT, Gain, PAE and IDD_LNA vs. Input Power, 14 GHz, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA= 0 V, Transmit State Off Rev. A | Page 19 of 28 Data Sheet 105 POUT GAIN PAE IDD_LNA 10 100 95 5 90 0 85 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 80 INPUT POWER (dBm) 27 24 24 OIP3 (dBm) 27 +85C +25C -40C 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) 15 25 20 20 OIP3 (dBm) 25 10 4 6 2.0V 3.0V 3.3V 3.6V 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 15 0dBm 5dBm 10 5 5 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) 0 22146-077 0 2 FREQUENCY (GHz) 30 50mA 100mA 85mA, SELF BIAS MODE 0 Figure 79. OIP3 vs. Frequency for Various VDD_LNA, POUT/Tone = 0 dBm, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Transmit State Off 30 15 -2 21 18 Figure 76. OIP3 vs. Frequency for Various Temperatures, POUT/Tone = 0 dBm, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off -4 Figure 78. Power Dissipation vs. Input Power at TA = 85C, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off 30 21 -6 INPUT POWER (dBm) 30 15 OIP3 (dBm) 0 -20 -18 -16 -14 -12 -10 -8 22146-076 OIP3 (dBm) Figure 75. POUT, Gain, PAE and IDD_LNA vs. Input Power, 18 GHz, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off 18 6GHz 8GHz 10GHz 12GHz 14GHz 16GHz 18GHz 0.2 Figure 77. OIP3 vs. Frequency for Various IDQ_LNA, POUT/Tone = 0 dBm, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Controlled VGG_LNA, Transmit State Off 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FREQUENCY (GHz) 22146-080 -5 -20 0.3 0.1 22146-075 15 MAX PDISS 0.4 22146-078 20 0.5 22146-079 110 POWER DISSIPATION (W) 25 IDD_LNA (mA) POUT (dBm), GAIN (dB), PAE (%) ADTR1107 Figure 80. OIP3 vs. Frequency for Various POUT/Tone, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off Rev. A | Page 20 of 28 Data Sheet ADTR1107 70 45 40 60 35 50 OIP2 (dBm) 40 6GHz 8GHz 10GHz 12GHz 14GHz 16GHz 18GHz 30 20 1 2 3 4 5 0 22146-081 0 40 35 35 30 30 OIP2 (dBm) 40 15 9 10 11 12 2.0V 3.0V 3.3V 3.6V 5 13 14 15 16 17 18 25 20 50mA 100mA 85mA, SELF BIAS MODE 15 10 10 5 7 8 9 10 11 12 13 14 15 16 17 18 0 22146-082 6 FREQUENCY (GHz) Figure 82. OIP2 vs. Frequency for Various VDD_LNA, POUT/Tone = 0 dBm, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Transmit State Off 6 7 8 9 10 11 12 13 14 15 16 17 18 FREQUENCY (GHz) Figure 85. OIP2 vs. Frequency for Various IDQ_LNA, POUT/Tone = 0 dBm, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Controlled VGG_LNA, Transmit State Off 45 90 40 35 85 IDD_LNA (mA) 30 OIP2 (dBm) 8 Figure 84. OIP2 vs. Frequency for Various Temperatures, POUT/Tone = 0 dBm, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off 45 20 7 FREQUENCY (GHz) 45 25 6 22146-084 5 Figure 81. IM3 vs. POUT/Tone, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off 0 +85C +25C -40C 10 POUT/TONE (dBm) OIP2 (dBm) 20 15 10 0 25 22146-085 IM3 (dBc) 30 25 0dBm 5dBm 20 6GHz 8GHz 10GHz 12GHz 14GHz 16GHz 18GHz 80 15 75 10 6 7 8 9 10 11 12 13 14 FREQUENCY (GHz) 15 16 17 18 70 -20 22146-083 0 Figure 83. OIP2 vs. Frequency for Various POUT/Tone, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off -15 -10 -5 INPUT POWER (dBm) 0 5 22146-086 5 Figure 86. IDD_LNA vs. Input Power for Various Frequencies, Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off Rev. A | Page 21 of 28 ADTR1107 Data Sheet 120 120 100 100 80 IDQ_LNA (mA) IDQ_LNA (mA) 80 60 40 60 40 20 -1.0 -0.5 VGG_LNA (V) 0 0 22146-087 -20 -1.5 Figure 87. IDQ_LNA vs. VGG_LNA, VDD_LNA = 3.3 V, Controlled VGG_LNA, Receive State, Path = ANT to RX_OUT, Transmit State Off 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 VDD_LNA (V) 2.4 2.7 3.0 3.3 3.6 22146-088 20 0 Figure 88. IDQ_LNA vs. VDD_LNA, Self Biased Mode, VGG_LNA = 0 V, Receive State, Path = ANT to RX_OUT, Transmit State Off Rev. A | Page 22 of 28 Data Sheet ADTR1107 THEORY OF OPERATION The ADTR1107 is a multichip transmit/receive module that consists of an LNA, a medium power amplifier, and a silicon SPDT reflective switch. The ANT antenna port is dc-coupled to 0 V and no dc block is required at this port when the RF line potential is equal to 0 V. The switch has an integrated driver to perform logic functions internally and provides a simplified complementary metal-oxide semiconductor (CMOS)/low voltage transistor to transistor logic (LVTTL)-compatible control interface. The driver features a single digital control input pin, CTRL_SW. The logic level applied to CTRL_SW determines whether the ADTR1107 is in transmit state or receive state (see Table 8). The receive path contains a self biased LNA with optional bias control using the VGG_LNA pin for bias adjustment. For self biased operation, the VGG_LNA pin is set to 0 V or connected to ground. The receive path output (RX_OUT) is dc-coupled to ground through an 8 k resistor. No dc block is required at this port when the RF line potential is equal to 0 V. The transmit path contains a power amplifier. The bias current is set using VGG_PA. The transmit path input (TX_IN) is dc-coupled to ground through a 2.5 k resistor. No dc block is required at this port when the RF line potential is equal to 0 V. A directional coupler is incorporated into the ADTR1107 to allow for monitoring of the transmit power level. Rev. A | Page 23 of 28 ADTR1107 Data Sheet APPLICATIONS INFORMATION The basic connections for operating the ADTR1107 are shown in Figure 89. The power amplifier on the transmit path is biased with +5 V on the VDD_PA pin and a voltage from -1.75 V to -0.25 V is applied to the VGG_PA pin to achieve 220 mA quiescent current. The LNA on the receive path operates as either self biased or external biased mode. For self biased mode, apply 3.3 V to the VDD_LNA pin and leave the VGG_LNA pin supplied with 0 V or connected to ground. For external biased mode, apply +3.3 V to the VDD_LNA pin and adjust the VGG_LNA pin with a voltage range of -1.5 V to 0 V to achieve the desired IDQ_PA. The SPDT switch is biased with +3.3 V on the VDD_SW pin and -3.3 V on the VSS_SW pin. The CTRL_SW pin sets the path state shown in Table 8. High logic state is set at 3.3 V and low logic state is set at 0 V. All required decoupling capacitors for the dc power supply lines are internal to the ADTR1107. RECOMMENDED BIAS SEQUENCING The recommended bias sequence during transmit state power-up is as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. Connect all GND pins to ground. Set the VDD_SW pin to 3.3 V. Set the VSS_SW pin to -3.3 V. Set the CTRL_SW pin to 0 V. Set the VGG_LNA pin to 0 V. Set the VDD_LNA pin to 0 V. Set the VGG_PA pin to -1.75 V. Set the VDD_PA pin to 5 V. Increase the VGG_PA voltage to achieve the desired IDQ_PA. 10. Apply the RF signal to the TX_IN pin. The recommended bias sequence during receive state power-up is as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. The recommended receive state bias sequence during power-down is as follows: 1. 2. 3. 4. 5. Turn off the RF signal. Set the VDD_LNA pin to 0 V. Set the CTRL_SW pin to 0 V. Set the VSS_SW pin to 0 V. Set the VDD_SW pin to 0 V. All measurements and data shown in this data sheet were taken using the typical application circuit (see Figure 89) and biased per the conditions in this section, unless otherwise noted. The bias conditions described in this section are the operating points recommended to optimize the overall device performance. Operation using other bias conditions can result in performance that differs from what is shown in the Typical Performance Characteristics section. To obtain optimal performance while not damaging the device, follow the recommended biasing sequences described in this section and adhere to the values shown in the Absolute Maximum Ratings section. The recommended transmit state bias sequence during power-down is as follows: 1. 2. 3. 4. 5. Connect all GND pins to ground. Set the VDD_SW pin to 3.3 V. Set the VSS_SW pin to -3.3 V. Set the CTRL_SW pin to 3.3 V. Set the VGG_PA pin to -1.75 V. Set the VDD_PA pin to 0 V. Set the VGG_LNA pin to 0 V. Set the VDD_LNA pin to 3.3 V. Apply the RF signal to the ANT pin. Turn off the RF signal. Decrease the VGG_PA voltage to -1.75 V. Set the VDD_PA pin to 0 V. Set the VSS_SW pin to 0 V. Set the VDD_SW pin to 0 V. Rev. A | Page 24 of 28 Data Sheet ADTR1107 TYPICAL APPLICATION CIRCUIT +3.3V 0V/+3.3V -3.3V 0V 1 2 3 4 5 6 GND ANT GND GND GND GND 18 17 16 15 14 13 7 8 9 10 11 12 TRANSMIT PATH INPUT GND RX_OUT GND GND ADTR1107 TX_IN GND VGG_PA VDD_PA NIC NIC GND CPLR_OUT COUPLED OUTPUT GND +5V -1.75V TO -0.25V Figure 89. Typical Application Circuit Rev. A | Page 25 of 28 22146-090 RECEIVE PATH OUTPUT PAD VDD_LNA VGG_LNA GND VSS_SW CTRL_SW VDD_SW PAD 24 23 22 21 20 19 +3.3V ADTR1107 Data Sheet INTERFACING THE ADTR1107 TO THE ADAR1000 X BAND AND KU BAND BEAMFORMER 100 10 1 0.1 5 7 9 11 13 15 17 19 ADTR1107 OUTPUT POWER (dBm) 21 23 22146-091 While the ADTR1107 LNA gate voltage is self biased (the VGG_LNA pin is connected to 0 V or grounded), the voltage can also be controlled from the ADAR1000. In this case, there is a single LNA_BIAS voltage (0 V to -4.8 V) controlled by an 8-bit DAC that can be used to bias four ADTR1107 devices connected to each ADAR1000. The ADTR1107 CPLR_OUT coupler output can be tied back to one of the four ADAR1000 RF detector inputs (DET1 to DET4). These diode based RF detectors have an input range of -20 dBm to +10 dBm. The coupling factor of the ADTR1107 directional coupler ranges from 28 dB at 6 GHz to 18 dB at 18 GHz. At 12 GHz, with a coupling factor of 22 dB and a maximum power amplifier output of 26 dBm, the coupled output power is a maximum of 4 dBm. If the coupler output is connected directly to the detector input, this connection provides a detection range of 24 dB. Figure 90 shows the relationship between the ADTR1107 output power and the ADC code of the ADAR1000 detector at 12 GHz. In this case, the ADTR1107 output power is swept to a maximum level of approximately 22 dBm. ADAR1000 RF DETECTOR OUTPUT CODE (Decimal) ADTR1107 can be interfaced to the ADAR1000 X band and Ku band quad beamformer IC, as shown in Figure 91. Note that only a single channel of the ADAR1000 is shown in Figure 91 and additional components have been omitted for clarity. The ADAR1000 provides multiple bias voltages and control signals, resulting in a glueless interface and no need for any additional control signals to the ADTR1107. The gate voltage for the ADTR1107 power amplifier (VGG_PA) is provided by the ADAR1000 PA_BIAS3 pin. One of four independent negative gate voltages is needed for power amplifier gate biasing. Each voltage is set by an 8-bit digital-to-analog converter (DAC) with an output voltage range of 0 V to -4.8 V. The typical gate voltage required to bias the ADTR1107 power amplifier is -1.1 V (see Figure 49). This voltage can be asserted by the ADAR1000 TR input pin (rising edge enables the power amplifier) or by a serial peripheral interface (SPI) write. Asserting the ADAR1000 TR pin switches the polarity of the ADAR1000 TR_SW_NEG pin and TR_SW_POS pin. The TR_SW_POS pin can drive the gates of up to four switches and can be used to control the ADTR1107 SPDT switch. Figure 90. ADAR1000 RF Detector Output Code vs. ADTR1107 Output Power at 12 GHz Rev. A | Page 26 of 28 ADTR1107 AVDD1 LDO 1.8V +3.3V AVDD3 ADAR1000 TO PA BIAS DET3 ADC VGG_PA 100k PA BIAS +5V CPLR_OUT VDD_PA PA_BIAS3 TX_IN TX3 ANT ADTR1107 RX_OUT LNA_BIAS 1 LNA BIAS VGG_LNA VDD_LNA +3.3V TR_SW_POS GND ADDR0 ADDR1 SCLK SDIO CSB SDO TR TX_LOAD RX_LOAD -3.3V VDD_SW +3.3V TO ADDITIONAL LNA GATES SPI RF_IO VSS_SW CTRL_SW RX3 1 LNA_BIAS IS A SINGLE PIN THAT CAN DRIVE UP TO FOUR GATES AND IS AN OPTIONAL CONNECTION THAT CAN BE USED TO VARY THE BIAS CURRENT OF THE ADTR1107. Figure 91. Interfacing the ADTR1107 to the ADAR1000 X and Ku Band Beamformer, One Channel Shown Rev. A | Page 27 of 28 22146-092 -5V PA_ON Data Sheet ADTR1107 Data Sheet OUTLINE DIMENSIONS PIN 1 INDICATOR AREA 5.10 5.00 SQ 4.90 0.35 0.30 0.25 0.50 0.45 0.40 1 3.25 REF SQ 0.65 BSC TOP VIEW PIN 1 INDICATOR C 0.30 x 0.45 24 19 18 3.30 SQ BSC EXPOSED PAD 6 13 7 12 BOTTOM VIEW PKG-005635 1.13 MAX SIDE VIEW FOR PROPER CONNECTION OF THE EXPOSED PADS, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.70 REF 0.356 0.326 0.296 SEATING PLANE 03-26-2019-B 0.15 REF Figure 92. 24-Terminal Land Grid Array [LGA] (CC-24-8) Dimensions shown in millimeters ORDERING GUIDE Model1 ADTR1107ACCZ ADTR1107ACCZ-R7 ADTR1107-EVAL 1 2 3 Temperature Range -40C to +85C -40C to +85C MSL Rating2 3 3 Package Description3 24-Terminal Land Grid Array [LGA] 24-Terminal Land Grid Array [LGA] Evaluation Board Z = RoHS Compliant Part. See the Absolute Maximum Ratings section for additional information. The lead finish of the ADTR1107ACCZ and the ADTR1107ACCZ-R7 is nickel palladium gold (NiPdAu). (c)2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D22146-4/20(A) Rev. A | Page 28 of 28 Package Option CC-24-8 CC-24-8