GS816018BT-250V - Giga Semiconductor, Inc.

GS8160xxBT-xxxV

1M x 18, 512K x 32, 512K x 36

18Mb Sync Burst SRAMs

250 MHz–150 MHz

1.8 V or 2.5 V VDD

1.8 V or 2.5 V I/O

100-Pin TQFP

Commercial Temp

Industrial Temp

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Features

• FT pin for user-configurable flow through or pipeline

operation

• Single Cycle Deselect (SCD) operation

• 1.8 V or 2.5 V core power supply

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Functional Description

Applications

The GS8160xxBT-xxxV is an 18,874,368-bit (16,777,216-bit

for x32 version) high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS8160xxBT-xxxV operates on a 1.8 V or 2.5 V power

supply. All inputs are 1.8 V or 2.5 V compatible. Separate

output power (VDDQ) pins are used to decouple output noise

from the internal circuits and are 1.8 V or 2.5 V compatible.

Parameter Synopsis

-250 -200 -150 Unit

Pipeline

3-1-1-1

tKQ

tCycle

3.0

4.0

3.0

5.0

3.8

6.7

Curr (x18)

Curr (x32/x36)

280

330

230

270

185

210

Flow Through

2-1-1-1

tKQ

tCycle

5.5

6.5

7.5

Curr (x18)

Curr (x32/x36)

210

240

185

205

170

190

VDDQ

VSS

DQB

VSS

VDDQ

DQB

VDD

VSS

DQB

VDDQ

VSS

DQB

DQPB

VSS

VDDQ

VSS

DQA

VSS

VDDQ

DQA

VSS

VDD

DQA

VDDQ

VSS

DQA

VSS

VDDQ

LBO

VSS

VDD

VSS

ADSC

ADSP

ADV

1M x 18

Top View

DQPA

NC 10099989796959493929190898887868584838281

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

GS8160xxBT-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS816018BT-xxxV 100-Pin TQFP Pinout

VDDQ

VSS

DQC

VSS

VDDQ

DQC

VDD

VSS

DQD

VDDQ

VSS

DQD

VSS

VDDQ

VSS

DQB

VSS

VDDQ

DQB

VSS

VDD

DQA

VDDQ

VSS

DQA

VSS

VDDQ

LBO

VSS

VDD

VSS

ADSC

ADSP

ADV

512K x 32

Top View

DQB

DQA

DQC

DQD

DQC

NC 10099989796959493929190898887868584838281

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

GS8160xxBT-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS816032BT-xxxV 100-Pin TQFP Pinout

VDDQ

VSS

DQC

VSS

VDDQ

DQC

VDD

VSS

DQD

VDDQ

VSS

DQD

VSS

VDDQ

VSS

DQB

VSS

VDDQ

DQB

VSS

VDD

DQA

VDDQ

VSS

DQA

VSS

VDDQ

LBO

VSS

VDD

VSS

ADSC

ADSP

ADV

512K x 36

Top View

DQB

DQPB

DQB

DQA

DQPA

DQC

DQD

DQPD

DQC

DQPC

10099989796959493929190898887868584838281

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

GS8160xxBT-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS816036BT-xxxV 100-Pin TQFP Pinout

TQFP Pin Description

Symbol Type Description

A0, A1IAddress field LSBs and Address Counter preset Inputs

A I Address Inputs

DQA

DQB

DQC

DQD

I/O Data Input and Output pins

NC No Connect

BW IByte Write—Writes all enabled bytes; active low

BA, BB, BC, BDIByte Write Enable for DQA, DQB Data I/Os; active low

CK IClock Input Signal; active high

GW IGlobal Write Enable—Writes all bytes; active low

E1, E3IChip Enable; active low

E2IChip Enable; active high

G I Output Enable; active low

ADV IBurst address counter advance enable; active low

ADSP, ADSC IAddress Strobe (Processor, Cache Controller); active low

ZZ ISleep Mode control; active high

FT IFlow Through or Pipeline mode; active low

LBO ILinear Burst Order mode; active low

VDD ICore power supply

VSS II/O and Core Ground

VDDQ IOutput driver power supply

GS8160xxBT-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8160xxBT-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

A0 A0

D1 Q1

Counter

Load

A0–An

LBO

ADV

ADSC

ADSP

ZZ Power Down

Control

Memory

Array

36 36

DQx1–DQx9

Note: Only x36 version shown for simplicity.

DCD=1

GS8160xxB-xxxV Block Diagram

Mode Pin Functions

Mode Name Pin Name State Function

Burst Order Control LBO LLinear Burst

HInterleaved Burst

Output Register Control FT LFlow Through

H or NC Pipeline

Power Down Control ZZ L or NC Active

H Standby, IDD = ISB

GS8160xxBT-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Note:

There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in

the default states as specified in the above table.

Note:

The burst counter wraps to initial state on the 5th clock.

Note:

The burst counter wraps to initial state on the 5th clock.

Linear Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01

4th address 11 00 01 10

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 00 11 10

3rd address 10 11 00 01

4th address 11 10 01 00

Burst Counter Sequences

BPR 1999.05.18

GS8160xxBT-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Byte Write Truth Table

Function GW BW BABBBCBDNotes

Read H H X X X X 1

Read H L H H H H 1

Write byte a H L L H H H 2, 3

Write byte b H L H L H H 2, 3

Write byte c H L H H L H 2, 3, 4

Write byte d H L H H H L 2, 3, 4

Write all bytes HLLLLL2, 3, 4

Write all bytes L X X X X X

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x32 and x36 versions.

Synchronous Truth Table

Operation Address

Used

State

Diagram

Key5

E1E2ADSP ADSC ADV W3DQ4

Deselect Cycle, Power Down None X H X X L X X High-Z

Deselect Cycle, Power Down None X L F L X X X High-Z

Deselect Cycle, Power Down None X L F H L X X High-Z

Read Cycle, Begin Burst External R L T L X X X Q

Read Cycle, Begin Burst External R L T H L X F Q

Write Cycle, Begin Burst External W L T H L X T D

Read Cycle, Continue Burst Next CR X X H H L F Q

Read Cycle, Continue Burst Next CR H X X H L F Q

Write Cycle, Continue Burst Next CW X X H H L T D

Write Cycle, Continue Burst Next CW H X X H L T D

Read Cycle, Suspend Burst Current X X H H H F Q

Read Cycle, Suspend Burst Current H X X H H F Q

Write Cycle, Suspend Burst Current X X H H H T D

Write Cycle, Suspend Burst Current H X X H H T D

Notes:

1. X = Don’t Care, H = High, L = Low

2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.

4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as “Q” in the Truth Table above).

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

GS8160xxBT-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

First Write First Read

Burst Write Burst Read

Deselect

CRCW

Simple Synchronous OperationSimple Burst Synchronous Operation

CW CR

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW)

control inputs, and that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and

assumes ADSP is tied high and ADV is tied low.

GS8160xxBT-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Simplified State Diagram

First Write First Read

Burst Write Burst Read

Deselect

CRCW

CW CR

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

GS8160xxBT-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Simplified State Diagram with G

GS8160xxBT-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Absolute Maximum Ratings

(All voltages reference to VSS)

Symbol Description Value Unit

VDD Voltage on VDD Pins –0.5 to 4.6 V

VDDQ Voltage on VDDQ Pins –0.5 to VDD V

VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 4.6 V max.) V

VIN Voltage on Other Input Pins –0.5 to VDD +0.5 (≤ 4.6 V max.) V

IIN Input Current on Any Pin +/–20 mA

IOUT Output Current on Any I/O Pin +/–20 mA

PDPackage Power Dissipation 1.5 W

TSTG Storage Temperature –55 to 125 oC

TBIAS Temperature Under Bias –55 to 125 oC

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of

this component.

Power Supply Voltage Ranges (1.8 V/2.5 V Version)

Parameter Symbol Min. Typ. Max. Unit Notes

1.8 V Supply Voltage VDD1 1.7 1.8 2.0 V

2.5 V Supply Voltage VDD2 2.3 2.5 2.7 V

1.8 V VDDQ I/O Supply Voltage VDDQ1 1.7 1.8 VDD V

2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 VDD V

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-

tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

GS8160xxBT-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

VDDQ2 & VDDQ1 Range Logic Levels

Parameter Symbol Min. Typ. Max. Unit Notes

VDD Input High Voltage VIH 0.6*VDD —VDD + 0.3 V 1

VDD Input Low Voltage VIL –0.3 —0.3*VDD V 1

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-

tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

Recommended Operating Temperatures

Parameter Symbol Min. Typ. Max. Unit Notes

Ambient Temperature (Commercial Range Versions) TA025 70 °C 2

Ambient Temperature (Industrial Range Versions) TA–40 25 85 °C 2

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-

tions quoted are evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

20% tKC

SS – 2.0 V

50%

VSS

VIH

Undershoot Measurement and Timing Overshoot Measurement and Timing

20% tKC

VDD + 2.0 V

50%

VDD

VIL

Capacitance

oC, f = 1 MHZ, VDD

Parameter Symbol Test conditions Typ. Max. Unit

Input Capacitance CIN VIN = 0 V 4 5 pF

Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF

Note:

These parameters are sample tested.

(TA = 25 = 2.5 V)

AC Test Conditions

Parameter Conditions

VDDQ/2

50Ω30pF*

Output Load 1

* Distributed Test Jig Capacitance

Figure 1

Input high level VDD – 0.2 V

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level VDD/2

Output reference level VDDQ/2

Output load Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

GS8160xxBT-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

DC Electrical Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage Current

(except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA

FT, ZZ Input Current IIN VDD ≥ VIN ≥ 0 V –100 uA 100 uA

Output Leakage Current IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA

DC Output Characteristics (1.8 V/2.5 V Version)

Parameter Symbol Test Conditions Min Max

1.8 V Output High Voltage VOH1 IOH = –4 mA, VDDQ = 1.6 V VDDQ – 0.4 V —

2.5 V Output High Voltage VOH2 IOH = –8 mA, VDDQ = 2.375 V 1.7 V —

1.8 V Output Low Voltage VOL1 IOL = 4 mA —0.4 V

2.5 V Output Low Voltage VOL2 IOL = 8 mA —0.4 V

Operating Currents

Parameter Test Conditions Mode Symbol

-250 -200 -150

Unit

70°C

–40

85°C

70°C

–40

85°C

70°C

–40

85°C

Operating

Current

Device Selected;

All other inputs

≥VIH or ≤ VIL

Output open

(x32/

x36)

Pipeline IDD

IDDQ

290

300

240

250

190

200

20 mA

Flow Through IDD

IDDQ

220

230

190

200

175

185

15 mA

(x18)

Pipeline IDD

IDDQ

260

270

215

225

170

180

15 mA

Flow Through IDD

IDDQ

200

210

175

185

160

170

10 mA

Standby

Current ZZ ≥ VDD – 0.2 V —

Pipeline ISB 40 50 40 50 40 50 mA

Flow Through ISB 40 50 40 50 40 50 mA

Deselect

Current

Device Deselected;

All other inputs

≥ VIH or ≤ VIL

—

Pipeline IDD 85 90 75 80 60 65 mA

Flow Through IDD 60 65 50 55 50 55 mA

GS8160xxBT-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Notes:

1. IDD and IDDQ apply to any combination of VDD and VDDQ operation.

2. All parameters listed are worst case scenario.

AC Electrical Characteristics

Parameter Symbol -250 -200 -150 Unit

Min Max Min Max Min Max

Pipeline

Clock Cycle Time tKC 4.0 —5.0 —6.7 —ns

Clock to Output Valid tKQ —3.0 —3.0 —3.8 ns

Clock to Output Invalid tKQX 1.5 —1.5 —1.5 —ns

Clock to Output in Low-Z tLZ11.5 —1.5 —1.5 —ns

Setup time tS 1.4 —1.4 —1.5 —ns

Hold time tH 0.2 —0.4 —0.5 —ns

Flow Through

Clock Cycle Time tKC 5.5 —6.5 —7.5 —ns

Clock to Output Valid tKQ —5.5 —6.5 —7.5 ns

Clock to Output Invalid tKQX 2.0 —2.0 —2.0 —ns

Clock to Output in Low-Z tLZ12.0 —2.0 —2.0 —ns

Setup time tS 1.5 —1.5 —1.5 —ns

Hold time tH 0.5 —0.5 —0.5 —ns

Clock HIGH Time tKH 1.3 —1.3 —1.5 —ns

Clock LOW Time tKL 1.7 —1.7 —1.7 —ns

Clock to Output in

High-Z tHZ11.5 2.5 1.5 3.0 1.5 3.0 ns

G to Output Valid tOE —2.5 —3.0 —3.8 ns

G to output in Low-Z tOLZ10—0—0—ns

G to output in High-Z tOHZ1—2.5 —3.0 —3.8 ns

ZZ setup time tZZS25—5—5—ns

ZZ hold time tZZH21—1—1—ns

ZZ recovery tZZR 20 —20 —20 —ns

GS8160xxBT-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

GS8160xxBT-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Pipeline Mode Timing

Begin Read A Cont Cont Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont Deselect

tHZ

tKQXtKQ

tLZtH

tOHZtOE

tHtS

Burst ReadBurst ReadSingle Write

tKCtKC

tKLtKL

tKH

Single WriteSingle Read

tKH

Single Read

Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3)

ABC

Deselected with E1

E1 masks ADSP

E2 and E3 only sampled with ADSP and ADSC

ADSC initiated read

ADSP

ADSC

ADV

A0–An

Ba–Bd

DQa–DQd

GS8160xxBT-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Flow Through Mode Timing

Begin Read A Cont Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont Deselect

tHZ

tKQX

tKQ

tLZ

tOHZtOE

tKCtKC

tKLtKL

tKHtKH

ABC

Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C)

E2 and E3 only sampled with ADSC

ADSC initiated read

Deselected with E1

Fixed High

ADSP

ADSC

ADV

A0–An

Ba–Bd

DQa–DQd

GS8160xxBT-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,

the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to

low, the SRAM operates normally after ZZ recovery time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of

Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become

disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.

When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated

until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands

may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing

tZZR

tZZHtZZS

Hold

Setup

tKLtKL

tKHtKH

tKCtKC

ADSP

ADSC

Application Tips

Single and Dual Cycle Deselect

SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with

the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually

assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste

bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at

bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention.

GS8160xxBT-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

TQFP Package Drawing (Package T)

Pin 1

Notes:

1. All dimensions are in millimeters (mm).

2. Package width and length do not include mold protrusion.

Symbol Description Min. Nom. Max

A1 Standoff 0.05 0.10 0.15

A2 Body Thickness 1.35 1.40 1.45

b Lead Width 0.20 0.30 0.40

c Lead Thickness 0.09 —0.20

D Terminal Dimension 21.9 22.0 22.1

D1 Package Body 19.9 20.0 20.1

E Terminal Dimension 15.9 16.0 16.1

E1 Package Body 13.9 14.0 14.1

e Lead Pitch —0.65 —

L Foot Length 0.45 0.60 0.75

L1 Lead Length —1.00 —

Y Coplanarity 0.10

θLead Angle 0°—7°

GS8160xxBT-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Ordering Information for GSI Synchronous Burst RAMs

Org Part Number1Type Voltage

Option Package Speed2

(MHz/ns) TA3Status4

1M x 18 GS816018BT-250V Synchronous Burst 1.8 V or 2.5 V TQFP 250/5.5 CMP

1M x 18 GS816018BT-200V Synchronous Burst 1.8 V or 2.5 V TQFP 200/6.5 CMP

1M x 18 GS816018BT-150V Synchronous Burst 1.8 V or 2.5 V TQFP 150/7.5 CMP

512K x 32 GS816032BT-250V Synchronous Burst 1.8 V or 2.5 V TQFP 250/5.5 CMP

512K x 32 GS816032BT-200V Synchronous Burst 1.8 V or 2.5 V TQFP 200/6.5 CMP

512K x 32 GS816032BT-150V Synchronous Burst 1.8 V or 2.5 V TQFP 150/7.5 CMP

512K x 36 GS816036BT-250V Synchronous Burst 1.8 V or 2.5 V TQFP 250/5.5 CMP

512K x 36 GS816036BT-200V Synchronous Burst 1.8 V or 2.5 V TQFP 200/6.5 CMP

512K x 36 GS816036BT-150V Synchronous Burst 1.8 V or 2.5 V TQFP 150/7.5 CMP

1M x 18 GS816018BT-250IV Synchronous Burst 1.8 V or 2.5 V TQFP 250/5.5 IMP

1M x 18 GS816018BT-200IV Synchronous Burst 1.8 V or 2.5 V TQFP 200/6.5 IMP

1M x 18 GS816018BT-150IV Synchronous Burst 1.8 V or 2.5 V TQFP 150/7.5 IMP

512K x 32 GS816032BT-250IV Synchronous Burst 1.8 V or 2.5 V TQFP 250/5.5 IMP

512K x 32 GS816032BT-200IV Synchronous Burst 1.8 V or 2.5 V TQFP 200/6.5 IMP

512K x 32 GS816032BT-150IV Synchronous Burst 1.8 V or 2.5 V TQFP 150/7.5 IMP

512K x 36 GS816036BT-250IV Synchronous Burst 1.8 V or 2.5 V TQFP 250/5.5 IMP

512K x 36 GS816036BT-200IV Synchronous Burst 1.8 V or 2.5 V TQFP 200/6.5 IMP

512K x 36 GS816036BT-150IV Synchronous Burst 1.8 V or 2.5 V TQFP 150/7.5 IMP

1M x 18 GS816018BGT-250V Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 250/5.5 CPQ

1M x 18 GS816018BGT-200V Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 200/6.5 CPQ

1M x 18 GS816018BGT-150V Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 150/7.5 CPQ

512K x 32 GS816032BGT-250V Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 250/5.5 CPQ

512K x 32 GS816032BGT-200V Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 200/6.5 CPQ

512K x 32 GS816032BGT-150V Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 150/7.5 CPQ

512K x 36 GS816036BGT-250V Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 250/5.5 CPQ

512K x 36 GS816036BGT-200V Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 200/6.5 CPQ

512K x 36 GS816036BGT-150V Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 150/7.5 CPQ

1M x 18 GS816018BGT-250IV Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 250/5.5 IPQ

1M x 18 GS816018BGT-200IV Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 200/6.5 IPQ

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816018BT-150IvT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device

is Pipeline/Flow through mode-selectable by the user.

3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. MP = Mass Production. PQ = Pre-Qualification.

5. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are cov-

ered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

GS8160xxBT-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

1M x 18 GS816018BGT-150IV Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 150/7.5 IPQ

512K x 32 GS816032BGT-250IV Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 250/5.5 IPQ

512K x 32 GS816032BGT-200IV Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 200/6.5 IPQ

512K x 32 GS816032BGT-150IV Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 150/7.5 IPQ

512K x 36 GS816036BGT-250IV Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 250/5.5 IPQ

512K x 36 GS816036BGT-200IV Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 200/6.5 IPQ

512K x 36 GS816036BGT-150IV Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 150/7.5 IPQ

Ordering Information for GSI Synchronous Burst RAMs (Continued)

Org Part Number1Type Voltage

Option Package Speed2

(MHz/ns) TA3Status4

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816018BT-150IvT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device

is Pipeline/Flow through mode-selectable by the user.

3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.

4. MP = Mass Production. PQ = Pre-Qualification.

5. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are cov-

ered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

18Mb Sync SRAM Datasheet Revision History

DS/DateRev. Code: Old;

New

Types of Changes

Format or Content Page;Revisions;Reason

8160VxxB_r1 • Creation of new datasheet

8160VxxB_r1;

8160xx-xxxV_r1_01 Content • Change part numbering due to nomenclature change

GS8160xxBT-xxxV

Preliminary

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.