       
    
 
SLVS293D − NOVEMBER 2000 − REVISED MAY 2002
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D5-A Low-Dropout Voltage Regulator
DAvailable in 1.5-V, 1.8-V, 2.5-V, and 3.3-V
Fixed-Output and Adjustable Versions
DOpen Drain Power-Good (PG) Status
Output (Fixed Options Only)
DDropout Voltage Typically 250 mV at 5 A
(TPS75533)
DLow 125 µA Typical Quiescent Current
DFast Transient Response
D3% Tolerance Over Specified Conditions for
Fixed-Output Versions
DAvailable in 5-Pin TO−220 and TO−263
Surface-Mount Packages
DThermal Shutdown Protection
description
The TPS755xx family of 5-A low dropout (LDO) regulators contains four fixed voltage option regulators with
integrated power-good (PG) and an adjustable voltage option regulator. These devices are capable of supplying
5 A of output current with a dropout of 250 mV (TPS75533). Therefore, the device is capable of performing a
3.3-V to 2.5-V conversion. Quiescent current is 125 µA at full load and drops down to less than 1 µA when the
device is disabled. The TPS755xx is designed to have fast transient response for large load current changes.
t − Time − µs
TPS75515
LOAD TRANSIENT RESPONSE
I − Output Current − A
O
VO
− Change in Output Voltage − mV
−100
0
0604020 80 100 140120 160 180 200
0
50
−50
VO = 1.5 V
Co = 100 µF
−150 5
di
dt +1.25 A
ms
100
150
0
50
100
150
200
250
300
350
400
−40 −25 −10 5 20 35 50 65 80 95 110 125
TJ − Junction Temperature − °C
− Dropout Voltage − mV
VDO
TPS75533
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
IO = 5 A
VO = 3.3 V
Copyright 2001, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TO−220 (KC) PACKAGE
(TOP VIEW)
1
2
3
4
5
EN
IN
GND
OUTPUT
FB/PG
1
TO−263 (KTT) PACKAGE
(TOP VIEW)
2
3
4
5
EN
IN
GND
OUTPUT
FB/PG
Tab is GND
Tab is GND
  !"#$ % &'!!($ #%  )'*+&#$ ,#$(-
!,'&$% &!" $ %)(&&#$% )(! $.( $(!"%  (/#% %$!'"($%
%$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',(
$(%$2  #++ )#!#"($(!%-
       
    
 
SLVS293D − NOVEMBER 2000 − REVISED MAY 2002
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description (continued)
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 250 mV
at an output current of 5 A for the TPS75533) and is directly proportional to the output current. Additionally, since
the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output
loading (typically 125 µA over the full range of output current). These two key specifications yield a significant
improvement in operating life for battery-powered systems.
The device is enabled when EN is connected to a low-level voltage. This LDO family also features a sleep mode;
applying a TTL high signal to E N (enable) shuts down the regulator, reducing the quiescent current to less than
1 µA at TJ = 25°C. The power-good terminal (PG) is an active low, open drain output, which can be used to
implement a power-on reset or a low-battery indicator.
The TPS755xx is offered in 1.5-V, 1.8-V, 2.5-V, and 3.3-V fixed-voltage versions and in an adjustable version
(programmable over the range of 1.22 V to 5 V). Output voltage tolerance is specified as a maximum of 3% over
line, load, and temperature ranges. The TPS755xx family is available in a 5-pin T O−220 (KC) and T O−263 (KTT)
packages.
AVAILABLE OPTIONS
TJOUTPUT VOLTAGE
(TYP) TO−220 (KC) TO−263(KTT)
3.3 V TPS75533KC TPS75533KTT
2.5 V TPS75525KC TPS75525KTT
−40°C to 125°C1.8 V TPS75518KC TPS75518KTT
−40 C to 125 C
1.5 V TPS75515KC TPS75515KTT
Adjustable 1.22 V to 5 V TPS75501KC TPS75501KTT
NOTE: The TPS75501 is programmable using an external resistor divider (see application
information). The KTT package is available taped and reeled. Add an R suffix to the
device type (e.g., TPS75501KTTR) to indicate tape and reel.
See application information section for capacitor selection details.
PG
OUT
2
1
IN
EN
GND
3
5
4
VI
1 µF
PG
VO
47 µF
+Co
Figure 1. Typical Application Configuration (For Fixed Output Options)
       
    
 
SLVS293D − NOVEMBER 2000 − REVISED MAY 2002
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
functional block diagram—adjustable version
_+
Thermal
Shutdown
Bandgap
Reference
VIN
Current
Sense
R2
V
IN
GND
EN
V
OUT
SHUTDOWN
Vref = 1.22 V
UVLO
ILIM
External to
the Device
FB
R1
UVLO
functional block diagram—fixed version
_+
Thermal
Shutdown
Falling
Edge Delay
VIN
Current
Sense
R1
R2
V
IN
GND
EN
V
OUT
PG
SHUTDOWN
UVLO
ILIM
Bandgap
Reference
UVLO
Vref = 1.22 V
Terminal Functions (TPS755xx)
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
EN 1 I Enable input
FB/PG 5 I Feedback input voltage for adjustable device/PG output for fixed options
GND 3 Regulator ground
IN 2 I Input voltage
OUTPUT 4 O Regulated output voltage
       
    
 
SLVS293D − NOVEMBER 2000 − REVISED MAY 2002
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TPS755xx PG timing diagram
NOTE A: VIT −Trip voltage is typically 9% lower than the output voltage (91%VO). VIT− to VIT+ is the hysteresis voltage.
t
t
t
Threshold
Voltage
PG
Output
VIT+(see Note A)
VIN1
VOUT
VIT
(see Note A)
VUVLO
VUVLO
detailed description
The TPS755xx family includes four fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V, and 3.3 V), and an
adjustable regulator, the TPS75501 (adjustable from 1.22 V to 5 V). The bandgap voltage is typically 1.22 V.
pin functions
enable (EN)
The EN terminal is an input which enables or shuts down the device. If EN is a logic high, the device will be in
shutdown mode. When EN goes to logic low, the device will be enabled.
power-good (PG)
The PG terminal for the fixed voltage option devices is an open drain, active low output that indicates the status
of VO (output of the LDO). When VO reaches approximately 91% of the regulated voltage, PG will go to a low
impedance state. It will go to a high-impedance state when VO falls below approximately 89% (i.e. over load
condition) of the regulated voltage. The open drain output of the PG terminal requires a pullup resistor.
feedback (FB)
FB is an input terminal used for the adjustable-output option and must be connected to the output terminal either
directly, in order to generate the minimum output voltage of 1.22 V, or through an external feedback resistor
divider for other output voltages. The FB connection should be as short as possible. It is essential to route it in
such a way to minimize/avoid noise pickup. Adding RC networks between FB terminal and VO to filter noise is
not recommended because it may cause the regulator to oscillate.
       
    
 
SLVS293D − NOVEMBER 2000 − REVISED MAY 2002
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
detailed description (continued)
input voltage (IN)
The VIN terminal is an input to the regulator.
output voltage (OUTPUT)
The VOUTPUT terminal is an output to the regulator.
absolute maximum ratings over operating junction temperature range (unless otherwise noted)Ĕ
Input voltage range, VI 0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at EN −0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum PG voltage (fixed options only) 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak output current Internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage, VO (OUTPUT, FB) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating junction temperature range, TJ −40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD rating, HBM 2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD rating, CDM 500 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network terminal ground.
DISSIPATION RATING TABLE
PACKAGE RθJC (°C/W) RθJA (°C/W)§
TO−220 2 58.7
TO−263 2 38.7#
§For both packages, the RθJA values were computed using JEDEC high K board (2S2P)
with 1 ounce internal copper plane and ground plane. There was no air flow across the
packages.
RθJA was computed assuming a vertical, free standing TO-220 package with pins
soldered to the board. There is no heatsink attached to the package.
#RθJA was computed assuming a horizontally mounted TO-263 package with pins
soldered to the board. There is no copper pad underneath the package.
recommended operating conditions
MIN MAX UNIT
Input voltage, VI|| 2.8 5.5 V
Output voltage range, VO1.22 5 V
Output current, IO0 5 A
Operating virtual junction temperature, TJ−40 125 °C
|| To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load).
       
    
 
SLVS293D − NOVEMBER 2000 − REVISED MAY 2002
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range (TJ = −40°C to
125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 100 µF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
1.22 V VO 5.5 V, TJ = 25°C VO
Adjustable voltage
1.22 V VO 5.5 V 0.97 VO1.03 VO
V
Adjustable voltage
1.22 V VO 5.5 V, TJ = 0 to 125°C
(see Note 1) 0.98 VO1.02 VO
V
1.5 V Output
TJ = 25°C, 2.8 V < VI < 5.5 V 1.5
Output voltage (see Note 2)
1.5 V Output 2.8 V VI 5.5 V 1.455 1.545
V
Output voltage (see Note 2)
1.8 V Output
TJ = 25°C, 2.8 V < VI < 5.5 V 1.8 V
1.8 V Output 2.8 V VI 5.5 V 1.746 1.854
2.5 V Output
TJ = 25°C, 3.5 V < VI < 5.5 V 2.5
V
2.5 V Output 3.5 V VI 5.5 V 2.425 2.575 V
3.3 V Output
TJ = 25°C, 4.3 V < VI < 5.5 V 3.3
V
3.3 V Output 4.3 V VI 5.5 V 3.201 3.399 V
Quiescent current (GND current) (see Notes 2 and 3)
TJ = 25°C 125
A
Quiescent current (GND current) (see Notes 2 and 3) 200 µA
Output voltage line regulation (VO/VO) (see Note 3)
VO + 1 V VI 5.5 V, TJ = 25°C 0.04
%/V
Output voltage line regulation (VO/VO) (see Note 3) VO + 1 V VI < 5.5 V 0.1 %/V
Load regulation (see Note 2) 0.35 %/V
Output noise voltage TPS75515 BW = 300 Hz to 50 kHz, TJ = 25°C, VI = 2.8 V 35 µVrms
Output current limit VO = 0 V 5.5 10 14 A
Thermal shutdown junction temperature 150 °C
Standby current
EN = VI,T
J = 25°C 0.1 µA
Standby current EN = VI10 µA
FB input current TPS75501 FB = 1.5 V −1 1 µA
Power supply ripple rejection TPS75515 f = 100 Hz, TJ = 25°C,
VI = 2.8 V, IO = 5 A 60 dB
Minimum input voltage for valid PG IO(PG) = 300 µA, V(PG) 0.8 V 0 V
PG trip threshold voltage Fixed options only VO decreasing 89 93 %VO
PG hysteresis voltage Fixed options only Measured at VO0.5 %VO
PG output low voltage Fixed options only VI = 2.8 V, IO(PG) = 1 mA 0.15 0.4 V
PG leakage current Fixed options only V(PG) = 5 V 1µA
NOTES: 1. The adjustable option operates with a 2% tolerance over TJ = 0 to 125 °C.
2. IO = 1 mA to 5 A
3. If VO 2.5 V then VImin = 2.8 V, VImax = 5.5 V:
Line regulation (mV) +ǒ%ńVǓ VOǒVImax *2.8 VǓ
100 1000
If VO > 2.5 V then VImin = VO + 1 V, VImax = 5.5 V:
Line regulation (mV) +ǒ%ńVǓ
VOǒVImax *ǒVO)1V
ǓǓ
100 1000
       
    
 
SLVS293D − NOVEMBER 2000 − REVISED MAY 2002
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range (TJ = −40°C to
125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 100 µF (unless otherwise noted) (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EN = VI−1 1 µA
Input current (EN)EN = 0 V −1 0 1 µA
High level EN input voltage 2 V
Low level EN input voltage 0.7 V
Dropout voltage, (3.3 V output) (see Note 4)
IO = 5 A, VI = 3.2 V, TJ = 25°C 250
mV
V
O
Dropout voltage, (3.3 V output) (see Note 4) IO = 5 A, VI = 3.2 V 500 mV
VO
Discharge transistor current VO = 1.5 V, TJ = 25°C 10 25 mA
VI
UVLO TJ = 25°C, VI rising 2.2 2.75 V
VIUVLO hysteresis TJ = 25°C, VI falling 100 mV
NOTE 4: IN voltage equals VO(typ) − 100 mV ; TPS75515, TPS75518, and TPS75525 dropout voltage limited by input voltage range limitations
(i.e., TPS75533 input voltage is set to 3.2 V for the purpose of this test).
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VO
Output voltage
vs Output current 2, 3
VOOutput voltage vs Junction temperature 4, 5
Ground current vs Junction temperature 6
Power supply ripple rejection vs Frequency 7
Output spectral noise density vs Frequency 8
zoOutput impedance vs Frequency 9
VDO
Dropout voltage
vs Input voltage 10
VDO Dropout voltage vs Junction temperature 11
VIMinimum required input voltage vs Output voltage 12
Line transient response 13, 15
Load transient response 14, 16
VOOutput voltage and enable voltage vs Time (start-up) 17
Equivalent series resistance vs Output current 19, 20
       
    
 
SLVS293D − NOVEMBER 2000 − REVISED MAY 2002
8POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 2
IO − Output Current − A
TPS75533
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.330
3.270
3.315
3.285
3.255 15
3.345
0
− Output Voltage − V
VO
3
VI = 4.3 V
TJ = 25°C
24
3.3
Figure 3
IO − Output Current − A
TPS75515
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1.530
1.485
1.515
1.5
1.470
1.545
0
− Output Voltage − V
VO
1.455 152
VI = 2.8 V
TJ = 25°C
34
Figure 4
TJ − Junction Temperature − °C
TPS75533
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
− Output Voltage − V
VO
3.315
5 125
3.33
3.3
20 80
3.270
3.285
3.255
3.345 VI = 4.3 V
−40 −25 10 35 50 65 11095
Figure 5
TJ − Junction Temperature − °C
TPS75515
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
− Output Voltage − V
VO
1.470
1.485
1.455
1.530
VI = 2.8 V
1.5
1.515
1.545
−40 20 11035 95−25 −10 5 50 65 80 125
       
    
 
SLVS293D − NOVEMBER 2000 − REVISED MAY 2002
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 6
75
100
125
150
−40 −25 −10 5 20 35 50 65 80 95 110 125
TJ − Junction Temperature − °C
TPS755xx
GROUND CURRENT
vs
JUNCTION TEMPERATURE
Ground Current − Aµ
VI = 5 V
IO = 5 A
POWER SUPPLY RIPPLE REJECTION
vs
FREQUENCY
TPS75733
100k10k
PSRR − Power Supply Ripple Rejection − dB
f − Frequency − Hz
70
60
50
40
30
20
10
0
90
80
1k10010 1M
IO = 1 mA
IO = 5 A
10M
Figure 7
VI = 4.3 V
Co = 100 µF
TJ = 25°C
Figure 8
0
0.5
1
1.5
2
2.5
IO = 5 A
IO = 1 mA
f − Frequency − Hz
1010 100 1k 10k 100k
VI = 4.3 V
VO = 3.3 V
Co = 100 µF
TJ = 25°C
TPS75533
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
V/ HzOutput Spectral Noise Density − µ
Figure 9
TPS75533
OUTPUT IMPEDANCE
vs
FREQUENCY
f − Frequency − Hz
− Output Impedance −zo
10 100 100k 1M
0.001 10k1k 10M
1
100
IO = 1 mA
0.01
0.1
10
IO = 5 A
VI = 4.3 V
Co = 100 µF
TJ = 25°C
       
    
 
SLVS293D − NOVEMBER 2000 − REVISED MAY 2002
10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 10
0
50
100
150
200
250
300
350
400
450
2.5 3 3.5 4 4.5 5
TPS75501
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
VI − Input Voltage − V
− Dropout Voltage − mV
VDO
IO = 5 A
TJ = 25°C
TJ = −40°C
TJ = 125°C
Figure 11
0
50
100
150
200
250
300
350
400
−40 −25 −10 5 20 35 50 65 80 95 110 125
TJ − Junction Temperature − °C
− Dropout Voltage − mV
VDO
TPS75533
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
IO = 5 A
VO = 3.3 V
2
3
4
1.5 2.5 3.523
TJ = 125°C
TJ = 25°C
TJ = −40°C
IO = 5 A
− Minimum Required Input Voltage − V
MINIMUM REQUIRED INPUT VOLTAGE
vs
OUTPUT VOLTAGE
VO − Output Voltage − V
VI
1.75 2.25 2.75 3.25
2.8
Figure 12 Figure 13
VO− Change in
3.8
50
−50
TPS75515
LINE TRANSIENT RESPONSE
VI
t − Time − µs
0 15010050 200 250 350300 400 450 500
− Input Voltage − V
Output Voltage − mV
VO = 1.5 V
IO = 5 A
Co = 100 µF
2.8
−100
0
       
    
 
SLVS293D − NOVEMBER 2000 − REVISED MAY 2002
11
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
t − Time − µs
TPS75515
LOAD TRANSIENT RESPONSE
I − Output Current − A
O
VO
− Change in Output Voltage − mV
−100
0
0604020 80 100 140120 160 180 200
0
50
−50
VO = 1.5 V
Co = 100 µF
−150 5
di
dt +1.25 A
ms
Figure 14
100
150
TPS75533
LINE TRANSIENT RESPONSE
t − Time − µs
V
I
− Input Voltage − V
−100
5.3
−50
4.3
VO = 3.3 V
IO = 5 A
Co = 100 µF
50
0 15010050 200 250 350300 400 450 500
Figure 15
VO
− Change in Output Voltage − mV
0
100
Figure 16
t − Time − µs
TPS75533
LOAD TRANSIENT RESPONSE
I − Output Current − A
O
−100
0
200
100
VO =3 .3 V
Co = 100 µF
5
VO
− Change in Output Voltage − mV
0604020 80 100 140120 160 180 200
di
dt +1.25 A
ms
0
Figure 17
t − Time (Start-Up) − ms
VI = 4.3 V
IO = 10 mA
TJ = 25°C
0
3.3
0
0
4.3
0.2 10.4 0.6 0.8
− Output Voltage − V
VO
Enable Voltage − V
TPS75533
OUTPUT VOLTAGE AND ENABLE VOLTAGE
vs
TIME (START-UP)
       
    
 
SLVS293D − NOVEMBER 2000 − REVISED MAY 2002
12 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
IN
EN
OUT
+
GND Co
ESR
RL
VITo Load
Figure 18. Test Circuit for Typical Regions of Stability (Figures 19 and 20) (Fixed Output Options)
Figure 19
0.0105
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE
vs
OUTPUT CURRENT
10
IO − Output Current − A
ESR − Equivalent Series Resistance −
1
0.1
Region of Stability
0.015 Region of Instability
Co = 680 µF
TJ = 25°C
1234
Figure 20
0.0105
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE
vs
OUTPUT CURRENT
10
IO − Output Current − A
1
0.2
ESR − Equivalent Series Resistance −
Co = 47 µF
TJ = 25°C
Region of Stability
Region of Instability
1234
Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally,
and PWB trace resistance to Co.
       
    
 
SLVS293D − NOVEMBER 2000 − REVISED MAY 2002
13
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
THERMAL INFORMATION
The amount of heat that an LDO linear regulator generates is directly proportional to the amount of power it
dissipates during operation. All integrated circuits have a maximum allowable junction temperature (TJmax)
above which normal operation is not assured. A system designer must design the operating environment so
that the operating junction temperature (TJ) does not exceed the maximum junction temperature (TJmax). The
two main environmental variables that a designer can use to improve thermal performance are air flow and
external heatsinks. The purpose of this information is to aid the designer in determining the proper operating
environment for a linear regulator that is operating at a specific power level.
In general, the maximum expected power (PD(max)) consumed by a linear regulator is computed as:
PDmax +ǒVI(avg) *VO(avg)Ǔ IO(avg) )VI(avg)xI
(Q) (1)
Where:
VI(avg) is the average input voltage.
VO(avg) is the average output voltage.
IO(avg) is the average output current.
I(Q) is the quiescent current.
For most TI LDO regulators, the quiescent current is insignificant compared to the average output current;
therefore, the term VI(avg) x I(Q) can be neglected. The operating junction temperature is computed by adding
the ambient temperature (TA) and the increase in temperature due to the regulators power dissipation. The
temperature rise is computed by multiplying the maximum expected power dissipation by the sum of the thermal
resistances between the junction and the case (RθJC), the case to heatsink (RθCS), and the heatsink to ambient
(RθSA). Thermal resistances are measures of how effectively an object dissipates heat. Typically, the larger the
device, the more surface area available for power dissipation and the lower the object’s thermal resistance.
Figure 21 illustrates these thermal resistances for (a) a TO−220 package attached to a heatsink, and (b) a
TO−263 package mounted on a JEDEC High-K board.
A
B
C
A
B
C
TJ
A
RθJC
TC
B
RθCS
TA
C
RθSA
(a)
(b)
TO−263 Package
TO−220 Package
Figure 21. Thermal Resistances
       
    
 
SLVS293D − NOVEMBER 2000 − REVISED MAY 2002
14 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
THERMAL INFORMATION
Equation 2 summarizes the computation:
TJ+TA)PDmax x ǒRθJC )RθCS )RθSAǓ(2)
The RθJC is specific to each regulator as determined by its package, lead frame, and die size provided in the
regulator’s datasheet. The RθSA is a function of the type and size of heatsink. For example, black body radiator
type heatsinks, like the one attached to the TO−220 package in Figure 21(a), can have RθCS values ranging
from 5°C/W for very large heatsinks to 50°C/W for very small heatsinks. The RθCS is a function of how the
package is attached to the heatsink. For example, if a thermal compound is used to attach a heatsink to a
TO−220 package, RθCS of 1°C/W is reasonable.
Even i f n o external black body radiator type heatsink is attached to the package, the board on which the regulator
is mounted will provide some heatsinking through the pin solder connections. Some packages, like the TO−263
and TI’s TSSOP PowerPAD packages, use a copper plane underneath the package or the circuit board’s
ground plane for additional heatsinking to improve their thermal performance. Computer aided thermal
modeling can be used to compute very accurate approximations of an integrated circuit’s thermal performance
in di fferent operating environments (e.g., di fferent types of circuit boards, different types and sizes of heatsinks,
and different air flows, etc.). Using these models, the three thermal resistances can be combined into one
thermal resistance between junction and ambient (RθJA). This RθJA is valid only for the specific operating
environment used in the computer model.
Equation 2 simplifies into equation 3:
TJ+TA)PDmax x RθJA (3)
Rearranging equation 3 gives equation 4:
RθJA +TJ–TA
PDmax (4)
Using equation 3 and the computer model generated curves shown in Figures 22 and 25, a designer can quickly
compute the required heatsink thermal resistance/board area for a given ambient temperature, power
dissipation, and operating environment.
PowerPAD is a trademark of Texas Instruments.
       
    
 
SLVS293D − NOVEMBER 2000 − REVISED MAY 2002
15
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
THERMAL INFORMATION
TO−220 power dissipation
The TO−220 package provides an effective means of managing power dissipation in through-hole applications.
The TO−220 package dimensions are provided in the Mechanical Data section at the end of the data sheet. A
heatsink can be used with the TO−220 package to effectively lower the junction-to-ambient thermal resistance.
To illustrate, the TPS75525 in a TO−220 package was chosen. For this example, the average input voltage is
3.3 V, the output voltage is 2.5 V, the average output current is 3 A, the ambient temperature 55°C, the air flow
is 150 LFM, and the operating environment is the same as documented below. Neglecting the quiescent current,
the maximum average power is:
PDmax +(3.3–2.5
)Vx3A +2.4 W (5)
Substituting TJmax for TJ into equation 4 gives equation 6:
RθJAmax +(125 55)°Cń2.4 W +29°CńW(6)
From Figure 22, RθJA vs Heatsink Thermal Resistance, a heatsink with RθSA = 22°C/W is required to dissipate
2.4 W. The model operating environment used in the computer model to construct Figure 22 consisted of a
standard JEDEC High-K board (2S2P) with a 1 oz. internal copper plane and ground plane. Since the package
pins were soldered to the board, 450 mm2 of the board was modeled as a heatsink. Figure 23 shows the side
view of the operating environment used in the computer model.
Figure 22
5
15
25
35
45
55
65
0510152025
RθSA − Heatsink Thermal Resistance − °C/W
THERMAL RESISTANCE
vs
HEATSINK THERMAL RESISTANCE
− Thermal Resistance −
θJA
R C/W
°
No Heatsink
Natural Convection
Air Flow = 150 LFM
Air Flow = 250 LFM
Air Flow = 500 LFM
       
    
 
SLVS293D − NOVEMBER 2000 − REVISED MAY 2002
16 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
THERMAL INFORMATION
TO−220 power dissipation (continued)
1 oz. Copper
Power Plane
1 oz. Copper
Ground Plane
0.21 mm 0.21 mm
Figure 23
From the data in Figure 22 and rearranging equation 4, the maximum power dissipation for a dif ferent heatsink
RθSA and a specific ambient temperature can be computed (see Figure 24).
Figure 24
1
10
01020
− Power Dissipation Limit − W
PD
POWER DISSIPATION
vs
HEATSINK THERMAL RESISTANCE
RθSA − Heatsink Thermal Resistance − °C/W
No Heatsink
TA = 55°C
Natural Convection
Air Flow = 150 LFM
Air Flow = 250 LFM
Air Flow = 500 LFM
       
    
 
SLVS293D − NOVEMBER 2000 − REVISED MAY 2002
17
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
THERMAL INFORMATION
TO−263 power dissipation
The TO−263 package provides an effective means of managing power dissipation in surface mount
applications. The TO−263 package dimensions are provided in the Mechanical Data section at the end of the
data sheet. The addition of a copper plane directly underneath the TO−263 package enhances the thermal
performance of the package.
To illustrate, the TPS75525 in a TO−263 package was chosen. For this example, the average input voltage is
3.3 V, the output voltage is 2.5 V, the average output current is 3 A, the ambient temperature 55°C, the air flow
is 150 LFM, and the operating environment is the same as documented below. Neglecting the quiescent current,
the maximum average power is:
PDmax +(3.3–2.5
)Vx3A +2.4 W (7)
Substituting TJmax for TJ into equation 4 gives equation 8:
RθJAmax +(125 55)°Cń2.4 W +29°CńW(8)
From Figure 25, RθJA vs Copper Heatsink Area, the ground plane needs to be 2 cm2 for the part to dissipate
2.4 W. The model operating environment used in the computer model to construct Figure 25 consisted of a
standard JEDEC High-K board (2S2P) with a 1 oz. internal copper plane and ground plane. The package is
soldered to a 2 oz. copper pad. The pad is tied through thermal vias to the 1 oz. ground plane. Figure 26 shows
the side view of the operating environment used in the computer model.
Figure 25
15
20
25
30
35
40
0 0.01 0.1 1 10 100
THERMAL RESISTANCE
vs
COPPER HEATSINK AREA
Copper Heatsink Area − cm2
− Thermal Resistance −
θJA
R C/W
°
No Air Flow
150 LFM
250 LFM
       
    
 
SLVS293D − NOVEMBER 2000 − REVISED MAY 2002
18 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
THERMAL INFORMATION
TO−263 power dissipation (continued)
1 oz. Copper
Power Plane
1 oz. Copper
Ground Plane
2 oz. Copper Solder Pad
with 25 Thermal Vias
Thermal Vias, 0.3 mm
Diameter, 1.5 mm Pitch
Figure 26
From the data in Figure 25 and rearranging equation 4, the maximum power dissipation for a different ground
plane area and a specific ambient temperature can be computed (see Figure 27).
Figure 27
1
2
3
4
5
0 0.01 0.1 1 10 100
MAXIMUM POWER DISSIPATION
vs
COPPER HEATSINK AREA
− Maximum Power Dissipation − W
PD
Copper Heatsink Area − cm2
TA = 55°C
No Air Flow
150 LFM
250 LFM
       
    
 
SLVS293D − NOVEMBER 2000 − REVISED MAY 2002
19
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
programming the TPS75501 adjustable LDO regulator
The output voltage of the TPS75501 adjustable regulator is programmed using an external resistor divider as
shown in Figure 28. The output voltage is calculated using:
VO+Vref ǒ1)R1
R2Ǔ(
9)
Where:
V
ref
= 1.224 V typ (the internal reference voltage)
Resistors R1 and R2 should be chosen for approximately 40-µA divider current. Lower value resistors can be
used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage
currents at FB increase the output voltage error. The recommended design procedure is to choose
R2 = 30.1 k to set the divider current at 40 µA and then calculate R1 using:
R1 +ǒVO
Vref *1Ǔ R2 (10)
VO
VI
OUT
FB
R1
R2
GND
EN
IN
0.7 V
2 V
TPS75501
1 µF
Co
OUTPUT VOLTAGE
PROGRAMMING GUIDE
OUTPUT
VOLTAGE R1 R2
2.5 V
3.3 V
3.6 V
UNIT
31.6
51
58.3
30.1
30.1
30.1
k
k
k
Figure 28. TPS75501 Adjustable LDO Regulator Programming
regulator protection
The TPS755xx PMOS-pass transistor has a built-in back diode that conducts reverse currents when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be
appropriate.
The TPS755xx also features internal current limiting and thermal protection. During normal operation, the
TPS755xx limits output current to approximately 10 A. When current limiting engages, the output voltage scales
back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device
failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of
the device exceeds 150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below
130°C(typ), regulator operation resumes.