CY7S1049G
CY7S1049GE
4-Mbit (512K words × 8-bit) Static RAM
with PowerSnooze™
and Error Correcting Code (ECC)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-95414 Rev. *F Revised April 3, 2018
4-Mbit (512K wo rds × 8-bit) Static RAM with Powe rSnooze™ and Er ror Correcting Code (ECC)
Features
■High speed
❐Access time (tAA) = 10 ns / 15 ns
■Ultra-low power Deep-Sleep (DS) current
❐IDS = 15 µA
■Low active and standby currents
❐Active Current ICC = 38-mA typical
❐Standby Current ISB2 = 6-mA typical
■Wide operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V,
4.5 V to 5.5 V
■Embedded ECC for single-bit error correction[1, 2]
■Error indication (ERR) pin to indicate 1-bit error detection and
correction
■1.0-V data retention
■TTL- compatible inputs and outputs
■Available in Pb-free 44-pin TSOP II, and 36-pin (400-mil)
molded SOJ
Functional Description
The CY7S1049G/CY7S1049GE[1] is a high-performance
PowerSnooze™ static RAM organized as 512K words × 8 bits.
This device features fast access times (10 ns) and a unique
ultra-low power Deep-Sleep mode[3]. With Deep-Sleep mode
currents as low as 15 µA, the CY7S1049G/CY7S1049GE
devices combine the best features of fast and low- power SRAMs
in industry-standard package options. The device also features
embedded ECC. logic which can detect and correct single-bit
errors in the accessed location.
Deep-Sleep input (DS) must be deasserted HIGH for normal
operating mode.
To perform data writes, assert the Chip Enable (CE) and Write
Enable (WE) inputs LOW, and provide the data and address on
device data pins (I/O0 through I/O7) and address pins (A0
through A18) respectively.
To perform data reads, assert the Chip Enable (CE) and Output
Enable (OE) inputs LOW and provide the required address on
the address lines. Read data is accessible on the I/O lines (I/O0
through I/O7).
The device is placed in a low-power Deep-Sleep mode when the
Deep-Sleep input (DS) is asserted LOW. In this state, the device
is disabled for normal operation and is placed in a low power data
retention mode. The device can be activated by deasserting the
Deep-Sleep input (DS) to HIGH.
The CY7S1049G is available in 44-pin TSOP II, and 36-pin
Molded SOJ (400 Mils).
Product Portfolio
Product[4] Range VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC,
(mA) Standby, ISB2
(mA)
Deep-Sleep
current (µA)
f = fmax
Typ [5] Max Typ [5] Max Typ [5] Max
CY7S1049G(E)18 Industrial 1.65 V–2.2 V 15 – 40 6 8 – 15
CY7S1049G(E)30 2.2 V–3.6 V 10 38 45
CY7S1049G(E) 4.5–5.5 V 10 38 45
Notes
1. This device does not support automatic write back on error detection.
2. SER FIT Rate <0.1 FIT/Mb. Refer AN88889 for details.
3. Refer AN89371 for details on PowerSnooze™ feature.
4. ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information on page 17 for details.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC =3V
(for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
Document Number: 001-95414 Rev. *F Page 2 of 21
CY7S1049G
CY7S1049GE
Logic Block Diagram – CY7S1049G
512Kx8
RAMARRAY
ROWDECODER
A1
A2
A3
A4
A5
A6
A7
A8
A9
A0
COLUMN
DECODER
A10
SENSE
AMPLIFIERS
ECCDECODER
A11
A12
A13
A14
A15
A16
A17
A18
ECCENCODER DATAIN
DRIVERS
I/O0‐I/O7
WE
OE CE
Power Management
Block
DS
Logic Block Diagram – CY7S1049GE
512Kx8
RAMARRAY
ROWDECODER
A1
A2
A3
A4
A5
A6
A7
A8
A9
A0
COLUMN
DECODER
A10
SENSE
AMPLIFIERS
ECCDECODER
A11
A12
A13
A14
A15
A16
A17
A18
ECCENCODER DATAIN
DRIVERS
I/O0‐I/O7
WE
OE CE
ERR
Power Management
Block
DS
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CY7S1049G
CY7S1049GE
Contents
Pin Configurations ........................................................... 4
Maximum Ratings ............................................................. 6
Operating Range ............................................................... 6
DC Electrical Characteristics .......................................... 6
Capacitance ...................................................................... 7
Thermal Resistance .......................................................... 7
AC Test Loads and Waveforms ....................................... 8
Data Retention Characteristics ....................................... 9
Data Retention Waveform ................................................ 9
Deep-Sleep Mode Characteristics ................................. 10
AC Switching Characteristics ....................................... 11
Switching Waveforms .................................................... 12
Truth Table ...................................................................... 16
ERR Output – CY7S1049GE ........................................... 16
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 17
Package Diagrams .......................................................... 18
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 21
Worldwide Sales and Design Support ....................... 21
Products .................................................................... 21
PSoC® Solutions ...................................................... 21
Cypress Developer Community ................................. 21
Technical Support ..................................................... 21
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Pin Configurations
Figure 1. 44-pin TSOP II pinout without ERR [6]
Figure 2. 44-pin TSOP II pinout with ERR [6, 7]
NCNC 243
DSA0 342
A18A1 441
A15A4 738
A16
639
A3
I/O7I/O0 936
I/O6I/O1 10 35
VSSVCC 11 34
VCCVSS 12 33
I/O5
I/O2 13 32
I/O4
I/O3 14 31
A14
/WE 15 30
A13
A5 16 29
A12A6 17 28
A11A7 18 27
A10A8 19 26
NCA9 20 25
NC
NC 21 24
NC 22 23
NCNC 144
/OE/CE 837
A17A2 540
NC
44-pin TSOP II
NCNC 243
DSA0 342
A18A1 441
A15A4 738
A16
639
A3
I/O7I/O0 936
I/O6I/O1 10 35
VSSVCC 11 34
VCCVSS 12 33
I/O5
I/O2 13 32
I/O4
I/O3 14 31
A14
/WE 15 30
A13
A5 16 29
A12A6 17 28
A11A7 18 27
A10A8 19 26
NCA9 20 25
ERR
NC 21 24
NC 22 23
NCNC 144
/OE/CE 837
A17A2 540
NC
44-pin TSOP II
Notes
6. NC pins are not connected internally to the die.
7. ERR is an output pin.
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CY7S1049G
CY7S1049GE
Figure 3. 36-pin SOJ pinout without ERR [8]
Figure 4. 36-pin SOJ pinout with ERR [8, 9]
Pin Configurations (continued)
SOJ
A18A1235
A17
A2334
A16A3433
I/O7I/O0730
OE
631
CE
GNDVCC 928
VCCGND 10 27
I/O5I/O211 26
I/O4I/O312 25
A14
WE 13 24
A13
A514 23
A12
A615 22
A11
A716 21
A10
A817 20
NCA918 19
DSA0136
I/O6I/O1829
A15A4532
SOJ
A18A1235
A17A2334
A16A3433
I/O7I/O0730
OE
631
CE
GNDVCC 928
VCC
GND 10 27
I/O5I/O211 26
I/O4I/O312 25
A14
WE 13 24
A13
A514 23
A12
A615 22
A11A716 21
A10
A817 20
ERRA918 19
DSA0136
I/O6I/O1829
A15A4532
Notes
8. NC pins are not connected internally to the die.
9. ERR is an output pin.
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CY7S1049G
CY7S1049GE
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature
with power applied ................................... –55 C to +125 C
Supply voltage
on VCC relative to GND [10] ................. –0.5 V to VCC + 0.5 V
DC voltage applied to outputs
in HI-Z State [10] .................................. –0.5 V to VCC + 0.5 V
DC input voltage [10] ........................... –0.5 V to VCC + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Latch-up current .................................................... > 140 mA
Operating Range
Range Ambient Temperature VCC
Industrial –40 C to +85 C 1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
DC Electrical Characteristics
Over the Operating Range of –40 C to +85 C
Parameter Description Test Conditions 10 ns/ 15 ns Unit
Min Typ [11] Max
VOH Output HIGH
voltage
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA 1.4 – – V
2.2 V to 2.7 V VCC = Min, IOH = –1.0 mA 2 – –
2.7 V to 3.6 V VCC = Min, IOH = –4.0 mA 2.4 – –
4.5 V to 5.5 V VCC = Min, IOH = –4.0 mA 2.4 – –
4.5 V to 5.5 V VCC = Min, IOH = –0.1 mA VCC – 0.5 [12] ––
VOL Output LOW
voltage
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA – – 0.2 V
2.2 V to 2.7 V VCC = Min, IOL = 2 mA – – 0.4
2.7 V to 3.6 V VCC = Min, IOL = 8 mA – – 0.4
4.5 V to 5.5 V VCC = Min, IOL = 8 mA – – 0.4
VIH[10, 13] Input HIGH
voltage
1.65 V to 2.2 V – 1.4 – VCC + 0.2 V
2.2 V to 2.7 V – 2 – VCC + 0.3
2.7 V to 3.6 V – 2 – VCC + 0.3
4.5 V to 5.5 V – 2 – VCC + 0.5
VIL [10, 13] Input LOW
voltage
1.65 V to 2.2 V – –0.2 – 0.4 V
2.2 V to 2.7 V – –0.3 – 0.6
2.7 V to 3.6 V – –0.3 – 0.8
4.5 V to 5.5 V – –0.5 – 0.8
IIX Input leakage current GND < VIN < VCC –1 – +1 A
IOZ Output leakage current GND < VOUT < VCC, Output disabled –1 – +1 A
ICC VCC operating supply current
VCC = Max,
IOUT = 0 mA,
CMOS levels
f = 100 MHz – 38 45 mA
f = 66.7 MHz – – 40
ISB1 Standby current – TTL inputs Max VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX
––15mA
Notes
10. VIL (min) = –2.0 V and VIH (max) = VCC + 2 V for pulse durations of less than 20 ns.
11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC =3V
(for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
12. Guaranteed by design and not tested.
13. For the DS pin, VIH (min) is VCC – 0.2 V and VIL (max) is 0.2 V.
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CY7S1049G
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ISB2 Standby current – CMOS inputs Max VCC, CE > VCC – 0.2 V,
DS > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
–68mA
IDS Deep-Sleep current Max VCC, CE > V CC – 0.2 V, DS < 0 . 2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
– – 15 µA
DC Electrical Characteristics (continued)
Over the Operating Range of –40 C to +85 C
Parameter Description Test Conditions 10 ns/ 15 ns Unit
Min Typ [11] Max
Capacitance
Parameter [14] Description Test Conditions All packages Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VCC(typ) 10 pF
COUT I/O capacitance 10 pF
Thermal Resistance
Parameter [14] Description Test Conditions 36-pin SOJ
Package
44-pin TSOP II
Package Unit
JA Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
59.52 68.85 C/W
JC Thermal resistance
(junction to case)
31.48 15.97 C/W
Note
14. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-95414 Rev. *F Page 8 of 21
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AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms [15]
90%
10%
VHIGH
GND
90%
10%
All Input Pulses
VCC
Output
5 pF*
* Including
JIG and
Scope (b)
R1
R2
Rise Time: Fall Time:
> 1 V/ns
(c)
Output
50
Z
0
= 50
V
TH
30 pF*
* Capacitive Load Consists
of all Components of the
Test Environment
HI-Z Characteristics:
(a)
> 1 V/ns
Parameters 1.8 V 3.0 V 5.0 V Unit
R1 1667 317 317
R2 1538 351 351
VTH VCC/2 1.5 1.5 V
VHIGH 1.8 3.0 3.0 V
Note
15. Full-device AC operation assumes a 100-s ramp time from 0 to VCC(min) or 100-s wait time after VCC stabilization.
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Data Retention Characteristics
Over the Operating Range of –40C to +85 C
Parameter Description Conditions [16] Min Max Unit
VDR VCC for data retention – 1.0 – V
ICCDR Data retention current VCC = VDR, CE > VCC – 0.2 V, DS > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
–8mA
tCDR [17] Chip deselect to data retention
time
–0–ns
tR[17, 18] Operation recovery time 2.2 V < VCC < 5.5 V 10 – ns
VCC < 2.2 V 15 – ns
Data Retention Waveform
Figure 6. Data Retention Waveform [18]
tCDR tR
VDR = 1.0 V
DATA RETENTION MODE
VCC(min) VCC(min)
VCC
CE
Notes
16. DS signal must be HIGH during Data Retention Mode.
17. These parameters are guaranteed by design.
18. Full-device operation requires linear VCC ramp from VDR to VCC(min.) 100 s or stable at VCC(min.) 100 s.
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Deep-Sleep Mode Characteristics
Over the Operating Range of –40 C to +85 C
Parameter Description Conditions Min Max Unit
IDS Deep-Sleep mode current VCC = VCC (max), DS < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
–15µA
tPDS[19] Minimum time for DS to be LOW
for part to successfully exit
Deep-Sleep mode
– 100 – ns
tDS[20] DS assertion to Deep-Sleep
mode transition time
––1ms
tDSCD[19] DS deassertion to chip disable If tPDS > tPDS(min) –100s
If tPDS < tPDS(min) –0s
tDSCA DS deassertion to chip access
(Active/Standby)
If tPDS > tPDS(min) 300 – s
If tPDS < tPDS(min)
Figure 7. Active, Standby, and Deep-Sleep Operation Modes
DS
Chip
Access
Mode Active/Standby
Mode
Standby
Mode DeepSleepMode
tDS tDSCD
Allowed NotAllowed Allowed
ENABLE/
DISABLE DON’TCARE
CE DISABLE ENABLE/
DISABLE
Standby
Mode
tDSCA
Active/Standby
Mode
tPDS
Notes
19. CE must be pulled HIGH within tDSCD time of DS de-assertion to avoid SRAM data loss.
20. After assertion of DS signal, device will take a maximum of tDS time to stabilize to Deep-Sleep current IDS. During this period, DS signal must continue to be asserted
to logic level LOW to keep the device in Deep-Sleep mode.
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AC Switching Characteristics
Over the Operating Range of –40 C to +85 C
Parameter [21] Description 10 ns 15 ns Unit
Min Max Min Max
Read Cycle
tRC Read cycle time 10 – 15 – ns
tAA Address to data valid – 10 – 15 ns
tOHA Data hold from address change 3 – 3 – ns
tACE CE LOW to data valid – 10 – 15 ns
tDOE OE LOW to data valid – 4.5 – 8 ns
tLZOE OE LOW to low impedance [22, 23, 24] 0–0–ns
tHZOE OE HIGH to HI-Z [22, 23, 24] –5–8ns
tLZCE CE LOW to low impedance [22, 23, 24] 3–3–ns
tHZCE CE HIGH to HI-Z [22, 23, 24] –5–8ns
tPU CE LOW to power-up [24] 0–0–ns
tPD CE HIGH to power-down [24] –10–15ns
Write Cycle [25, 26]
tWC Write cycle time 10 – 15 – ns
tSCE CE LOW to write end 7 – 12 – ns
tAW Address setup to write end 7 – 12 – ns
tHA Address hold from write end 0–0 – ns
tSA Address setup to write start 0 – 0 – ns
tPWE WE pulse width 7 – 12 – ns
tSD Data setup to write end 5 – 8 – ns
tHD Data hold from write end 0 – 0 – ns
tLZWE WE HIGH to low impedance [22, 23, 24] 3–3–ns
tHZWE WE LOW to HI-Z [22, 23, 24] –5–8ns
Notes
21. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the read cycle use output loading shown in part (a) of Figure 5 on page 8, unless specified otherwise.
22. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 8. Transition is measured 200 mV from steady state voltage.
23. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
24. These parameters are guaranteed by design.
25. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL ,DS = VIH and WE, CE, signals must be LOW
and DS must be HIGH to initiate a write, and a HIGH transition of any of WE, CE, signals or LOW transition on DS signal can terminate the operation.
The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
26. The minimum write pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be the sum of tHZWE and tSD.
Document Number: 001-95414 Rev. *F Page 12 of 21
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Switching Waveforms
Figure 8. Read Cycle No. 1 of CY7S1049G (Address Transition Controlled) [27, 28, 29]
Figure 9. Read Cycle No. 2 of CY7S1041GE (Address Transition Controlled) [27, 28, 29]
ADDRESS
DATA I/O PREVIOUS DATAOUT
VALID DATAOUT VALID
tRC
tOHA
tAA
ADDRESS
DATA I/O PREVIOUS DATAOUT
VALID DATAOUT VALID
tRC
tOHA
tAA
ERR PREVIOUS ERR VALID ERR VALID
tOHA
tAA
Notes
27. The device is continuously selected. OE = VIL, CE = VIL.
28. WE is HIGH for read cycle.
29. DS is HIGH for chip access.
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Figure 10. Read Cycle No. 3 (OE Controlled) [30, 31, 32]
Switching Waveforms (continued)
tRC
tHZCE
tPD
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE DATA OUT
VALID HIGH
IMPEDANCE
ADDRESS
CE
OE
tHZOE
ISB
VCC
SUPPLY
CURRENT
DATA I /O
Notes
30. WE is HIGH for read cycle.
31. Address valid prior to or coincident with CE LOW transition.
32. DS must be HIGH for chip access.
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Figure 11. Write Cycle No. 1 (CE Controlled) [33, 34, 35]
Figure 12. Write Cycle No. 2 (WE Controlled, OE LOW) [33, 34, 35, 36]
Switching Waveforms (continued)
ADDRESS
CE
WE
DATA I/O
OE
tWC
tSCE
tAW
tSA
tPWE
tHA
tHD
tHZOE tSD
DATAIN VALID
ADDRESS
CE
DATA I/O
tWC
tSCE
tHD
tSD
tAW tHA
tSA tPWE
tLZWE
tHZWE
WE
DATAIN VALID
Notes
33. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, DS = VIH and WE, CE signals must be LOW
and DS must be HIGH to initiate a write, and a HIGH transition of any of WE, CE signals or LOW transition on DS signal can terminate the operation.
The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
34. Data I/O is in HI-Z state if CE = VIH, or OE = VIH.
35. DS must be HIGH for chip access.
36. The minimum write pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
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Figure 13. Write Cycle No. 3 (WE Controlled) [37, 38, 39]
Switching Waveforms (continued)
ADDRESS
CE
WE
D A TA I/O
OE
tWC
tSCE
tAW
tSA
tPWE
tHA
tHD
tHZOE tSD
DATAIN V A LID
Note 40
Notes
37. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, DS = VIH and WE, CE, signals must be LOW
and DS must be HIGH to initiate a write, and a HIGH transition of any of WE, CE, signals or LOW transition on DS signal can terminate the operation.
The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
38. Data I/O is in HI-Z state if CE = VIH, or OE = VIH or DS = VIL.
39. DS must be HIGH for chip access.
40. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-95414 Rev. *F Page 16 of 21
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Truth Table
DS CE OE WE I/O0–I/O7Mode Power
HHX
[41] X[41] HIGH-Z Standby Standby (ISB)
H L L H Data out Read all bits Active (ICC)
H L X L Data in Write all bits Active (ICC)
H L H H HI-Z Selected, outputs disabled Active (ICC)
L[42] X X X HI-Z Deep-Sleep Deep-Sleep Ultra Low Power (IDS)
ERR Output – CY7S1049GE
Output [43] Mode
0 Read operation, no single-bit error in the stored data.
1 Read operation, single-bit error detected and corrected.
High-Z Device deselected / outputs disabled / Write operation
Notes
41. The input voltage levels on these pins should be either at VIH or VIL.
42. VIL on DS must be < 0.2 V.
43. ERR is an Output pin.If not used, this pin should be left floating.
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Ordering Code Definitions
Ordering Information
Speed
(ns)
Voltage
Range Ordering Code Package
Diagram Package Type (All Pb-free) Operating
Range
10 2.2 V–3.6 V CY7S1049G30-10VXI 51-85090 36-pin SOJ Industrial
CY7S1049G30-10VXIT 51-85090 36-pin SOJ, Tape and Reel
CY7S1049GE30-10VXI 51-85090 36-pin SOJ, ERR Output
CY7S1049GE30-10VXIT 51-85090 36-pin SOJ, ERR Output, Tape and Reel
SCY 1 -XX X7 04 G9 XX X
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range: X = I
I = Industrial
Pb-free
Package Type: XX = V
V = 36-pin SOJ
Speed: XX = 10
10 = 10 ns
Voltage Range: XX = 30
30 = 2.2 V to 3.6 V
X = blank or E
blank = without ERR output; E = with ERR Output
Process Technology: Revision Code “G” = 65 nm Technology
Data Width: 9 = × 8-bits
Density: 04 = 4-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
S = Deep-Sleep feature
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
XX
XX
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Package Diagrams
Figure 14. 36-pin SOJ V36.4 (Molded) Package Outline, 51-85090
Figure 15. 44-pin TSOP II Package Outline, 51-85087
51-85090 *G
51-85087 *E
Document Number: 001-95414 Rev. *F Page 19 of 21
CY7S1049G
CY7S1049GE
Acronyms Document Conventions
Units of Measure
Acronym Description
CE Chip Enable
CMOS Complementary Metal Oxide Semiconductor
I/O Input/Output
OE Output Enable
SOJ Small-Outline J-lead
SRAM Static Random Access Memory
TSOP Thin Small Outline Package
TTL Transistor-Transistor Logic
WE Write Enable
ECC Write Enable
Symbol Unit of Measure
°C degrees Celsius
MHz megahertz
Amicroampere
smicrosecond
mA milliampere
mm millimeter
ns nanosecond
ohm
%percent
pF picofarad
Vvolt
Wwatt
Document Number: 001-95414 Rev. *F Page 20 of 21
CY7S1049G
CY7S1049GE
Document History Page
Document Title: CY7S1049G/CY7S1049GE, 4-Mbit (512K words × 8-bit) Sta t i c R A M w i t h P o w e r S n o o z e ™ a n d Error Correcting
Code (ECC)
Document Number: 001-95414
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
*B 5025315 VINI 11/24/2015 Changed status from Preliminary to Final.
*C 5090263 NILE 01/18/2016 Updated Ordering Information:
Updated part numbers.
Completing Sunset Review.
*D 5428860 NILE 09/07/2016 Updated Functional Description:
Added Note 1 and referred the same note in “CY7S1049G/CY7S1049GE”.
Updated Maximum Ratings:
Updated Note 10 (Replaced “2 ns” with “20 ns”).
Updated DC Electrical Characteristics:
Changed minimum value of VOH parameter from 2.2 V to 2.4 V corresponding
to Operating Range “2.7 V to 3.6 V” and Test Condition
“VCC = Min, IOH = –4.0 mA”.
Changed minimum value of VIH parameter from 2.2 V to 2 V corresponding to
Operating Range “4.5 V to 5.5 V”.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*E 5981584 AESATMP8 12/01/2017 Updated logo and Copyright.
*F 6120487 NILE 04/03/2018 Updated Features:
Referred Note 1 in “Embedded ECC for single-bit error correction”.
Added Note 2 and referred the same note in “Embedded ECC for single-bit
error correction”.
Updated Functional Description:
Added Note 3 and referred the same note at the end of sentence “This device
features fast access times (10 ns) and a unique ultra-low power Deep-Sleep
mode”.
Updated to new template.
Completing Sunset Review.
Document Number: 001-95414 Rev. *F Revised April 3, 2018 Page 21 of 21
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