STw5095 Low-power asynchronous stereo audio Codec with integrated power amplifiers Features 20 bit audio resolution, 8 kHz to 96 kHz independent rate ADC and DAC Asynchronous sampling ADC and DAC: they do not require oversampled clock and information on the audio data sampling frequency (fs). Jitter tolerant fs 4 MHz to 32 MHz master clock range I2C/SPI compatible control I/F Stereo headphones drivers, handsfree loudspeaker driver, line out drivers Mixable analog line inputs Analog output drivers Voice filters: 8/16 kHz with voice channel filters Automatic gain control for microphone and linein inputs Stereo headphones outputs driving capability: 40 mW (0.1% THD) over 16 with 40 dB range programmable gain Two programmable master/slave serial audio data interfaces (I2S, SPI, PCM compatible and other formats) Common mode voltage headphones driver (phantom ground) Balanced loudspeaker output driving capability: up to 500 mW (VCCLS>3.5 V; 1% THD) over 8 with 30 dB range programmable gain Transient supression filter during power up and power down Balanced/unbalanced stereo line outputs driving capability 1 k Frequency programmable clock outputs Multibit modulators with data weighted averaging ADC and DAC DSP functions for bass-treble-volume control, mute, mono/stereo selection, voice channel filters, de-emphasis filter and dynamic compression. 93 dB dynamic range ADC, 0.001% THD with full scale output @ 2.7 V 95 dB dynamic range DAC, 0.02% THD performance @ 2.7 V over 16 load Analog inputs Selectable stereo differential or single-ended microphone amplifier inputs with 51dB range programmable gain One microphone biasing output Microphone plug-in and push-button detection input August 2009 STw5095 TFBGA64 5x5 (64 pins) Selectable stereo differential or single-ended line inputs with 38 dB range programmable gain Applications Digital cellular telephones with mp3 player, stereo recorder, fm radio stereo listening and recording functions, live music recording Portable digital players and recorders Description STw5095 is a low power asynchronous stereo audio CODEC device with headphones amplifiers for high quality audio listening and recording. Rev 5 1/72 www.stericsson.com 1 Contents STw5095 Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 2/72 4.1 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 Device programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 Power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 Master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 Data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 Clock generators and master mode function . . . . . . . . . . . . . . . . . . . . . . 15 4.7 Audio digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.8 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.9 Analog output drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.10 Analog mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.11 AD path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.12 DA path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.13 Analog-only operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.14 Automatic Gain Control (AGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.15 Interrupt request: IRQ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.16 Headset plug-in and push-button detection . . . . . . . . . . . . . . . . . . . . . . . 21 4.17 Microphone biasing circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 Supply and power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3 Gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4 DSP control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.5 Analog functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.6 Digital audio interfaces master mode and clock generators . . . . . . . . . . . 34 STw5095 6 Contents 5.7 Digital audio interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.8 Digital filters, software reset and master clock control . . . . . . . . . . . . . . . 38 5.9 Interrupt control and control interface SPI out mode . . . . . . . . . . . . . . . . 38 5.10 AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Control interface and master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.1 Control interface I2C mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.2 Control interface SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.3 Master clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7 Audio interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8 Timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9 Operative ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10 11 9.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.2 Operative supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.3 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.4 Typical power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.1 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.2 AMCK with sinusoidal input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.3 Analog interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.4 Headset plug-in and push-button detector . . . . . . . . . . . . . . . . . . . . . . . . 56 10.5 Microphone bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.6 Power supply rejection ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.7 LS gain limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Analog input/output operative ranges . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.1 Analog levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.2 Microphone input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.3 Line input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.4 Line output levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.5 Power output levels HP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3/72 Contents STw5095 11.6 Power output levels LS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12 Stereo audio ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 13 Stereo audio DAC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 14 AD to DA mixing (sidetone) specifications . . . . . . . . . . . . . . . . . . . . . . 63 15 Stereo analog-only path specifications . . . . . . . . . . . . . . . . . . . . . . . . 64 16 ADC (TX) and DAC (RX) specifications with voice filters selected . . . 65 17 Typical performance plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 18 Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 19 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 20 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4/72 STw5095 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Control interface timing with IC format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Control interface timing with SPI format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 AMCK timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Audio interface signals timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Operative power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typical power dissipation - No master clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typical power dissipation - Master clock AMCK = 13 MHz . . . . . . . . . . . . . . . . . . . . . . . . 54 Digital interfaces electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 AMCK with sinusoidal input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Analog interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Headset plug-in and push-button detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Microphone bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Power supply ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 LS gain limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Reference full scale analog levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Absolute levels at pins connected to preamplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Absolute levels at pins connected to the line-in amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . 59 Absolute levels at OLP/OLN, ORP/ORN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Absolute levels at HPL - HPR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Absolute levels at LSP - LSN (differential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Stereo audio ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Stereo audio DAC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 AD to DA mixing (sidetone) specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Stereo analog-only path specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 ADC and DCA specifications with voice filters selected . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Package dimensions (mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5/85 List of figures STw5095 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. 6/85 Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 STw5095 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power up block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Plug-in and push-button detection application note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Control interface I2C format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Control interface: I2C format timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Control interface SPI format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Control interface: SPI format timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Audio interfaces formats: delayed, left and right justified . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Audio interfaces formats: DSP, SPI and PCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Audio interface timings: Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Audio interface timing: Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 A.C. testing input-output waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Bass treble control, de-emphasis filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Dynamic compressor transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ADC audio path measured filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ADC in band audio path measured filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 DAC digital audio filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 DAC in band digital audio filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ADC 96 kHz audio path measured filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 ADC 96 kHz audio in-band measured filter response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 ADC voice TX path measured filter response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 ADC voice TX path measured in-band filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 DAC voice (RX) digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 DAC voice (RX) in-band digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 ADC path FFT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 ADC S/N versus input-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 DAC path FFT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 DAC S/N versus input-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Analog path FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Analog path S/N versus input-level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 STw5095 application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 STw5095 1 Overview Overview The STw5095 control registers are accessed through a selectable I2C-bus compatible or SPI compatible interface. The STw5095 asynchronous stereo audio CODEC is designed to easily fit in most audio systems because it supports an extended master clock range (any value between 4 MHz and 32 MHz) and at the same time it supports any audio data rate (independent in AD and DA paths) from 8 kHz to 48 kHz and from 88 kHz to 96 kHz, moreover it can tolerate jitter on audio data without degrading performance. The audio data serial interfaces (for AD and DA) can be Master or Slave, are I2S compatible and they support other formats that can easily interface to standard serial ports. The two audio interfaces can be used as a single bidirectional interface. Two frequency programmable clock sources are available to generate the master clock for the audio sub-system of other devices. The internal D to A and A to D converters work with up to 24 bit resolution. The supply voltage can be the same for the whole device, in the range 2.4 V to 2.7 V, or it can be differentiated for digital (VCC: 1.8 V to 2.7 V), analog (VCCA: 2.4 V to 3.3 V) and loudspeaker driver (VCCLS: VCCA to 5.5 V) to obtain best performance and maximum power to the loudspeaker (up to 500 mW). STw5095 has multiple analog mixable inputs and outputs. It can directly drive Stereo Headphones without external capacitors and it has a Loudspeaker driver that can also be used for monophonic group listening. Stereo differential and single ended microphones, auxiliary line in stereo and mono signals can be mixed and connected to the ADC or directly to the drivers, mixed also with DAC audio signals. STw5095 stereo audio Codec main applications include multimedia handheld devices such as cellular phones with added low-power high-quality MP3 andor FM radio listening/recording features, or any battery powered equipment such as PDAs, Camcorders, etc. that require Stereo Audio Codec with Headphones drivers. Figure 1. Pin configuration (top view) GND SCLK AD_OCK DA_OCK AD_CK AMCK AD_SYNC DA_DATA HDET VCCA VCC SDA/SDIN DA_CK AUX1L MICLN VCCA CMOD AS/CSB VCC GND MBIAS CAPMIC MICLP AUX3L GNDA VCCIO VCCA MICRN AUX1R AUX2LN AUX2LP LINEINL CAPLS AUX3R GNDA OLN GNDCM VCMHPS LSPS LSNS LINEINR AUX2RP AUX2RN OLP GNDP VCMHP LSP LSN VCCP GNDP ORN VCCP HPL VCCLS GNDP GNDP VCCLS HPR ORP 1 2 3 4 5 6 7 8 A AD_DATA DA_SYNC IRQ B C D CAPLINEIN MICRP E F G H 7/85 MICLP LSNS LSN CAPLS LSP LSPS HPR VCMHPS VCMHP HPL ORN ORP HPRG HPLG Mono Driver Right Driver CM Driver Left Driver Right LineOut LSSEL L (L+R)/2 R LSG -24:6 dB Step 2 Transient Suppr. Filter -40:0 dB Step 2 Transient Suppr. Filter Voltage Reference Transient Suppr. Filter -40:0 dB Step 2 R L R L MIXLIN MIXDAC Analog Filter Stereo Path Modulator Stereo DAC DAC DA_SYNC CurrentBias Bandgap Oscillator AD_SYNC ADC Stereo ADC DA Sample Rate Converter Digital DA-PLL Digital AD-PLL AD Sample Rate Converter STw5095 GNDP Filter Audio/Voice AD to DA Mixing Gain (sidetone) Filter Audio/Voice VCC Control Logic GND DAC Digital Gain ADC Digital Gain DAMONO (Audio only) Bass Treble (Audio Only) DA to AD Mixing Gain Dyn.Comp. AGC (Mic&Lin) Registers VCCIO ADMONO DSP ADRTOL Power-On Reset GNDCM PLL Audio DA-I/F CK Gen/ Master Mode MCK CK Gen/ Master Mode Audio AD-I/F Control I/F HDET Headset Detection DA_DATA DA_CK DA_SYNC DA_OCK AMCK AD_OCK AD_SYNC AD_CK AD_DATA CMOD AS/CSB SCLK SDA/SDIN IRQ IRQ Gen STw5095 block diagram MICLO MICLA MICRA -12/0 dB Step 1.5 AGC (from DSP) R L VCCLS Figure 2. Left LineOut MIC L-R PreAmps MICLG MICRG 0/39 dB Step 1.5 LIN L-R Amps AGC (from DSP) LINLG LINRG -20:+18 dB Step 2 VCCP Functional block diagram OLN 2.1V Reference MIC AUX1 AUX2 AUX3 MUTE MICSEL LOG: -18:0 dB Step 3 Mic. Bias Comm. Mode Stereo Sing.E. Stereo Sing.E. Stereo Diff. Stereo Sing.E. LINEIN AUX1 AUX2 AUX3 MUTE LINSEL GNDA 2 OLP MBIAS CAPLINEIN CAPMIC LINEINL LINEINR AUX3R AUX3L AUX2NR AUX2PR AUX2NL AUX2PL AUX1R AUX1L MICRN MICRP Stereo Diff. ADLIN 8/85 ADMIC Note: MICLN VCCA Functional block diagram STw5095 This diagram shows the functionality of the device and of some control registers bits but it does not necessarily reflect the exact hardware implementation. MIXMIC STw5095 Pin description 3 Pin description Table 1. Pin description Pin N Name Type Description D2 C2 E8 D7 MICLP MICLN MICRP MICRN AI Left and Right channel differential pins for microphone input. C8 MBIAS AO Microphone Biasing Pin. Fixed voltage reference. D1 CAPMIC AI A capacitor must be connected between CAPMIC and Ground. C1 D8 AUX1L AUX1R AI Left and Right channel single ended pins for microphone or line input. E2 E1 F7 F8 AUX2LP AUX2LN AUX2RP AUX2RN AI Left and Right channel differential pins for microphone or line input. D3 E5 AUX3L AUX3R AI Left and Right channel single ended pins for microphone or line input. E3 F6 LINEINL LINEINR AI Left and Right channel single ended pins for line input. E7 CAPLINEIN AI A capacitor must be connected between CAPLINEIN and Ground. G4 G5 LSP, LSN AO Analog differential loudspeaker amplifier output for Left channel or Right channel or the sum of both. This output can drive 50nF (with series resistor) or directly an earpiece transductor of 8 ; It can deliver up to 500mW. F4 F5 LSPS, LSNS AO LSPS, LSNS (sense) pins must be connected on the application board to LSP, LSN pins respectively (see application note). The connection must be as close as possible to the pins. E4 CAPLS AI A capacitor can be connected between this node and Ground. See application notes H2 H7 HPL HPR AO Audio single ended headphones amplifier outputs for Left and Right channels. The outputs can drive 50nF (with series resistor) or directly an earpiece transductor of 16. G3 VCMHP AO Common mode voltage headphones output. The negative pins of headphones left and right speakers can be connected to this pin to avoid decoupling capacitors. F3 VCMHPS AO VCMHPS (sense) pin must be connected on the application board to VCMHP pin (see application note). The connection must be as close as possible to the pins. G1 F1 H8 G8 OLP OLN ORP ORN AO Audio differential line out amplifier for Left and Right channels. This outputs can drive up to 1k resistive load. Can be used as single ended outputs. 9/85 Pin description Table 1. STw5095 Pin description Pin N Name Type Description C4 CMOD DI Control interface type selector: I2C-bus mode or SPI mode. A2 SCLK DI Control interface serial clock input. B4 SDA/SDIN DIOD C5 AS/CSB DI A7 AD_SYNC DIO Frame Sync for stereo A/D converter. B7 DA_SYNC DIO Frame Sync for stereo D/A converter. A5 AD_CK DIO Serial Data Clock for stereo A/D converter. B5 DA_CK DIO Serial Data Clock for stereo D/A converter. B6 AD_DATA DO Serial Data Out for stereo A/D converter. A8 DA_DATA DI Serial Data In for stereo D/A converter. B1 HDET AI Headset detection input (Microphone Plug-in and Push-Button detection). B8 IRQ DO Programmable Interrupt output. Active low signal. A3 AD_OCK DO Oversampled Clock Out from AD clock generator. A4 DA_OCK DO Oversampled Clock Out from DA clock generator. A6 AMCK DI AI Master Clock Input. Accepted range 4 MHz to 32 MHz. AMCK is a Digital square wave AMCK is an Analog sinewave (see AMCKSIN Section 5.8 on page 38) B2 C3 D6 VCCA P Power Supply pins for the analog section. Standard Operating range: from 2.7 V to 3.3 V Low Voltage (LV) Range: from 2.4 V to 2.7 V D4 E6 GNDA P Ground pins for the analog section. F2 GNDCM P Ground pin for analog reference. GNDCM can be connected to GNDA. Control interface serial data input-output in I2C mode (SDA), Control interface serial data input in SPI mode (SDIN). Control interface address select in I2C mode (AS). Interface enable signal in SPI mode (CSB). G6 H1 VCCP P Power Supply pins for the left and right output drivers (headphones and line-out). Operating range: from VCCA to 3.3V H3 H6 VCCLS P Power Supply pins for the mono differential output driver. Operating range: from VCCA to 5.5V G2 G7 H4 H5 GNDP P Ground pins for the left, right and mono-differential output drivers. GNDP and GNDA must be connected together. B3 C6 VCC P Power Supply pins for the digital section. Operating range: from 1.71 V to 2.7 V 10/85 STw5095 Table 1. Pin description Pin description Pin N Name Type A1 C7 GND P Ground pins for the digital section. D5 VCCIO P Power Supply pin for the Digital I/O buffers. Operating ranges: from 1.2 V to 1.8 V and from 1.71 V to VCC Note: Description VCC, VCCA, VCCP, VCCLS can be connected together for low cost applications: Operating range: 2.4 V-2.7 V. Type definitions AI - Analog input AO - Analog Output AIO - Analog Input Output DI - Digital Input DO - Digital output DIO - Digital Input Output DIOD - Digital Input Output Open Drain P - Power Supply or Ground 11/85 Functional description 4 Functional description 4.1 Power supply STw5095 STw5095 can have different supply voltages for different blocks, to optimize performance, power consumption and connectivity. See Operative supply voltage on page 52 for voltage definition. The correct sequence to apply supply voltage is to set first (and unset last) the digital I/O supply (VCCIO). The other supply voltages can be set in any order and can be disconnected individually, if needed. Disconnection does not cause any harm to the device and no extra current is pulled from any supply during this operation. Moreover if a voltage conflict is detected, like VCCA < VCC (not allowed), simply all blocks connected to VCCA are set to power down and no extra current is pulled from supply. When VCCIO is set and VCC (digital supply) is not set, all the digital output pins are in high impedance state, while the digital inputs are disconnected to avoid power consumption for any input voltage value between GND and VCCIO. Before VCC is disconnected the device has to be reset (SWRES bit in CR30). When the analog supply (VCCA) is set and VCC is not set, all the analog inputs are in high impedance state. The control registers are powered by VCC pin (digital supply) so if this pin is disconnected all the information stored in control registers is lost. When the digital supply voltage is set, a power-on-reset (POR) circuit sets all the registers content to the default value and then generates an IRQ signal writing 1 in bits PORMSK and POREV in CR31 and CR32 respectively. All supplies must be on during operation. 4.2 Device programming STw5095 can be programmed by writing Control Registers with SPI or I2C compatible control interface (both slave). The interface is always active, there is no need to have the master clock running to program the device registers. The choice between the two interfaces is done via an input pin (CMOD): 1. CMOD connected to GND: I2C compatible mode selected The device address is selected with AS pin: AS connected to GND: chip address 00110101(35hex) for reading, 00110100 (34hex) for writing AS connected to VCCIO: chip address 00110111(37hex) for reading, 00110110 (36hex) for writing 12/85 2. When this mode is selected control registers are accessed through pins: SCLK (clock) SDA (serial data out/in, open drain) 3. CMOD connected to VCCIO: SPI compatible mode selected When this mode is selected control registers are accessed through: CSB (chip select, active low) SCLK (clock) SDIN (serial data in) AD_OCK or DA_OCK or IRQ (serial data out, if selected) STw5095 Functional description Device Programming: I2C. The I2C Control Interface timing is shown in Section 6.1 on page 43. The interface has an internal counter that keeps the current address of the control register to be read or written. At each write access of the interface the address counter is loaded with the data of the register address field. The value in the address counter is increased after each data byte read or write. It is possible to access the interface in 2 modes: single-byte mode in which the address and data of a single register are specified, and multi-byte mode in which the address of the first register to be written or read is specified and all the following bytes exchanged are the data of successive registers starting from the one specified (in multi-byte mode the internal address counter restart from register 0 after the last register 36). Using the multi-byte mode it is possible to write or read all the registers with a single access to the device on the I2C bus. Device Programming: SPI. The SPI Control Interface timing is shown in Section 6.2 on page 44. Bits SPIOSEL (SPI Output Select) in CR33 control the out pin selection for serial data out (none, AD_OCK, DA_OCK or IRQ), while bit SPIOHIZ=1 in CR33 selects the high impedance state of serial data out pin when idle. The first bit sent on SDIN, after CSB falling edge, sets the interface for writing (SDIN=1) or reading (SDIN=0), then a 7-bit Control Register address follows. If the interface is set for writing then the last 8 bits on SDIN are written in the control register. If the interface is set for reading then after the 7 bit address STw5095 sends out 8 bits data on the pin selected with bits SPIOSEL in CR33, while bits present at SDIN pin are ignored. If SPIOSEL=00 (no out pin selected) the reading access on SPI interface can still be useful to clear the IRQ event bits in CR32. 4.3 Power up STw5095 internal blocks can individually be switched on and off according to the user needs. A general Power Up bit is present at bit 7 of CR0. The output drivers should always be powered up after the general power up. See the following drawing to select the needed block for the desired function. A fast-settling function is activated to quickly charge external capacitors when the device is switched on (CAPLS, CAPLINEIN and CAPMIC). 13/85 Functional description Figure 3. STw5095 Power up block diagram ENANA ENMICL ENHSD POWERUP MBIAS ENMICR ENADCL ENLINL ENADCR STw5095 ENADCKGEN ENLINR ADMAST ENADOCK ENLOL AUDIO I/F DAMAST ENDAOCK ENHPL ENMIXL ENLS ENDACL ENMIXL ENHPR ENDACR ENLOR ENOSC=0 ENOSC=1 ENHPVCM 4.4 ENDACKGEN ENPLL ENAMCK ENOSC Master clock The master clock pin (AMCK) accepts any frequency from 4 MHz to 32 MHz. The 4-32 MHz range is divided in sub-ranges that have to be programmed in bits CKRANGE in CR30. The jitter and spectral properties of this clock have a direct impact on the DAC and ADC performance because it is used to directly or by integer division drive the continuous-time to sampled-time interfaces. Note that AMCK clock des not need to have any relation to any other digital or analog input or output. AMCK can be either a squarewave or a sinewave, bit AMCKSIN in CR30 selects the proper input mode. When a sinewave is used as input, AMCK pin must be decoupled with a capacitor. Specification for sinusoidal input can be found in Section 10.2: AMCK with sinusoidal input on page 55. The AMCK clock is not needed when only analog functions are used. For this purpose an internal oscillator with no external components can be used to operate the device (see Analog-only operation on page 19). 14/85 STw5095 4.5 Functional description Data rates STw5095 supports any data rate in 2 ranges: 8 kHz to 48 kHz and 88 kHz to 96 kHz. The range is selected with bits DA96K and AD96K in CR29 for AD and DA paths respectively. Note: When AD96K=1 it is required to have DA96K=1. The rates are fully independent in A/D and D/A paths. Moreover the rates do not have to be specified to the device and they can change on the fly, within one range, while data is flowing. The 2 audio data interfaces (for A/D and D/A) can independently operate in master or slave mode. 4.6 Clock generators and master mode function STw5095 provides 2 internal clock generators that can drive, if needed, the audio interfaces (master mode), and/or two independent master clocks. The AMCK clock input frequency is internally raised via a PLL to obtain a clock (MCK) in the range 32 MHz to 48 MHz. The ratio MCK/AMCK is defined in CR30 (see MCKCOEFF in Section 5.6 on page 34). MCK is used to obtain, by fractional division, the oversampled clock (OCK), word clock (SYNC) and bit clock (CK), that will therefore have edges aligned with MCK (the OCK period can have jitter of 1 MCK period). The frequency of OCK, SYNC and CK is set with DAOCKF in CR21/20 for DA interface, and ADOCKF in CR24/23 for AD interface. The ratio between OCK and SYNC clocks is selected with bit DAOCK512 in CR22 for DA interface and bit ADOCK512 in CR25 for AD interface. The ratio between CK and SYNC clocks depends on the selected interface format (see Audio digital interfaces paragraph below). Note that SPI format can only be slave. The ADOCK and DAOCK output clocks are activated by bits ENADOCK and ENDAOCK respectively, while master mode generation is activated with two bits: first ADMAST (DAMAST) sets ADSYNC and ADCK (DASYNC and DACK) pins as outputs, then ADMASTGEN (DAMASTGEN) generates the SYNC and CK clocks. The logical value at SYNC and CK pins before data generation depends on the interface selected format. See description of CR20 to CR25 for further details. 4.7 Audio digital interfaces Two separate audio data interfaces are provided for AD and DA paths to have maximum flexibility in communicating with other devices. The 2 interfaces can have different rates and can work in different formats and modes (i.e AD interface can be 8 kHz PCM slave while DA is 44.1 kHz I2S master). The pins used by the interfaces are: AD_SYNC, AD_CK and AD_DATA for AD path word clock, bit clock and data, respectively, and DA_SYNC, DA_CK and DA_DATA for DA path word clock, bit clock and data, respectively. 15/85 Functional description STw5095 Data is exchanged with MSB first and left channel data first in all formats. Data word-length is selected with bits DAWL in CR26 and ADWL in CR27. AD_DATA pin, outside the selected time slot, is in the impedance condition selected by bit ADHIZ in CR28 in all data formats except Right-Aligned-Format. In the following paragraphs SYNC, CK and DATA will be used when the distinction between AD and DA is not relevant. When Master Mode is selected (bits DAMAST and ADMAST in CR22 and CR25 respectively) the SYNC and CK clocks are generated internally. In addition, an oversampled clock can be generated for each interface (AD_OCK and DA_OCK). The OCK clock is available in Slave Mode also, if needed. The AD and DA interfaces can also be used as a single bidirectional interface when they are configured with the same format (Delayed, DSP, etc.) and AD_SYNC is connected to DA_SYNC and DA_CK to AD_CK. Master Mode is still available selecting ADMAST or DAMAST (not both). The interfaces features are controlled with control registers CR26, CR27 and CR28. Supported operating formats: 16/85 Delayed-Format (I2S compatible) (DAFORM or ADFORM =000): the Audio Interface is I2S compatible (Figure 9 on page 47). The number of CK periods within one SYNC period is not relevant, as long as enough CK periods are used to transfer the data and the maximum frequency limit specified for bit clock is not exceeded. CK can be either a continuous clock or a sequence of bursts. In master mode there are 32 CK periods per SYNC period (that means 16 CK periods per channel) when the word length is 16 bit, while there are 64 CK periods per SYNC period (or 32 CK periods per channel) when word length is 18bit or higher. Bits ADSYNCP, DASYNCP and ADCKP, DACKP affect the interface format inverting the polarity of SYNC and CK pins respectively. Left-Aligned-Format (DAFORM or ADFORM =001): this format is equivalent to Delayed-Format without the 1 bit clock delay at the beginning of each frame (Figure 9 on page 47). Right-Aligned-Format (DAFORM or ADFORM =010): this format is equivalent to Delayed-Format, except that the Audio Data is right aligned and that the number of CK periods is fixed to 64 for each SYNC period (Figure 9 on page 47). DSP-Format (DAFORM or ADFORM =011) in this format the Audio Interface starting from a frame sync pulse on SYNC receives (DA) or sends (AD) the Left and Right data one after the other (Figure 10 on page 48). The number of CK periods within one SYNC period is not relevant, as long as enough CK periods are used to transfer the data and the maximum frequency limit specified for bit clock is not exceeded. CK can be either a continuous clock or a sequence of bursts. In Master Mode there are 32 CK periods per SYNC period when the word length is 16 bit, while there are 64 CK periods per SYNC period when word length is 18bit or higher. Bit CKP (ADCKP and DACKP) affects the interface format inverting the polarity of CK pin. Bit SYNCP (ADSYNCP and DASYNCP) switches between delayed (SYNCP=0) and non delayed (SYNCP=1) formats. DSP-Format is suited to interface with a Multi-Channel Serial Port. SPI-Format (DAFORM or ADFORM =100) in this format Left and Right data is received with separate data burst. Every burst is identified with a low level on SYNC signal (Figure 10 on page 48). There is no timing difference between the Left and Right data burst: the two channels are identified by the startup order: the first burst after AD path or DA path power-up identifies the Left channel data, the second one is the Right channel data, then Left and Right data repeat one after the other. CK must have 16 periods per channel in case of 16 bit data word and 32 periods per channel in case of STw5095 Functional description 18 bit to 32 bit data word. The SPI interface can be configured as a single-channel (mono) interface with bit SPIM (ADSPIM and DASPIM). The mono interface always exchanges the left channel sample. SPI-Format can only be Slave: if Master Mode is selected the CK and SYNC pins are set to 0. Bit CKP (ADCKP and DACKP) affects the interface format inverting the polarity of CK pin. 4.8 PCM-Format (DAFORM or ADFORM =111): this format is monophonic, as it can only receive (DA) and transmit (AD) single channel data (Figure 10 on page 48). It is mainly used when voice filters are selected. If audio filters are used then the same sample is sent from DA-PCM interface to both channel of DA path, and the left channel sample from AD path is sent to AD-PCM interface. If in the AD path the right channel has to be sent to the PCM interface then the following must be set: ADRTOL=1 (CR27) and ENADCL=0 (CR1). In Master Mode the number of CK periods per SYNC period is between 16 and 512 (see DAPCMF in CR22 and ADPCMF in CR25, Section 5.6 on page 34 for details). Bit CKP (ADCKP and DACKP) affects the interface format inverting the polarity of CK pin. Bit SYNCP (ADSYNCP and DASYNCP) switches between delayed (SYNCP=0) and non delayed (SYNCP=1) formats. Analog inputs STw5095 has a stereo Microphone preamplifier and a stereo Line In amplifier, with inputs selectable among 5: MIC (for Microphone preamplifier only), LINEIN (for Line In amplifier only) and 3 different AUX inputs (for Microphone and Line In amplifiers). The AUX inputs can be used simultaneously for Line In amplifiers and Microphone preamplifiers. Microphone preamplifier: it has a very low noise input, specifically designed for low amplitude signals. For this reason it has a high input gain (up to 39 dB) keeping a constant 50 k input impedance for the whole gain range. However it can also be used as a line in preamplifier because it can accept a high dynamic input signal (up to 4 Vpp). There are two separate gain and attenuation stages in order to improve the S/N ratio when the preamplifier output range is below full scale (volume control).The gain and attenuation controls are separate for left and right channel (CR3 and CR4 respectively). The Preamplifier input is selected with bits MICSEL in CR18, and it is disconnected when MICMUTE=1. If a single ended input is selected then the preamplifier uses the selected pin as the positive input and connects the negative input (for both left and right channels) to CAPMIC pin, which has to be connected through a capacitor to a low noise ground (typically the same reference ground of the input). The stereo Microphone preamplifier is powered up with bits ENMICL and ENMICR in CR1. Line In amplifier: it is designed for high level input signal. The input gain is in the range -20 dB up to 18 dB. The Line In amplifier input is selected with bits LINSEL in CR18, and it is disconnected when LINMUTE=1. If a single ended input is selected then the amplifier uses the selected pin as the positive input and connects the negative input (for both left and right channels) to CAPLINEIN pin, which has to be connected through a capacitor to a low noise ground (typically the same reference ground of the input). The stereo Line In amplifier is powered up with bits ENLINL and ENLINR in CR1. 17/85 Functional description 4.9 STw5095 Analog output drivers STw5095 provides 3 different analog signal outputs and 1 common mode reference output: Note: 18/85 Line Out Drivers: it is a stereo differential output, it can be used as single-ended output just by using the positive or negative pin. It can drive 1 k resistive load. The load can be connected between the positive and negative pins or between one pin and ground through a decoupling capacitor. The output gain is regulated with LOG bits in CR7, in the range 0 to -18 dB, simultaneously for left and right channels. When used as a single ended output the effective gain is 6 dB lower. It is muted with bit MUTELO in CR19. The input signal of this stereo output can come from the analog mixer or directly from MIC preamplifiers. The output Common Mode Voltage level is controlled with bits VCML in CR19. The supply voltage of line out drivers is VCCP . The Line Out Drivers are powered up with bits ENLOL and ENLOR in CR1. The output pins are in high impedance state with a 180k pull-down resistor when the Line Out Drivers are powered down. Headphones Drivers: it is a stereo single ended output. It can drive 16 Ohm resistive load and deliver up to 40 mW. The output gain is regulated with HPLG and HPRG bits in CR8 and CR9 respectively, with a range of -40 to 6 dB. It is muted with bit MUTEHP in CR19. The input signal of this stereo output comes from the analog mixer.The output Common Mode Voltage is controlled with bits VCML in CR19. The supply voltage of headphones drivers is VCCP . The Headphones Drivers are powered up with bits ENHPL and ENHPR in CR2.The output pins are in high impedance state when the Headphones Drivers are powered down. Common Mode Voltage Driver: it is a single ended output with output voltage value selectable with bits VCML in CR19, from 1.2 V to 1.65 V in steps of 150 mV. The output voltage should be set to the value closest to VCCP/2 to optimize output drivers performance. The Common Mode Voltage Driver is designed to be connected to the common pin of stereo headphones, so that decoupling capacitors are not needed at HPL and HPR outputs. The supply voltage of the common mode voltage driver is VCCP . The Common Mode Voltage Driver is powered up with bit ENHPVCM in CR2.The output pin is in high impedance state when the Common Mode Voltage Driver is powered down. Loudspeaker Driver: it is a monophonic differential output. It can drive 8 resistive load and deliver up to 500 mW to the load. The output gain is regulated with LSG bits in CR7, in the range -24 to +6 dB. The input signal of the loudspeaker driver comes from the analog mixers: bits LSSEL in CR29 select left channel, right channel, (L+R)/2 (mono) or mute. The output Common Mode Voltage is obtained with an internal voltage divider from VCCLS and it is connected to CAPLS pin. The supply voltage of the loudspeaker driver is VCCLS. The Loudspeaker Driver is powered up with bit ENLS in CR2.The output pin is in high impedance state when the Loudspeaker Driver is powered down. Note on direct connection of VCCLS To the battery: The voltage of batteries of handheld devices during charging is usually below 5.5 V, making VCCLS supply pin suitable for a direct connection to the battery. In this case if STw5095 is delivering the maximum power to the load and the ambient temperature is above 70 C then the simultaneous charging of the battery can overheat the device. A basic protection scheme is implemented in STw5095 (activated with bit LSLIM in CR19): it limits the maximum gain of the loudspeaker to -6 dB when VCCLS is above 4.2 V, and it removes the limit for VCCLS below 4.0 V. The loudspeaker gain is left unchanged if it is set below -6 dB STw5095 Functional description with bits LSG. This event (VCCLS > 4.2 V) can generate, if enabled (bit VLSMSK in CR31), an IRQ signal. 4.10 Analog mixer STw5095 can send to the output drivers the sum of stereo audio signals from 3 different sources, DA path (bit MIXDAC in CR17), Microphone Preamplifiers (bit MIXMIC in CR17) and Line In Amplifiers (bit MIXLIN in CR17). The mixer does not have a gain control on the inputs, therefore the user should reduce the levels of the input signals within the analog signal range. The stereo Analog Mixer is powered up with bits ENMIXL and ENMIXR in CR2. 4.11 AD path The AD path converts audio signals from Microphone Preamplifiers (selected with bit ADMIC in CR17) and Line In Amplifiers (bit ADLIN in CR17) inputs to digital domain. If both inputs are selected then the sum of the two is converted. After AD conversion the audio data is resampled with a sample rate converter and then processed with the internal DSP. Two different filters are selectable in the DSP (bit ADVOICE in CR29): stereo Audio Filter, with DC offset removal and FIR image filtering; and a standard mono Voice-channel filter (uses left channel input and feeds both channel output). The AD path includes a digital gain control (ADCLG, ADCRG in CR12 and CR13 respectively) in the range -57 to +8 dB. The maximum gain from Mic Preamplifier to AD interface is then 47 dB. When Audio filter is selected in both AD and DA paths then DA audio data can be summed to AD data and sent to the AD Audio Interface (see DA2ADG in CR15). Left and Right channels can be independently switched on and off to save power, if needed (bits ENADCL and ENADCR in CR1) 4.12 DA path The DA path converts digital data from the digital audio interface to analog domain and feeds it to the analog mixer. Incoming audio data is processed with a DSP where different filters are selectable (bit DAVOICE in CR29): Audio Filter, stereo, with FIR image filtering, bass and treble controls (bits BASS and TREBLE in CR14), de-emphasis filter; and a standard Voice-channel filter, mono (uses left channel input and feeds both channel output). A dynamic compression function is available for both audio and voice filters (bit DYNC in CR14). The DA path includes a digital gain control (DACLG, DACRG in CR10 and CR11 respectively) in the range -65 to 0 dB. AD to DA mixing (sidetone) can be enabled: see CR16 for details. Left and Right channel can be independently switched on and off to save power, if needed (bits ENDACL and ENDACR in CR1) 4.13 Analog-only operation STw5095 can operate without AMCK master clock if analog-only functions are used. It is possible to mix Microphone and Line In preamplifiers signals and listen through headphones, loudspeaker or send them to line-out. The analog-only operation is enabled with bit ENOSC in CR0. When ENOSC=1 the AD and DA paths cannot be used. 19/85 Functional description STw5095 In Analog Mode STw5095 can handle two different stereo audio signals, so it can be used as a front end for an external voice codec that does not include microphone preamplifiers and power drivers: mic signal is sent through Microphone preamplifiers directly to line out drivers (Transmit path), while Receive signal is sent through Line In amplifiers to the selected power drivers. 4.14 Automatic Gain Control (AGC) STw5095 provides a digital Automatic Gain Control in AD path. The circuit can control the input gain at MIC preamplifier, Line In amplifier or both (bits ENAGCMIC and ENAGCLIN in CR35). When one input is selected, the center gain value used for the input is fixed with bits MICLG, MICRG, LINLG and LINRG in CR3 to CR6 (like in normal operation), then the AGC circuit adds to all the gains a value in the range -10.5 dB to +10.5 dB (or, extended with bit AGCRANGE in CR35, -21 dB to 21 dB), in order to obtain an average level at the digital interface output in the range -6 dB to -30 dB (selected with bits AGCLEV in CR35). The AGC added gain acts directly in the input gain, to avoid input saturation and improve S/N ratio, so it cannot exceed the input gain range. When MIC and Line-In inputs are selected simultaneously the control is performed on the sum of the two, preserving the balance fixed with input gains. Different values for Attack and Decay constants can be selected, depending on the kind of signal the AGC has to control (i.e. voice, music). The Attack and Decay time constants are related to the AD data rate (see bits AGCATT and AGCDEL in CR34). 4.15 Interrupt request: IRQ pin STw5095 interrupt request feature can signal to a control device the occurrence of particular events. Two control registers are used to choose the behavior of IRQ pin: the first is a Status/Event Register (CR32), where bits can represent the status of an internal function (i.e. a voltage is above or below a threshold) or an event (i.e. a voltage changed crossing a threshold); the second is a Mask Register (CR31) where if a bit in the mask is set to 1 then the corresponding bit in the Status/Event Register can affect IRQ pin status. The IRQ pin is always active low. At VCC power up an interrupt request is generated by the Power-On-Reset circuit that sets to 1 bits PORMSK in CR31 and POREV in CR32. After this event the PORMSK bit should be cleared by the user and bit IRQCMOS in CR33 should be set according to the application (open drain or CMOS). When an IRQ event occurs and SPI control interface is selected with no serial output pin it is still possible to identify the event (and relative status) that generated the interrupt request. This can be done by setting the IRQ mask/enable bits (in CR31) one at the time (with successive writings) and reading the IRQ pin status. A simple example of this is the headset plug-in detection: at first we set bit HSDETMSK=1 in CR31 (with all the other bits set to 0). If there is an interrupt request then we set HSDETMSK=0 and HSDETEN=1, so we can read the HSDET status at IRQ pin. Then we read CR32 to clear its content (even if no data is sent out). 20/85 STw5095 4.16 Functional description Headset plug-in and push-button detection STw5095 can detect the plug-in of a microphone connector and the press/release event of a call/answer push-button. An application example can be found below, while specifications can be found in Section 10.4 on page 56. Figure 4. Plug-in and push-button detection application note HDET AUX1L 200nF AUX1R VCCA 3k 1.5k Call/Answer Button STw5095 200nF CAPMIC 10F From Driver Generic Connector 4.17 Microphone biasing circuit The Microphone Biasing Circuit can drive mono or stereo microphones and can switch them off when not needed in order to save the current used by the microphone biasing network. Two bits control the behavior of the microphone bias circuit: MBIAS in CR17 enables the circuit (fixed voltage at MBIAS pin), while bit MBIASPD in CR17 affects the behavior of MBIAS pin when the function is not enabled. In particular when MBIASPD=1 the MBIAS pin is pulled down, otherwise it is left in tristate mode. The specification for the microphone biasing circuit can be found in Section 4.17 on page 21, and an application note is shown in Section 18 on page 69. 21/85 Control registers STw5095 5 Control registers 5.1 Summary CR# (hex) Description D7 D6 D5 D4 D3 CR0 (00h) Supply & Power Control #1 CR1 (01h) Power Control #2 POWERUP ENANA ENAMCK ENOSC ENPLL ENHSD ENADCL ENADCR ENDACL ENDACR ENMICL ENMICR CR2 (02h) Power Control #3 ENLOL CR3 (03h) Mic Gain Left ENLOR ENHPL ENHPR ENHPVCM ENLS ENMIXL ENMIXR CR4 (04h) Mic Gain Right CR5 (05h) Line in Gain Left X X X LINLG(4:0) 0000 1001 CR6 (06h) Line in Gain Right X X X LINRG(4:0) 0000 1001 CR7 (07h) LO gain & LS gain X CR8 (08h) HPL Gain X X X HPLG(4:0) 0000 0011 CR9 (09h) HPR Gain X X X HPRG(4:0) 0000 0011 MICLA(2:0) MICRA(2:0) D2 D1 D0 Def. A24V D12V 0000 0000 ENLINL ENLINR 0000 0000 0000 0000 MICLG(4:0) 0000 0000 MICRG(4:0) 0000 0000 LOG(2:0) LSG(3:0) 0000 0011 CR10 (0Ah) DAC Digital Gain Left X X DACLG(5:0) 0000 0000 CR11 (0Bh) DAC Digital Gain Right X X DACRG(5:0) 0000 0000 CR12 (0Ch) ADC Digital Gain Left X X ADCLG(5:0) 0000 1000 CR13 (0Dh) ADC Digital Gain Right X X ADCRG(5:0) 0000 1000 CR14 (0Eh) Bass/Treble/De-emphasis CR15 (0Fh) DA to AD mixing gain X X CR16 (10h) AD to DA mix/sidetone gain X X CR17 (11h) Mixer Switches & Mic Bias MBIAS MBIASPD ADMIC CR18 (12h) Input Switches X IN2VCM LINMUTE CR19 (13h) Drivers Control CR20 (14h) DAOCK Frequency Ls byte DAOCKF(7:0) 0000 0000 CR21 (15h) DAOCK Frequency Ms byte DAOCKF(15:8) 0000 0000 CR22 (16h) DA Clock Generator Control CR23 (17h) ADOCK Frequency Ls byte ADOCKF(7:0) CR24 (18h) ADOCK Frequency Ms byte ADOCKF(15:8) CR25 (19h) AD Clock Generator Control X CR26 (1Ah) DAC Data IF Control X CR27 (1Bh) ADC Data IF Control ADRTOL CR28 (1Ch) DAC&ADC Data IF Control AMCKINV DACKP DASYNCP DAMONO CR29 (1Dh) Digital Filters Control X DAVOICE DA96K CR30 (1Eh) Soft Reset & AMCK Range SWRES X X CR31 (1Fh) interrupt Mask VLSHEN PUSHBEN CR32 (20h) Interrupt Status VLSH CR33 (21h) Misc. Control X CR34 (22h) AGC Attack/Decay coeff. CR35 (23h) AGC Control X ENAGCLIN ENAGCMIC AGCRANGE CR36 (24h) RESERVED X X X X Note: X reserved, write zero 22/85 DYNC TREBLE(2:0) X 0000 0000 DA2ADG(4:0) 0000 0000 AD2DAG(5:0) VCML(1:0) X BASS(3:0) X X DAMAST X ADMAST ADLIN MIXMIC LINSEL(1:0) MUTELO DAMASTGEN ADMASTGEN DAFORM(2:0) MUTEHP ENDAOCK ENADOCK 0000 0000 MIXLIN MICSEL(1:0) 0010 0100 LSSEL(1:0) 0101 1000 DAOCK512 DAPCMF(1:0) 0000 0000 0000 0000 0000 0000 ADOCK512 ADPCMF(1:0) 0000 0000 DAWL(2:0) 0000 0000 ADWL(2:0) ADCKP ADSYNCP RXNH ADVOICE AD96K X AMCKSIN HSDETEN VLSHMSK PUSHBMSK PUSHB HSDET VLSHEV PUSHBEV X SPIOHIZ 0000 0000 ADMONO ADHIZ ADNH TXNH CKRANGE(2:0) HSDETMSK 0000 0000 0000 0000 0000 0000 OVFMSK PORMSK 0000 0000 HSDETEV OVFEV POREV 0000 0000 IRQCMOS OVFDA OVFAD AGCATT(3:0) AGCDEC(3:0) X 0000 0000 0000 0000 AGCLEV(3:0) X 0000 0000 LSLIM ADSPIM SPIOSEL(1:0) MICLO MICMUTE DASPIM ADFORM2:0) MIXDAC 0000 0000 X X 0000 0000 STw5095 Control registers 5.2 CR# (hex) Supply and power control Description D7 D6 D5 D4 D3 D2 D1 D0 Def. CR0 (00h) Supply & Power Control #1 POWERUP ENANA ENAMCK ENOSC ENPLL ENHSD A24V D12V 0000 0000 CR1 (01h) Power Control #2 ENADCL ENADCR ENDACL ENDACR ENMICL ENMICR ENLINL ENLINR 0000 0000 CR2 (02h) Power Control #3 ENLOL ENLOR ENHPL ENHPR ENHPVCM ENLS ENMIXL ENMIXR 0000 0000 Bits Name Val. CR0 Description Def. 7 POWERUP 1 0 All the enabled analog and digital blocks are in power up All the device is in power down 0 6 ENANA 1 0 The analog blocks can be enabled All the analog blocks are in power down 0 5 ENAMCK 1 0 AMCK clock input pin is enabled AMCK clock input pin is disabled 0 1 4 ENOSC 0 0 The Internal Oscillator is enabled. The analog blocks use Oscillator clock The Internal Oscillator is in power down 3 ENPLL 1 0 The PLL is enabled The PLL is in power down 0 2 ENHSD 1 0 The Headset Plug-in Detector is enabled The Headset Plug-in Detector is disabled 0 1 A24V 1 0 Analog Supply Pins voltage range is 2.4V<VCCA<2.7V 0 D12V 1 0 Digital I/O Pins voltage range is 1.2V<VCCIO<1.8V Analog Supply Pins voltage range is 2.7V<VCCA<3.3V Digital I/O Pins voltage range is 1.71V<VCCIO<VCC 0 0 23/85 Control registers Bits Name STw5095 Value CR1 Description Def. 7 ENADCL 1 0 The left channel A/D converter is enabled The left channel A/D converter is in power down 0 6 ENADCR 1 0 The right channel A/D converter is enabled The right channel A/D converter is in power down 0 5 ENDACL 1 0 The left channel D/A converter is enabled The left channel D/A converter is in power down 0 4 ENDACR 1 0 The right channel D/A converter is enabled The right channel D/A converter is in power down 0 3 ENMICL 1 0 The left channel microphone preamplifier is enabled The left channel microphone preamplifier is in power down 0 2 ENMICR 1 0 The right channel microphone preamplifier is enabled The right channel microphone preamplifier is in power down 0 1 ENLINL 1 0 The left channel line-in preamplifier is enabled The left channel line-in preamplifier is in power down 0 0 ENLINR 1 0 The right channel line-in preamplifier is enabled The right channel line-in preamplifier is in power down 0 Bit # Name Value CR2 Description Def. 7 ENLOL 1 0 The left channel line out driver is enabled The left channel line out driver is in power down (default) 0 6 ENLOR 1 0 The right channel line out driver is enabled The right channel line out driver is in power down (default) 0 5 ENHPL 1 0 The left channel headphones driver is enabled The left channel headphones driver is in power down (default) 0 4 ENHPR 1 0 The right channel headphones driver is enabled The right channel headphones driver is in power down (default) 0 3 ENHPVCM 1 0 The headphones reference voltage generator is enabled The headphones reference voltage generator is in power down (def) 0 2 ENLS 1 0 The 8 loudspeaker amplifier is enabled The 8 loudspeaker amplifier is in power down (default) 0 1 ENMIXL 1 0 The left channel analog output mixer is enabled The left channel analog output mixer is in power down (default) 0 0 ENMIXR 1 0 The right channel analog output mixer is enabled The right channel analog output mixer is in power down (default) 0 24/85 STw5095 5.3 Control registers Gains CR# (hex) Description D7 D6 D5 D4 D3 D2 D1 D0 Def. CR3 (03h) Mic Gain Left MICLA(2:0) MICLG(4:0) 0000 0000 CR4 (04h) Mic Gain Right MICRA(2:0) MICRG(4:0) 0000 0000 CR5 (05h) Line in Gain Left X X X LINLG(4:0) 0000 1001 CR6 (06h) Line in Gain Right X X X LINRG(4:0) 0000 1001 CR7 (07h) LO gain & LS gain X CR8 (08h) HPL Gain X X X HPLG(4:0) 0000 0011 CR9 (09h) HPR Gain X X X HPRG(4:0) 0000 0011 LOG(2:0) LSG(3:0) 0000 0011 CR10 (0Ah) DAC Digital Gain Left X X DACLG(5:0) 0000 0000 CR11 (0Bh) DAC Digital Gain Right X X DACRG(5:0) 0000 0000 CR12 (0Ch) ADC Digital Gain Left X X ADCLG(5:0) 0000 1000 CR13 (0Dh) ADC Digital Gain Right X X ADCRG(5:0) 0000 1000 Bits 7-5 4-0 Bits 4-0 Name CR3 Name CR4 MICLA(2:0) MICRA(2:0) MICLG(4:0) MICRG(4:0) Name CR5 Name CR6 LINLG(4:0) LINRG(4:0) Value CR3 and CR4 Description 000 001 010 ... 110 111 Left (CR3) and Right (CR4) Channels Microphone Attenuation 0.0 dB Gain (default) -1.5 dB Gain -3.0 dB Gain ...step 1.5 dB -9.0 dB Gain -12.0 dB Gain 00000 00001 00010 ... 11010 Left (CR3) and Right (CR4) Channels Microphone Gain 0.0 dB Gain (default) 1.5 dB Gain 3.0 dB Gain ...step 1.5 dB 39.0 dB Gain Value 00000 00001 00010 ... 01001 ... 10011 CR5 and CR6 Description Left (CR5) and Right (CR6) Channels Line In Gain 18.0 dB Gain 16.0 dB Gain 14.0 dB Gain ...step 2.0 dB 0.0 dB Gain (default) ...step 2.0 dB -20.0 dB Gain Def. 000 00000 Def. 01001 25/85 Control registers Bits Name STw5095 Value CR7 Description Def. Left and Right Channel Line Out Drivers Gain 6-4 3-0 Bits 4-0 26/85 LOG(2:0) LSG(3:0) Name CR8 Name CR9 HPLG(4:0) HPRG(4:0) 000 001 010 ... 110 0000 0001 0010 0011 ... 1111 Value 00000 00001 00010 00011 ... 10100 Gain to Differential Output -18.0 dB Gain (default) -15.0 dB Gain -12.0 dB Gain ...step 3 dB 00 dB Gain Equivalent Single-Ended Gain -24.0 dB Gain (default) -21.0 dB Gain -18.0 dB Gain ...step 3 dB -6.0 dB Gain 8 Loudspeaker Gain 6.0dB Gain 4.0dB Gain 2.0 dB Gain 0.0dB Gain (default) ...step 2.0 dB -24.0dB Gain CR8 and CR9 Description Left (CR8) and Right (CR9) Channels Headphones Driver Gain 0.0dB Gain -2.0dB Gain -4.0dB Gain -6.0dB Gain (default) ...step 2.0 dB -40.0dB Gain 000 0011 Def. 00011 STw5095 Bits 5-0 Name CR10 Name CR11 DACLG(5:0) DACRG(5:0) Control registers Value 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 CR10 and CR11 Description Left (CR10) and Right (CR11) Channels DAC Digital Gain 0.0dB Gain (default) -1.0dB Gain -2.0dB Gain -3.0dB Gain -4.0dB Gain -5.0dB Gain -6.0dB Gain -7.0dB Gain -8.0dB Gain -9.0dB Gain -10.0dB Gain -11.0dB Gain -12.0dB Gain -13.0dB Gain -14.0dB Gain -15.0dB Gain -16.0dB Gain -17.0dB Gain -18.0dB Gain -20.0dB Gain -22.0dB Gain -24.0dB Gain -26.0dB Gain -28.0dB Gain -30.0dB Gain -32.0dB Gain -34.0dB Gain -36.0dB Gain -38.0dB Gain -41.0dB Gain -44.0dB Gain -47.0dB Gain -50.0dB Gain -53.0dB Gain -56.0dB Gain -59.0dB Gain -65.0dB Gain -dB Gain Def. 000000 27/85 Control registers Bits 5-0 28/85 Name CR12 Name CR13 ADCLG(5:0) ACDRG(5:0) STw5095 Value 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 CR12 and CR13 Description Left (CR12) and Right (CR13) Channels ADC Digital Gain 8.0dB Gain 7.0dB Gain 6.0dB Gain 5.0dB Gain 4.0dB Gain 3.0dB Gain 2.0dB Gain 1.0dB Gain 0.0dB Gain (default) -1.0dB Gain -2.0dB Gain -3.0dB Gain -4.0dB Gain -5.0dB Gain -6.0dB Gain -7.0dB Gain -8.0dB Gain -9.0dB Gain -10.0dB Gain -11.0dB Gain -12.0dB Gain -14.0dB Gain -16.0dB Gain -18.0dB Gain -20.0dB Gain -22.0dB Gain -24.0dB Gain -26.0dB Gain -28.0dB Gain -30.0dB Gain -33.0dB Gain -36.0dB Gain -39.0dB Gain -42.0dB Gain -45.0dB Gain -48.0dB Gain -51.0dB Gain -57.0dB Gain -dB Gain Def. 001000 STw5095 Control registers 5.4 DSP control CR# (hex) Description D7 D6 CR14 (0Eh) Bass/Treble/De-emphasis CR15 (0Fh) DA to AD mixing gain X X CR16 (10h) AD to DA mix/sidetone gain X X Bits 7 6-4 3-0 Name DYNC TREBLE(2:0) BASS(3:0) DYNC D5 D4 D3 D2 TREBLE(2:0) BASS(3:0) X Value D1 DA2ADG(4:0) AD2DAG(5:0) CR14 Description D0 Def. 0000 0000 0000 0000 0000 0000 Def. 1 0 Audio Dynamic Compression in D/A path is enabled Audio Dynamic Compression in D/A path is disabled 011 010 001 000 111 110 101 100 Treble Control in D/A path +6.0dB Treble Gain +4.0dB Treble Gain +2.0dB Treble Gain 0.0dB Treble Gain -2.0dB Treble Gain -4.0dB Treble Gain -6.0dB Treble Gain De-emphasis filter enabled 000 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 Bass Control in D/A path +12.5dB Bass Gain +10.0dB Bass Gain +7.5dB Bass Gain +5.0dB Bass Gain +2.5dB Bass Gain 0.0dB Bass Gain -2.5dB Bass Gain -5.0dB Bass Gain -7.5dB Bass Gain -10.0dB Bass Gain -12.5dB Bass Gain 0000 0 29/85 Control registers Bits 4-0 Name DA2ADG(4:0)* STw5095 Value 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 CR15 Description DA to AD mixing (Audio filter in D/A and A/D path selected) DA to AD mixing Disabled (default) +2.0dB Gain 0.0dB Gain -2.0dB Gain -4.0dB Gain -6.0dB Gain -8.0dB Gain -10.0dB Gain -12.0dB Gain -14.0dB Gain -16.0dB Gain -18.0dB Gain -20.0dB Gain -22.0dB Gain -24.0dB Gain -26.0dB Gain -28.0dB Gain -30.0dB Gain -32.0dB Gain -34.0dB Gain -36.0dB Gain -38.0dB Gain -40.0dB Gain * When Voice filter in D/A or A/D path is selected this function is disabled Note: D/A to A/D mixing is performed at AD data rate, so if A/D and D/A rates are different then asynchronous sampling artifacts may occur. 30/85 Def. 00000 STw5095 Bits 5-0 Control registers Name AD2DAG(5:0) Value 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 CR16 Description AD to DA mixing (sidetone) AD to DA mixing Disabled (default) -1.0dB Gain -2.0dB Gain -3.0dB Gain -4.0dB Gain -5.0dB Gain -6.0dB Gain -7.0dB Gain -8.0dB Gain -9.0dB Gain -10.0dB Gain -11.0dB Gain -12.0dB Gain -13.0dB Gain -14.0dB Gain -15.0dB Gain -16.0dB Gain -17.0dB Gain -18.0dB Gain -19.0dB Gain -20.0dB Gain -21.0dB Gain -22.0dB Gain -23.0dB Gain -24.0dB Gain -25.0dB Gain -26.0dB Gain -27.0dB Gain -28.0dB Gain -29.0dB Gain -30.0dB Gain -31.0dB Gain -32.0dB Gain -33.0dB Gain -34.0dB Gain -35.0dB Gain -36.0dB Gain -37.0dB Gain -38.0dB Gain -39.0dB Gain -40.0dB Gain -41.0dB Gain -42.0dB Gain Def. 000000 31/85 Control registers 5.5 Analog functions CR# (hex) Description CR17 (11h) Mixer Switches & Mic Bias CR18 (12h) Input Switches CR19 (13h) Drivers Control Bits STw5095 Name D7 D6 D5 D4 D3 MBIAS X MBIASPD ADMIC ADLIN MIXMIC IN2VCM LINMUTE VCML(1:0) Value X LINSEL(1:0) MUTELO D2 D1 D0 MIXLIN MIXDAC MICLO Def. 0000 0000 MICMUTE MICSEL(1:0) 0010 0100 LSLIM LSSEL(1:0) 0101 1000 MUTEHP CR17 Description Def. 1 0 Microphone Bias Enabled (2.1V typ at MBIAS Pin) Microphone Bias Disabled 0 1 0 MBIAS Pin is pulled down when Microphone Bias is disabled MBIAS Pin is in High Impedance state when Microphone Bias is disabled 0 ADMIC 1 0 Microphone Preamplifiers are connected to AD path Microphone Preamplifiers are not connected to AD path 0 4 ADLIN 1 0 Line In Preamplifiers are connected to AD path Line In Preamplifiers are not connected to AD path 0 3 MIXMIC 1 0 Microphone Preamplifiers are connected to Mixers Microphone Preamplifiers are not connected to Mixers 0 2 MIXLIN 1 0 Line In Preamplifiers are connected to Mixers Line In Preamplifiers are not connected to Mixers 0 1 MIXDAC 1 0 Stereo DAC path is connected to Mixers Stereo DAC path is not connected to Mixers 0 0 MICLO 1 0 Microphone Preamplifiers are connected to Line Out Drivers Mixers are connected to Line Out Drivers 0 7 MBIAS 6 MBIASPD 5 32/85 STw5095 Bits Control registers Name Value CR18 Description Def. 6 IN2VCM 1 0 Unused Analog input pins are biased to Common Mode voltage Unused Analog input pins are in high impedance state 0 5 LINMUTE 1 0 Line In Preamplifiers are muted Line In Preamplifiers are not muted 1 Input Pins connected to Line In Preamplifiers (if LINMUTE=0) 4-3 2 LINSEL(1:0) MICMUTE 00 01 10 11 LINEIN AUX1 AUX2 AUX3 (LINEINL, LINEINR) (AUX1L, AUX1R) (AUX2LP-AUX2LN, AUX2RP-AUX2RN) 1 0 Microphone Preamplifiers are muted Microphone Preamplifiers are not muted 00 (AUX3L, AUX3R) 1 Input Pins connected to Microphone Preamplifiers (if MICMUTE=0) 1-0 Bits MICSEL(1:0) Name MIC AUX1 AUX2 AUX3 00 01 10 11 (MICLP-MICLN, MICRP-MICRN) (AUX1L, AUX1R) (AUX2LP-AUX2LN, AUX2RP-AUX2RN) 00 (AUX3L, AUX3R) Value CR19 Description Def. 00 01 10 11 Common Mode Voltage Level for Line Out and Headphones drivers 1.20 V 1.35 V (default) 1.50 V 1.65 V 01 7-6 VCML(1:0) 4 MUTELO 1 0 Line Out Drivers are muted Line Out Drivers are not muted 1 3 MUTEHP 1 0 Headphones Drivers (HP) are muted Headphones Drivers (HP) are not muted 1 1 Loudspeaker Driver (LS) gain is limited when VCCLS is above 4.2V typ Loudspeaker Driver (LS) gain is not limited 0 2 LSLIM 0 1-0 LSSEL(1:0) 00 01 Mute Right 10 Left 11 Mono Loudspeaker Driver (LS) is muted Right Channel Mixer only connected to Loudspeaker driver Left Channel Mixer only connected to Loudspeaker driver (Left + Right)/2 Channel Mixers connected to Loudspeaker driver 00 33/85 Control registers 5.6 STw5095 Digital audio interfaces master mode and clock generators CR# (hex) Description CR20 (14h) DAOCK Frequency Ls byte DAOCKF(7:0) 0000 0000 CR21 (15h) DAOCK Frequency Ms byte DAOCKF(15:8) 0000 0000 CR22 (16h) DA Clock Generator Control CR23 (17h) ADOCK Frequency Ls byte CR24 (18h) ADOCK Frequency Ms byte CR25 (19h) AD Clock Generator Control Bits Name CR21-20 Name CR24-23 D7 D6 X X D5 D4 DAMAST DAMASTGEN D3 ENDAOCK D2 DAOCK512 D1 D0 DAPCMF(1:0) ADOCKF(7:0) X ADMAST Value ADMASTGEN ENADOCK 0000 0000 0000 0000 ADOCKF(15:8) X Def. 0000 0000 ADOCK512 ADPCMF(1:0) CR21-20 and CR24-23 Description 0000 0000 Def. The following formulas can be used to obtain the value of K for the desired FS or OCK respectively in the clock generator K ( FS ) = round 2 25 FS ------------------------------------------------------------ AMCK MCKCOEFF K ( OCK ) = round 2 15-0 DAOCKF(15:0) ADOCKF(15:0) 25 OCK ------------------------------------------------------------------------------ AMCK MCKCOEFF OSR K 0000h FS: OCK: AMCK: MCKCOEFF: OSR: Data Rate (DA_SYNC or AD_SYNC frequency in Master Mode) Oversampled Clock Frequency (DA_OCK or AD_OCK) Input Master Clock Frequency See CR30 for definition See bit 2 in CR22 and CR25 Note: CR21-20 and CR24-23 are meaningful in Master Mode Only. 34/85 STw5095 Bits Name CR22 (Name CR25) Control registers Value CR22 and CR25 Description Def. 5 DAMAST (ADMAST) 1 0 DA (AD) Audio interface is in Master Mode (low impedance output) DA (AD) Audio interface is in Slave Mode (high impedance input) 0 4 DAMASTGEN (ADMASTGEN) 1 0 DA (AD) Master Generator is enabled DA (AD) Master Generator is disabled 0 3 ENDAOCK (ENADOCK) 1 0 DA_OCK (AD_OCK) Output Clock is enabled DA_OCK (AD_OCK) Output Clock is disabled 0 Definition of DA_OSR (AD_OSR) DA_OCK/DA_SYNC (AD_OCK/AD_SYNC) Ratio In Master Mode is 512 DA_OCK/DA_SYNC (AD_OCK/AD_SYNC) Ratio In Master Mode is 256 0 DA_CK/DA_SYNC (AD_CK/AD_SYNC) Ratio in PCM Master Mode - 16when CR26 DAWL=000 (CR27 ADWL=000) - 32when CR26 DAWL000 (CR27 ADWL000) - 64 - 128 - 256when CR22 DAOCK512=0 (CR25 ADOCK512=0) - 512when CR22 DAOCK512=1 (CR25 ADOCK512=1) 00 2 1-0 DAOCK512 (ADOCK512) DAPCMF(1:0) (ADPCMF(1:0)) 1 0 00 00 01 10 11 11 35/85 Control registers 5.7 STw5095 Digital audio interfaces CR# (hex) Description D7 D6 D5 D4 D3 D2 D1 D0 Def. CR26 (1Ah) DAC Data IF Control X DAFORM(2:0) DASPIM DAWL(2:0) 0000 0000 CR27 (1Bh) ADC Data IF Control ADRTOL ADFORM2:0) ADSPIM ADWL(2:0) 0000 0000 CR28 (1Ch) DAC&ADC Data IF Control AMCKINV Bits Name DACKP DASYNCP DAMONO Value ADCKP ADSYNCP ADMONO ADHIZ CR26 Description 0000 0000 Def. DA Audio Interface Format Selection 6-4 DAFORM(2:0) 3 DASPIM 2-0 Bits 7 DAWL(2:0) Name ADRTOL 000 001 010 011 100 111 1 0 000 001 010 011 100 Delayed Format (I2S Compatible) Left Aligned Format Right Aligned Format DSP Format SPI Format PCM Format (uses left channel) DA interface in SPI mode receives one word for both channels DA interface in SPI mode receives two words (alternated, left channel first) DA interface word length 16 bit 18 bit 20 bit 24 bit 32 bit Value 1 0 000 0 000 CR27 Description AD Right Channel sent to PCM I/F (must set ENADCR=0 in CR1) Normal Operation Def. 0 AD Audio Interface Format Selection 6-4 ADFORM(2:0) 3 ADSPIM 2-0 36/85 ADWL(2:0) 000 001 010 011 100 111 1 0 000 001 010 011 100 Delayed Format (I2S compatible) Left Aligned Format Right Aligned Format DSP Format SPI Format PCM Format (sends out left channel) AD interface in SPI mode sends one channel (left) AD interface in SPI mode sends two channels (alternated, left first) AD interface word length 16 bit 18 bit 20 bit 24 bit 32 bit 000 0 000 STw5095 Bits Control registers Name Value CR28 Description Def. 7 AMCKINV 1 0 AMCK is inverted AMCK is not inverted 0 6 DACKP 1 0 DA Bit Clock Pin (DA_CK) polarity is inverted DA Bit Clock Pin (DA_CK) polarity is not inverted 0 1 0 DSP and PCM Formats in DA Interface Non Delayed format Delayed Format 1 0 Delayed, Left-aligned, Right-aligned and SPI Formats in DA Interface DA Sync Pin (DA_SYNC) polarity is inverted DA Sync Pin (DA_SYNC) polarity is not inverted 5 DASYNCP 0 1 4 3 2 0 0 Mono Mode: (L+R)/2 from Audio Interface is used on both DAC channels Stereo Mode 1 0 AD Bit Clock Pin (AD_CK) polarity is inverted AD Bit Clock Pin (AD_CK) polarity is not inverted 0 1 0 DSP and PCM Formats in AD Interface Non Delayed format Delayed Format 1 0 Delayed, Left-aligned, Right-aligned and SPI Formats in AD Interface DA Sync Pin (DA_SYNC) polarity is inverted DA Sync Pin (DA_SYNC) polarity is not inverted DAMONO ADCKP ADSYNCP 1 1 ADMONO 0 1 0 ADHIZ 0 0 Mono Mode: (L+R)/2 from ADC is sent to both channels in the Audio Interface Stereo Mode 0 AD data pin (AD_DATA) is in high impedance state when no data is available AD data pin (AD_DATA) is forced to 0 when no data is available 0 37/85 Control registers 5.8 STw5095 Digital filters, software reset and master clock control CR# (hex) Description CR29 (1Dh) Digital Filters Control CR30 (1Eh) Soft Reset & AMCK Range Bits Name D7 D6 D5 D4 X DAVOICE DA96K SWRES X X Value D3 D2 RXNH ADVOICE AD96K X AMCKSIN D1 D0 ADNH TXNH CKRANGE(2:0) Def. 0000 0000 0000 0000 CR29 Description Def. 6 DAVOICE 1 0 DA path Voice RX filter is enabled (single channel, left used) DA path Audio filters are enabled 0 5 DA96K 1 0 DA path data rate is in the range 88 kHz to 96 kHz DA path data rate is in the range 8 kHz to 48 kHz 0 4 RXNH 1 0 DA path High pass Voice RX filter is disabled DA path High pass Voice RX filter is enabled (300Hz @ 8kHz rate) 0 3 ADVOICE 1 0 AD path Voice TX filter is enabled (single channel, left used) AD path Audio filters are enabled 0 2 AD96K 1 0 AD path data rate is in the range 88 kHz to 96 kHz AD path data rate is in the range 8 kHz to 48 kHz 0 1 ADNH 1 0 AD path Audio DC filter is disabled AD path Audio DC filter is enabled 0 0 TXNH 1 0 AD path High pass Voice TX filter is disabled AD path High pass Voice TX filter is enabled (300Hz @ 8kHz rate) 0 Bits Name Value CR30 Description Def. 7 SWRES 1 0 Software reset: All registers content is reset to the default value Control Register content is left unchanged 0 3 AMCKSIN 1 0 Signal at AMCK pin is a sinusoid Signal at AMCK pin is a square wave 0 2-0 CKRANGE(2:0) 5.9 CR# (hex) CR31 (1Fh) 38/85 000 001 010 011 100 101 4.0 6.0 8.0 12.0 16.0 24.0 AMCK range MHz to6.0MHz MHz to8.0MHz MHz to12.0MHz MHz to16.0MHz MHz to24.0MHz MHz to32.0MHz MCKCOEFF 8.0 6.0 4.0 3.0 2.0 1.5 000 Interrupt control and control interface SPI out mode Description interrupt Mask D7 D6 D5 D4 D3 D2 D1 D0 Def. VLSHEN PUSHBEN HSDETEN VLSHMSK PUSHBMSK HSDETMSK OVFMSK PORMSK 0000 0000 STw5095 CR# (hex) Control registers Description CR32 (20h) Interrupt Status CR33 (21h) Misc. Control Bits Name D7 D6 VLSH X Value D5 D4 D3 PUSHB HSDET VLSHEV PUSHBEV X SPIOHIZ SPIOSEL(1:0) D2 D1 D0 Def. HSDETEV OVFEV POREV 0000 0000 IRQCMOS OVFDA OVFAD 0000 0000 CR31 Description Def. 7 VLSHEN 1 0 VLSH status can be seen at IRQ output VLSH status is masked 0 6 PUSHBEN 1 0 PUSHB status can be seen at IRQ output PUSHB status is masked 0 5 HSDETEN 1 0 HSDET status can be seen at IRQ output HSDET status is masked 0 4 VLSHMSK 1 0 VLSH event can be seen at IRQ output VLSH event is masked 0 3 PUSHBMSK 1 0 PUSHB event can be seen at IRQ output PUSHB event is masked 0 2 HSDETMSK 1 0 HSDET event can be seen at IRQ output HSDET event is masked 0 1 OVFMSK 1 0 OVF event can be seen at IRQ output OVF event is masked 0 0 PORMSK 1 0 POR event can be seen at IRQ output POR event is masked 0 Note: Value at IRQ pin is: IRQ = (1 or Z) when (CR31 & CR32) = 00 hex 0 when (CR31 & CR32) 00 hex 39/85 Control registers Bits Name STw5095 Read only CR32 Description Def. 7 VLSH* 1 0 VCCLS is above 4.2 V 6 PUSHB* 1 0 Headset Button is pressed Headset Button is released 0 5 HSDET* 1 0 Headset Connector is inserted Headset Connector is not inserted 0 4 VLSHEV 1 0 VLSH bit has changed VLSH bit has not changed 0 3 PUSHBEV 1 0 Headset Button Status has changed Headset Button Status has not changed 0 2 HSDETEV 1 0 Headset Connector Status has changed Headset Connector Status has not changed 0 1 OVFEV 1 0 An Audio Data overflow has occurred in DSP No Audio Data overflow has occurred in DSP 0 0 POREV 1 0 Device was reset by Power-On-Reset Device was not reset by Power-On-Reset 0 0 VCCLS is below 4.0 V Note: content of bits 4 to 0 in CR32 is cleared after reading, while it is left unchanged if accessed for writing. *Bits 7 to 5 represent the status when the Control register is read, not when the event occurred. Bits Name Val. 1 5 4-3 Def. 0 0 SPI Control Interface Out Pin is set to high impedance state when inactive SPI Control Interface Out Pin is set to zero when inactive 00 01 10 11 Out Pin Selection for SPI Control Interface No output. Control registers cannot be read in SPI mode SPI Output sent to IRQ pin SPI Output sent to DA_OCK pin SPI Output sent to AD_OCK pin 00 SPIOHIZ SPIOSEL(1:0) CR33 Description 2 IRQCMOS 1 0 IRQ Interrupt Request Pin is set to CMOS (active low) IRQ Interrupt Request Pin is set to Pull Down 0 1 OVFDA 1 0 An overflow (saturation) occurred in DA path No overflow occurred in DA channel 0 0 OVFAD 1 0 An overflow (saturation) occurred in AD path No overflow occurred in AD channel 0 Note: content of bits 1 to 0 in CR33 is cleared after reading, while it is left unchanged if accessed for writing. 40/85 STw5095 5.10 CR# (hex) Control registers AGC Description CR34 (22h) AGC Attack/Decay coeff. CR35 (23h) AGC Control Bits Name D7 D6 X ENAGCLIN D5 D4 D3 AGCATT(3:0) ENAGCMIC Value AGCRANGE D2 D1 D0 Def. AGCDEC(3:0) 0000 0000 AGCLEV(3:0) 0000 0000 CR34 Description Def. AGC Attack Time Constant; FS=AD data rate 7-4 AGCATT(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Audio filter in AD path 4096/ FS 2048/ FS 1365/ FS 1024/ FS 683/ FS 512/ FS 341/ FS 256/ FS 171/ FS 128/ FS 85/ FS 64/ FS 43/ FS 32/ FS Voice filter in AD path 8192/ FS 4096/ FS 2731/ FS 2048/ FS 1365/ FS 1024/ FS 683/ FS 512/ FS 341/ FS 256/ FS 171/ FS 128/ FS 85/ FS 64/ FS 0000 AGC Decay Time Constant; FS=AD data rate 3-0 AGCDEC(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Audio filter in AD path 65536/ FS 32768/ FS 21845/ FS 16384/ FS 10923/ FS 8192/ FS 5461/ FS 4096/ FS 2731/ FS 2048/ FS 1365/ FS 1024/ FS 683/ FS 512/ FS 341/ FS 256/ FS Voice filter in AD path 131072/ FS 65536/ FS 43691/ FS 32768/ FS 21845/ FS 16384/ FS 10923/ FS 8192/ FS 5461/ FS 4096/ FS 2731/ FS 2048/ FS 1365/ FS 1024/ FS 683/ FS 512/ FS 0000 41/85 Control registers Bits Name STw5095 Value CR35 Description Def. 6 ENAGCLIN 1 0 AGC control on AD path acts on Line In Gain AGC control on AD path does not act on Line In Gain 0 5 ENAGCMIC 1 0 AGC control on AD path acts on Mic Gain AGC control on AD path does not act on Mic Gain 0 4 AGCRANGE 1 0 AGC action range is -21.0 dB to +21.0 dB AGC action range is -10.5 dB to +10.5 dB 0 3-0 42/85 AGCLEV(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 AGC requested output level -30.0dB Gain -30.0dB Gain -27.0dB Gain -24.0dB Gain -21.0dB Gain -18.0dB Gain -15.0dB Gain -12.0dB Gain -9.0dB Gain -6.0dB Gain 0000 STw5095 Control interface and master clock 6 Control interface and master clock 6.1 Control interface I2C mode Figure 5. Control interface I2C format ACK WRITE SINGLE BYTE DEVICE ADDRESS 0 0 1 1 0 1 ACK ACK REG n DATA IN REG n ADDRESS AS 0 START STOP ACK WRITE MULTI BYTE DEVICE ADDRESS 0 0 1 1 0 1 ACK ACK REG n+m DATA IN START m+1 data bytes ACK CURRENT ADDR READ SINGLE BYTE DEVICE ADDRESS 0 0 1 1 0 1 NO ACK AS 1 STOP ACK DEVICE ADDRESS 0 0 1 1 0 1 ACK Curr REG+m DATA OUT AS 1 m+1 data bytes ACK DEVICE ADDRESS 0 0 1 1 0 1 STOP ACK ACK DEVICE ADDRESS REG n ADDRESS AS 0 0 START 0 1 1 0 1 NO ACK REG n DATA OUT AS 1 START ACK RANDOM ADDR READ MULTI BYTE NO ACK ACK Current REG DATA OUT START RANDOM ADDR READ SINGLE BYTE STOP Current REG DATA OUT START CURRENT ADDR READ MULTI BYTE ACK ACK REG n DATA IN REG n ADDRESS AS 0 DEVICE ADDRESS 0 0 1 1 0 1 STOP ACK ACK DEVICE ADDRESS REG n ADDRESS AS 0 0 START 0 1 1 0 1 ACK REG n DATA OUT CMOD pin tied to GND Figure 6. Control interface: I2C format timing REG n+m DATA OUT AS 1 START Note: NO ACK ACK m+1 data bytes STOP SDA tBUF tHD (STA) tLOW tHD (DAT) tHIGH tSU (DAT) tSU (STA) tHD (STA) tSU (STO) SCLK tR P S tF Sr P P = STOP S = START Sr = START repeated 43/85 Control interface and master clock Table 2. STw5095 Control interface timing with IC format Symbol Parameter Test Condition Min. Typ. Max. Unit 400 kHz fSCL Clock frequency tHIGH Clock pulse width high 600 ns tLOW Clock pulse width low 1300 ns tR SDA and SCLK rise time 1000 ns tF SDA and SCLK fall time 300 ns tHD:STA Start condition hold time 600 ns tSU:STA Start condition setup time 600 ns tHD:DAT Data input hold time 0 ns tSU:DAT Data input setup time 250 ns tSU:STO Stop condition setup time 600 ns tBUF Bus free time 1300 ns 6.2 Control interface SPI mode Figure 7. Control interface SPI format(a) CSB SCLK SDIN W/R A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 8 bit Address SDO SPIOHIZ=1 D4 D7 D6 D5 D4 D3 8 bit Data a. CMOD pin tied to VCCIO; SDO pin position selected with bits SPIOSEL in CR33. 44/85 D3 D2 D1 D0 D2 D1 D0 8 bit Data STw5095 Figure 8. Control interface and master clock Control interface: SPI format timing tHICS CSB tPSCK tSCSF tLSCK SCLK 0 tSDI SDIN 8 tHDI D7 W/R SPIOHIZ=1 Symbol D0 tDDO tDDOL D7 SPIOHIZ=0 Table 3. tSCSR 15 tDDOF SDO tHCS tHSCK D0 Control interface timing with SPI format Parameter Test Condition Min. Typ. Max. Unit tHICS CSB pulse width high 80 ns tSCSR Setup time CSB rising edge to SCLK rising edge 20 ns tSCSF Setup time CSB falling edge to SCLK rising edge 20 ns tHCS Hold time CSB rising edge from SCLK rising edge 20 ns tSDI Setup time SDIN to SCLK rising edge 20 ns tHDI Hold time SDIN from SCLK rising edge 20 ns tDDOF SDO first Delay time from SCLK falling edge 30 ns tDDO SDO Delay time from SCLK falling edge 20 ns tDDOL SDO Delay time from CSB rising edge 30 ns tPSCK Period of SCK tHSCK SCK pulse width high tLSCK SCK pulse width low 100 ns Measured from VIH to VIH 40 ns Measured from VIL to VIL 40 ns 45/85 Control interface and master clock STw5095 6.3 Master clock timing Table 4. AMCK timing Symbol tCKDC 46/85 Parameter AMCK duty cycle AMCK range 4 MHz-8 MHz 8 MHz-32 MHz Min. 45 40 Typ. Max. Unit 55 60 % % STw5095 Audio interfaces 7 Audio interfaces Figure 9. Audio interfaces formats: delayed, left and right justified I2S format (delayed) with default polarity settings, ADHIZ=0 DA_SYNC/ AD_SYNC DA_CK/ AD_CK 1 AD_CK/DA_CK DA_DATA AD_DATA 1 MSB 2 1 MSB 2 1 AD_CK/DA_CK n-1 n-bit word Left data n-1 n-bit word Left data n LSB 1 MSB n-bit word Right data 2 n-1 n LSB 1 MSB n-bit word Right data 2 n-1 n LSB n LSB Left justified format with default polarity settings, ADHIZ=0 DA_SYNC/ AD_SYNC DA_CK/ AD_CK DA_DATA AD_DATA 1 MSB 2 1 MSB 2 n-1 n-bit word Left data n-1 n-bit word Left data n LSB 1 MSB n-bit word Right data 2 n-1 n LSB 1 MSB n-bit word Right data 2 n-1 n LSB n LSB Right justified format with default polarity settings 32 AD_CK/DA_CK 32 AD_CK/DA_CK DA_SYNC/ AD_SYNC DA_CK/ AD_CK DA_DATA AD_DATA 1 MSB 2 1 MSB 2 n-1 n-bit word Left data n-1 n-bit word Left data n LSB 1 MSB n-bit word Right data 2 n LSB 1 MSB n-bit word Right data 2 n-1 n-1 n LSB n LSB 47/85 Audio interfaces STw5095 Figure 10. Audio interfaces formats: DSP, SPI and PCM DSP format delayed and non-delayed (default AD_CK/DA_CK polarity, ADHIZ=0) DA_SYNC/ AD_SYNC { SYNCP=0 SYNCP=1 DA_CK/ AD_CK DA_DATA AD_DATA 1 MSB 2 1 MSB 2 n-1 n-bit word Left data n-1 n-bit word Left data n 1 LSB MSB n-bit word Right data 2 n 1 LSB MSB n-bit word Right data 2 n-1 n LSB n-1 n LSB SPI format (slave only) (default AD_CK/DA_CK polarity, ADHIZ=1 - Stereo or Mono) DA_SYNC/ AD_SYNC DA_CK/ AD_CK DA_DATA AD_DATA x 1 MSB 2 1 MSB 2 3 n-1 n-bit word Left/Mono data 3 n-1 n-bit word Left/Mono data n LSB 1 MSB High impedance n LSB x 1 MSB 2 3 n-bit word Right/Mono data 2 3 n-bit word Right/Mono data PCM format (default AD_CK/DA_CK polarity, ADHIZ=1) DA_SYNC/ AD_SYNC { SYNCP=0 SYNCP=1 DA_CK/ AD_CK DA_DATA AD_DATA 48/85 1 MSB 2 1 MSB 2 3 n-1 n LSB n-1 n LSB n-bit word Mono data 3 n-bit word Mono data 1 MSB High impedance 1 MSB STw5095 Audio interfaces Figure 11. Audio interface timings: Master mode DA_SYNC/ AD_SYNC tDSY DA_CK/ AD_CK { CKP=0 CKP=1 tSDDA tHDDA DA_DATA tDAD AD_DATA PCM format only tDAD tDADZ ADHIZ=1 ADHIZ=1 ADHIZ=0 ADHIZ=0 tDAD AD_DATA All other formats ADHIZ=1 ADHIZ=1 ADHIZ=0 ADHIZ=0 Figure 12. Audio interface timing: Slave mode DA_SYNC/ AD_SYNC tHSY DA_CK/ AD_CK { tSSY CKP=0 tHCK tLCK CKP=1 tSDDA tHDDA tPCK DA_DATA tDADST AD_DATA PCM format tDAD tDADZ ADHIZ=1 ADHIZ=1 ADHIZ=0 ADHIZ=0 tDAD AD_DATA All other formats ADHIZ=1 ADHIZ=1 ADHIZ=0 ADHIZ=0 tDAD 49/85 Audio interfaces Table 5. Symbol STw5095 Audio interface signals timing Parameter Test Condition Min. Typ. Max. Unit 10 ns tDSY Delay of AD_SYNC/DA_SYNC Master Mode edge from AD_CK/DA_CK active edge tSDDA Setup time DA_DATA to DA_CK active edge 10 ns tHDDA Hold time DA_DATA from DA_CK active edge 10 ns tDAD Delay of AD_DATA edge from AD_CK active edge 30 ns tDADST Delay of the first AD_DATA AD_SYNC active edge comes edge from AD_SYNC after AD_CK active edge active edge 30 ns tDADZ Delay of AD_DATA high impedance from AD_SYNC inactive edge PCM format 10 50 ns tSSY Setup time AD_SYNC/DA_SYNC to AD_CK/DA_CK active edge Slave Mode 20 ns tHSY Hold time AD_SYNC/DA_SYNC from Slave Mode AD_CK/DA_CK active edge 20 ns tPCK Period of AD_CK/DA_CK Slave Mode 100 ns tHCK AD_CK/DA_CK pulse width high Measured from VIH to VIH 40 ns tLCK AD_CK/DA_CK pulse width low Measured from VIL to VIL 40 ns 50/85 STw5095 8 Timing specifications Timing specifications Unless otherwise specified, VCCIO = 1.71 V to 2.7 V,Tamb = -30C to 85C, max capacitive load 20 pF; typical characteristics are specified at VCCIO = 2.4 V, Tamb = 25 C; all signals are referenced to GND, see Note below figure for timing definitions. Figure 13. A.C. testing input-output waveform INPUT OUTPUT 0.8*VCCIO 0.7*VCCIO 0.2*VCCIO 0.3*VCCIO TEST POINTS 0.7*VCCIO 0.3*VCCIO AC Testing: inputs are driven at 0.8*VCCIO for a logic `1' and 0.2*VCCIO for a logic `0'. Timing measurements are made at 0.7*VCCIO for a logic `1' and 0.3*VCCIO for a logic `0'. Note: A signal is valid if it is above VIH or below VIL and invalid if it is between VIL and VIH. For the purpose of this specification the following conditions apply (see Figure 13 above): a) All input signal are defined as: VIL = 0.2*VCCIO, VIH = 0.8*VCCIO, tR < 10ns, tF < 10ns. b) Delay times are measured from the inputs signal valid to the output signal valid. c) Setup times are measured from the data input valid to the clock input invalid. d) Hold times are measured from the clock signal valid to the data input invalid. Note: All timing specifications subject to change. 51/85 Operative ranges STw5095 9 Operative ranges 9.1 Absolute maximum ratings Table 6. Absolute maximum ratings Parameter Value Unit VCC or VCCIO to GND -0.5 to 3.6 V VCCA or VCCP to GND -0.5 to 5 V VCCLS to GND -0.5 to 7 V GND-0.5 to VCCA+0.5 V Maximum power delivered to the load from LSP/N 500 mW Peak current at HPR,HPL 100 mA Current at VCCP, VCCLS, GNDP 350 mA Current at any digital output 50 mA GND-0.5 to VCCIO+0.5 V Storage temperature range -65 to 150 C Operating temperature range(1) -30 to 85 C -2 to +2 -500 to +500 kV V Voltage at analog inputs (VCCA 3.3V) Voltage at any digital input (VCCIO 2.7V); limited at 50mA Electrostatic discharge voltage (Vesd) Human body model(2) Charge device model(3) 1. in some operating conditions the temperature can be limited to 70 C. See Loudspeaker Driver description from Section 4.9 for details. 2. HBM tests have been performed in compliance with JESD22-A114-B and ESD STM 5.1-2001.HBM 3. CDM tests have been performed in compliance with CDM ANSI-ESDSTM5.3.1-1999 9.2 Operative supply voltage Table 7. Operative power supply Symbol Parameter Condition Min. Max. Unit 1.71 2.7 V VCC Digital supply VCCA Analog supply Note: VCCA VCC A24V=0 (bit 1 in CR0) A24V=1 (bit 1 in CR0) 2.7 2.4 3.3 2.7 V V VCCIO Digital I/O supply D12V=0 (bit 0 in CR0) D12V=1 (bit 0 in CR0) 1.71 1.2 VCC 1.8 V V VCCP Stereo power drivers supply VCCA 3.3 V VCCLS Mono power driver supply VCCA 5.5 V VG Single supply voltage range 2.4 2.7 V 52/85 VCC=VCCA=VCCIO=VCCP=VCCLS A24V=1 (bit 1 in CR0) STw5095 9.3 Operative ranges Power dissipation Unless otherwise specified, VCCP = VCCLS = VCCA = 2.7V to 3.3V, VCCIO = VCC = 1.71V to 2.7V, Tamb = -30C to 85C, all analog outputs not loaded; typical characteristics are specified at VCCIO = VCC = 1.8V, VCCP = VCCLS = VCCA = 2.7V, Tamb = 25C. Table 8. Power dissipation Symbol Parameter Test Condition Min. Typ. Max. Unit 0.4 2.9 W W Stereo ADC power 26.3 mW PDA Stereo DAC power 23.3 mW PDAAD Stereo ADC+DAC power 46.9 mW PAA Stereo Analog Path power 13.8 mW POFF Power Down Dissipation PAD 9.4 No Master Clock AMCK=13MHz Typical power dissipation Tamb = 25C; analog supply: VCCP = VCCLS = VCCA = 2.7V; digital supply: VCCIO = VCC = 1.8V Full scale signal in every path, 20k load at analog outputs. Table 9. N. Typical power dissipation - No master clock Function CR0-CR2 setting Other settings Supply Current Power Analog: Digital: Total: 0.02 A 0.20 A 0.05 W 0.36 W 0.41 W 1 Power Down CR0=0x00 CR1=0x00 CR2=0x00 2 Stereo analog path (Mic-LO) CR0=0xD0 CR1=0x0C CR2=0xC0 MICLO=1 MICSEL=2 Analog: Digital: Total: 4.3 mA 2.0 A 11.6 mW 0.0 mW 11.6 mW 3 Stereo analog path (Mic-Mixer-LO) CR0=0xD0; CR1=0x0C; CR2=0xC3 MIXMIC=1 MICSEL=2 Analog: Digital: Total: 5.4 mA 2.0 A 14.6 mW 0.0 mW 14.6 mW 53/85 Operative ranges Table 10. N. STw5095 Typical power dissipation - Master clock AMCK = 13 MHz Function CR0-CR2 setting Other settings Supply Current Power Analog: Digital: Total: 0.02 A 2.20 A 0.05 W 3.96 W 4.01 W Power Down CR0=0x00 CR1=0x00 CR2=0x00 5 Stereo ADC CR0=0xE8 CR1=0xCC CR2=0x00 MICSEL=1 ADMIC=1 Analog: Digital: Total: 7.9 mA 2.8 mA 21.3 mW 5.0 mW 26.3 mW 6 Stereo DAC CR0=0xE8 CR1=0x30 CR2=0x33 MIXDAC=1 Analog: Digital: Total: 6.1 mA 3.8 mA 16.5 mW 6.8 mW 23.3 mW 7 Stereo analog path (Mic-LO) CR0=0xE8 CR1=0x0C CR2=0xC0 MICLO=1 MICSEL=2 Analog: Digital: Total: 4.8 mA 0.8 mA 13.0 mW 1.4 mW 13.8 mW 8 Stereo ADC Stereo DAC CR0=0xE8 CR1=0xFC CR2=0x33 MICSEL=2 ADMIC=1 MIXDAC=1 Analog: Digital: Total: 13.5 mA 5.8 mA 36.5 mW 10.4 mW 46.9 mW 9 Stereo ADC Stereo DAC Stereo analog path CR0=0xE8 CR1=0xFF CR2=0xF3 LINSEL=2; MICSEL=2 ADLIN=1;MIXDAC=1 MICLO=1 Analog: Digital: Total: 15.2 mA 5.8 mA 41.0 mW 10.4 mW 51.4 mW MICSEL=2; LSMODE=2 ADMIC=1 MIXDAC=1 ADVOICE=1 DAVOICE=1 VCCA,VCCP: Voice TX+RX CR0=0xE8 CR1=0xA8 CR2=0x06 6.8 mA 1.3 mA 2.5 mA 18.4 mW 5.5 mW 4.5 mW 28.4 mW 4 10 54/85 VCCLS: Digital Total: STw5095 10 Electrical characteristics Electrical characteristics Unless otherwise specified, VCCIO = 1.71 V to 2.7 V, Tamb = -30C to 85C; typical characteristic are specified at VCCIO = 2.0 V, Tamb = 25C; all signals are referenced to GND. 10.1 Digital interfaces Table 11. Digital interfaces electrical characteristics Symbol Parameter VIL Input low voltage VIH Input high voltage VOL Output low voltage VOH Output high voltage Test Condition All digital inputs Min. Typ. DC AC Max. Unit 0.3*VCCIO V V 0.2*VCCIO DC 0.7*VCCIO AC 0.8*VCCIO All digital inputs, All digital outputs IL = 10A IL = 2A All digital outputs IL = 10A VCCIO-0.1 IL = 2A VCCIO-0.4 V V 0.1 0.4 V V V V IIL Input low current Any digital input, GND < VIN < VIL -1 1 A IIH Input high current Any digital input, VIH < VIN < VCCIO -1 1 A IOZ Output current in high impedance (Tristate) Tristate outputs -1 1 A Max. Unit Note: See Figure 13: A.C. testing input-output waveform on page 51. 10.2 AMCK with sinusoidal input Table 12. AMCK with sinusoidal input Symbol Parameter Test Condition Min. CAMCK Minimum External Capacitance AMCKSIN=1, see CR30 100 VAMCK AMCK sinusoidal voltage swing AMCKSIN=1, see CR30 0.5 Typ. pF VCCIO VPP 55/85 Electrical characteristics STw5095 10.3 Analog interfaces Table 13. Analog interfaces Symbol Parameter Test Condition GND< VMIC< VCCA Min. IMIC MIC input leakage RMIC MIC input resistance 30 RLIN Line in input resistance 30 RLHP Headphones (HP) drivers load resistance HPL, HPR to GNDP or VCMHP CLHP Headphones (HP) drivers load capacitance HPL, HPR to GNDP or VCMHP RLLS Loudspeaker (LS) differential driver load resistance LSP to LSN CLLS Loudspeaker (LS) differential driver load capacitance LSP to LSN VOFFLS Differential offset voltage at LSP, LSN RL = 50 RLOL Line out (OL) diff./singleended driver load resistance OLP/ORP to OLN/ORN or OLP/ORP to GND (decoupled) Typ. -100 14.4 Max. Unit +100 A 50 k k 16/32 50 50* 6.4 pF nF 8 -50 50 50* pF nF +50 mV 1 k * with series resistor 10.4 Headset plug-in and push-button detector Table 14. Headset plug-in and push-button detector Symbol Parameter Test Condition HDVL Plug-in detected Voltage at HDET HDVH Plug-in undetected Voltage at HDET HDH Plug-in detector hysteresis PBVL Push-button pressed Voltage at HDET PBVH Push-button released Voltage at HDET PBD Push-button de-bounce time 56/85 Min. Typ. Max. Unit VCCA-1 V VCCA-0.5 V 100 mV 0.5 1 15 V V 50 ms STw5095 Electrical characteristics 10.5 Microphone bias Table 15. Microphone bias Symbol Parameter VMBIAS MBIAS output voltage IMBIAS MBIAS output current RMBIAS MBIAS output load CMBIAS MBIAS output capacitance PSRMB4 PSRMB20 MBIAS power supply rejection Test Condition Max. Unit 1.95 2.1 2.25 V 1.1 mA 3.5 k 150 f<4kHz f<20kHz Power supply rejection ratio Table 16. Power supply ratio Parameter Test Condition 60 50 pF dB dB Min. Typ. Max. Unit Each output(LSP, LSN) f<20kHz f<200kHz 65 47 dB dB PSRR VCCP Headphones f<20kHz Line out single ended f<20kHz Line out differential f<20kHz 65 65 65 dB dB dB PSRR VCCA Mic input f<20kHz Line In f<20kHz 50 50 dB dB PSRL20 PSRL200 PSRR VCCLS PSRPH PSRPOS PSRPOD PSRAM PSRAL 10.7 LS gain limiter Table 17. LS gain limiter Symbol Typ. From MBIAS to ground 10.6 Symbol Min. Parameter Test Condition Min. Typ. Max. Unit VLSLIMH High voltage at VCCLS (VLSH=1) VCCLS raising 4.2 V VLSLIML Low voltage at VCCLS (VLSH=0) VCCLS falling 4.0 V VLSLIMD VCCLS Hysteresis 200 mV Note: See CR32 for VLSH definition. See Loudspeaker driver description in Section 4.9 for details. 57/85 Analog input/output operative ranges STw5095 11 Analog input/output operative ranges 11.1 Analog levels Table 18. Reference full scale analog levels Symbol 11.2 Parameter Test Condition Min. Typ. Max. Unit 0dBFS level 2.7V < VCCA < 3.3V 12 4 dBVpp 0dBFS level low voltage mode 2.4V < VCCA < 2.7V 10 3.18 dBVpp Vpp Vpp Microphone input levels Analog supply range: 2.7 V < VCCA < 3.3 V Table 19. Symbol Absolute levels at pins connected to preamplifiers Parameter Test Condition Typ. Max. Unit 707 2 -6 mVRMS Vpp dBFS MIC gain > 6dB - (MIC_Gain) dBFS MIC gain = 0dB 1.41 4 0 mVRMS Vpp dBFS - (MIC_Gain) dBFS Overload level, single ended MIC gain = 0 to 6dB Overload level,single ended, versus MIC gain Overload level, differential Overload level, differential, MIC gain > 0dB versus MIC gain Note: When 2.4 V < VCCA < 2.7 V, voltage values are reduced by 2dB. 58/85 Min. STw5095 11.3 Analog input/output operative ranges Line input levels Analog supply range: 2.7 V < VCCA < 3.3 V Table 20. Symbol Absolute levels at pins connected to the line-in amplifiers Parameter Test Condition Overload level, single ended Line in gain from -20dB to 6dB Overload level (single ended) versus line in gain Line in gain > 6dB Min. Overload level (differential) Line in gain from -20dB to 0dB Overload level (differential) Line in gain > 0dB versus line in gain Typ. Max. Unit 707 2 -6 mVRMS Vpp dBFS - (Line_In_Gain) dBFS 1.41 4 0 mVRMS Vpp dBFS - (Line_In_Gain) dBFS Typ. Unit Note: When 2.4 V < VCCA < 2.7 V, the values are reduced by 2dB 11.4 Line output levels Analog supply range: 2.7 V < VCCA < 3.3 V Table 21. Symbol Absolute levels at OLP/OLN, ORP/ORN Parameter Test Condition Min. Max. Output level, single ended 0 dB gain Full scale digital input 707 2 -6 mVRMS Vpp dBFS Output level, differential 0 dB gain Full scale digital input 1.41 4 0 mVRMS Vpp dBFS Note: When 2.4 V < VCCA < 2.7 V, the values are reduced by 2dB 59/85 Analog input/output operative ranges 11.5 STw5095 Power output levels HP Analog supply range: 2.7 V < VCCA < 3.3 V Table 22. Symbol Absolute levels at HPL - HPR Parameter Output level Max output power(1) Test Condition Min. Max. Unit mVRMS Vpp 707 2 -6 -6dB gain Full scale digital input 16 load VCCP > 3.2 V Typ. dBFS 40 mW Note: When 2.4 V < VCCA < 2.7 V, the values are reduced by 2dB 11.6 Power output levels LS Analog supply range: 2.7 V < VCCA < 3.3 V Table 23. Symbol Absolute levels at LSP - LSN (differential) Parameter Output level Max output power(1) Test Condition Min. 1.41 4 0 0 dB gain Full scale digital input 8 load VCCLS > 4V Typ. 500 Max. Unit VRMS Vpp dBFS mW 1. In some operating conditions the maximum output power can be limited. See "Section 9.1: Absolute maximum ratings" and "Loudspeaker Driver" description from Section 4.9: Analog output drivers for details. Note: When 2.4 V < VCCA < 2.7 V, the values are reduced by 2dB 60/85 STw5095 12 Stereo audio ADC specifications Stereo audio ADC specifications Typical measures-VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8 V; Tamb=25C;13 MHz AMCK Table 24. Symbol ADN Stereo audio ADC specifications Parameter Test Condition Min. Typ. Resolution ADDRM ADDRLI Dynamic range 20Hz to 20kHz, A-weighted Measured at -60dBFS MIC input, 21dB gain Line-In, 0dB gain ADSNA ADSN Signal to noise ratio Max level at MIC input, 21dB gain A-weighted Unweighted (20 Hz to 20 kHz) 87 89 Max. Unit 20 Bits 91 93 dB dB 90 86 dB dB 37 3.3 1.9 30 7.5 V V V V V A-weighted Input referred ADC noise ADTHD ADfPB ADfSB ADtgd Mic input 0dB Gain Mic input 21dB Gain Mic input 39dB Gain Line in input 0dB Gain Line in input 18dB Gain Total harmonic distortion Max level at MIC input, 21dB gain Deviation from linear phase Measurement bandwidth 20Hz to 20kHz, Fs= 48kHz. Combined digital and analog filter characteristics Passband Combined digital and analog filter characteristics AD96K=0 Passband ripple Combined digital and analog filter characteristics AD96K=0 Stopband Combined digital and analog filter characteristics AD96K=0 0.55Fs kHz Stopband Attenuation Measurement bandwidth up to 3.45Fs. Combined digital and analog filter characteristics, AD96K=0 60 dB Group delay Audio filters, 96kHz FS Audio filters, 48kHz FS Audio filters, 8kHz FS Interchannel isolation 0.001 0 0.003 % 1 Deg 0.45Fs kHz 0.2 dB 0.11 0.4 2.6 ms ms ms 90 dB Interchannel gain mismatch 0.2 dB Gain error 0.5 dB Note: When 2.4 V < VCCA < 2.7 V, the values are reduced by 2dB 61/85 Stereo audio DAC specifications 13 STw5095 Stereo audio DAC specifications Typical measures - VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25C;13MHz AMCK Table 25. Symbol DAN Stereo audio DAC specifications Parameter Test Condition Min. Typ. Resolution 20Hz to 20kHz, A-weighted. Measured at -60dBFS Differential line out Single-ended line out HPL/HPR to GND or VCMHP LSP-LSN 92 Max. Unit 20 Bits 95 93 94 94 dB dB dB dB 94 90 dB dB DADR Dynamic range DASNA DASN 2Vpp output HPL, HPR gain set to -6dB, 16 load Signal to noise ratio A-weighted Unweighted (20 Hz to 20 kHz) DATHDL Total harmonic distortion Worst case load HPL, HPR gain set to -6dB, 16 load DATHD Total harmonic distortion 2Vpp output, HPL, HPR gain set to -6dB, 1k load Deviation from linear phase Measurement bandwidth 20Hz to 20kHz, Fs= 48kHz. Combined digital and analog filter characteristics Passband Combined digital and analog filter characteristics, DA96K=0 Passband ripple Combined digital and analog filter characteristics, DA96K=0 Stopband Combined digital and analog filter characteristics, DA96K=0 0.55Fs kHz Stopband attenuation Measurement bandwidth up to 3.45Fs. Combined digital and analog filter characteristics, DA96K=0 50 dB DAfPB DAfSB TSF Transient suppression filter cut-off frequency Out of band noise DAtgd 62/85 2Vpp output Group delay 0.02 0.004 0 15 Measurement bandwidth 20 kHz to 100 kHz. Zero input signal Audio filters, 96kHz FS Audio filters, 48kHz FS Audio filters, 8kHz FS 0.04 % % 1 Deg 0.45Fs kHz 0.2 dB 23 Hz -85 dBr 0.09 0.4 2.6 ms ms ms STw5095 Table 25. Symbol AD to DA mixing (sidetone) specifications Stereo audio DAC specifications Parameter Interchannel isolation SUT Test Condition Min. 2Vpp output HPR, HPL unloaded HPR, HPL with 16 to VCMHP Typ. Max. 100 60 Unit dB dB Interchannel gain mismatch 0.2 dB Gain error 0.5 dB Startup time from power up FS=48 kHz Line out HPL/R out 1 10 ms ms Note: When 2.4 V < VCCA < 2.7 V, values are reduced by 2 dB 14 AD to DA mixing (sidetone) specifications Typical measures - VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25C;13MHz AMCK Table 26. Symbol STDEL AD to DA mixing (sidetone) specifications Parameter AD to DA mixing (sidetone) delay Test Condition Valid for audio and voice filters Min. Typ. Max. Unit 5 10 s 63/85 Stereo analog-only path specifications 15 STw5095 Stereo analog-only path specifications Measured at differential line-out, ENOSC=1, No master clock. Typical measures at VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25C Table 27. Symbol Stereo analog-only path specifications Parameter Test Condition Min. Typ. 90 90 95 97 dB dB 97 94 dB dB AADRM AADRLI Dynamic range 20Hz to 20kHz, A-weighted. Measured at -60dBFS MIC input, 21dB gain Line-In, 0dB gain AASNA AASN Signal to noise ratio Max level at line-in input, 0dB gain, A-weighted Unweighted (20 Hz to 20 kHz) AATHD Total harmonic distortion Unit 1kHz @ 0dBFS MIC input, 21dB gain Line-in input, 0dB gain Note: When 2.4V<VCCA<2.7V, the values are reduced by 2dB. 64/85 Max. 0.003 0.004 0.01 0.02 % % STw5095 16 ADC (TX) and DAC (RX) specifications with voice filters selected ADC (TX) and DAC (RX) specifications with voice filters selected Typical measures - VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8V; Tamb=25C;13MHz AMCK Table 28. Symbol ADC and DCA specifications with voice filters selected Parameter Test Condition Min. Typ. Max. Unit 86 83 89 86 dB dB TXDR RXDR Dynamic range 300Hz to 3.4kHz; 1kHz @ -60dBFS TX Path, MIC input, 21dB gain RX Path, LS Output, 0dB gain TXSN RXSN Signal to noise ratio 300Hz to 3.4kHz; 1kHz @ 0dBFS TX Path, MIC input, 21dB gain RX Path, LS Output, 0dB gain 88 86 dB dB THD THD 1kHz @ 0dBFS TX Path, MIC input, 21dB gain RX Path, LS Output, 0dB gain <0.001 0.005 % % TXG RXG TX gain mask f=60Hz f=100Hz f=200Hz f=300Hz f=400Hz-3000Hz f=3400Hz f=4000H f=4600Hzz f=8000Hz RX gain mask f=60Hz f=100Hz f=200Hz f=300Hz f=400Hz-3000Hz f=3400Hz f=4000Hz f=5000Hz RX out of band noise Measurement bandwidth 4kHz to 100kHz. Zero input signal Group delay TX path RX path -1.5 -0.5 -1.5 -1.5 -0.5 -1.5 -30 -24 -6 0.5 0.5 0.0 -14 -35 -47 dB dB dB dB dB dB dB dB dB -20 -12 -2 0.5 0.5 0.0 -14 -50 dB dB dB dB dB dB dB dB -85 dBr 0.32 0.28 ms ms Note: When 2.4V<VCCA<2.7V, the values are reduced by 2dB 65/85 Typical performance plots 17 STw5095 Typical performance plots Figure 14. Bass treble control, de-emphasis filter Figure 15. Dynamic compressor transfer function 1 10 Output Amplitude [FS] Gain @ Fs=44.1 kHz [dB] 15 5 0 -5 -10 0.75 0.5 0.25 0 -0.25 -0.5 -0.75 -15 100 1k Frequency [Hz] -1 10k -1 -0.75-0.5-0.25 0 0.25 0.5 0.75 1 Input Amplitude [FS] Bass and treble gains are independently selectable in any combination. The de-emphasis filter (thick line, alternative to treble control) compensates for pre-emphasis used on some audio CDs. Gain error < 0.1dB. Filter characteristics at Fs=44.1kHz are plotted Figure 16. ADC audio path measured filter response Audio signal transfer function when the Dynamic Compressor is active. Figure 17. ADC in band audio path measured filter response 0 -10 Gain [dB] Gain [dB] -20 -30 -40 -50 -60 -70 -80 100 1k 10k Frequency [Hz] 100k 48 kHz sample rate. Full ADC path Frequency response up to 100 kHz. Gain [dB] Gain [dB] -20 -40 -60 -80 100k DA96K=0; 48 kHz Sample Rate Frequency response up to 166kHz (3.45 Fs @ 48kHz sampling rate) 66/85 5k 10k 15k Frequency [Hz] 20k Figure 19. DAC in band digital audio filter characteristics 0 1k 10k Frequency [Hz] 0 48 kHz Sample Rate. In band Frequency response Figure 18. DAC digital audio filter characteristics 100 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 5k 10k 15k Frequency [Hz] 48 kHz Sample Rate In band Frequency response 20k STw5095 Typical performance plots Figure 20. ADC 96 kHz audio path measured filter response Figure 21. ADC 96 kHz audio in-band measured filter response 1 0 0 -10 Gain [dB] Gain [dB] -20 -30 -40 -50 -60 -1 -2 -3 -4 -70 -5 -80 10 100 1k Frequency [Hz] 10k 0 100k 5k 10k 15k 20k 25k 30k 35k 40k 45k Frequency [Hz] The plot is extended down to 5 Hz to show the high pass filter implemented in the ADC 96 kHz sample rate, 96 kHz audio filter selected signal from Mic input 96 kHz sample rate, 96 kHz audio filter selected signal from Mic input. Figure 22. ADC voice TX path measured filter response Figure 23. ADC voice TX path measured inband filter response 0 -20 Gain [dB] Gain [dB] -10 -30 -40 -50 -60 -70 100 1k Frequency [Hz] 10k Figure 24. DAC voice (RX) digital filter characteristics -20 Gain [dB] Gain [dB] -10 -30 -40 -50 -60 8 kHz sample rate, rx voice filter 1k 1500 2k 2500 Frequency [Hz] 3k 3500 4k Figure 25. DAC voice (RX) in-band digital filter characteristics 0 1k Frequency [Hz] 500 8 kHz sample rate, tx voice filter selected signal from Mic input. 8 kHz Sample rate, tx voice filter selected. Signal from Mic input -70 100 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 10k 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 500 1k 1500 2k 2500 Frequency [Hz] 3k 3500 4k 8 kHz sample rate, rx voice filter 67/85 Typical performance plots Figure 26. ADC path FFT STw5095 Figure 27. ADC S/N versus input-level 100 90 -20 80 -40 70 S/N [dB] Amplitude [dBFS] 0 -60 -80 60 50 40 -100 -120 30 0 2k 4k 6k 20 8k 10k 12k 14k 16k 18k 20k Frequency [Hz] 12 MHz master clock. Differential input at Mic preamplifier, 21 dB gain. 48 kHz sampling rate. Both channels active Figure 28. DAC path FFT -10 0 100 90 -20 80 -40 S/N [dB] Amplitude [dBFS] -40 -30 -20 Input Level [dBFS] Figure 29. DAC S/N versus input-level -60 -80 -120 70 60 50 40 -100 30 0 2k 4k 6k 20 8k 10k 12k 14k 16k 18k 20k Frequency [Hz] 12 MHz master clock. 48 kHz sampling rate Differential output at line-out, 1k load. Both channels active Figure 30. Analog path FFT -60 -50 -40 -30 -20 Input Level [dBFS] -10 0 12 MHz master clock. 48 kHz Sampling Rate Differential output at Line-Out, 1k load. A-Weighted, Both channels active Figure 31. Analog path S/N versus input-level 100 0 90 -20 80 -40 S/N [dB] Amplitude [dBFS] -50 12 MHz master clock Differential input at Line-In Amplifier, 0 dB Gain. 48 kHz Sampling Rate A-Weighted, Both channels active 0 -60 -80 70 60 50 40 -100 -120 30 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k Frequency [Hz] Differential input at Mic Preamplifier, 21 dB Gain. Direct Mic to Line-Out connection (MICLO=1) Differential output at Line-Out, 20k load. Both channels active 68/85 -60 20 -60 -50 -40 -30 -20 Input Level [dBFS] -10 0 Differential input at Line-In Amplifier, 0 dB Gain. Line-In to DA-Mixer to Line-Out connection. Differential output at Line-Out, 20k load. A-weighted, both channels active STw5095 Application schematics 18 Application schematics Figure 32. STw5095 application schematics MBIAS 2.7k 750 100nF MIC1LP See application example in Section 4.16 on page 21 HDET Electret 10F 100nF MIC1LN 750 Needed if IRQ is not set to CMOS VCCIO 2.7k 2.7k 750 IRQ 100nF MIC1RP Electret 10F 100nF MIC1RN 750 2.7k Line IN CAPMIC 100nF L Melody IN LINEINR 0.47F AUX1L AUX1R 0.47F AUX2LP AUX2RP Voice IN 0.47F FM IN STw5095 AD_DATA Interface AD_Data Clock AD_CK To have a single bidirectional interface connect: AD_SYNC to DA_SYNC AD_CK to DA_CK AUX3L 0.47F R AD_Fs [8kHz-48kHz] A/D [88kHz-96kHz] Audio Data AD_Data AD_SYNC AUX2LN AUX2RN 0.47F L OCKDA LINEINL 100nF R MasterClocks for Other Digital Device or for Digital Audio Data Source OCKAD 200nF AUX3R 16/32 Typ Differential Connector 40mW Max. 10F CAPLINEIN DA_Fs DA_SYNC [8kHz-48kHz] [88kHz-96kHz] DA_DATA DA_Data DA_CK DA_Data HPR SENSE VCMHP VCMHPS Clock D/A Audio Data Interface HPL 10F Standard HP Connection As Close as possible to the pins 100pF CAPLS AMCK LSP 8 typ 500mW Max. As Close as possible to the pins SENSE SENSE System Clock [4MHz-32MHz] LSPS LSNS LSN SDA/SDIN OLP SCLK Data I2C compat. Bus L Clock AS/CSB OLN Line OUT CMOD ORP I2C compat. Bus selected R 100nF VCCA VCCP 100nF 100nF VCCIO VCC GND GNDCM GNDP VCCP VCCLS VCCA unconnected when used in Single-Ended Configuration GNDA ORN Leave the negative pins VCCD VCCIO 100nF 1F 10F 69/85 Package outline STw5095 19 Package outline Table 29. Package dimensions (mm) Ref. Min. A (1) 1.010 A1 0.150 Typ. Max. Outline and mechanical data 1.200 (2) A2 0.820 b 0.250 0.300 0.350 D 4.850 5.000 5.150 D1 3.500 E 4.850 5.000 E1 5.150 3.500 e 0.450 0.500 0.550 f 0.600 0.750 0.900 TFBGA 5x5x1.20 64 F8x8 0.50 0.080 Thin Profile Fine Pitch Ball Grid Array ddd 1. The total profile height is measured from the seating plane to the top of the component. 2. Max mounted height is 1.12mm.Based on a 0.28mm ball pad diameter. Solder paste is 0.15mm thickness and 0.28mm diameter. Figure 33. Package mechanical data SEATING PLANE C D D1 f A2 e E1 H G F E D C B A E f e 1 2 3 4 5 6 7 8 A1 A1 CORNER INDEX AREA See Note 1 Ob (64 BALLS) A ddd C BOTTOM VIEW Note: 70/85 1 The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional. STw5095 20 Ordering information Ordering information Table 30. Order codes Part Number 21 Package Packing STw5095 TFBGA 64 Tray STw5095T TFBGA 64 Tape and reel Revision history Table 31. Document revision history Date Revision 0.8-Nov-2005 1 Initial release. 2 Document status update to final datasheet. Section 4.3: Power up - Added details about general power up bit. Table 25: Stereo audio DAC specifications - Update of minimum value for dynamic range at differential line out. 23-Apr-2007 3 Updated PAD, PDA and PDAAD in Table 8: Power dissipation. Updated PSRpos, PSRpod and PSRal in Table 16: Power supply ratio. Updated IMBIAS value in Table 15: Microphone bias. Added Electrostatic discharge voltage and updated the minimum storage temperature value in Table 6: Absolute maximum ratings. 21-Aug-2009 4 Re-branding to ST-Ericsson 26-Aug-2009 5 Additional changes related to re-branding to ST-Ericsson 16-May-2006 Changes 71/85 STw5095 Please Read Carefully: The contents of this document are subject to change without prior notice. ST-Ericsson makes no representation or warranty of any nature whatsoever (neither expressed nor implied) with respect to the matters addressed in this document, including but not limited to warranties of merchantability or fitness for a particular purpose, interpretability or interoperability or, against infringement of third party intellectual property rights, and in no event shall ST-Ericsson be liable to any party for any direct, indirect, incidental and or consequential damages and or loss whatsoever (including but not limited to monetary losses or loss of data), that might arise from the use of this document or the information in it. ST-Ericsson and the ST-Ericsson logo are trademarks of the ST-Ericsson group of companies or used under a license from STMicroelectronics NV or Telefonaktiebolaget LM Ericsson. All other names are the property of their respective owners. (c) ST-Ericsson, 2009 - All rights reserved Contact information at www.stericsson.com under Contacts www.stericsson.com 72/72