PCF8564AU/5BB/1 - NXP - Datasheet.Live

1. General description

The PCF8564A is a CMOS1 real-time clock and calendar optimized for low power

consumption. A programmable clock output, interrupt output and voltage low detector are

also provided. All addresses and data are transferred serially via a two-line bidirectional

I2C-bus. Maximum bus speed is 400 kbit/s. The built-in word address register is

incremented automatically after each written or read data byte.

2. Features

nProvides year, month, day, weekday, hours, minutes, and seconds based on a

32.768 kHz quartz crystal

nCentury ﬂag

nWide clock operating voltage: 1.0 V to 5.5 V

nLow back-up current typical 250 nA at 3.0 V and 25 °C

n400 kHz two-wire I2C interface (1.8 V to 5.5 V)

nLow-voltage detector

nAlarm and timer functions

nTwo integrated oscillator capacitors

nProgrammable clock output for peripheral devices (32.768 kHz, 1.024 kHz, 32 Hz and

1 Hz)

nInternal Power-On Reset (POR)

nI2C slave address: read A3h, write A2h

3. Applications

nMobile telephones

nPortable instruments

nElectronic metering

nBattery powered products

PCF8564A

Real time clock and calendar

Rev. 1 — 8 October 2009 Product data sheet

1. The deﬁnition of the abbreviations and acronyms used in this data sheet can be found in Section 20.

Product data sheet Rev. 1 — 8 October 2009 2 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

4. Ordering information

[1] Not to be used for new designs.

5. Marking

Table 1. Ordering information

Type number Package

Name Description Delivery form Version

Die type 1[1]

PCF8564AU/5BD/1 PCF8564AU wire bond die; 9 bonding pads unsawn wafer;

thickness 280 µmPCF8564AU

PCF8564AU/5GE/1 PCF8564AU wire bond die; 9 bonding pads unsawn wafer;

thickness 687 µmPCF8564AU

PCF8564AU/10AA/1 PCF8564AU wire bond die; 9 bonding pads wafer sawn on FFC;

thickness 200 µmPCF8564AU

Die type 2

PCF8564AU/5BB/1 PCF8564AU wire bond die; 9 bonding pads unsawn wafer;

thickness 280 µmPCF8564AU

PCF8564AU/5GB/1 PCF8564AU wire bond die; 9 bonding pads unsawn wafer;

thickness 687 µmPCF8564AU

PCF8564AU/10AB/1 PCF8564AU wire bond die; 9 bonding pads wafer sawn on FFC;

thickness 200 µmPCF8564AU

Die type 3

PCF8564ACX9/1 PCF8564ACX9 wafer level chip-size package;

9 bumps; 1.27 ×1.9 ×0.29 mm wafer sawn on FFC;

thickness 200 µm;

die with solder bumps

PCF8564ACX9

PCF8564ACX9/B/1 PCF8564ACX9 wafer level chip-size package;

9 bumps; 1.27 ×1.9 ×0.29 mm tape and reel;

thickness 200 µm;

die with solder bumps

PCF8564ACX9

Table 2. Marking codes

Type number Marking code

Die type 1

PCF8564AU/5BD/1 PC8564A-1

PCF8564AU/5GE/1 PC8564A-1

PCF8564AU/10AA/1 PC8564A-1

Die type 2

PCF8564AU/5BB/1 PC8564A-1

PCF8564AU/5GB/1 PC8564A-1

PCF8564AU/10AB/1 PC8564A-1

Die type 3

PCF8564ACX9/1 PC8564A-1

PCF8564ACX9/B/1 PC8564A-1

Product data sheet Rev. 1 — 8 October 2009 3 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

6. Block diagram

Fig 1. Block diagram of PCF8564A

001aah660

PCF8564A

OSCILLATOR

32.768 kHz DIVIDER CLOCK OUT

INTERRUPT

CLKOUT

CLKOE

INT

MONITOR

POWER ON

RESET

WATCH

DOG

I2C

INTERFACE

OSCI

SCL

SDA

OSCO

VDD

VSS

TIMER FUNCTION

Timer_ctrl0Eh

Timer0Fh

CONTROL

Control_100h

Control_201h

CLKOUT_ctrl0Dh

TIME

Seconds02h

Minutes03h

Hours04h

Days05h

ALARM FUNCTION

Minute_alarm09h

Hour_alarm0Ah

Day_alarm0Bh

Weekday_alarm0Ch

Weekdays06h

Months07h

Years08h

Product data sheet Rev. 1 — 8 October 2009 4 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

7. Pinning information

7.1 Pinning

7.2 Pin description

[1] The substrate (rear side of the die) is wired to VSS but should not be electrically contacted.

Viewed from pad side. For mechanical details, see

Figure 27.Viewed from bump side. For mechanical details, see

Figure 28.

Fig 2. Pinning diagram of PCF8564AU Fig 3. Pinning diagram of PCF8564ACX9

PCF8564AU

013aaa032

OSCI

OSCO

INT SDA

CLKOUT

VDD

CLKOE

SCL

VSS

0,0

0,0 x

PCF8564ACX

013aaa033

OSCI

OSCO

INT

VSS

SCL

SDA

CLKOUT

VDD

CLKOE

Table 3. Pin description

Symbol Pin Description

OSCI 1 oscillator input

OSCO 2 oscillator output

INT 3 interrupt output, open-drain, active LOW

VSS 4 ground[1]

SDA 5 serial data input and output

SCL 6 serial clock input

CLKOUT 7 clock output, push-pull

VDD 8 supply voltage

CLKOE 9 CLKOUT output enable

Product data sheet Rev. 1 — 8 October 2009 5 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

8. Functional description

The PCF8564A contains sixteen 8-bit registers with an auto-incrementing address

which provides the source clock for the RTC, a programmable clock output, a timer, a

voltage low detector, and a 400 kHz I2C-bus interface.

All sixteen registers (see Table 4) are designed as addressable 8-bit parallel registers

although not all bits are implemented. The ﬁrst two registers (memory address 00h and

01h) are used as control and/or status registers. The addresses 02h through 08h are used

as counters for the clock function (seconds up to years counters). Address locations 09h

through 0Ch contain alarm registers which deﬁne the conditions for an alarm. Address

0Dh controls the CLKOUT output frequency. 0Eh and 0Fh are the timer control and timer

registers, respectively.

The seconds, minutes, hours, days, weekdays, months, years, as well as the minute

alarm, hour alarm, day alarm, and weekday alarm registers are all coded in BCD format.

8.1 CLKOUT output

A programmable square wave is available at the CLKOUT pin. Frequencies of 32.768 kHz,

1.024 kHz, 32 Hz and 1 Hz can be generated for use as a system clock, microcontroller

clock, input to a charge pump, or for calibration of the oscillator. CLKOUT is a CMOS

push-pull output, and if disabled it becomes logic 0.

Product data sheet Rev. 1 — 8 October 2009 6 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

8.2 Register organization

Table 4. Register overview

Bit positions labelled as - are not implemented. Bit positions labelled as N should always be written with logic 0. After reset, all

registers are set according to Table 27.

Address Register name Bit

76543210

Control registers

00h Control_1 TEST1 N STOP N TESTC N N N

01h Control_2 N N N TI_TP AF TF AIE TIE

Time and date registers

02h Seconds VL SECONDS (0 to 59)

03h Minutes - MINUTES (0 to 59)

04h Hours - - HOURS (0 to 23)

05h Days - - DAYS (1 to 31)

06h Weekdays - ----WEEKDAYS

07h Months C - - MONTH (1 to 12)

08h Years YEARS (0 to 99)

Alarm registers

09h Minute_alarm AE_M MINUTE_ALARM (0 to 59)

0Ah Hour_alarm AE_H - HOUR_ALARM (0 to 23)

0Bh Day_alarm AE_D - DAY_ALARM (1 to 31)

0Ch Weekday_alarm AE_W ----WEEKDAY_ALARM

CLKOUT control register

0Dh CLKOUT_ctrl FE -----FD

Timer registers

0Eh Timer_ctrl TE -----TD

0Fh Timer TIMER_VALUE

Product data sheet Rev. 1 — 8 October 2009 7 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

8.3 Control registers

8.3.1 Register Control_1

[1] Default value.

[2] Bits labeled as N should always be written with logic 0.

8.3.2 Register Control_2

[1] Bits labeled as N should always be written with logic 0.

[2] Default value.

Table 5. Control_1 - control and status register 1 (address 00h) bit description

Bit Symbol Value Description Reference

7 TEST1 0[1] normal mode;

•must be set to logic 0 during normal operations Section 8.9

1 EXT_CLK test mode (see Section 8.9)

6N 0

[2] default value

5STOP0

[1] RTC source clock runs Section 8.10

1•RTC divider chain ﬂip-ﬂops are asynchronously set to logic 0

•the RTC clock is stopped (CLKOUT at 32.768 kHz is still available)

4N 0

[2] default value

3 TESTC 0 Power-On Reset (POR) override facility is disabled;

•set to logic 0 for normal operation (see Section 8.11.1)Section 8.11.1

1[1] Power-On Reset (POR) override is enabled

2 to 0 N 000[2] default value

Table 6. Control_2 - control and status register 2 (address 01h) bit description

Bit Symbol Value Description Reference

7 to 5 N 000[1] default value

4 TI_TP 0[2] INT is active when TF is active (subject to the status of TIE)

1INT pulses active according to Table 7 (subject to the status of TIE);

•Remark: note that if AF and AIE are active then INT will be

permanently active

Section 8.3.2.1

and

Section 8.8

3AF 0

[2] alarm ﬂag inactive Section 8.3.2.1

1 alarm ﬂag active

2TF 0

[2] timer ﬂag inactive Section 8.3.2.1

1 timer ﬂag active

1 AIE 0[2] alarm interrupt disabled Section 8.3.2.1

1 alarm interrupt enabled

0 TIE 0[2] timer interrupt disabled Section 8.3.2.1

1 timer interrupt enabled

Product data sheet Rev. 1 — 8 October 2009 8 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

8.3.2.1 Interrupt output

Bits TF and AF: When an alarm occurs, AF is set to 1. Similarly, at the end of a timer

countdown, TF is set to 1. These bits maintain their value until overwritten using the

interface. If both timer and alarm interrupts are required in the application, the source of

the interrupt can be determined by reading these bits. To prevent one ﬂag being

overwritten while clearing another, a logic AND is performed during a write access.

Bits TIE and AIE: These bits activate or deactivate the generation of an interrupt when

TF or AF is asserted respectively. The interrupt is the logical OR of these two conditions

when both AIE and TIE are set.

Countdown timer interrupts: The pulse generator for the countdown timer interrupt

uses an internal clock and is dependent on the selected source clock for the countdown

timer and on the countdown value n. As a consequence, the width of the interrupt pulse

varies (see Table 7).

[1] TF and INT become active simultaneously.

[2] n = loaded countdown value. Timer is stopped when n = 0.

When bits TIE and AIE are disabled, pin INT will remain high-impedance.

Fig 4. Interrupt scheme

013aaa087

COUNTDOWN COUNTER

AF: ALARM

FLAG

CLEAR

SET

to interface:

read AF

TF: TIMER

CLEAR

SET

PULSE

GENERATOR 2

CLEAR

TRIGGER

TIE

INT

from interface:

clear TF

from interface:

clear AF

set alarm

flag, AF

to interface:

read TF

TI_TP

AIE

E.G.AIE

Table 7. INT operation (bit TI_TP = 1)[1]

Source clock (Hz) INT period (s)

n = 1[2] n > 1

4096 1⁄8192 1⁄4096

64 1⁄128 1⁄64

11⁄64 1⁄64

1⁄60 1⁄64 1⁄64

Product data sheet Rev. 1 — 8 October 2009 9 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

8.4 Time and date registers

The majority of the registers are coded in the BCD format to simplify application use.

8.4.1 Register Seconds

[1] Start-up value.

8.4.1.1 Voltage low detector and clock monitor

The PCF8564A has an on-chip voltage low detector. When VDD drops below Vlow the VL

(Voltage Low) ﬂag is set to indicate that the integrity of the clock information is no longer

guaranteed. The VL ﬂag can only be cleared by using the interface.

Table 8. Seconds - seconds and clock integrity status register (address 02h) bit

description

Bit Symbol Value Place value Description

7 VL 0 - clock integrity is guaranteed

1[1] - integrity of the clock information is not guaranteed

6 to 4 SECONDS 0 to 5 ten’s place actual seconds coded in BCD format, see Table 9

3 to 0 0 to 9 unit place

Table 9. Seconds coded in BCD format

Seconds value in

decimal Upper-digit (ten’s place) Digit (unit place)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00 0000000

01 0000001

02 0000010

09 0001001

10 0010000

58 1011000

59 1011001

Fig 5. Voltage low detection

VL set

normal power

operation

period of battery

operation

VDD

Vlow

mgr887

Product data sheet Rev. 1 — 8 October 2009 10 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

The VL ﬂag is intended to detect the situation when VDD is decreasing slowly, for example

under battery operation. Should the oscillator stop or VDD reach Vlow before power is

re-asserted, then the VL ﬂag will be set. This indicates that the time is possibly corrupted.

8.4.2 Register Minutes

8.4.3 Register Hours

8.4.4 Register Days

[1] The PCF8564A compensates for leap years by adding a 29th day to February if the year counter contains a

value which is exactly divisible by 4, including the year 00.

8.4.5 Register Weekdays

Table 10. Minutes - minutes register (address 03h) bit description

Bit Symbol Value Place value Description

7 - - - unused

6 to 4 MINUTES 0 to 5 ten’s place actual minutes coded in BCD format

3 to 0 0 to 9 unit place

Table 11. Hours - hours register (address 04h) bit description

Bit Symbol Value Place value Description

7 to 6 - - - unused

5 to 4 HOURS 0 to 2 ten’s place actual hours coded in BCD format

3 to 0 0 to 9 unit place

Table 12. Days - days register (address 05h) bit description

Bit Symbol Value Place value Description

7 to 6 - - - unused

5to4 DAYS

[1] 0 to 3 ten’s place actual day coded in BCD format

3 to 0 0 to 9 unit place

Table 13. Weekdays - weekdays register (address 06h) bit description

Bit Symbol Value Description

7 to 3 - - unused

2 to 0 WEEKDAYS 0 to 6 actual weekday values, see Table 14

Product data sheet Rev. 1 — 8 October 2009 11 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

[1] Deﬁnition may be re-assigned by the user.

8.4.6 Register Months

[1] This bit may be re-assigned by the user.

[2] This bit is toggled when the register Years overﬂows from 99 to 00.

Table 14. Weekday assignments

Day[1] Bit

210

Sunday 0 0 0

Monday 0 0 1

Tuesday 0 1 0

Wednesday 0 1 1

Thursday 1 0 0

Friday 1 0 1

Saturday 1 1 0

Table 15. Months - months and century ﬂag register (address 07h) bit description

Bit Symbol Value Place value Description

[1] 0[2] - indicates the century is x

1 - indicates the century isx+1

6 to 5 - - - unused

4 MONTHS 0 to 1 ten’s place actual month coded in BCD format, see Table 16

3 to 0 0 to 9 unit place

Table 16. Month assignments coded in BCD format

Month Upper-digit

(ten’s place) Digit (unit place)

Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

January 0 0 0 0 1

February 0 0 0 1 0

March 0 0 0 1 1

April 0 0 1 0 0

May00101

June00110

July00111

August 0 1 0 0 0

September 0 1 0 0 1

October 1 0 0 0 0

November 1 0 0 0 1

December 1 0 0 1 0

Product data sheet Rev. 1 — 8 October 2009 12 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

8.4.7 Register Years

[1] When the register Years overﬂows from 99 to 00, the century bit C in the register Months is toggled.

The PCF8564A compensates for leap years by adding a 29th day to February if the year

counter contains a value which is divisible by 4, including the year 00.

8.5 Setting and reading the time

Figure 6 shows the data ﬂow and data dependencies starting from the 1 Hz clock tick.

During read/write operations, the time counting circuits (memory locations 02h through

08h) are blocked.

This prevents

•Faulty reading of the clock and calendar during a carry condition

•Incrementing the time registers, during the read cycle

After this read/write access is completed, the time circuit is released again and any

pending request to increment the time counters, that occurred during the read access, is

serviced. A maximum of 1 request can be stored; therefore, all accesses must be

completed within 1 second (see Figure 7).

Table 17. Years - years register (08h) bit description

Bit Symbol Value Place value Description

7 to 4 YEARS 0 to 9 ten’s place actual year coded in BCD format[1]

3 to 0 0 to 9 unit place

Fig 6. Data ﬂow for the time function

013aaa092

1 Hz tick

WEEKDAY

SECONDS

MINUTES

HOURS

DAYS

LEAP YEAR

CALCULATION

MONTHS

YEARS

Product data sheet Rev. 1 — 8 October 2009 13 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

As a consequence of this method, it is very important to make a read or write access in

one go, that is, setting or reading seconds through to years should be made in one single

access. Failing to comply with this method could result in the time becoming corrupted.

As an example, if the time (seconds through to hours) is set in one access and then in a

second access the date is set, it is possible that the time may increment between the two

accesses. A similar problem exists when reading. A roll over may occur between reads

thus giving the minutes from one moment and the hours from the next.

Recommended method for reading the time:

1. Send a START condition and the slave address for write (A2h).

2. Set the address pointer to 2 (seconds) by sending 02h.

3. Send a RE-START condition or STOP followed by START.

4. Send the slave address for read (A3h).

5. Read the seconds.

6. Read the minutes.

7. Read the hours.

8. Read the days.

9. Read the weekdays.

10. Read the century and month.

11. Read the years.

12. Send a STOP condition.

8.6 Alarm registers

8.6.1 Register Minute_alarm

[1] Default value.

Fig 7. Access time for read/write operations

START slave address data data data STOP

t < 1 s

013aaa215

Table 18. Minute_alarm - minute alarm register (address 09h) bit description

Bit Symbol Value Place value Description

7 AE_M 0 - minute alarm is enabled

1[1] - minute alarm is disabled

6 to 4 MINUTE_ALARM 0 to 5 ten’s place minute alarm information coded in BCD

format

3 to 0 0 to 9 unit place

Product data sheet Rev. 1 — 8 October 2009 14 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

8.6.2 Register Hour_alarm

[1] Default value.

8.6.3 Register Day_alarm

[1] Default value.

8.6.4 Register Weekday_alarm

[1] Default value.

8.6.5 Alarm ﬂag

By clearing the MSB of one or more of the alarm registers AE_x (Alarm Enable), the

corresponding alarm condition(s) are active. When an alarm occurs, AF is set to logic 1.

The asserted AF can be used to generate an interrupt (INT). The AF is cleared using the

interface.

The registers at addresses 09h through 0Ch contain alarm information. When one or

more of these registers is loaded with a valid minute, hour, day or weekday and its

corresponding Alarm Enable bit (AE_x) is logic 0, then that information is compared with

the current minute, hour, day and weekday. When all enabled comparisons ﬁrst match, the

Alarm Flag (AF in register Control_2) is set to logic 1.

Table 19. Hour_alarm - hour alarm register (address 0Ah) bit description

Bit Symbol Value Place value Description

7 AE_H 0 - hour alarm is enabled

1[1] - hour alarm is disabled

6 - - - unused

5 to 4 HOUR_ALARM 0 to 2 ten’s place hour alarm information coded in BCD

format

3 to 0 0 to 9 unit place

Table 20. Day_alarm - day alarm register (address 0Bh) bit description

Bit Symbol Value Place value Description

7 AE_D 0 - day alarm is enabled

1[1] - day alarm is disabled

6 - - - unused

5 to 4 DAY_ALARM 0 to 3 ten’s place day alarm information coded in BCD

format

3 to 0 0 to 9 unit place

Table 21. Weekday_alarm - weekday alarm register (address 0Ch) bit description

Bit Symbol Value Description

7 AE_W 0 weekday alarm is enabled

1[1] weekday alarm is disabled

6 to 3 - - unused

2 to 0 WEEKDAY_ALARM 0 to 6 weekday alarm information coded in BCD format

Product data sheet Rev. 1 — 8 October 2009 15 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

The generation of interrupts from the alarm function is controlled via bit AIE. If bit AIE is

enabled, the INT pin follows the condition of bit AF. AF will remain set until cleared by the

interface. Once AF has been cleared it will only be set again when the time increments to

match the alarm condition once more. Alarm registers which have their AE_x bit at logic 1

are ignored.

8.7 Register CLKOUT_ctrl and clock output

A programmable square wave is available at pin CLKOUT. Operation is controlled by the

FE bit in register CLKOUT_ctrl at address 0Dh and the CLKOUT output enable pin

(CLKOE). To enable pin CLKOUT pin CLKOE must be set HIGH.

Frequencies of 32.768 kHz (default), 1.024 kHz, 32 Hz and 1 Hz can be generated for use

as a system clock, microcontroller clock, input to a charge pump, or for calibration of the

oscillator.

(1) Only when all enabled alarm settings are matching.

It’s only on increment to a matched case that the alarm ﬂag is set, see Section 8.6.5.

Fig 8. Alarm function block diagram

013aaa088

WEEKDAY ALARM

AE_W

WEEKD AY TIME

DAY ALARM

AE_D

D AY TIME

HOUR ALARM

AE_H

HOUR TIME

MINUTE ALARM

AE_M

MINUTE TIME

check now signal

set alarm flag, AF(1)

AE_M= 1

example

Product data sheet Rev. 1 — 8 October 2009 16 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

[1] Default value.

8.8 Timer function

The 8-bit countdown timer at address 0Fh is controlled by the timer control register at

address 0Eh. The timer control register determines one of 4 source clock frequencies for

the timer (4.096 kHz, 64 Hz, 1 Hz, or 1⁄60 Hz) and enables or disables the timer. The timer

counts down from a software-loaded 8-bit binary value. At the end of every countdown,

the timer sets the TF (Timer Flag) to logic 1. The TF may only be cleared using the

interface.

The generation of interrupts from the timer function is controlled via bit TIE. If bit TIE is

enabled the INT pin follows the condition of bit TF. The interrupt may be generated as a

pulsed signal every countdown period or as a permanently active signal which follows the

condition of the timer ﬂag TF. TI_TP is used for this mode control. When reading the timer,

the current countdown value is returned.

8.8.1 Register Timer_ctrl

[1] Default value.

[2] These bits determine the source clock for the countdown timer; when not in use, TD[1:0] should be set to

1⁄60 Hz for power saving.

Table 22. CLKOUT_ctrl - CLKOUT control register (address 0Dh) bit description

Bit Symbol Value Description

7 FE 0 the CLKOUT output is inhibited and CLKOUT output is

set to logic 0

1[1] the CLKOUT output is activated

6 to 2 - - unused

1 to 0 FD[1:0] frequency output at pin CLKOUT

00[1] 32.768 kHz

01 1.024 kHz

10 32 Hz

11 1 Hz

Table 23. Timer_ctrl - timer control register (address 0Eh) bit description

Bit Symbol Value Description

7TE 0

[1] timer is disabled

1 timer is enabled

6 to 2 - - unused

1 to 0 TD[1:0] timer source clock frequency select[2]

00 4.096 kHz

01 64 Hz

10 1 Hz

11[2] 1⁄60 Hz

Product data sheet Rev. 1 — 8 October 2009 17 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

8.8.2 Register Timer

The timer register is an 8-bit binary countdown timer. It is enabled or disabled via the timer

control register. The source clock for the timer is also selected by the timer control

controlled via the register Control_2 (address 01h).

For accurate read back of the count down value, the I2C-bus clock (SDA) must be

operating at a frequency of at least twice the selected timer clock. Since it is not possible

to freeze the countdown timer counter during read back, it is recommended to read the

8.9 EXT_CLK test mode

The test mode is entered by setting the TEST1 bit of register Control_1 to logic 1. The

CLKOUT pin then becomes an input. The test mode replaces the internal 64 Hz signal

with that applied to the CLKOUT pin. Every 64 positive edges applied to CLKOUT then

generates an increment of one second.

The signal applied to the CLKOUT pin should have a minimum pulse width of 300 ns and

a maximum period of 1000 ns. The 64 Hz clock, now sourced from CLKOUT, is divided

down to 1 Hz by a 26divide chain called a prescaler. The prescaler can be set to a known

state by using the STOP bit. When the STOP bit is set, the prescaler is reset to logic 0.

(STOP must be cleared before the prescaler can operate.)

From a STOP condition, the ﬁrst 1 second increment will take place after 32 positive

edges on CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment.

Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock.

When entering the test mode, no assumption as to the state of the prescaler can be

made.

8.9.1 Operation example

1. Set EXT_CLK test mode (Bit 7 Control_1 = 1).

2. Set STOP (Bit 5 Control_1 = 1).

3. Clear STOP (Bit 5 Control_1 = 0).

4. Set time registers to desired value.

5. Apply 32 clock pulses to CLKOUT.

6. Read time registers to see the ﬁrst change.

Table 24. Timer - timer register (address 0Fh) bit description

Bit Symbol Value Description

7 to 0 TIMER_VALUE[7:0] 00h to FFh countdown value = n;

Table 25. Timer register bits value range

Bit

7 6 5 4 3 2 1 0

128 64 32 16 8 4 2 1

CountdownPeriod n

SourceClockFrequency

---------------------------------------------------------------

Product data sheet Rev. 1 — 8 October 2009 18 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

7. Apply 64 clock pulses to CLKOUT.

8. Read time registers to see the second change.

Repeat 7 and 8 for additional increments.

8.10 STOP bit function

The function of the STOP bit is to allow for accurate starting of the time circuits. The STOP

bit function will cause the upper part of the prescaler (F2 to F14) to be held in reset and

thus no 1 Hz ticks will be generated (see Figure 9). The time circuits can then be set and

will not increment until the STOP bit is released (see Figure 10 and Table 26).

The STOP bit function will not affect the output of 32.768 kHz on CLKOUT, but will stop

the generation of 1.024 kHz, 32 Hz and 1 Hz.

The lower two stages of the prescaler (F0 and F1) are not reset and because the I2C-bus

is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be

between zero and one 8.192 kHz cycle (see Figure 10).

Fig 9. STOP bit functional diagram

Fig 10. STOP bit release timing

013aaa089

OSC

32768 Hz

16384 Hz

OSC STOP

DETECTOR

F0F1F13

RES

F14

RES

2 Hz

1024 Hz

32 Hz

1 Hz tick

stop

CLKOUT source

reset

8192 Hz

4096 Hz

32768 Hz

1 Hz

001aaf912

8192 Hz

stop released

0 µs to 122 µs

Product data sheet Rev. 1 — 8 October 2009 19 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

[1] F0 is clocked at 32.768 kHz.

The ﬁrst increment of the time circuits is between 0.507813 s and 0.507935 s after STOP

bit is released. The uncertainty is caused by the prescaler bits F0 and F1 not being reset

(see Table 26) and the unknown state of the 32 kHz clock.

8.11 Reset

The PCF8564A includes an internal reset circuit which is active whenever the oscillator is

stopped. In the reset state the I2C-bus logic is initialized including the address pointer and

all registers are set according to Table 27. I2C-bus communication is not possible during

reset.

Table 26. First increment of time circuits after STOP bit release

Bit Prescaler bits [1] 1 Hz tick Time Comment

STOP F0F1-F2 to F14 hh:mm:ss

Clock is running normally

01-0 0001 1101 0100

12:45:12 prescaler counting normally

STOP bit is activated by user. F0F1 are not reset and values cannot be predicted externally

XX-0 0000 0000 0000

12:45:12 prescaler is reset; time circuits are frozen

New time is set by user

XX-0 0000 0000 0000

08:00:00 prescaler is reset; time circuits are frozen

STOP bit is released by user

XX-0 0000 0000 0000

08:00:00 prescaler is now running

XX-1 0000 0000 0000

08:00:00 -

XX-0 1000 0000 0000

08:00:00 -

XX-1 1000 0000 0000

08:00:00 -

11-1 1111 1111 1110

08:00:00 -

00-0 0000 0000 0001

08:00:01 0 to 1 transition of F14 increments the time circuits

10-0 0000 0000 0001

08:00:01 -

11-1 1111 1111 1111

08:00:01 -

00-0 0000 0000 0000

08:00:01 -

10-0 0000 0000 0000

08:00:01 -

11-1 1111 1111 1110

08:00:01 -

00-0 0000 0000 0001

08:00:02 0 to 1 transition of F14 increments the time circuits

013aaa076

0.507813- 0.507935 s

1.000000 s

Product data sheet Rev. 1 — 8 October 2009 20 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

[1] Registers marked ‘x’ are undeﬁned at power-on and unchanged by subsequent resets.

8.11.1 Power-On Reset (POR) override

The POR duration is directly related to the crystal oscillator start-up time. Due to the long

start-up times experienced by these types of circuits, a circuit has been implemented to

disable the POR and speed up functional test of the module. The setting of this mode

requires that the I2C signals on the pins SDA and SCL are toggled as illustrated in

Figure 11. All timings shown are required minimums.

Once the override mode has been entered, the chip immediately stops, being reset, and

normal operation may begin, i.e., entry into the EXT_CLK test mode via I2C access. The

override mode may be cleared by writing logic 0 to TESTC. TESTC must be set to logic 1

before re-entry into the override mode is possible. Setting TESTC to logic 0 during normal

operation has no effect, except to prevent entry into the POR override mode.

Table 27. Register reset values[1]

Address Register name Bit

7 6 5 4 3 2 1 0

00h Control_1 0 0 0 0 1 0 0 0

01h Control_2 0 0 0 0 0 0 0 0

02h Seconds 1 x x x x x x x

03h Minutes x x x x x x x x

04h Hours x x x x x x x x

05hDays xxxxxxxx

06h Weekdays x x x x x x x x

07h Months x x x x x x x x

08h Years x x x x x x x x

09h Minute_alarm 1 x x x x x x x

0Ah Hour_alarm 1 x x x x x x x

0Bh Day_alarm 1 x x x x x x x

0Ch Weekday_alarm 1 x x x x x x x

0Dh CLKOUT_ctrl 1 x x x x x 0 0

0Eh Timer_ctrl 0 x x x x x 1 1

0Fh Timer x x x x x x x x

Allow 500 ns between the edges of either signal.

Fig 11. POR override sequence

mgm664

SCL

500 ns 2000 ns

SDA

8 ms

override active

power up

Product data sheet Rev. 1 — 8 October 2009 21 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

9. Characteristics of the I2C-bus

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial Data Line (SDA) and a Serial Clock Line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only

when the bus is not busy.

9.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal (see Figure 12).

9.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH, is deﬁned as the START condition (S).

A LOW-to-HIGH transition of the data line, while the clock is HIGH, is deﬁned as the STOP

condition (P), see Figure 13.

9.3 System conﬁguration

A device generating a message is a transmitter, a device receiving a message is the

receiver. The device that controls the message is the master; and the devices which are

controlled by the master are the slaves (see Figure 14).

Fig 12. Bit transfer

mbc621

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 13. Deﬁnition of START and STOP conditions

mbc622

SDA

SCL P

STOP condition

SDA

SCL

START condition

Product data sheet Rev. 1 — 8 October 2009 22 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

9.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

cycle.

•A slave receiver, which is addressed, must generate an acknowledge after the

reception of each byte.

•Also a master receiver must generate an acknowledge after the reception of each

byte that has been clocked out of the slave transmitter.

•The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be taken into

consideration).

•A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I2C-bus is shown in Figure 15.

Fig 14. System conﬁguration

mba605

MASTER

TRANSMITTER /

RECEIVER

SLAVE

RECEIVER SLAVE

TRANSMITTER /

RECEIVER

MASTER

TRANSMITTER MASTER

TRANSMITTER /

RECEIVER

SDA

SCL

Fig 15. Acknowledgment on the I2C-bus

mbc602

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from

master

Product data sheet Rev. 1 — 8 October 2009 23 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

10. I2C-bus protocol

10.1 Addressing

Before any data is transmitted on the I2C-bus, the device which should respond is

addressed ﬁrst. The addressing is always carried out with the ﬁrst byte transmitted after

the start procedure.

The PCF8564A acts as a slave receiver or slave transmitter. Therefore, the clock signal

SCL is only an input signal, but the data signal SDA is a bidirectional line.

Two slave addresses are reserved for the PCF8564A:

Read: A3h (10100011)

Write: A2h (10100010)

The PCF8564A slave address is shown in Figure 15.

10.2 Clock and calendar READ or WRITE cycles

Figure 17,Figure 18, and Figure 19 show the I2C-bus conﬁguration for the different

PCF8564A READ and WRITE cycles. The word address is a 4-bit value that deﬁnes

which register is to be accessed next. The upper four bits of the word address are not

used.

Fig 16. Slave address

mce189

1 0 1 0 0 0 1 R/W

group 1 group 2

Fig 17. Master transmits to slave receiver (WRITE mode)

S0ASLAVE ADDRESS WORD ADDRESS A ADATA P

acknowledgement

from slave acknowledgement

from slave

R/W

auto increment

memory word address

mbd822

n bytes

Product data sheet Rev. 1 — 8 October 2009 24 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

Fig 18. Master reads word after setting word address (write word address; READ data)

S0ASLAVE ADDRESS WORD ADDRESS A ASLAVE ADDRESS

acknowledgement

from slave

R/W

013aaa034

R/W

acknowledgement

from slave acknowledgement

from master

no acknowledgement

from master

auto increment

memory word address

auto increment

memory word address

at this moment master transmitter

becomes master receiver and

PCF8564A slave receiver

becomes slave transmitter

last byte

DATA

n bytes

Fig 19. Master reads slave immediately after ﬁrst byte (READ mode)

S1A

SLAVE ADDRESS DATA A1DATA

acknowledgement

from slave acknowledgement

from master no acknowledgement

from master

R/W

auto increment

word address

mgl665

auto increment

word address

n bytes last byte

Product data sheet Rev. 1 — 8 October 2009 25 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

11. Internal circuitry

12. Limiting values

[1] Pass level; Human Body Model (HBM) according to Ref. 6 “JESD22-A114”.

[2] Pass level; Machine Model (MM), according to Ref. 7 “JESD22-A115”.

[3] Pass level; latch-up testing, according to Ref. 8 “JESD78” at maximum ambient temperature

(Tamb(max) = +85 °C).

[4] According to the NXP store and transport conditions (see Ref. 10 “SNW-SQ-623”) the devices have to be

stored at a temperature of +5 °C to +45 °C and a humidity of 25 % to 75 %.

Fig 20. Device diode protection diagram

013aaa035

SDA

SCL

VDD

CLKOE

OSCI

OSCO

VSS PCF8564A

INT

CLKOUT

Table 28. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.5 +6.5 V

VIinput voltage −0.5 +6.5 V

VOoutput voltage −0.5 +6.5 V

IDD supply current −50.0 +50.0 mA

IIinput current −10.0 +10.0 mA

IOoutput current −10.0 +10.0 mA

ISS ground supply current −50.0 +50.0 mA

Ptot total power dissipation - 300 mW

Tamb ambient temperature −40.0 +85 °C

VESD electrostatic discharge voltage HBM [1]

die type 1 and 3 - ±2500 V

die type 2 - ±3500 V

MM [2]

die type 1 and 3 - ±200 V

die type 2 - ±250 V

Ilu latch-up current all pins but OSCI [3] - 100 mA

Tstg storage temperature [4] −65.0 +150 °C

Product data sheet Rev. 1 — 8 October 2009 26 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

13. Static characteristics

Table 29. Static characteristics

= 1.8 V to 5.5 V; V

=0V; T

amb

−

C to +85

C; f

osc

= 32.768 kHz; quartz R

=40k

Ω

; C

= 8 pF; unless otherwise

speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VDD supply voltage interface inactive;

Tamb =25°C[1] 1.0 - 5.5 V

interface active;

fSCL = 400 kHz [1] 1.8 - 5.5 V

for clock data integrity;

Tamb =25°CVlow - 5.5 V

IDD supply current interface active

fSCL = 400 kHz - - 800 µA

fSCL = 100 kHz - - 200 µA

interfaceinactive(fSCL = 0 Hz);

CLKOUT disabled;

Tamb =25°C

[2] [3]

[4]

VDD = 5.0 V - 275 550 nA

VDD = 3.0 V - 250 500 nA

VDD = 2.0 V - 225 450 nA

interfaceinactive(fSCL = 0 Hz);

CLKOUT disabled;

Tamb =−40 °C to +85 °C

[2] [3]

[4]

VDD = 5.0 V - 500 750 nA

VDD = 3.0 V - 400 650 nA

VDD = 2.0 V - 400 600 nA

interfaceinactive(fSCL = 0 Hz);

CLKOUT enabled at 32 kHz;

Tamb =25°C

[4] [5]

[6]

VDD = 5.0 V - 1500 3000 nA

VDD = 3.0 V - 1000 2000 nA

VDD = 2.0 V - 700 1400 nA

interfaceinactive(fSCL = 0 Hz);

CLKOUT enabled at 32 kHz;

Tamb =−40 °C to +85 °C

[4] [5]

[6]

VDD = 5.0 V - 1700 3400 nA

VDD = 3.0 V - 1100 2200 nA

VDD = 2.0 V - 800 1600 nA

Inputs

VIinput voltage on pins SDA and SCL −0.5 - +5.5 V

on pins CLKOE and CLKOUT

(test mode) −0.5 - VDD + 0.5 V

VIL LOW-level input voltage - - 0.3VDD V

Product data sheet Rev. 1 — 8 October 2009 27 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

[1] For reliable oscillator start-up at power-on: VDD(po)min =V

DD(min) + 0.3 V.

[2] Timer source clock = 1⁄60 Hz.

[3] CLKOUT disabled (FE = 0 or CLKOE = 0).

[4] VIL and VIH with an input voltage swing of VSS to VDD.

[5] CLKOUT is open circuit.

[6] Current consumption when the CLKOUT pin is enabled is a function of the load on the pin, the output frequency, and the supply voltage.

The additional current consumption for a given load is calculated from: .

[7] Tested on sample basis.

VIH HIGH-level input voltage 0.7VDD --V

ILI input leakage current VI=V

DD or VSS −10 +1µA

Ciinput capacitance [7] --7pF

Outputs

VOoutput voltage on pin CLKOUT −0.5 - VDD + 0.5 V

on pin INT −0.5 - +5.5 V

IOL LOW-level output current on pin SDA;

VOL = 0.4 V; VDD =5V 3- - mA

on pin INT;

VOL = 0.4 V; VDD =5V −1- - mA

on pin CLKOUT:

VOL = 0.4 V; VDD =5V −1- - mA

IOH HIGH-level output current on pin CLKOUT;

VOH = 4.6 V; VDD =5V 1- - mA

ILO output leakage current VO=V

DD or VSS −10 +1µA

Voltage detector

Vlow low voltage Tamb =25°C - 0.9 1.0 V

Table 29. Static characteristics

…continued

= 1.8 V to 5.5 V; V

=0V; T

amb

−

C to +85

C; f

osc

= 32.768 kHz; quartz R

=40k

Ω

; C

= 8 pF; unless otherwise

speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

CLKOUT

××=

Product data sheet Rev. 1 — 8 October 2009 28 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

Tamb =25°C; timer = 1 minute; CLKOUT disabled. Tamb =25°C; timer = 1 minute; CLKOUT = 32 kHz.

Fig 21. IDD as a function of VDD Fig 22. IDD as a function of VDD

VDD = 3 V; timer = 1 minute; CLKOUT = 32 kHz. Tamb =25°C; normalized to VDD =3V.

Fig 23. IDD as a function of T Fig 24. Frequency deviation as a function of VDD

02 6

mgr888

4VDD (V)

0.4

0.2

0.8

0.6

IDD

(µA)

02 6

mgr889

4VDD (V)

0.4

0.2

0.8

0.6

IDD

(µA)

−40 0 40 120

mgr890

80 T (°C)

0.4

0.2

0.8

0.6

IDD

(µA)

02 6

−4

−2

mgr891

4VDD (V)

frequency

deviation

(ppm)

Product data sheet Rev. 1 — 8 October 2009 29 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

14. Dynamic characteristics

[1] Integrated load capacitance, CL(itg), is a calculation of COSCI and COSCO in series: .

[2] Unspeciﬁed for fCLKOUT = 32.768 kHz.

[3] All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage

swing of VSS to VDD.

[4] A detailed description of the I2C-bus speciﬁcation is given in Ref. 11 “UM10204”.

Table 30. Dynamic characteristics

= 1.8 V to 5.5 V; V

=0V; T

amb

−

C to +85

C; f

osc

= 32.768 kHz; quartz R

=40k

Ω

; C

= 8 pF; unless otherwise

speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Oscillator

CL(itg) integrated load capacitance [1] 6 8 10 pF

∆fosc/fosc relative oscillator frequency variation ∆VDD = 200 mV;

Tamb =25°C- 0.2 - ppm

Quartz crystal parameters

Rsseries resistance - - 100 kΩ

CLload capacitance - 8 - pF

CLKOUT output

δCLKOUT duty cycle on pin CLKOUT [2] -50-%

I2C-bus timing characteristics (see Figure 25)[3][4]

fSCL SCL clock frequency - - 400 kHz

tHD;STA hold time (repeated) START condition 0.6 - - µs

tSU;STA set-up time for a repeated START

condition 0.6 - - µs

tLOW LOW period of the SCL clock 1.3 - - µs

tHIGH HIGH period of the SCL clock 0.6 - - µs

trrise time of both SDA and SCL signals - - 0.3 µs

tffall time of both SDA and SCL signals - - 0.3 µs

Cbcapacitive load for each bus line - - 400 pF

tSU;DAT data set-up time 100 - - ns

tHD;DAT data hold time 0 - - ns

tSU;STO set-up time for STOP condition 0.6 - - µs

tw(spike) spike pulse width - - 50 ns

CLitg() COSCI COSCO

⋅()

COSCI COSCO

+()

--------------------------------------------

Product data sheet Rev. 1 — 8 October 2009 30 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

15. Application information

Fig 25. I2C-bus timing waveforms

SDA

mga728

SDA

SCL

tSU;STA tSU;STO

tHD;STA

tBUF tLOW

tHD;DAT tHIGH

tSU;DAT

Fig 26. Application diagram

013aaa193

SCL

SDA

VSS

OSCI

OSCO

CLOCK/CALENDAR

PCF8564A

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

VDD

SDA SCL

VDD

(I2C-bus)

1 F

Product data sheet Rev. 1 — 8 October 2009 31 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

16. Bare die outline

Fig 27. Bare die outline of PCF8564AU

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

PCF8564AU

pcf8564au_do

09-08-25

09-09-10

Unit

mm max

nom

min 0.2 1.26 1.05 0.22 0.9 0.1 0.1 0.09

A(3)

Dimensions Die type 2

Note

1. Chip dimensions including sawline.

2. Marking code: PC8564A-1

3. Dimension depending on delivery form

Wire bond die; 9 bonding pads PCF8564AU

D(1) E(1)

1.89

1e2P1P2

0.09

P3P4

Unit

mm max

nom

min 0.2 1.27 1.05 0.22 0.9 0.1 0.1 0.09

A(3)

Dimensions Die type 1

D(1) E(1)

1.9

1e2P1P2

0.09

P3P4

0 0.5 1 mm

scale

detail X

P4P3

(2)

0,0 x

Product data sheet Rev. 1 — 8 October 2009 32 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

Table 31. Bonding pad description for all PCF8564AU types

All x/y coordinates represent the position of the center of each pad with respect to the center

(x/y = 0) of the chip; see Figure 27.

Symbol Pad X (µm) Y (µm) Description

OSCI 1 −523.0 689.4 oscillator input

OSCO 2 −523.0 469.4 oscillator output

INT 3 −523.0 −429.8 open-drain interrupt output (active LOW)

VSS 4−523.0 −684.4 ground (substrate)

SDA 5 524.9 −523.8 serial data I/O

SCL 6 524.9 −138.6 serial clock input

CLKOUT 7 524.9 162.5 CMOS push-pull clock output

VDD 8 524.9 443.3 supply

CLKOE 9 524.9 716.3 CLKOUT output enable

Product data sheet Rev. 1 — 8 October 2009 33 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

Fig 28. Bare die outline of PCF8564ACX9

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

PCF8564ACX9

pcf8564acx9_po

09-08-25

09-09-09

Unit

mm max

nom

min 0.29 0.09 0.2 1.27 1.9 0.73 0.27

Dimensions

Note

1. Chip dimensions including sawline.

2. Marking code: PC8564A-1

WLCSP9: wafer level chip-size package; 9 bumps; 1.27 x 1.9 x 0.29 mm PCF8564ACX9

A1A2

0.2

(1) E(1) ee

0.45

0 0.5 1 mm

scale

(2) detail X

A2A

0,0 x

Table 32. Solder bump description for all PCF8564ACX types

All x/y coordinates represent the position of the center of each bump with respect to the center

(x/y = 0) of the chip; see Figure 28.

Symbol Bump X (µm) Y (µm) Description

OSCI 1 −368 738 oscillator input

OSCO 2 −368 188 oscillator output

INT 3 −368 −262 open-drain interrupt output (active LOW)

VSS 4−368 −712 ground (substrate)

SDA 5 362 −712 serial data I/O

SCL 6 362 −262 serial clock input

CLKOUT 7 362 188 CMOS push-pull clock output

VDD 8 0 456 supply

CLKOE 9 362 738 CLKOUT output enable

Product data sheet Rev. 1 — 8 October 2009 34 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

17. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in

JESD625-A

IEC61340-5

or equivalent

standards.

Fig 29. Alignment marks of all PCF8564A types

Table 33. Alignment marks of all PCF8564A types

All x/y coordinates represent the position of the REF point (see Figure 29) with respect to the center

(x/y = 0) of the chip; see Figure 27 and Figure 28.

Alignment markers Size (µm) X (µm) Y (µm)

C1 100 × 100 465.2 −826.3

C2 100 × 100 −523.0 890.0

F90× 117 −569.9 −885.5

REF

013aaa036

REF

Product data sheet Rev. 1 — 8 October 2009 35 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

18. Packing information

18.1 Wafer and FFC information

Wafer thickness, see Table 1.

Fig 30. Wafer layout of PCF8564AU

Saw lane

detail X

Marking code

Straight edge

of the wafer

013aaa037

Pin 1

18 µm

die type 1 = 84 µm

die type 2 = 74 µm

die type 1 = 84 µm

die type 2 = 74 µm

Seal ring plus gap to

active circuit ~18 µm

18 µm

Product data sheet Rev. 1 — 8 October 2009 36 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

Wafer thickness, see Table 1.

Fig 31. Wafer layout of PCF8564ACX9

Saw lane

detail X

Straight edge

of the wafer

013aaa192

18 µm

84 µm

Seal ring plus gap to

active circuit ~18 µm

18 µm

Marking code Pin 1

84 µm

Product data sheet Rev. 1 — 8 October 2009 37 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

18.2 Tape and reel information

[1] Die is placed in pocket bump side down.

19. Soldering of WLCSP packages

19.1 Introduction to soldering WLCSP packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note

AN10439 “Wafer Level Chip Scale Package”

and in application note

AN10365 “Surface

mount reﬂow soldering description”

Wave soldering is not suitable for this package.

Fig 32. Tape and reel details for PCF8564ACX9/B/1

Table 34. Tape and reel dimensions [1]

Dimension Description Value

W tape width 8 mm

A0 pocket length 1.5 mm

B0 pocket width 2.2 mm

K0 pocket depth 0.25 mm

P1 pocket pitch 4 mm

Transparent top view. The orientation of the IC in a pocket is indicated by the position of pin 1, with

respect to the sprocket holes.

Fig 33. Pin 1 indication for PCF8564ACX9/B/1

4 mm K0

direction of feed

013aaa202

013aaa191

pin 1

Product data sheet Rev. 1 — 8 October 2009 38 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

All NXP WLCSP packages are lead-free.

19.2 Board mounting

Board mounting of a WLCSP requires several steps:

1. Solder paste printing on the PCB

2. Component placement with a pick and place machine

3. The reﬂow soldering itself

19.3 Reﬂow soldering

Key characteristics in reﬂow soldering are:

•Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 34) than a PbSn process, thus

reducing the process window

•Solder paste printing issues, such as smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature), and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic) while being low enough that the packages and/or boards are not

damaged. The peak temperature of the package depends on package thickness and

volume and is classiﬁed in accordance with Table 35.

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 34.

Table 35. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 1 — 8 October 2009 39 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

For further information on temperature proﬁles, refer to application note

AN10365

“Surface mount reﬂow soldering description”

19.3.1 Stand off

The stand off between the substrate and the chip is determined by:

•The amount of printed solder on the substrate

•The size of the solder land on the substrate

•The bump height on the chip

The higher the stand off, the better the stresses are released due to TEC (Thermal

Expansion Coefﬁcient) differences between substrate and chip.

19.3.2 Quality of solder joint

A ﬂip-chip joint is considered to be a good joint when the entire solder land has been

wetted by the solder from the bump. The surface of the joint should be smooth and the

shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps

after reﬂow can occur during the reﬂow process in bumps with high ratio of bump diameter

to bump height, i.e. low bumps with large diameter. No failures have been found to be

related to these voids. Solder joint inspection after reﬂow can be done with X-ray to

monitor defects such as bridging, open circuits and voids.

19.3.3 Rework

In general, rework is not recommended. By rework we mean the process of removing the

chip from the substrate and replacing it with a new chip. If a chip is removed from the

substrate, most solder balls of the chip will be damaged. In that case it is recommended

not to re-use the chip again.

MSL: Moisture Sensitivity Level

Fig 34. Temperature proﬁles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Product data sheet Rev. 1 — 8 October 2009 40 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

Device removal can be done when the substrate is heated until it is certain that all solder

joints are molten. The chip can then be carefully removed from the substrate without

damaging the tracks and solder lands on the substrate. Removing the device must be

done using plastic tweezers, because metal tweezers can damage the silicon. The

surface of the substrate should be carefully cleaned and all solder and ﬂux residues

and/or underﬁll removed. When a new chip is placed on the substrate, use the ﬂux

process instead of solder on the solder lands. Apply ﬂux on the bumps at the chip side as

well as on the solder pads on the substrate. Place and align the new chip while viewing

with a microscope. To reﬂow the solder, use the solder proﬁle shown in application note

AN10365 “Surface mount reﬂow soldering description”

19.3.4 Cleaning

Cleaning can be done after reﬂow soldering.

Product data sheet Rev. 1 — 8 October 2009 41 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

20. Abbreviations

21. References

[1] AN10365 — Surface mount reﬂow soldering description

[2] AN10706 — Handling bare die

[3] IEC 60134 — Rating systems for electronic tubes and valves and analogous

semiconductor devices

[4] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[5] IPC/JEDEC J-STD-020 — Moisture/Reﬂow Sensitivity Classiﬁcation for

Nonhermetic Solid State Surface Mount Devices

[6] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[7] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model

(MM)

[8] JESD78 — IC Latch-Up Test

[9] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[10] SNW-SQ-623 — NXP store and transport conditions

[11] UM10204 — I2C-bus speciﬁcation and user manual

Table 36. Abbreviations

Acronym Description

BCD Binary Coded Decimal

CMOS Complementary Metal Oxide Semiconductor

FFC Film Frame Carrier

HBM Human Body Model

I2C Inter-Integrated Circuit

IC Integrated Circuit

LSB Least Signiﬁcant Bit

MM Machine Model

MOS Metal Oxide Semiconductor

MSB Most Signiﬁcant Bit

MSL Moisture Sensitivity Level

PCB Printed-Circuit Board

POR Power-On Reset

ROM Read Only Memory

RTC Real Time Clock

SCL Serial Clock Line

SDA Serial Data Line

SRAM Static Random Access Memory

WLCSP Wafer Level Chip-Size Package

Product data sheet Rev. 1 — 8 October 2009 42 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

22. Revision history

Table 37. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCF8564A_1 20091008 Product data sheet - -

Product data sheet Rev. 1 — 8 October 2009 43 of 44

NXP Semiconductors PCF8564A

Real time clock and calendar

23. Legal information

23.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

23.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

23.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Bare die — All die are tested on compliance with their related technical

speciﬁcations as stated in this data sheet up to the point of wafer sawing and

are handled in accordance with the NXP Semiconductors storage and

transportation conditions. If there are data sheet limits not guaranteed, these

will be separately indicated in the data sheet. There are no post-packing tests

performed on individual die or wafers.

NXP Semiconductors has no control of third party procedures in the sawing,

handling, packing or assembly of the die. Accordingly, NXP Semiconductors

assumes no liability for device functionality or performance of the die or

systems after third party sawing, handling, packing or assembly of the die. It

is the responsibility of the customer to test and qualify their application in

which the die is used.

All die sales are conditioned upon and subject to the customer entering into a

written die sale agreement with NXP Semiconductors through its legal

department.

23.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

24. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors PCF8564A

Real time clock and calendar

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 8 October 2009

Document identifier: PCF8564A_1

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

25. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

8 Functional description . . . . . . . . . . . . . . . . . . . 5

8.1 CLKOUT output . . . . . . . . . . . . . . . . . . . . . . . . 5

8.2 Register organization . . . . . . . . . . . . . . . . . . . . 6

8.3 Control registers . . . . . . . . . . . . . . . . . . . . . . . . 7

8.3.1 Register Control_1 . . . . . . . . . . . . . . . . . . . . . . 7

8.3.2 Register Control_2 . . . . . . . . . . . . . . . . . . . . . . 7

8.3.2.1 Interrupt output. . . . . . . . . . . . . . . . . . . . . . . . . 8

8.4 Time and date registers . . . . . . . . . . . . . . . . . . 9

8.4.1 Register Seconds . . . . . . . . . . . . . . . . . . . . . . . 9

8.4.1.1 Voltage low detector and clock monitor . . . . . . 9

8.4.2 Register Minutes. . . . . . . . . . . . . . . . . . . . . . . 10

8.4.3 Register Hours . . . . . . . . . . . . . . . . . . . . . . . . 10

8.4.4 Register Days. . . . . . . . . . . . . . . . . . . . . . . . . 10

8.4.5 Register Weekdays. . . . . . . . . . . . . . . . . . . . . 10

8.4.6 Register Months . . . . . . . . . . . . . . . . . . . . . . . 11

8.4.7 Register Years . . . . . . . . . . . . . . . . . . . . . . . . 12

8.5 Setting and reading the time. . . . . . . . . . . . . . 12

8.6 Alarm registers . . . . . . . . . . . . . . . . . . . . . . . . 13

8.6.1 Register Minute_alarm . . . . . . . . . . . . . . . . . . 13

8.6.2 Register Hour_alarm . . . . . . . . . . . . . . . . . . . 14

8.6.3 Register Day_alarm . . . . . . . . . . . . . . . . . . . . 14

8.6.4 Register Weekday_alarm . . . . . . . . . . . . . . . . 14

8.6.5 Alarm ﬂag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

8.7 Register CLKOUT_ctrl and clock output. . . . . 15

8.8 Timer function. . . . . . . . . . . . . . . . . . . . . . . . . 16

8.8.1 Register Timer_ctrl . . . . . . . . . . . . . . . . . . . . . 16

8.8.2 Register Timer . . . . . . . . . . . . . . . . . . . . . . . . 17

8.9 EXT_CLK test mode. . . . . . . . . . . . . . . . . . . . 17

8.9.1 Operation example . . . . . . . . . . . . . . . . . . . . . 17

8.10 STOP bit function . . . . . . . . . . . . . . . . . . . . . . 18

8.11 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8.11.1 Power-On Reset (POR) override . . . . . . . . . . 20

9 Characteristics of the I2C-bus. . . . . . . . . . . . . 21

9.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

9.2 START and STOP conditions . . . . . . . . . . . . . 21

9.3 System conﬁguration . . . . . . . . . . . . . . . . . . . 21

9.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 22

10 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 23

10.1 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

10.2 Clock and calendar READ or WRITE cycles . 23

11 Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 25

12 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 25

13 Static characteristics . . . . . . . . . . . . . . . . . . . 26

14 Dynamic characteristics. . . . . . . . . . . . . . . . . 29

15 Application information . . . . . . . . . . . . . . . . . 30

16 Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 31

17 Handling information . . . . . . . . . . . . . . . . . . . 34

18 Packing information . . . . . . . . . . . . . . . . . . . . 35

18.1 Wafer and FFC information . . . . . . . . . . . . . . 35

18.2 Tape and reel information. . . . . . . . . . . . . . . . 37

19 Soldering of WLCSP packages . . . . . . . . . . . 37

19.1 Introduction to soldering WLCSP packages. . 37

19.2 Board mounting . . . . . . . . . . . . . . . . . . . . . . . 38

19.3 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 38

19.3.1 Stand off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

19.3.2 Quality of solder joint . . . . . . . . . . . . . . . . . . . 39

19.3.3 Rework. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

19.3.4 Cleaning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

20 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 41

21 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

22 Revision history . . . . . . . . . . . . . . . . . . . . . . . 42

23 Legal information . . . . . . . . . . . . . . . . . . . . . . 43

23.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 43

23.2 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

23.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 43

23.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 43

24 Contact information . . . . . . . . . . . . . . . . . . . . 43

25 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44