HIGH-SPEED 4K x 8 DUAL-PORT STATIC SRAM IDT7134SA/LA Features * High-speed access ~ Military: 25/35/45/55/70ns (max.) - Industrial: 55ns (max.) ~ Commercial: 20/25/35/45/55/70ns (max.) * Low-power operation - IDT7134SA Active: 700mW (typ.) Standby: 5mW (typ) - IDT7I134LA Active: 700mW (typ.) Standby: ImW (typ. Fully asynchronous operation from either port Battery backup operation2V data retention TTL-compatible; single 5V (10%) power supply Available in 48-pin DIP, LCC, Flatpack and 52-pin PLCC Military product compliant to MIL-PRF-38535 QML Industrial temperature range (-40 C to +85 C) is available for selected speeds o & + Description The 'DT7134 is a high-speed 4K x 8 Dual-Port Static RAM designed to be used in systems where on-chip hardware port arbitration is not needed. This part lends itself to those systems which cannot tolerate wail states or are designed to be able to externally arbitrate or withstand contention when both sides simultaneously access the same Dual-Port RAM location. The (DT? 134 provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. Itis the user's responsibility to ensure data integrity when simultaneously accessing the same memory location from both ports. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDTs CMOS high-performance technology, these Dual-Port typically operate on only 700mW of power. Low-power (LA) versions offer battery backup data retention capability, with each port typically consuming 200yW from a 2V battery. The 1DT7134 is packaged on either a sidebraze or plastic 48-pin DIP, 48-pin LCC, 52-pin PLCC and 48-pin Flatpack. Military grade product is manufactured in compliance with the latest revision of MIL- PRF-38535 QML, making it ideaily suited to military temperature applications demanding the highestlevel of performance and reliability. Functional Block Diagram RW - R/WR CEL t CER OE. d_/ \__P_ OEr y q y 7 COLUMN COLUMN VOot- /O7L <_______ VO VO V/Oor- YO7R } 7 mae BE ae ADDRE: . MEMORY lo AoL- Att DECODE "| "ARRAY DECODE Aor- A11R LOGIC LOGIC 2720 drw 01 MARCH 1999 OSC-2728IDT7134SA/LA High-Speed 4K * 8 Dual-Port Stave SRAM Pin Configurations" 2:) Bac MELLO ES Cate MciR SMe Orel tel inic goats TM Rel T ster TESTE) Ranges _ XA aa #220 [= 408 = oct a Ww f&rs nn) awe 48} veo NOX ga 2e3ee 88'S 22 Aiwll3 46, R/WrR UEUURUTUUUOOUN Ato.O] 4 45] A1iR 765 43 2 5251 5049 4847 Oct 5 44] Aior Auf] 8 1 46 (J OER Ao. 6 431] OER Aa fd 9 45 pon Aill7 42[] Aor Aa] 10 Aas int7isaporc 41L Air t 44(4 ain Aa Et past 40-1 Aan Aap 11 43] Aer AI coe SA he L SBF AAR As. [2] 13 IDT7134J ai AeLLJ1i2 48-Pin 37LJA5R J52-1(4) AaR An Hig ton, 36LJAcr An.E] 14 40} Asp AaLll14 Yew get] Arr Aa. fo] 15 52-Pin PLCC 39] a Ast (15 34|_] Asr E Top View(s) 6A voo.l] 16 33[] Aor Aat fF 16 38 CY are vO 1.017 32 VO7R vOo. 1 17 37 CY asr VO 218 31 /Oser 18 VO 3 19 301] YOsA vou r 19 86 Asn V0 aL] 20 291] /OaR VOat 35 C4 wc vos] 24 281] /O3R Ost fF] 20 34} yor VO 6d 22 271 /OeR 21 22 23 24 25 26 27 28 29 30 31 32 33 vo nl}23 20 /0rr \ ooo on ooannnY 24 25} /OoR za# 27080 6886228588 G8 8 2720 drw 93 2720 drw 02 _~ = Se Sta SS FS ga 22g gGS So INDEX 262226 $16 =z Zzlo 65 4 3 TyUToTOT \ Ait 7 1 42] Aor Axl] 8 419 air As. 9 404] Aor Aa. F110 IDT7134L48 or F sol 438 Asi i] 11 L48-1(4) or 38L] Aar Ae. Ll 12 rae) 37] Asr Ant 13 367] Asr Ast] 14 4e-Pin LOC/Flatpack 35] avr op View(s) At 15 347] Asa Oot FJ 16 33] Aor VOit FJ 17 32] vo7r NorEs: VOat [J 18 31] /Osr a 19 20 21 22 23 24 25 26 27 28 29 30 1. All Vcc pins must be connected to the power supply. \ 2. AI GND pins must be connected to the ground supply. DODO OoOODoHoOoOoO OG / 3. P48-1 package body is approximately 55 in x61 in x 19 in. azgzgdde Q coe oe x or 2720 drw 04 C48-2 package body is approximately .62 in x 2.43 in x .15 in. Oo Oo Q OQ Oo 5 6 Oo Q Q J2-1 package body is approximately .75 in x .75 in x .17 in. = L48-1 package body is approximately .57 in x .57 in x .68 in. F48-1 package body is approxiamtely .75 in x .75 in x .11 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of actual part-marking.OR PAR Sor time) High-Speed 4K x u Gual-Pori Stuue SRAW faustial anc Commercia: feinperature Ranges Absolute Maximum Ratings") Recommended Operating Symbol Rating Commercial | Military | unit| Temperature and Supply Voltage) & Industrial Grade Ambient GND Vee Vierm@ | Terminal Voltage 0.5 0 +7.0 0.5 fo +7.0 V Temperature with Respect _ to GND Military ~55C to +125C ov 5.0V + 10% Tals Temperature -55 to +125 5 to +135 C Commercial 0C to +70C ov 5.0V + 10% Under Bias industiai 40C to +85C OV 5.0V + 10% TstG Storage -55 to +125 -5 to +150 C mew 2720 b Temperature NOTES: pre Power 15 45 w 1. This is the parameter Ta. Dissipation 2. Industrial temperature: for specific speeds, packages and powers contact your sales office. lout DC Output 50 50 mA Current NOTES: 2720 tbl 01 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may . cause permanent damage to the device. This is a stress rating only andfunctiond Recommended DC Operating operation of the device at these or any other conditions above those indicated in the ati operational sections of this specification is not implied. Exposure to absolute Conditions maximum rating conditions for extended periods may affect reliability. Symbol Parameter Min. | Typ. | Max | Unit 2. VTERM must not exceed Vcc + 10% for more than 25%of the cycle time or 10 ns maximum, and is limited to < 20mA for the period of Vrerm> Vcc +10%. Vec | Supply Voltage 45 50] 55 |] V 3 VTERM = 5.5V. GND | Ground 0} of ov Vik | Input High Voltage 22 | 607] Vv Vi | Input Low Voltage 0.5 | | 08] Vv Capacitance") (Ta = +25C, f = 1.0MHz) NOTES: wo Symbol Parameter Conditions? | Max | Unit} 1. Vu (min) 2 -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vec + 109%. ON Input Capacitance Vin = 3dV "1 pF Cout | Output Capacitance Vout = 3dV "1 pF 2720 thi 02 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and output signals switch from OV to 3V and from 3V to OV. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (Vcc = 5v + 10%) T1345A TI34LA Symbol Parameter Test Conditions Min. Max. Min. Max. Unit flu Input Leakage Current Voc = 5.5V, Vin = OV to Voc 10 ~ 5 uA [iLo| Output Leakage Curent CE-Vu,Vour=0VtoVeo i assisdL 10 oa 5 yA Vo. Output Low Voltage fo. = 6mMA ~ 0.4 ~ 0.4 Vv fo. = 8mA _ 0.5 ~ 0.5 Vv Vou Output High Voltage Jou = -4mA 24 ~ 24 _ V NOTES: 2720 thi 05 1. At Vcc < 2.0V input leakages are undefined.RP ARE Sr as High-Speed & SURES S Lonel CPL ecam cts (a0e [2-9 DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range?*) (vcc = 5.0v + 10%) 7434X20 7434X25 7134X35 Com't Only Com'l & Com'l & Military Military Symbol Parameter Test Condition Version Typ. Max. | Typ. Max | Typ. Max | Unit icc | Dynamic Operating GE = vu COM'L SA} 170 | 280 160 | 280 150 | 260 | mA Current Outputs Open tA | 170 | 240 160 | 220 150 | 210 (Both Ports Active) f= fax?) MIL & SA 160 | 310 150 | 300 IND LA 160 | 260 150 | 250 isb1 | Standby Current CEL and CEr = Vn COM'L SA| 2 100 25 80 25 75 | mA (Both Ports - TTL f= fuax) lA] & 80 25 50 25 45 Level Inputs) MIL & SA 25 400 25 75 IND LA 25 80 25 55 isa2__| Standby Current CEs" = Vi and CEs = Vin COM'L SA] 105 | 180 95 180 85 170 | ma (One Port - TTL Active Port Outputs Open, LA] 105 150 95 140 85 130 Level Inputs) fefuax) MIL & SA 95 210 85 200 IND LA 95 170 85 160 iss3| Full Standby Current Both Ports CEL and CoML SA] 1.0 15 10 15 1.0 145 | mA (Both Ports - CEr 2 Vec - 0.2V tA] 02 45 0.2 4.0 0.2 40 CMOS Level Inputs} Vin 2 Vec - 0.2V or Vin < 0.2V, f= 0 MIL & SA 1.0 30 1.0 30 IND LA 0.2 10 0.2 10 isa4 | Full Standby Current One Port CE-a" or COM'L SA| 105 | 170 95 170 85 160 | mA (One Port - CEs" > Vec - 0.2V LA | 105 130 95 120 85 10 CMOS Level Inputs) Vin 2 Vee - 0.2V or VN < 0.2V Active Port Outputs Open, MIL & SA 95 210 85 190 f= Mae IND LA 95 150 85 130 2720 fbi 06a 713445 7134X55 7134X70 Com'l & Com't, Ind Com & Military & Military Military Symbol Parameter Test Condition Version Typ. | Max | Typ. | Max | Typ. | Max | Unit icc | Dynamic Operating CE = Vi COM'L SA} 140 | 240 140 | 240 440 | 240 | mA Current Outputs Open \A | 140 | 200 140 | 200 140 200 (Both Ports Active) f= faa? MIL & SA} 140 | 280 140 | 270 140 | 270 IND iA | 140 | 240 140 | 220 140 | 220 lss1 | Standby Current CE and CEr = Vin COM'L SA| 25 70 25 70 25 70 | mA (Both Ports - TTL f = fax) LA} 25 40 25 40 25 40 Level Inputs) MIL & SA] 25 70 25 70 25 70 IND tA] 25 50 25 50 25 50 Isa2__| Standby Current CE-: = Vi and CEB = Vin COM'L SA] 75 160 75 160 75 160 | mA (One Port - TL Active Port Outputs Open. iA] 75 130 i) 430 % 130 Level inputs) fax? MIL & SA| 75 190 5 180 75 180 IND tA] 75 150 75 150 75 150 Isa3| Full Standby Curent Both Ports CEL and COM'L SA | 1.0 15 1.0 15 1.0 15 | mA (Both Ports - CER 2 Voc - 0.2V tA] 02 4.0 0.2 4.0 0.2 40 CMOS Level inputs} Vin 2 Vec - 0.2V or VIN < 0.2V, f= 0? MIL & SAl 1.0 30 1.0 30 1.0 30 IND iA | 02 10 0.2 10 0.2 10 Ise | Full Standby Current One Port CE*a* or COML SA] 75 150 75 150 75 150 | mA (One Port - CEs 2 Vcc - 0.2V tA} 75 100 15 4 75 400 CMOS Level Inputs) Vin 2 Vec - 0.2V or VN < 0.2V Active Port Outputs Open, MIL & SA | 75 180 75 470 75 470 f= fot? IND iA | 75 120 75 420 75 120 2720 thi 0b NOTES: 'X in part number indicates power rating (SA or LA}. 1, 2. 3. 4 Vcc = 5V, Ta = +25 T for typical, and parameters are not production tested. fMax = 1hRc = All inputs cycling at f = T/trc (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby Ise. industrial temperature: for other speeds, packages and powers contact your sales office.IDT7134SA/LA High-Speed 44 8 Bual Prat Staue SHAM MHiitary. industial and Commercial Temperature Ranges Data Retention Characteristics Over All Temperature Ranges (LA Version Only) Vic = 0.2V, Vic = Vcc - 0.2V Symbol Parameter Test Condition Min, Typ." Max | Unit VbR Vcc for Data Retention Vec = 2V 20 a V Iccor Data Retention Current CE 2 Vic MIL. & IND. ~ 100 4000 | HA Vin > Vuc or < Vic COM'L. 100 1500 tcor) Chip Deselect to Data Retention Time 1) os ~ ns Ro Operation Recovery Time tac?) _ ns 2720 tol 07 NOTES: 1. Vec = 2V, Ta = +25 C, and are not production tested. 2. Inc = Read Cycle Time. 3. This parameter is guaranteed by device characterization, but not production tested. Data Retention Waveform Vec 4.5V VpR> 2V 4.5V tcDR iR >| CE vi N VaR av RX) vi 2720 drw 05 AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fatl Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Figures 1 and 2 2720 tb! 08 +5V +5V 12500 1250Q DATAouT DATAouT 7762 SOpF 775Q 5pF * 2720 drw 06 2720 dew O7 Figure 1. AC Output Test Load Figure 2. Output Test Load (for tLz, tuz, twz, tow) Including scope and jigIDT7134SA/L A High-Speed 4K x Oual-Port Static SRARI Sitiary. industial and Contnercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage**) 7134X20 7134X25 7134X35 Com'l Only Com & Com'l & Military Military Symbol Parameter Min. Max. Min. Max. Min. Max. Unit READ CYCLE tre Read Cycle Time 20 25 _ 35 ns tA Address Access Time _ 2 _ 2 35 ns {ACE Chip Enable Access Time _ 20 2 35 ns taoe Output Enable Access Time 15 _ 15 20 ns tow Output Hold from Address Change 0 _ 0 _ 0 vee ns uz Output Low-Z Time 0 ~ 0 _ 0 ns Hz Output High-Z Time"? _ 45 - 15 _ 20 ns Pu Chip Enable to Power Up Time 0 _ 0 _ 0 ns Pb Chip Disable to Power Down Time 20 _ 5) _ 35 ns 2720 tbl 08a 7134X45 7134X55 7134X70 Com'l & Com't, Ind Com'l & Military & Military Military Symbol Parameter Min. | Max. Min. | Max. Min. Max Unit READ CYCLE ARC Read Cycle Time 4 J oe 55 70 ns tea Address Access Time 45 _ 55 70 ns tace Chip Enabie Access Time 45 _ 55 70 ns tao Output Enable Access Time 25 _ Ke) 40 ns tou Output Hold from Address Change 0 0 ~~ 0 - ns Zz Output Low-Z Time! #) 5 _ 5 ~ 5 ~ ns HZ Output High-Z Time! oo 2 oo 25 =~ 30 ns tu Chip Enable to Power Up Time 0 - 0 _ 0 ~ ns PD Chip Disable to Power Down Time 45 _ 50 50 ns 2720 tbl 09b NOTES: 1. Transition is measured +500mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is quaranteed by device characterization, but is not production tested. 3. 'X' in part number indicates power rating (SA ar LA). 4. Industrial temperature: for other speeds, packages and powers contact your sales office.IDT7134SA/LA High-Speed 4 x 8 Oual-Port State SRAM RUAUULCALE SUR CELOL OE DURTeimecEhs me Oa* Ir ties (ct Seti t ME abtTe ec E etiam TC Ine =1-) Timing Waveform of Read Cycle No. 1, Either Sidd'?:*) tt tRc > ADDRESS *K *K + taa(s) | < tOH > p+ ton DATAout PREVIOUS DATA VALID DATA VALID 2720 drw 08 Timing Waveform of Read Cycle No. 2, Either Sidd'*) ~t tACE > cE K A + taoe > + tz > OE iN 2 >| tz) e} aK / wg 4 DATAout eeeg VALID DATA p + tuz) > icc * teu >| p+*__ tPp CURRENT | a 50% 50% SB 2720 drw 09 NOTES: Timing depends on which signal is asserted last, OE or CE. Timing depends on which signal is de-asserted first, OE or CE. RAW = Vin. Start of valid data depends on which timing becomes effective, tack, LACE or IAA taa for RAM Address Access and tsaa for Semaphore Address Access. nPWwhDIDT7134SA/LA High-Speed 4h x 5 Uual-Pott Stauc SRA Rss ec te en tkeLe A and Gomimercia: benipeiature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage*) 7134X20 7134X25 7134X35 Com'l Only Com't & Com'l & Military Military Symbol Parameter Min. | Max. Min. Max. Min. Max. Unit WRITE CYCLE twe Write Cycle Time 20 _ 25 _ 35 - ns tew Chip Enable to End-of White 15 20 ~ 30 ns taw Address Valid to End-of-Write 15 20 30 ns tas Address Set-up Time 0 0 - 0 ns twp Write Pulse Width 45 20 - 25 _ ns iwR Write Recovery Time 0 - 0 - 0 ns tow Data Valid to End-of-Write 15 15 _ 20 - ns tz Output High-Z Time!) 15 15 -- 20 ns DH Data Hold Time 0 0 - 30 | -- ns twz Write Enable to Output in High-Z'? 15 15 20 ns tow Output Active from End-of- Write?) 3 - 3 ~ 3 - ns twoo Write Pulse to Data Delay" 40 == 50 a 60 ns top Write Data Valid to Read Data Delay ~~ 30 ~ 30 ~ 35 ns 2720 thi 19a 7134X45 7134X55 7134X70 Com'l & Com't, Ind Com'! & Military & Military Military Symbol Parameter Min. | Max. Min. Max. Min. Max. Unit WRITE CYCLE two Write Cycle Time 45 55 - 70 ~ ns tew Chip Enable to End-of Write 40 50 ~ 60 - ns tAw Address Valid to End-of-Write 40 50 60 - ns TAS Address Setup Time 0 0 0 _ ns twe Write Pulse Width 40 50 _ 60 ns twR Write Recovery Time 0 _ 0 ~ 0 ns tow Data Valid to End-of Write 20 25 ~ 30 ns Hz Output High-2 Time ~ 20 25 30 ns {DH Data Hold Time) 3 3 - 3 - ns {WZ Write Enable to Outputin High? 2 _ 25 = 30 ns tow Output Active from End-of Write? ne 3 - 3 ~ ns twoD Write Pulse to Data Delay 70 80 90 ns tooo Write Data Valid to Read Data Delay 45 ~ 55 ~~ 70 ns NOTES: 2720 tb! 10b 1. Transition is measured +500mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. The specification for toH must be met by the device supplying write data to the RAM under all operating conditions. Although tox and tow values will vary over voltage and temperature, the actual to will always be smaller than the actual tow. Port-to-port delay through RAM ceils from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read. X in part number indicates power rating (SA or LA). top = 35ns for military temperature range. Industrial temperature: for other speeds, packages and powers contact your sales office. NOsIDT7134SA/LA High-Speed 4K x & Gual-Part Siaue SRA Mitary. adusuial ang Commerc: fomperature Ranges Timing Waveform of Write with Port-to-Port Read) mm + twc > ADDR a i MATCH OK RAW a) ~* tow DATAIN "a" xK VALID x ADDR *s" x MATCH rt twoD > DATAouT 8" XK vat NOTES: top > 2720 drw 10 1. Write cycle parameters should be adhered to, in order to ensure proper writing. 2. CEL-CEr- Vi. OE = Vi. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". Timing Waveform of Write Cycle No. 1, RWW Controlled Timing >) + twc > ADDRESS xX XK + taste) > a OE / < taw me twrR?) > CE a HK < twe > * tHz -| RAW Ke He tH2'? # tow DATAouT (4) b tDH + tow DATAIN 2720 drw tt NOTES: RIW or CE must be HIGH during all address transitions. A write occurs during the overlap (tew or twe) of a CE =Vu and RAW = Vi. twe is measured from the earlier of CE or R/W going to Vin to the end-of-write cycle. During this period, the V/O pins are in the output state, and input signals must not be applied. if the CE = Vic transition occurs simultaneously with or after the R/W = Vit transition, the outputs remain in the High-impedance state. Timing depends on which enable signal (CE or R/W) is asserted last. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured +500mV from steady state with the Output Test Load (Figure 2). 8. If OE = Vit during a R/W controlled write cycle, the write pulse width must be the larger of twe or (twz + tow) to allow the I/O drivers to turn off data to be placed on the bus for the required tow. if OE = Vin during an RW controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twr. MOO PwNnn>IDT7134SA/. A High-Speed 4K x 8 Dua-Port State SRAL LGC MeRICiOE SIRT TREC] LEME OTSELAILE! ECoaeh ys 1c] get ge CoM E TER Lt) Timing Waveform of Write Cycle No. 2, CE Controlled Timing 4) y< Y twe ADDRESS y taw Q m 4 ol 4 \ \ tas) w tew twR?? Pt tow es DH DATAIN y 2720 dew 12 NOTES: 1. RAW or CE must be HIGH during all address transitions. 2. Awrite occurs during the overlap (tew or twe) of a CE =Vitand RW = Vit. 3. twe is measured from the earlier of CE or RW going HIGH to the end-of-write cycle. 4. ifthe CE LOW tansition occurs simultaneously with or after the RW LOW tansition, the outputs remain in the High-impedance state. 5. Timing depends on which enable signal (CE or RAW) is asserted last. Functional Description Truth Table I Read/Write Control The 1DT7134 provides two ports with separate control, address, Left or Right Port"! and I/O pins that permit independent access for reads or writes to any = - location in memory. These devices have an automatic power down RW | CE | OF Do? Function feature controlled by CE. The CE controls on-chip power down circuitry x | HI x Zz Port Deselected and in Power-Down that permits the respective port to go into standby mode when not Mode, isB2 or Isp selected (CE HIGH). When a port is enabled, access to the entire x lull x z CE = CE. = H, Power Down memory array is permitted. Each port has its own Output Enable Mode Ise: or Is83 control (OE). inthe read mode, the port's OE turns on the output drivers ae L L x DATA: Data rt written into when setLOW. Non-contention READWRITE conditions are illustrated ~ onpe umnemey in the table below. H L L DATAocuT | Data in memory output on port X x H 2 High impedance outputs 2720 toi 11 NOTE: 1. Aot - Atit # Aor - A1iR "H" = Vin, "L" = Vi, "X" = Don't Care, and "Z = High ImpedanceIDT7134SA/LA High-Speec 4K 8 Dudl-Pert Stauc SBA Industral and Commercial leinperature Ranges Ordering Information IDT _HXXXM LA 99 A A Device Type Power Speed Package Process/ Temperature Range Commercial (0C to +70C) Industrial (-40C to +85C) Military (-55C to +4125C) Compliant to MIL-PRF-38535 QML 48-pin Plastic DIP (P48-1)} 48-pin Ceramic DIP (C48-2) 52-pin PLCC (J52-1) 48-pin LCC (L48-1) 48-pin Ceramic Flatpack (F48-1} 20 Commercial Ont 25 Commercial & Muitary 35 Commercial & Military . 45 Commercial & Military Speed in nanoseconds 55 Commercial, Industrial & Military 70 Commercial & Military }LA Low Power 1 SA Standard Power 17134 32K (4K x 8-Bit) Dual-Port RAM 2720 drw 13 NOTE: 1. Industrial temperature is available for PLCC packages in standard power. For other speeds, packages and powers contact your sales office. Datasheet Document History 3/25/99 Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Pages 2 Added additional notes to pin configurations CORPORATE HEADQUARTERS for SALES: for Tech Support: a> IDT 2975 Stender Way 800-345-7015 or 408-727-5166 | 831-754-4613 Santa Clara, CA 95054 fax: 408-492-8674 DualPortHelp @idt.com www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc.