SEROCCO-D
2 Channel Serial Optimized
Communication Controller with
DMA
PEB 20542 Version 1.2
PEF 20542 Version 1.2
Never stop thinking.
Datacom
Data Sheet, DS 1, Sep. 2000
Edition 2000-09-14
Published by Infineon Technol ogi es AG ,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 9/14/00.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Ter m s of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manuf acturer.
Information
F or further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our I nfineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements com ponent s may cont ain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components ma y only be used in lif e-support devices or systems with the e xpress written
approv al of Infineon Technologies, if a f ailure of such components can reasonab ly be e xpected to cause the f ailure
of that life-support device or s ystem, or to affect the safety or effectiveness of t hat device or system. Life support
de vices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
SEROCCO-D
2 Channel Serial Optimized
Communication Controller with
DMA
PEB 20542 Version 1.2
PEF 20542 Version 1.2
Never stop thinking.
Datacom
Data Sheet, DS 1, Sep. 2000
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Repres entatives worldwide: s ee our webpage at http://www.infineon.com
PEB 20542
Revi si on History: 2000 -09-14 DS 1
Previous Versio n: MISTR AL V1.1 Prelimi nary Data Sheet, 08.99, DS1
Page
(previous
Version)
Page
(current
Version)
Subj ec ts (major chan ges since las t rev is i on)
34-36 36-38 Correction: signal ’OSR’ is multiplexed with signal ’CD’, signal
’OST’ is multiplexed with ’CTS’ (was vice versa)
85 87 correc t ed H D LC receive address recog nit ion table
218, 226 222, 230 Corrected location of TCD interrupt (async/bisync modes only)
in registers ISR0 and IMR0 from bit 7 to bit 2 .
- - removed referneces to Intel Multiplexed Mode
268 272 Chapter "Electrical Characteristics" updated with final
cha r acteri zation results.
PEB 20542
PEF 20542
Table of Contents Page
Data Sheet 5 2000-09- 14
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.2 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.3 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.3.1 System Integration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.3.2 Serial Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.4 Differences between SEROCCO-D and the ESCC Family . . . . . . . . . . . . 27
1.4.1 E nhancements to the ESCC Se rial Core . . . . . . . . . . . . . . . . . . . . . . . . 27
1.4.2 Simplifications to the ESCC Serial Core . . . . . . . . . . . . . . . . . . . . . . . . 27
2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.1 Pin Diagram P-TQFP-144-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2 Pin Definitions an d Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2 Serial Communication Controller (SCC) . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.2.1 Protocol Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.2.2 SCC FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.2.2.1 SCC Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2.2.2 SCC Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2.2.3 SCC FIFO Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.2.3 Clocking System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.2.3.1 Clock Mode 0 (0a/0b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.2.3.2 Clock Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.2.3.3 Clock Mode 2 (2a/2b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.2.3.4 Clock Mode 3 (3a/3b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.2.3.5 Clock Mode 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.2.3.6 Clock Mode 5a (Time Slot Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.2.3.7 Clock Mode 5b (Octet Sync Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.2.3.8 Clock Mode 6 (6a/6b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.2.3.9 Clock Mode 7 (7a/7b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.2.4 Baud Rate Generator (BRG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.2.5 Clock Recove ry (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.2.6 SCC Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.2.7 S CC Serial Bus Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.2.8 Serial Bus Access Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.2.9 Serial Bus Collisi ons and Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.2.10 Serial Bus Access Priority Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.2.11 Serial Bus Configuration Timing Modes . . . . . . . . . . . . . . . . . . . . . . . . 75
3.2.12 Functions Of Signal RTS in HDLC Mode . . . . . . . . . . . . . . . . . . . . . . . . 75
3.2.13 Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.2.13.1 NRZ and NRZI Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
PEB 20542
PEF 20542
Table of Contents Page
Data Sheet 6 2000-09- 14
3.2.13.2 FM0 and FM1 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.2.13.3 Manchester Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.2.14 Modem Control Signals (RTS, CTS, CD) . . . . . . . . . . . . . . . . . . . . . . . 78
3.2.14.1 RTS/CTS Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.2.14.2 Carrier Detect (CD) Receiver Control . . . . . . . . . . . . . . . . . . . . . . . . 79
3.2.15 Local Loop Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.3 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.4 Internal DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.4.1 Arbitration for Bu s Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.4.2 Performing DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.4.3 Bus Preemption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.4.4 Ending DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.5 Interrupt Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.6 General Purpose Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.6.1 GPP Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.6.2 GPP Interrupt Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4 Detailed Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.1 HDLC/SDLC Protocol Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.1.1 HDLC Submodes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.1.1.1 Automode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.1.1.2 Address Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.1.1.3 Address Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.1.1.4 Address Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.1.2 HDLC Receive Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.1.3 Receive Address Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.1.4 HDLC Transmit Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.1.5 Shared Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.1.6 One Bit Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.1.7 Preamble Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.1.8 CRC Generation and Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.1.9 Receive Length Check Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.2 Point-to-Point Protocol (PPP) Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.2.1 B it Synchronous PPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.2.2 O ctet Synchronous PPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.2.3 A synchronous PPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.2.4 Data Transparency in PPP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.3 Extended Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.4 Asynchronous (ASYNC) Protocol Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.4.1 Character Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.4.2 Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.4.2.1 Asynchron ous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.4.2.2 Isochronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
PEB 20542
PEF 20542
Table of Contents Page
Data Sheet 7 2000-09- 14
4.4.2.3 Storage of Receive Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.4.3 Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.4.4 Special Function s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.4.4.1 Break Detection/Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.4.4.2 In-band Flow Control by XON/XOFF Characters . . . . . . . . . . . . . . . 102
4.4.4.3 Out-of-band Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.5 BISYNC Protocol Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.5.1 Character Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.5.2 Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.5.3 Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.5.4 Special Function s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.5.4.1 Preamble Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.6 Procedural Support (Layer-2 Functions) . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.6.1 Full-Duplex LAPB/LAPD Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.6.2 Half-Duplex SDLC-NRM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.6.3 Signaling System #7 (SS7) Operation . . . . . . . . . . . . . . . . . . . . . . . . . 117
5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.1 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.2 Detailed Re gister Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.2.1 Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.2.2 Channel Sp ecific SCC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.2.3 Channel Sp ecific DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
5.2.4 Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
6 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
6.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
6.2 Interrupt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
6.2.1 Data Transmission (Interrupt Driven) . . . . . . . . . . . . . . . . . . . . . . . . . . 258
6.2.2 Data Reception (Interrupt Dri ven) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
6.3 Internal DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
6.3.1 Data Transmission (DMA Controlled ) . . . . . . . . . . . . . . . . . . . . . . . . . 263
6.3.2 Data Reception (DMA Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
6.3.3 Buffer Switched Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
7 El ectrical C h aracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
7.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
7.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
7.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
7.4 AC Characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
7.5 Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
7.6 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
7.7 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
7.7.1 Microprocessor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
PEB 20542
PEF 20542
Table of Contents Page
Data Sheet 8 2000-09- 14
7.7.1.1 Microprocessor Interface Clock Timing . . . . . . . . . . . . . . . . . . . . . . 276
7.7.1.2 Infineon/Intel Bus Interface Timing (Slave Access) . . . . . . . . . . . . . 277
7.7.1.3 Motorola Bus Interface Timing (Slave Access) . . . . . . . . . . . . . . . . 279
7.7.1.4 Infineon/Intel Bus Interface Timing (Master Access) . . . . . . . . . . . . 281
7.7.1.5 Motorola Bus Interface Timing (Master Access) . . . . . . . . . . . . . . . 283
7.7.1.6 Bus Arbitration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
7.7.2 PCM Serial In terface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
7.7.2.1 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
7.7.2.2 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
7.7.2.3 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
7.7.2.4 Clock Mode 1 Strobe Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
7.7.2.5 Clock Mode 4 Gating Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
7.7.2.6 Clock Mode 5 Frame Synchronisation Timing . . . . . . . . . . . . . . . . . 292
7.7.3 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
7.7.4 JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
8 Test M o d es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
8.1 JTAG Boundary Scan Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
9 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
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List of Figures Page
Data Sheet 9 2000-09- 14
Figure 1 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 2 System Integration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 3 Point-to-Point Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 4 Point-to-Multipoint Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 5 Multimaster Bus Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 6 Pin Configuration P-TQFP-144-10 Package . . . . . . . . . . . . . . . . . . . . 28
Figure 7 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 8 SCC Transmit FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 9 SCC Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 10 XFIFO/RFIFO Word Access (Intel Mode) . . . . . . . . . . . . . . . . . . . . . . 47
Figure 11 XFIFO/RFIFO Word Access (Motorola Mode). . . . . . . . . . . . . . . . . . . 47
Figure 12 Clock Supply Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 13 Clock Mode 0a/0b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 14 Clock Mode 1 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 15 Clock Mode 2a/2b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 16 Clock Mode 3a/3b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 17 Clock Mode 4 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 18 Selecting on e time-slot of programma ble delay an d width . . . . . . . . . 58
Figure 19 Selecting one or more time-slots of 8-bit width . . . . . . . . . . . . . . . . . . 60
Figure 20 Clock Mode 5a Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 21 Clock Mode 5a "Continuous Mode" . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 22 Clock Mode 5a "Non Continuous Mode" . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 23 Selecting one or more octet wide time-slots . . . . . . . . . . . . . . . . . . . . 65
Figure 24 Clock Mode 5b Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 25 Clock Mode 6a/6b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 26 Clock Mode 7a/7b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 27 DPLL Algo rithm (NRZ a nd N R ZI Encoding, Phas e Shift Enabled) . . . 71
Figu re 28 DPLL Algo rit hm (NRZ and N RZI Enc oding, Phase Shift Di s a bled) . . . 71
Fig ure 29 DPLL Algorithm fo r FM0, FM1 and Man c hes ter Encoding . . . . . . . . . 72
Figure 30 Request- to-Send in Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 31 NRZ and NRZI Data Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 32 FM0 and FM1 Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 33 Manchester Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 34 RTS/CTS Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 35 SCC Test Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 36 SEROCCO-D requests and gets the bus. . . . . . . . . . . . . . . . . . . . . . . 82
Figure 37 Un-interrupted Series of 32 DMA Bus Cycles . . . . . . . . . . . . . . . . . . . 82
Figure 38 Bus Preemption and Re-gain of Bus Control. . . . . . . . . . . . . . . . . . . . 83
Figure 39 SEROCCO-D requests and gets the bus. . . . . . . . . . . . . . . . . . . . . . . 83
Figure 40 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 41 HDLC Receive Data Processing in 16 bit Automode. . . . . . . . . . . . . . 89
Figure 42 HDLC Receive Data Processing in 8 bit Automode. . . . . . . . . . . . . . . 89
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List of Figures Page
Data Sheet 10 2000-09- 14
Figure 43 HDLC Receive Data Processing in Address Mode 2 (16 bit). . . . . . . . 90
Figure 44 HDLC Receive Data Processing in Address Mode 2 (8 bit). . . . . . . . . 90
Figure 45 HDLC Receive Data Processing in Address Mode 1. . . . . . . . . . . . . . 90
Figure 46 HDLC Receive Data Processing in Address Mode 0. . . . . . . . . . . . . . 91
Figure 47 SCC Transmit Data Flow (HDLC Modes) . . . . . . . . . . . . . . . . . . . . . . 92
Figure 48 PPP Mapping/Unmapping Example. . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 49 Asynchronous Character Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 50 Out-of-Band DTE-DTE Bi-directional Flow Control . . . . . . . . . . . . . . 105
Figure 51 Out-of-Band DTE-DCE Bi-directional Flow Control . . . . . . . . . . . . . . 106
Figure 52 BISYNC Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 53 Processing of Received Frames in Auto Mode . . . . . . . . . . . . . . . . . 111
Figure 54 Timer Procedu re/Poll Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 55 Transmissio n/ Rece p tio n of I-Frames an d Flow Con tro l. . . . . . . . . . . 114
Figure 56 Flow Control: Recepti on of S-Commands and P r ot oc ol Errors . . . . . 114
Figure 57 No Data to Send: Data Reception/Transmission . . . . . . . . . . . . . . . . 117
Figure 58 Data Transmission (without err o r), D at a T ransmissi on (with erro r) . . 117
Figure 59 Interrupt Driven Data Transmission (Flow Diagram) . . . . . . . . . . . . . 260
Figure 60 Interrupt Driven Data Reception (Flow Diagram). . . . . . . . . . . . . . . . 262
Figure 61 DMA Transmit (Single Buffer pe r Packet) . . . . . . . . . . . . . . . . . . . . . 264
Figure 62 Fragmented DMA Transmission (Multiple Buffers per Packet) . . . . . 265
Figure 63 DMA Control led Data Transmission (Flow Diagram). . . . . . . . . . . . . 266
Figure 64 DMA Receive (Single Buffer per Pa cket). . . . . . . . . . . . . . . . . . . . . . 267
Figure 65 Fragmented Reception per DMA (Example) . . . . . . . . . . . . . . . . . . . 268
Figure 66 Fragmented Reception Sequence (Example) . . . . . . . . . . . . . . . . . . 269
Figure 67 DMA Controlled Data Reception (Fl ow Diagram) . . . . . . . . . . . . . . . 270
Figure 68 Input/Output Waveform for AC Tests. . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 69 Microprocessor Interface Clock Timing . . . . . . . . . . . . . . . . . . . . . . . 276
Figure 70 Infineon/Intel Read Cycle Timing (Slave Access) . . . . . . . . . . . . . . . 277
Figure 71 Infineon/Intel Write Cycle Timing (Slave Access) . . . . . . . . . . . . . . . 277
Figure 72 Motorola Read Cycle Timing (Slave Access). . . . . . . . . . . . . . . . . . . 279
Figure 73 Motorola Write Cycle Timing (Slave Access). . . . . . . . . . . . . . . . . . . 279
Figure 74 Infineon/Intel Read Cycle Timing (Master Access) . . . . . . . . . . . . . . 281
Figure 75 Infineon/Intel Write Cycle Timing (Master Access) . . . . . . . . . . . . . . 282
Figure 76 Motorola Read Cycle Timing (Master Access). . . . . . . . . . . . . . . . . . 283
Figure 77 Motorola Write Cycle Timing (Master Access). . . . . . . . . . . . . . . . . . 284
Figure 78 Bus Arbitration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Figure 79 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Figure 80 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 81 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Figure 82 Clock Mode 1 Strobe Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Figure 83 Clock Mode 4 Receive Gating Timing . . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 84 Clock Mode 4 Transmit Gating Timing. . . . . . . . . . . . . . . . . . . . . . . . 291
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Data Sheet 11 2000-09- 14
Figure 85 Clock Mode 5 Frame Synchronisation Timing . . . . . . . . . . . . . . . . . . 292
Figure 86 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Figure 87 JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Figure 88 Block Diagram of Test Access Port an d Boundary Sc an Unit . . . . . . 295
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List of Tables Page
Data Sheet 12 2000-09- 14
Table 1 Microprocessor Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 2 Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 3 Serial Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 4 General Purpose Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 5 Test Interface Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 6 Power Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 7 Overview of Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 8 Clock Modes of the SCCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 9 BRRL/BRRH Register and Bit-Fields. . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 10 Data Bus Access 16-bit Intel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 11 Data Bus Access 16-bit Motorola Mode. . . . . . . . . . . . . . . . . . . . . . . . 81
Table 12 Protocol Mode Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 13 Address Comparison Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 14 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 15 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 16 Status In formation after RME interupt . . . . . . . . . . . . . . . . . . . . . . . . 261
Table 17 DMA Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Table 18 Capacitances
TA = 25 ×C; VDD3 = 3.3 V ± 0.3 V, VSS = 0 V . . . . . . . . . . . . . . . . . 274
Table 19 Thermal Package Characteristics P-TQFP-144-10 . . . . . . . . . . . . . . 275
Table 20 Microprocessor Interface Clock Timing . . . . . . . . . . . . . . . . . . . . . . . 27 6
Table 21 Infineo n/Intel Bus Interface Timing (Slave Access) . . . . . . . . . . . . . . 278
Table 22 Motorola Bu s Interface Timing (Sl ave Access) . . . . . . . . . . . . . . . . . 280
Table 23 Infineon/Inte l Bus Interface Timing (Master Access) . . . . . . . . . . . . . 282
Table 24 Motorola Bu s Interface Timing (Master Access) . . . . . . . . . . . . . . . . 284
Table 25 Bus Arbitrat ion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Table 26 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Table 27 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Table 28 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Table 29 Clock Mode 1 Strobe Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Table 30 Clock Mode 4 Gating Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Table 31 Clock Mode 5 Frame Synchronisation Timing . . . . . . . . . . . . . . . . . . 292
Table 32 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Table 33 JTAG-Bounda ry Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Table 34 Boundary Scan Sequence of SEROCCO-D . . . . . . . . . . . . . . . . . . . 296
Table 35 Boundary Scan Test Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
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List of Registers Page
Data Sheet 13 2000-09- 14
Register 1 GCMDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Register 2 GMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Register 3 DBSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Register 4 GSTAR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Register 5 GPDIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Register 6 GPDAT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Register 7 GPIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Register 8 GPIS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Register 9 DCMDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Register 10 DMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Register 11 DISR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Register 12 DIMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Register 13 FIFOL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Register 14 FIFOH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Register 15 STARL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Register 16 STARH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Register 17 CMDRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Register 18 CMDRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Register 19 CCR0L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Register 20 CCR0H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Register 21 CCR1L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Register 22 CCR1H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Register 23 CCR2L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Register 24 CCR2H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Register 25 CCR3L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Register 26 CCR3H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Register 27 PREAMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Register 28 TOLEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Register 29 ACCM0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Register 30 ACCM1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Register 31 ACCM2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Register 32 ACCM3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Register 33 UDAC0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Register 34 UDAC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Register 35 UDAC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Register 36 UDAC3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Register 37 TTSA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Register 38 TTSA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Register 39 TTSA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Register 40 TTSA3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Register 41 RTSA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Register 42 RTSA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
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Data Sheet 14 2000-09- 14
Register 43 RTSA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Register 44 RTSA3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Register 45 PCMTX0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Register 46 PCMTX1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Register 47 PCMTX2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Register 48 PCMTX3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Register 49 PCMRX0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Register 50 PCMRX1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Register 51 PCMRX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Register 52 PCMRX3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Register 53 BRRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Register 54 BRRH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Register 55 TIMR0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Register 56 TIMR1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Register 57 TIMR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Register 58 TIMR3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Register 59 XAD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Register 60 XAD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Register 61 RAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Register 62 RAH1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Register 63 RAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Register 64 RAH2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Register 65 AMRAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Register 66 AMRAH1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Register 67 AMRAL2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Register 68 AMRAH2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Register 69 RLCRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Register 70 RLCRH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Register 71 XON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Register 72 XOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Register 73 MXON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Register 74 MXOFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Register 75 TCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Register 76 TICR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Register 77 ISR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Register 78 ISR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Register 79 ISR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Register 80 IMR0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Register 81 IMR1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Register 82 IMR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Register 83 RSTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Register 84 SYNCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
PEB 20542
PEF 20542
List of Registers Page
Data Sheet 15 2000-09- 14
Register 85 SYNCH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Register 86 TBADDR1L. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Register 87 TBADDR1M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Register 88 TBADDR1H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Register 89 TBADDR2L. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Register 90 TBADDR2M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Register 91 TBADDR2H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Register 92 XBC1L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Register 93 XBC1H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Register 94 XBC2L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Register 95 XBC2H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Register 96 RBADDR1L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Register 97 RBADDR1M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Register 98 RBADDR1H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Register 99 RBADDR2L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Register 100 RBADDR2M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Register 101 RBADDR2H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Register 102 RMBSL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Register 103 RMBSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Register 104 RBCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Register 105 RBCH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Register 106 VER0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Register 107 VER1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Register 108 VER2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Register 109 VER3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
PEB 20542
PEF 20542
Data Sheet 16 2000-09-14
Preface
The 2 Channel Serial Optimized Communication Controller with DMA PEB 20542
(SEROCCO-D) is a Protocol Controller for a wide range of data communication and
telecommunication applications. This document provides complete reference
information on ha rdw are and software related is s ues as well as on general ope rat ion.
Organi za tion of this Docume nt
This D at a Sheet is divided into 9 cha p t ers. It is organized as follows:
•Chapter 1, Introduction
Give s a gene ral descr ipt ion of t he prod uc t , lists the key feat ures, and pres ent s som e
typical applications.
•Chapter 2, Pin Descriptions
Lists pin locations with associated signals, categorizes signals according to function,
and describes signals.
•Chapter 3, Functional Overview
This chapter provides detailed descriptions of all SEROCCO-D internal functional
blocks.
•Chapter 4, Detailed Protocol Description
Gives a detailed description of all protocols supported by the serial communication
controllers S CCs.
•Chapter 5, Reg is ter D escription
Give s a det ailed description of all S ER OCCO-D on c hip registers.
•Chapter 6, Programming
Provides prog ramming help for SEROCCO-D initialization procedure and operation.
•Chapter 7, Electrical C h aracteristics
Give s a detaile d descrip tion of a ll electric al DC a nd AC char acteristic s and pro vides
timing d iagrams and values for al l interfaces.
•Chapter 8, Test Modes
Gives a detailed des cription of the JTAG bo un dary scan unit .
•Chapter 9, Package Outlin es
PEB 20542
PEF 20542
Data Sheet 17 2000-09-14
Your Comments
We welcome your comments on this document. We are continuously trying improving
our documenta tio n. Please send yo ur rem arks and suggestions by e - m ail t o
sc.docu_comments@infineon.com
Please provide in the subject of your e- mail:
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(Versio n 1. 2),
and in the body of your e-mail:
document type (Data Sheet), issue date (2000-09-14) and document revision number
(DS 1).
PEB 20542
PEF 20542
Introduction
Data Sheet 18 2000-09-14
1 Introduction
The SEROCCO-D is a DMA Integrated Serial Communication Controller with two
independent serial channels1). The serial channels are derived from updated protocol
logic of the ESCC and DSCC4 device family providing a large set of protocol support and
variety in serial interface configuration. This allows easy integration to different
environments and applicat ions.
A gen eric 8- or 16 -bit de multiple x ed ma ster /sla ve interfa ce pro vid es fas t dev ice ac cess
with low bus utilization and easy software h andshaking. The internal DMA co ntroller is
optimized for a minimum CPU intervention. Different control mechanisms allow easy
software development well adapted to the needs of special applications (e.g. frame/
pack et oriented and c ont inuous transmission/reception).
Large on-chip FIFOs of 64 byte capacity per port and direction in combination with
enhanced threshold control mechanisms allow decoupling of traffic requirements on host
bus and serial interfaces with little exception probabilities such as data underruns or
overflows.
Each of the two Serial Communication Controllers (SCC) contains an independent Baud
Rate Generator, DPLL and programmable protocol processing (HDLC, PPP, ASYNC
and BISYNC). Data rates of up to 16 Mbit/s (HDLC, PPP, bit transparent) an d 2 Mbit/s
(DPLL assisted modes) are supported. The channels can also handle a large set of
layer-2 protocol f unctions (LA PD, SS7) r educing bus an d host C PU load. Two c hannel
spec ific t i m ers are provided t o support pro to c ol function s.
1) The serial channels are also called ’ports’ or ’cores’ depending on the context.
2 Channel Serial Optimized Communication Controller
with DMA
SEROCCO-D
PEB 20542
PEF 20542
Data Sheet 1-19 2000-09- 14
Version 1.2 CMOS
Type Package
PEB 20542, PEF 20 542 P-TQFP-144-10
1.1 Features
Serial communication controllers (SCCs)
•Two ind ependent channels
•Full duplex data rates on each channel of up to
16 Mbit/s sync - 2 M bit/s with DP LL
•64 Bytes dee p receive FIFO per SCC
•64 Bytes dee p tr ansmit FIFO per SCC
Serial Interface
•On-chip clock ge neration or ex t e rnal clock sources
•On-chip DPLLs for clock recovery
•Baud rate generator
•Clock gat ing signals
•Clock gapping capability
•Pr ogram mab le tim e-s lot c apabi lity fo r con nect ion to
TDM interfaces (e.g. T1, E1)
•NRZ, NRZI, FM and Manchester data encoding
•Optional data flow control using mo dem contr ol lines (RTS, CTS , CD)
•Support of bus configuration by collision detection and resolution
Bit Processor Functions
•HDLC/SDLC Protocol Modes
–Au tomatic flag detection and transm ission
–Shared opening and closing flag
–Generation of interframe-time fill ’1’s or flags
–Detecti o n of r ece ive line status
–Zero bi t i nsertion and deletion
P-TQFP-144-10
PEB 20542
PEF 20542
Introduction
Data Sheet 20 2000-09-14
–CRC generat i on and che cki n g (CRC-CCITT or CRC-3 2 )
–Trans parent CRC opt ion per channel and/or per fram e
–Programmab le Preamble (8 bit) with select able repetition rate
–Error detection (abort, long frame, CRC error, short frames)
•Bit Synchronous PPP Mode
–Bit oriented transmission of HDLC frame (flag, data, CRC, flag)
–Zero bit insertion/ deletion
–15 consecutive ’1’ bits ab ort sequence
•Octet Sy nc hronous PP P M ode
–Octet orie nted transmission of HDLC frame (flag, data, CRC, flag)
–Pr ogrammab le c haracter m ap of 32 hard-w ired charact ers (00H-1FH)
–Four programmable characters f or additional mapping
–Insertio n/ deletion of con tro l-es c ape charact er (7DH) for mapped characters
•Asynchronous PPP Mode
–Charac t e r oriented tra nsmission o f HD LC frame (fla g, data, CRC , flag)
–Start/ s top bit fram ing of single character
–Progr am m a ble charac ter map of 32 hard-wired characte rs (00H-1FH)
–Four programmable characters f or additional mapping
–Insertio n/ deletion of con tro l-es c ape charact er (7DH) for mapped characters
•Asynchronous (AS YN C ) Protocol Mod e
–Select able character length (5 to 8 bits)
–Even, odd, forced or no parity generation/checking
–1 or 2 stop bits
–Break detection/ generation
–In-band flow control by XON/XOFF
–Immediate character inse rt ion
–Termin at ion character detection for end of bloc k identificat ion
–Time out detection
–Error detectio n (parity error, framing err or)
•BISYNC Protocol Mode
–Progr am m able 6/8 bit SYN pat t ern (M ONOSYNC )
–Progr am mable 12 /16 bit SYN pattern (B ISYNC)
–Select able character length (5 to 8 bits)
–Even, odd, forced or no parity generation/checking
–Generation of interframe-time fill ’1’s or SYN characters
–CRC generat i on (CRC-16 or CRC-CCITT)
–Trans parent CRC opt ion per channel and/or per fram e
–Progr am m able Preamb le (8 bit ) w it h s electable re pet it ion rate
–Termin at ion character detection for end of bloc k identificat ion
–Error detectio n (parity error, framing err or)
•Exten ded Transparent Mo de
–Fully bit t rans parent (no fr am ing, no bit man ipulation)
–Octet-aligned transmission and recep tion
PEB 20542
PEF 20542
Introduction
Data Sheet 21 2000-09-14
•Protoc ol and Mode Independent
–Data bit inversion
–Data ov erflow and underrun detection
–Timer
Protocol Support
•Addre s s R ecognitio n Modes
–No address recogni tion (Address Mode 0)
–8- bit (high byte) address recog nition (Address M ode 1)
–8-bit (low byte) or 16-bit (high and low byte) address recognition (Address Mode 2)
•HDLC Automode
–8-bit or 16 -b i t address gener ation/recognition
–Su pport of LAPB / LAPD
–Au tomatic handling of S- and I-frames
–Au tomatic proc essing of control b yte(s)
–Modulo -8 or m odulo-128 operation
–Pr ogrammab le time-out and retry conditions
–SDLC Normal R es p onse Mod e (N R M) operatio n for slave
•Signal ing System #7 (S S7) support
–Detectio n of FISUs, MSUs and LSSUs
–Unchanged Fill-In Sign aling Units (FISUs) not forwarded
–Au tomatic generation of F IS Us in trans m it direction (incl. seque nc e number)
–Counti ng of errored signaling unit s
Integrated DMA Controller
•4 independent DM A c hannels
•Optimized for minimum CPU intervention
•Effici ent block -oriented data transf er
•Bus preemption
•Fragmented transmiss i on/reception of dat a packets f r om / i nt o multiple buffers
•Switched-Buff er mode for seamless update of bu ff er base ad dress and siz e
•24-bit ad res s able memor y ra nge
•Optiona l DTACK/READY controlled cycles
Microprocessor Interface
•8/16-bit bus interface
•De-multiplexed address/data bus
•Intel/Motorola style
•Asynchronous interface
•Maskable interrupts for each channel
PEB 20542
PEF 20542
Introduction
Data Sheet 22 2000-09-14
Gener al Pu rpose Port (GPP) Pins
General
•3.3V power supply wi t h 5V tolera nt inputs
•Low power consumption
•Pow er s af e f eatures
•P-TQ F P-144-10 Pac k age (Therma l R es i s ta nc e: RJA = 39K/W)
PEB 20542
PEF 20542
Introduction
Data Sheet 23 2000-09-14
1.2 Logi c S ymbol
Figure 1 Logic Symbol
A(23:1)
V
SS
V
DD3
TEST
TCK
TMS
TDI
TDO
TRST
Microprocessor
Interface
JTAG Test
Interface
TxDA
RxDA
RTSA/TxCLKOA
CTSA/CxDA/TCGA/OSTA
CDA/FSCA/RCGA/OSRA
TxCLKA
RxCLKA
Serial
Channel A
SEROCCO-D
PE B 20542
PEF 20 542
XTAL1
XTAL2
TxDB
RxDB
RTSB/TxCLKOB
CTSB/CxDB/TCGB/OSTB
CDB/FSCB/RCGB/OSRB
TxCLKB
RxCLKB
Serial
Channel B
D(15:0)
A0/BLE
DS/LDS
RD
WR
INT/INT
CLK
RESET
CS
READY
BREQ
BGACK
BGNT
GP0
GP1
GP2
Bus
Arbitration
Intel
Mode
General
Purpose Pins
BHE
W/R
ADS
A0/UDS
R/W
DTACK
AS
A(23:1)
D(15:0)
Motorola
Mode
PEB 20542
PEF 20542
Introduction
Data Sheet 24 2000-09-14
1.3 Typical Appli ca t ions
SEROCCO-D devices c an be used in L AN-WAN inte r-networkin g applications such as
Rout ers, Switches and Tru nk cards and support the commo n V.35, ISDN B R I (S/T) and
RFC1662 standards. Its new features provide powerful hardware and software
inte rf ac es to develop high perform a nce system s .
1.3.1 System Integration Example
Figure 2 System Integration
MISTRAL
PEB 20542
PEF 20542
. . .
. . .
. . .
. . .
Transceiver,
Framer
System Bus
CPU
RAM
Bank
Bus
Arbiter
PEB 20542
PEF 20542
Introduction
Data Sheet 25 2000-09-14
1.3.2 Serial Configuration Examples
SEROCCO-D supports a variety of serial configurations at Layer-1 and Layer-2 level.
The outstanding variety of clock modes supporting a large number of combinations of
exter nal and internal clock sources allows easy integration in application env ironment s.
Figure 3 Point-to-Point Configuration
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
TxDRxD RxD TxD
serial transm ission
optional modem control signals
Layer-2 LAPD/B or SS7
Protocol Support
SEROCCO-D
PEB 20542
PEF 20542
SEROCCO-D
PEB 20542
PEF 20542
PEB 20542
PEF 20542
Introduction
Data Sheet 26 2000-09-14
Figure 4 Point-to-Multi point Bus Configuration
Figure 5 Multimaster Bus Configura ti on
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
TxDRxD RxD TxD
. . .
. . .
. . .
. . .
RxD TxD
...
. . .
. . .
. . .
. . .
TxD
CxDCxDCxD
RxD
Master
Slave nSlave 2Slave 1
Layer-1 collision detection
or
Layer-2 SDLC-NRM operation
SEROCCO-D
PEB 20542
PEF 20542
SEROCCO-D
PEB 20542
PEF 20542
SEROCCO-D
PEB 20542
PEF 20542
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
TxDRxD RxD TxD
. . .
. . .
. . .
. . .
RxD TxD
...
CxDCxDCxD
Master nMaster 2Master 1
Layer-1 coll isio n detection
SEROCCO-D
PEB 20542
PEF 20542
SEROCCO-D
PEB 20542
PEF 20542
SEROCCO-D
PEB 20542
PEF 20542
PEB 20542
PEF 20542
Introduction
Data Sheet 27 2000-09-14
1.4 Differences between SEROCCO-D and the ESCC Family
This chapter is useful for all being fa m iliar with the ESC C fam ily.
1.4.1 Enhancements to the ESCC Serial Core
The SEROCCO-D SCC cores contain the core logic of the ESCC as the heart of the
device. Some enhanceme nts are inco rporated in the SCCs. T hese are:
•Integ rat ed four-cha nnel DMA co nt roller
•Octet -, Bit Synchronous and Async hronous PPP protocol support as in RFC-1662
•Sign al ing System #7 (S S7 ) supp o rt
•4-kB yte pack e t length by te counter
•Enhanced address filtering (16-bit maskable)
•Enhanced time slot as s igner
•Supp ort of hi gh data rates (16 Mbit/s)
1.4.2 Simplifications to the ESCC Serial Core
The fo llowing feat ures of the ES C C co re have been rem oved:
•Extended transparent mode 0
(this mode provided octet buffered data reception without usage of FIFOs;
SEROCCO-D supports octet buffered reception via appropriate threshold
config urations for the SCC rec eive FIFOs)
•Support of interrupt ack nowled g e cycles
•Multi pl e xed address/data bus in Infineon/Intel mode
•Master clock mode
PEB 20542
PEF 20542
Pin Desc riptions
Data Sheet 28 2000-09-14
2 Pin Descriptions
2.1 Pin Diag ram P-TQFP-144 -10
(top view)
Figure 6 Pin Configuration P-TQFP-144-10 Package
N.C.
N.C.
N.C.
TDO
TCK
VDD
VSS
CTSB#/CxDB/TCGB#/OSTB
N.C.
VSSA
XTAL2
XTAL1
VDDA
N.C.
CTSA#/CxDA/TCGA#/OSTA
CDA/FSCA/RCGA#/OSRA
RxDA
RxCLKA
TxDA
VDD
VSS
TxCLKA
RTSA#
RESET#
INT/INT#
VDD
VSS
A15
A14
A13
A12
VDD
VSS
N.C.
N.C.
N.C.
N.C.
N.C.
VSS
VDD
A19
A17
VSS
VDD
TMS
R/W# / W/R#
DS#/BHE#/LDS
#
CS#
BM
VSS
VDD
A0/BLE#/UDS#
A1
A2
A3
VDD
VSS
WIDTH
A4
A5
A6
A7
VSS
VDD
A8
A9
A10
A11
N.C.
N.C.
VDD
VSS
RD#
WR#
READY#/DTACK#
CLK
VDD
VSS
D0
D1
D2
D3
VDD
VSS
D4
D5
D6
D7
TEST1
TEST2
VDD
VSS
D8
D9
D10
D11
N.C.
N.C.
A18
A16
N.C.
N.C.
A20
A21
VDD
VSS
A22
A23
BGNT#
BGACK#
GP1
VDD
VSS
GP0
GP2
RTSB#
RxDB
VDD
VSS
RxCLKB
TxDB
TxCLKB
CDB/FSCB/RCGB#/OSRB
ADS#/AS#
VDD
VSS
TRST#
TDI
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VDD
VSS
D12
D13
D14
D15
VDD
VSS
BREQ#
SEROCCO-D
PEB 20542
PEF 20542
108 73104 100 96 92 88 84 80 76
144
109
140
136
132
128
124
120
116
112
37
72
40
44
48
52
56
60
64
68
14 8 12162024283236
P-TQFP-144-
PEB 20542
PEF 20542
Pin Desc riptions
Data Sheet 29 2000-09-14
2.2 Pin Definitions and Functions
Table 1 Micr oproc e ssor Bus Inte rface
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
117
116
115
114
106
105
104
103
98
97
96
95
92
91
90
89
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
I/O Data Bus
The data bus lines are bi-directional tri-state lines
which interface with th e system’s data bus.
PEB 20542
PEF 20542
Pin Desc riptions
Data Sheet 30 2000-09-14
80
79
76
75
68
67
66
65
28
29
30
31
39
40
41
42
45
46
47
48
52
53
54
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Addr ess Bus
Thes e pins connect to th e s ys t em’s address bus
to sel ect one of the int ernal regist ers for read or
write.
Durin g op er ation of the inte r nal DMA controller,
thes e lines output the destination address when
the bus is grante d t o the SEROCCO-D .
Thes e lines are tri-stat e when unus ed.
55 A0
BLE
UDS
I/O
I/O
I/O
Address Line A0 (8-bit modes)
In Motorola and in In tel 8 - bit mode this signal
repr es ents the lea st significant add r es s l ine.
Byte Low Enable (16-bit Intel bus mode)
This signal indicates a data tra ns f er on the lower
byte of the data bus (D7..D0). Together with
signal BHE the t yp e of bus access is determined
(byte or word acce ss at even or odd address ).
Upper Data Strobe (16-bit Motorola bus mode)
This active low strobe signal serves to control
read/write operations. Together with signal LDS
the ty pe of bus ac c ess is dete rm ined.
This line is tri-state wh en unused.
Table 1 Micr oproc e ssor Bus Inte rface
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
PEB 20542
PEF 20542
Pin Desc riptions
Data Sheet 31 2000-09-14
58 BM I Bus Mode
–BM = static ’1’ for operation in Motorola bus
mode (de-multi plex ed).
–BM = static ’0’ for operation in Intel bus mode
with de-multiplexed address and data buses.
pins A(15 : 0)D(15:0)
136 ADS
AS O
OAddress Strobe (Intel Bus Mode)
" (Motorola Bus Mode )
Indic at es that the SEROCCO-D is driving a v alid
address and bu s cycle defi nition on pins A(23:0 ),
BHE (Intel mode) and R/W.
This line is tri-state wh en unused.
60 DS
BHE
LDS
I/O
I/O
I/O
Data Strobe (8-bit Motorola bus mode only)
This active low strobe signal serves to control
read/write operations.
Bus High Enable (16-bit Intel bus mode only)
This signal indicates a data transfer on the upper
byte of the da ta bus (D15..D8). In 8-bit Intel bus
mode this sign al has no fu nc tion.
Lower Data Strobe (16-bit Motorol a bus mode)
This active low strobe signal serves to control
read/write operations. Together with signal UDS
the type of bus access is determined (byte or word
access at even or odd address ).
This line is tri-state wh en unused.
In 8- bit Intel bus mode, a p ull-up resi stor to VDD3
is recommended on this pin.
83 RD I/O Read Strobe (Intel bus mode only)
This signal indicates a read operation. The current
bus master is able to accept data on lines D(7:0) /
D(15:0) during an active RD signal.
This line is tri-state wh en unused.
In Motorola bus mode, a pull-up resistor to VDD3 is
recom m ended on this pin.
Table 1 Micr oproc e ssor Bus Inte rface
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
PEB 20542
PEF 20542
Pin Desc riptions
Data Sheet 32 2000-09-14
61 R/W
W/R
I/O
O
Read/Write Enable (Motorola bus mode)
This signal distinguishes between read and write
operation. As an input it must be valid during data
strobe (DS ).
Write/Read Enable (Intel bus mode)
During master bus accesses from SERO CCO-D
(DMA) thi s signal indicates the transacti o n
direction (write/read). W hen SEROCCO-D is
slav e, this s ignal is not evaluated.
This line is tri-state wh en unused.
If no t used in In tel b us mode , a pull -up resi stor to
VDD3 is recommended on this pin.
59 CS IChip Select
A low signa l se lects SEROCCO-D for read/write
operations.
84 WR I/O Write Strobe (Intel bus mode only)
This sig nal indicates a w rite operatio n. The
current bus maste r presents vali d dat a on lines
D(7: 0) / D(1 5: 0) during an act iv e WR signal.
This line is tri-state wh en unused.
In Motorola bus mode, a pull-up resistor to VDD3 is
recom m ended on this pin.
49 WIDTH I Width Of Bus Interfac e
A low signal on this input select s the 8-bit bus
interfac e mode.
A high signal on this input selects t he 16-bit bus
interface mode . In this c ase word trans fer to/from
the int ernal registe r s is enabled. Byte tran sf ers
are implemented by using BLE and BHE (Intel bus
mode) or LDS and UDS (M ot orola bus m ode)
86 CLK I Clock
The s yst em clock for SEROCCO-D is provided
throug h t his pin.
Table 1 Micr oproc e ssor Bus Inte rface
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
PEB 20542
PEF 20542
Pin Desc riptions
Data Sheet 33 2000-09-14
25 INT/INT O
o/d Interrupt Request
The INT/INT goes active when one or more of the
bits in regis t ers ISR0..ISR2 are set to ’1’. A read
to these regist ers clears the interr upt . The INT/
INT line is inactive when all interrupt status bits
are reset.
Interrupt sources can be unmasked in registers
IMR0..IMR2 by settin g the c or r esponding bi ts to
’0’.
85 READY
DTACK I/O
I/O Ready (Intel bus mode)
Data Transfer Acknowledge (Motorola mode)
During a slave access (register read/write) this
signal (output) indicates, that the SEROCCO-D is
ready for data transfer. The signal remains active
until t he data stro be (D S in Motorola bus mode,
RD/WR in Intel bus mode) an d/ or t h e chip select
(CS) go inactiv e .
When the SEROCCO-D performs a DMA master
access, the target may extend the read/write cycle
using this s ignal (input) when enabled in register
DCMDR.
This line is tri-state wh en unused.
A pull -up resistor to VDD3 is recommended if thi s
func tion is not used.
24 RESET IReset
With this activ e low signal the on-c hip registers
and stat e m achines are fo rced to reset s ta te.
During Reset all pin s ar e in a high impeda nc e
state.
Table 1 Micr oproc e ssor Bus Inte rface
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
PEB 20542
PEF 20542
Pin Desc riptions
Data Sheet 34 2000-09-14
Table 2 Bus Arbitration
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
120 BREQ O
o/d Bus Request
By asserting this signal to low, the SE ROCCO-D
requests master bus access from the external bus
arbite r. As soon as the bus is granted to t he
SEROCCO-D and BGACK is asserted, this signal
turns to inac t i ve.
If con f i gured as open-d rain output, bus
preempt i on can be forced by th e arbiter if it
asserts this signal during the SEROCCO-D drives
BGACK active (low).
A pull-up resistor < 1.5 kW to VDD3 mus t be
conn ec ted to this pin if configured as open-drain
output.
122 BGACK o/d Bus Grant Acknowledge
With this signal the SEROCCO-D indicates the
period the bus is occupied for master read or write
transf ers of the internal D M A c ontroller.
A pull-up re s istor to VDD3 must be connected to
this open-drain pin.
121 BGNT IBu s Grant
With thi s active-low in put signal the bus ar bi ter
grants the bu s to SE ROCCO-D. SEROCCO-D
waits fo r BGACK to go high (indicating that the
external bus master has release d t he bus) and
take s o v er the bus by as s e rting BGAC K low.
PEB 20542
PEF 20542
Pin Desc riptions
Data Sheet 35 2000-09-14
Table 3 Serial Port Pins
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
22 TxCLK
AI/O Transmit Clock Channel A
The function of t his pin depend s on the selec ted
clock mode and the value of bit ’TOE’ (CCR0L
regist er, refer to Table 8 "Clock Modes of the
SCCs" on Page 49).
If programmed as Input (CCR0L.TOE=’0’),
either
– the transmit clock for the channel (clock
mode 0a, 2a, 4, 5b, 6a) , or
– a transmit strobe signal for the channel (clock
mode 1)
can be provided t o this pin.
If programmed as Output (CCR0L.TOE=’1’),
this pin supp lies eit her
– the t r ansmi t c lock from th e ba ud r ate gen era tor
(clock mode 0b, 2b, 3b, 6b, 7b), or
– the transmit clock from the DPLL circuit (clock
mode 3a, 7a), or
– an active-low control signal marking the
programmed transmit time-slot in clock mode
5a.
18 RxCLK
AIReceive Clo ck Channel A
The function of t his pin d epends on the selected
clock mode (refe r to Table 8 "Clock Modes of
the SCCs" on Page 49).
A signal provided on pin RxCLKA may su pply
– the receive clock (clock mode 0, 4, 5b), or
– the receive and transmit clock (clock mode 1,
5a), or
– the clock input for the baud rate generator
(clock m od e 2, 3).
PEB 20542
PEF 20542
Pin Desc riptions
Data Sheet 36 2000-09-14
16 CDA
FSCA
RCGA
OSRA
I
I
I
I
Carrier Detect Channel A
The function of t his pin depends on th e s elected
clock mode.
It ca n s upply
– either a modem control or a general purpose
inpu t (clock mode s 0, 2, 3, 6, 7). If auto-s tart is
programmed, it functions as a receiver enable
signal.
– or a receive strobe signal (clock mode 1).
Polarity of CDA can be se t to ’active low’ with bit
ICD in register CCR1H.
Add itionally, an interrup t m ay be issued if a st at e
transi ti o n occurs at the CDA pin (p r og r ammable
feature).
Frame Sync Clock Channel A (cm 5a)
When the SCC is in the time-slot oriente d clock
mode 5a, this pin functi ons as the Frame
Sync hronization Clock input.
Receive Cloc k Gating Ch an n el A (cm 4)
In clock mode 4 this pin is used as Receive Clock
Gating signal.
If no cloc k gat ing funct ion is required, a pull - up
resistor to VDD3 is recommended.
Octet Sync Receive Channel A (cm 5b)
(clock mode 5b)
When the SCC is in the time-slot oriente d clock
mode with octet-alignment (clock mode 5b),
received octets are aligned to this synchronization
puls e input.
Table 3 Serial Port Pins (cont’d)
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
PEB 20542
PEF 20542
Pin Desc riptions
Data Sheet 37 2000-09-14
23 RTSA ORequest to Send Channel A
The function of this pin depends on the settings of
bits RTS, FRTS in register CCR1H .
In bus configuration, RTS can be programmed to:
– go low during the actual transmission of a
frame shifted by one clock period, excluding
collision bits.
– go low du ring receptio n of a dat a f ram e.
– stay always high (RTS disabled).
15 CTSA
CxDA
TCGA
OSTA
I
I
I
I
Clear to Send Channel A
A low on the CTSA input enables the transmitter.
Add itionally, an interrup t m ay be issued if a st at e
transition occurs a t the CT SA pin (pro grammab le
feature).
If no ’Clear To Send’ function is required, a pull-
down resistor to VSS is recommended.
Collision Data Channel A
In a bus configuratio n, the external ser ial bus
must be connected to the corresponding CxDA
pin for collision de te ction.
A collision is detected whenever a logical ’1’ is
driven on the open dr ain TxDA out put but a
logical ’0’ is detected via CxDA input.
Transmit Clock Gating Channel A (cm 4)
In clock mode 4 these pins are used as Transmit
Clock Gating signals.
If no cloc k gat ing funct ion is required, a pull - up
resistor to VDD3 is recommended.
Octet Sync Transmit Channel A (cm 5b)
When the SCC is in the time-slot oriente d clock
mode with octet-alignment (clock mode 5b), a
synchronization pulse on this input pin aligns
transmit octets.
Table 3 Serial Port Pins (cont’d)
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
PEB 20542
PEF 20542
Pin Desc riptions
Data Sheet 38 2000-09-14
19 TxDA O
o/d Transmit Data Channel A
Transmit data is shifted ou t via this pin . It c an be
conf igured as pus h/ pull or open dra in output
character istic via bit ’ODS’ in regi ster CCR1L.
17 RxDA I Receive Data Channel A
Seri al dat a is received on th is pin.
134 TxCLK
BI/O Transmit Clock Channel B
(cor r espondin g to channel A)
132 RxCLK
BIReceive Clo ck Channel B
(cor r espondin g to channel A)
135 CDB
FSCB
RCGB
OSRB
I
I
I
I
Carrier Detect Channel B
Frame Sync Clock Channel B (cm 5a)
Receive Cloc k Gating Ch an n el B (cm 4)
Octet Sync Receive Channel B (cm 5b)
(c or responding to channel A)
128 RTSB ORequest to Send Channel B
(cor r espondin g to channel A)
8CTSB
CxDB
TCGB
OSTB
I
I
I
I
Clear to Send Channel B
Collision Data Channel B
Transmit Clock Gating Channel B (cm 4)
Octet Sync Transmit Channel B (cm 5b)
(c or responding to channel A)
133 TxDB O
o/d Transmit Data Channel B
(cor r espondin g to channel A)
Table 3 Serial Port Pins (cont’d)
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
PEB 20542
PEF 20542
Pin Desc riptions
Data Sheet 39 2000-09-14
129 RxDB I Receive Data Channel B
(cor r espondin g to channel A)
12
11 XTAL1
XTAL2 I
OCrystal Connection
If the internal oscillator is used for clock
genera tion (clock modes 0b, 6, 7) the external
crys t al has to be connecte d to these pin s. The
internal oscillato r should be powered up
(GMODE:OSCPD = ’0’) and the signal shaper
may be ac t iv at ed (GMODE:DSHP = ’0’).
Moreover, XTAL 1 m ay be used as input for a
common cl ock sou rce to bo th SCCs , pro vid ed by
an external clock generator (oscillator). In this
case the oscillator unit may be powered down and
it is recom mended t o by pass the shaper of the
internal oscillato r unit by setting bit ’DSHP’ to ’1’.
A pull - dow n resis to r to VSS is recom m ended for
pin XTAL1 if not used .
Table 4 General Purpose Pins
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
127
123
126
GP2
GP1
GP0
I/O General Purpose Pins
These pins serve as general purpose input/output
pins.
A pull-up resistor to VDD3 is recommended if pin is
not used.
Table 3 Serial Port Pins (cont’d)
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
PEB 20542
PEF 20542
Pin Desc riptions
Data Sheet 40 2000-09-14
Table 5 Test Interfac e Pins
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
139 TRST IJTAG Reset Pin (internal pull-up)
For proper device operation, a res et for the
bound ary scan contro ller must be suppl ied to this
active low pin.
If th e boundary sc an of the SEROCCO-D is not
used, this pin can b e c onnected to V SS to keep it
in reset state.
5TCKI JTAG Test Clock (internal pull-up)
If th e boundary sc an of the SEROCCO-D is not
used, this pin may rem ain unconnected.
140 TDI I JTAG Test Data Input (internal pull-up)
If th e boundary sc an of the SEROCCO-D is not
used, this pin may rem ain unconnected.
4TDOOJTAG Test Data Output
62 TMS I JTAG Test Mode Select (internal pull-up)
If th e boundary sc an of the SEROCCO-D is not
used, this pin may rem ain unconnected.
99 TEST1 I Test Input 1
When connected to VDD3 the SER OCCO-D works
in a vendor specific test mode.
This pi n m us t be connect ed t o VSS.
100 TEST2 I Test Input 2
When connected to VDD3 the SER OCCO-D works
in a vendor specific test mode.
This pin must be connected to VSS.
PEB 20542
PEF 20542
Pin Desc riptions
Data Sheet 41 2000-09-14
Table 6 Power Pins
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
6, 20,
26, 32,
43, 51,
56, 63,
69, 77,
81, 87,
93,
101,
112,
118,
124,
130,
137
VDD3 -Digital Supply Voltage 3.3 V ±0.3 V
All pins must be connected to the same voltage
potential.
7, 21,
27, 33,
44, 50,
57, 64,
70, 78,
82, 88,
94,
102,
113,
119,
125,
131,
138
VSS -Digital Ground (0 V)
All pins must be connected to the same voltage
potential.
13 VDDA -Analog Supply Voltage 3.3 V ±0.3 V
This pin s upplies the on -c hip oscillator of the
SEROCCO-D. If no separate analog power
supply is available, this pin can be directly
connected to VDD3.
PEB 20542
PEF 20542
Pin Desc riptions
Data Sheet 42 2000-09-14
10 VSSA -Analog Ground (0 V)
This pin s upplies the ground level to the on-c hip
oscillator of the SEROCCO-D. If no separate
analog power supply is available, this pin can be
directly conn ected to VSS.
1, 2, 3,
9, 14,
34, 35,
36, 37,
38, 71,
72, 73,
74,
107,
108,
109,
110,
111,
141,
142,
143,
144
N.C. - Not Co n n ected
Table 6 Power Pins (cont’d)
Pin No. Symbol In (I)
Out (O) Function
P-TQFP-
144-10
PEB 20542
PEF 20542
Functional Overview
Data Sheet 43 2000-09-14
3 Functional Overview
The functional blocks of SEROCCO-D can be divided into two major domains:
–the microprocessor interface of SEROCCO-D provides access to on-chip registers
and to the "user" portion of the receive and transmit FIFOs (RFIFO/XFIFO). Optionally
these FIF Os can be acces s ed by the built-in 4-channel D M A controlle r.
–the Serial Communication Controller (SCC) is capable of processing bit-synchronous
(HDLC/SDLC/bitsync PPP) and octet-synchronous (octet-sync PPP) as well as fully
trans parent data traff ic .
Data exchange between the serial communication controller and the microprocessor
interface is perfo r m ed us ing FIFOs , de c oupling thes e tw o domains.
3.1 Block Diagram
Figure 7 Block Diagram
Microprocessor
Interface
JTAG Test
Interface Serial
Channel A
Decoder/
Collision
Detection
Clock
Control
DPLL
FIFO
(32 Byte)
FIFO
(32 Byte)
XFIFO
(32 B yte )
RFIFO
(32 B yte )
Transmit
Protocol
Machine
Receive
Protocol
Machine BRG
LAP D/B
SS7
Serial
Channel B
TSA
5
7
7
55 Oscillator
Rx/ T x DMA
Controller
HDLC, ASYNC,
PPP, BISYNC
XFIFO
(32 B yte )
RFIFO
(32 B yte )
Rx/Tx DMA
Controller
PEB 20542
PEF 20542
Functional Overview
Data Sheet 44 2000-09-14
3.2 Serial Communication Controller (SCC)
3.2.1 Protocol Modes Overview
The SCC is a multi-prot ocol comm unicatio n c ontroller. T he c ore logic p r ov ides different
protoc ol m odes which are listed below:
•HDLC Modes
–HDLC T r ansparent Operation (Address M ode 0)
–HDLC Address Recognition (Address Mode 1, Address Mode 2 8/16-bit)
–Full-D uplex LAPB/LAPD Operation (Automode 8/16-bit )
–Half-Duplex SDLC-NRM Operatio n (A utomode 8-b i t)
–Signaling System #7 (SS7) Operation
•Point-t o-Point Protoc ol (PPP) Mode s
–Bit Synchronous PPP
–Octet Synchronous PPP
–Asynchronous PPP
•ASYNC M odes
–Asynchronous Mode
–Isochronous Mode
•BISYNC Modes
–Bisynchronous Mode
–Monosynchronous Mode
•Exten ded Transparent Mo de
A detailed description of these protocol modes is given in Chapter 4, starting on
Page 86.
3.2.2 SCC FIFOs
Each SCC provides its own transmit and receive FIFOs to handle internal arbitration and
microcontroller latencies.
PEB 20542
PEF 20542
Functional Overview
Data Sheet 45 2000-09-14
3.2.2. 1 SCC Transmit FIFO
The SCC transmit FIFO is divided into two parts of 32 bytes each (’transmit pools’). The
interface between the two parts provides synchronization between the microprocessor
acce ss es and the pr otocol logic working with the serial t ransmit cloc k.
Figure 8 SCC Transmit FIFO
A 32 bytes FIFO part is accessable by the CPU/DMA controller; it accepts transmit data
even if th e SCC is in po we r -down conditi on (register CCR0H bit PU=’0’).
The only exception is a transmit data underrun (XDU) event. In case of an XDU event
(e.g. after excessive bus latency), the FIFO will neither accept more data nor transfer
anothe r byte t o the protoc ol logic. This XDU blo cki ng mech anism p reven ts unex pecte d
serial data. The blocking condition must be cleared by reading the interrupt status
register ISR1 after the XDU interrupt was generated. Thus, the XDU interrupt indication
shoul d not be masked in reg is t e r IMR1.
Trans fer of dat a to the 32 byte shad ow part on ly take s place if th e SCC is in power-u p
condition and an appropriate transmit clock is provided depending on the selected clock
mode.
Serial data transmission will start as soon as at least one byte is transferred into the
shadow FIFO and transmission is enabled depending on the selected clock mode (CTS
signal active, clock strobe signal active, timeslot valid or clock gapping signal inactive).
3.2.2. 2 SCC Receive FIFO
The SCC r eceiv e FIFO is divi ded in to two p arts of 32 by tes ea ch. The i nter face be tween
the two parts provides synchronization between the microprocessor accesses and the
protoc ol logic working with the serial receive clock.
32 byte Transmit Pool
(accessable by CPU)
32 byte Shadow part
(not accessab le by CPU)
Microprocessor/DMA
Interface
Transmit
Protocol M achine
PEB 20542
PEF 20542
Functional Overview
Data Sheet 46 2000-09-14
Figure 9 SCC Receive FIFO
New receive data is announced to the CPU with an interrupt latest when the FIFO fill
level reaches a chosen threshold level (selected with bitfield ’RFTH(1..0)’ in register
“CCR3H” on Page 171). Default value for this threshold level is 32 bytes in HDLC/PPP
modes and 1 byte in AS YN C or BI SYNC mo de.
If the SCC receive FIFO is completely filled, further incoming data is ignored and a
receive data overflow condition (’RDO’) is detected. As soon as the receive FIFO
provide s em p ty sp ac e, r eceiv e da ta is a cce pted ag ain after a fram e end o r fr ame abort
sequence. The automatically generated receive status byte (RSTA) will contain an ’RDO’
indication in this case and the next incom in g fram e w ill be receive d in a normal way.
Therefore no furthe r CPU intervention is necessa ry t o recover the SC C from an ’RDO’
condition.
A "frame" with ’RDO’ status might be a mixture of a frame partly received before the
’RDO’ event occured and the rest of this frame received after the receive FIFO again
accepted data and the frame was still incoming. A quite arbitrary series of data or
complete frames might get lost in case of an ’RDO’ event. Every frame which is
comp let ely discarded becaus e of an ’RDO’ condition generates an ’RFO’ interrupt.
The S CC receive FIFO can be clear ed by comm and ’RRES’ in re gister CMDRH. Note
that clearing the receive FIFO during operation might delete a frame end / block end
indication. A frame which was already partly transferred cannot be "closed" in this case.
A new frame received after receiver reset command will be appended to this "open"
frame.
Microprocessor/DMA
Interface
Receive
Protocol Machine
32 byte Receive Pool
(accessable by CPU)
32 byte Shadow part
(not accessable by CPU)
PEB 20542
PEF 20542
Functional Overview
Data Sheet 47 2000-09-14
3.2.2. 3 SCC FIFO Acce ss
Figure 10 and Figure 11 illustrate byte interpretation for Intel and Motorola 16-bit
acce sses to the t ransmit an d receive FIFOs.
Figure 10 XFIFO/RFIFO Word Access (Intel Mode)
Figure 11 XFIFO/RFIFO Word Access (Motorola Mode)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 32
D(7:0)D(15:8)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 32
D(7:0)D(15:8)
XFIFO RFIFO
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 32
D(7:0)D(15:8)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 32
D(7:0)D(15:8)
XFIFO RFIFO
PEB 20542
PEF 20542
Functional Overview
Data Sheet 48 2000-09-14
3.2.3 Clocking System
The SEROCCO-D includes an internal Oscillator (OSC) as well as two independent
Baud Rate Generators (B RG) and two Digital Ph ase Locked Loo p (DP LL) circuits.
The tran smi t and receive clock can be generated either
•extern ally , and supplied directly via the RxC LK and/o r T xCLK pins
(called ex t ernal clock modes)
•internally, by selecting
–the internal oscillator (OSC) and/or the channel specific baud rate generator (BRG)
–the internal DPLL, recovering the receive (and optionally transmit) clock from the
rece iv e dat a stream.
(called internal clock modes)
There are a total of 14 different clocking modes programmable via bit field ’CM’ in
register CCR0L, providing a wide variety of clock generation and clock pin functions, as
shown in Table 8.
The transmit clock pins (TxCLK) may also be configured as output clock and control
signals in c ertain cloc k modes if enab led via bit ’TOE’ in register CCR0L.
The clocking source for the DPLL’s is always the internal channel specific BRG; the
scaling factor (divider) of the BRG can be programmed through BRRL and BRRH
registers.
There are two channel specific int ernal opera ti onal clocks in t he SCC:
One operational clock (= transmit clock) for the transmitter part and one operational clock
(= receive clock) for the receiver part of the protocol logic.
Note: The internal timers always run using the internal transmit clock.
Table 7 Overview of Clock Modes
Clock
Type Source Generation Clock Mode
Receive
Clock
RxCLK Pins Externally 0, 1, 4, 5
OSC,
DPLL,
BRG,
Internally 2, 3a, 6, 7a
3b, 7b
Transmit
Clock
TxCLK Pin s ,
RxCLK Pins Externa lly 0a, 2a, 4, 6a
1,5
OSC,
DPLL,
BRG/BCR,
BRG
Internally 3a, 7a
2b, 6b
0b, 3b, 7b
PEB 20542
PEF 20542
Functional Overview
Data Sheet 49 2000-09-14
The internal structure of each SCC channel consists of a transmit protocol machine
clocked with the transmit frequency fTRM and a receive protocol machine clocked with the
receive f requency fREC.
The clocks fTRM and fREC are internal clocks only and need not be identical to external
clock inputs e.g. fTRM and TxCLK input pin.
The fe at ures of the different cl oc k modes are summarized in Table 8.
Note: If asynchronous operation is selected (asynchronous PPP, ASYNC mode), some
clock mode frequencies can or must be divided by 16 as selected by the Bit Clock
Rate bit CCR0L:BCR:
When bit clock rate is ‘16’ (bit BCR = ’1’), oversampling (3 samples) in conjunction
with majority decision is performed. BCR has no effect when using clock mode 2,
3a, 4, 5, 6, or 7a.
Table 8 Cloc k Modes o f the SCCs
Channel
Configuration Clock Sources Control Sources
Clock
Mode
CCR0L:
CM(2..0) CCR0L:
SSEL to
BRG to
DPLL to
REC to
TRM CD R- Strobe X- Strobe Frame-
Sync
Tx Rx
Output
via
TxCLK
(if CCR0L:
TOE = ‘1’)
0a
0b
1
2a
2b
3a
3b
4
5a
5b
6a
6b
7a
7b
0
1
X
0
1
0
1
X
0
1
0
1
0
1
–
OSC
–
RxCLK
RxCLK
RxCLK
RxCLK
–
–
–
OSC
OSC
OSC
OSC
–
–
–
BRG
BRG
BRG
–
–
–
–
BRG
BRG
BRG
–
RxCLK
RxCLK
RxCLK
DPLL
DPLL
DPLL
BRG
RxCLK
RxCLK
RxCLK
DPLL
DPLL
DPLL
BRG
TxCLK
BRG
RxCLK
TxCLK
BRG/16
DPLL
BRG
TxCLK
RxCLK
TxCLK
TxCLK
BRG/16
DPLL
BRG
CD
CD
–
CD
CD
CD
CD
–
–
–
CD
CD
CD
CD
–
–
CD
–
–
–
–
RCG
(TSAR/
PCMRX)
(TSAR/
PCMRX)
–
–
–
–
–
–
TxCLK
–
–
–
–
TCG
(TSAX/
PCMTX)
(TSAX/
PCMTX)
–
–
–
–
–
–
–
–
–
–
–
–
FSC
OST
–
–
–
–
–
–
–
–
–
–
–
–
FSC
OSR
–
–
–
–
–
BRG
–
–
BRG/16
DPLL
BRG
-
TS-Control
–
–
BRG/16
DPLL
BRG
Clock Mode fREC fTRM
0a
0b
1
3b, 7b
fRxCLK/BCR
fRxCLK/BCR
fRxCLK/BCR
fBRG/BCR
fTxCLK
fBRG
fRxCLK/BCR
fBRG/BCR
PEB 20542
PEF 20542
Functional Overview
Data Sheet 50 2000-09-14
Note: If one of the clock modes 0b, 6 or 7 is selected, the internal oscillator (OSC) should
be enabled by clearing bit GMODE:OSCPD. This allows connection of an external
cryst al to pins XTAL1-X TAL2. Th e outp ut signa l of the O SC can b e used for on e
serial channel, or for both serial channels (independent baud rate generators and
DPLLs). Moreover, XTAL1 alone can be used as input for an externally generated
clock.
The f irst two c olumns of Table 8 list all possible clock modes configured via bit field ’CM’
and bi t ’SSEL’ in register CCR0L.
For example, clock mode 6b is choosen by writing a ’6’ to register CCR0L.CM(2:0) and
by setting bit CCR0L.SSEL equal to ’1’. The following 4 columns (grouped as ’Clock
Sources’) specify the source of the int ernal clocks. Columns REC and TRM correspond
to the do m a in clock frequencies fREC and fTRM .
The columns grouped as ’Control Sources’ cover additional clock mode dependent
control signals like strobe signals (clock mode 1), clock gating signals (clock mode 4) or
synchronization signals (clock mode 5). The last column describes the function of signal
TxCLK which in some clock modes can be enabled as output signal monitoring the
effect iv e t ransmit cloc k or providing a time slot contro l signal (clock mode 5).
The fo llow ing is an example of how to rea d Table 8:
For clock mode 6b (row ’6b’) the TRM clock (column ’TRM’) is supplied by the baudrate
generator (BRG) output divided by 16 (source BRG/16). The BRG (column ’BRG’) is
derived from the internal oscillator which is suppl ied by pin XTAL1 and XTAL 2.
The REC clock (column ’REC’) is supplied by the internal DPLL which itse lf is supplied
by the baud rate genera t or (c olumn ’DPLL’) again.
Note: The REC cl ock is DPLL clock divided by 16.
If enabled by bit ’TOE’ in register CCR0L the resulting transmit clock can be monitored
via pin T xC LK (last colum n, row ’6b’).
PEB 20542
PEF 20542
Functional Overview
Data Sheet 51 2000-09-14
The clocking con cept is illustr ated in a block diag ram m an ner in the following figure:
Additional control signals are not illustrated (please refer to the detailed clock mode
descriptions below).
Figure 12 Cl oc k Supply Overvi ew
Oscillator
XTAL1
XTAL2
RxD
BRG
0b
6a/b
7a/b
2a/b
3a/b
DPLL 16:1
RxCLK
TxCLK
f
DPLL
f
BRG
f
BRG/16
f
RxCLK
f
TxCLK
f
DPLL
f
BRG
f
RxCLK
f
TRM
Transmitter Receiver
f
REC
TTL
or
CRYSTAL
f
DPLL
f
BRG
f
BRG/16
f
RxCLK
f
TxCLK
3a
7a 0b
3b
7b
2b
6b 1
5a 0a
2a
6a
4
5b
2a/b
3a
6a/b
7a
3b
7b 0a/b
1
5a/b
4
settings controlled by:
register CCR0, bit field 'CM'
selects the clock mode number
register CCR0, bit 'SSEL'
selects the additional a/b option
PEB 20542
PEF 20542
Functional Overview
Data Sheet 52 2000-09-14
Clock Modes
3.2.3.1 Clock Mode 0 (0a/0b)
Separate, extern ally generated receive and transmit c l ocks are su pplied to the SC C v ia
their respective pins. The transmit clock may be directly supplied by pin TxCLK
(clock mode 0a) or generated by the internal baud rate generator from the clock supplied
at pin XTAL1 (clock m ode 0b).
In clo ck mode 0b t he res ulti ng t rans mit cloc k ca n be drive n out to pin T xC LK if ena bled
via bit ’TOE’ in re gister CCR0L.
Figure 13 Clock Mode 0a /0b Configuration
RxCLK
CTS
, CxD, TCG
CD
, FSC, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
clock supply
1
2
RxCLK
CTS
, CxD, TCG
CD
, FSC, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
clock supply
1
or
(tx clock monitor output)
clock mode 0b
clock mode 0a
OSC
Ctrl.
Ctrl.
Ctrl.
Ctrl.
f
BRG
= f
OSC
/k
K=(n+1)/2
M
PEB 20542
PEF 20542
Functional Overview
Data Sheet 53 2000-09-14
3.2.3.2 Clock Mode 1
Externally generated RxCLK is supplied to both the receiver and transmitter. In addition,
a rece ive strobe can be c onnected via CD and a transmi t strobe via TxC LK pin. Thes e
strobe signals work on a per bit basis. This operating mode can be used in time division
multiplex applic at ions or for adjusting dis parate tra n s m it and receiv e data rates.
Note: In Extended Transparent Mode, the above mentioned strobe signals provide byte
synchronization (byte alignment).
This means that the strobe signal needs to be detected once only to transmit or
receive a complete byte.
Figure 14 Clock Mode 1 Configuration
RxCLK
CTS
, CxD, TCG
CD
, FSC, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
clock supply
1
clock mode 1
receive strobe
transmit strobe
RxD
CD
(rx strobe)
TxCLK
(tx strobe)
RxCLK
TxD
V
SS
(enables tra nsmit)
Note: In ex tende d t ran s par ent mo de the stro be s ignal s ne ed to be det ect ed o nce onl y to
tran smit or receive a complete byte. Thus byte alignment is provided in this mode.
Ctrl.
Ctrl.
PEB 20542
PEF 20542
Functional Overview
Data Sheet 54 2000-09-14
3.2.3.3 Clock Mode 2 (2a/2b)
The BR G is driven by an external cl ock (RxCLK pin) and delive rs a reference c lock for
the DPLL which is 16 times of the resulting DPLL output frequency which in turn supplies
the internal receive clock. Depending on the programming of register CCR0L bi t ’SSEL’,
the transmit clock will be either an extern al input clock signal provided at pin TxCLK in
clock mode 2a or the clock delivered by the BRG divided by 16 in clock mode 2b. In the
latter case , t he tra nsm it clo ck c an b e driv en ou t to pi n TxCL K if ena ble d via bit ’TOE’ in
register CCR0L.
Figure 15 Clock Mode 2a /2b Configuration
RxCLK
CTS
, CxD, TCG
CD
, FSC, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
clock supply
1
RxCLK
CTS
, CxD, TCG
CD
, FSC, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
clock supply
1
(tx clock monitor output)
clock mode 2b
clock mode 2a
BRG
DPLL 2
BRG
DPLL 16:1
Ctrl.
Ctrl.
Ctrl.
Ctrl.
PEB 20542
PEF 20542
Functional Overview
Data Sheet 55 2000-09-14
3.2.3.4 Clock Mode 3 (3a/3b)
The BRG is fed with an externally generated clock via pin RxCLK. Depending on the
value o f bit ’SSEL’ in register CCR0L the B RG deliver s either a referenc e clock for the
DPLL which is 16 times of the resulting DPLL output frequency (clock mode 3a) or
delivers directly the receive and transmit clock (clock mode 3b). In the first case the
DPLL output clock is used as receive an d transmit c lock.
Figure 16 Clock Mode 3a /3b Configuration
RxCLK
CTS
, CxD, TCG
CD
, FSC, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
clock supply
1
RxCLK
CTS
, CxD, TCG
CD
, FSC, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
clock supply
1
(tx clock monitor output)
clock mode 3b
clock mode 3a
BRG
DPLL
(tx clock monitor output)
BRG
Ctrl.
Ctrl.
Ctrl.
Ctrl.
PEB 20542
PEF 20542
Functional Overview
Data Sheet 56 2000-09-14
3.2.3.5 Clock Mode 4
Separate, externally generated receive and transmit clocks are supplied via pins RxCLK
and TxC LK. In a dditio n sep ara te rece ive a nd tr ansmit cloc k g ating si gnals are s up plied
via p ins RCG and T C G . T hese gatin g signals wo rk on a per bit basis .
Figure 17 Clock Mode 4 Configuration
RxCLK
CTS, CxD,
TCG
CD, FSC,
RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
clock supply
1
clock mode 4
transmit clock gate signal
receive clock gate signal
2
TxCLK
TCG
TxD
RxCLK
RCG
RxD
1 clock delay
Ctrl.
Ctrl.
PEB 20542
PEF 20542
Functional Overview
Data Sheet 57 2000-09-14
3.2.3.6 Clock Mode 5a (Time Slot Mode)
This operation mode has been designed for application in time-slot oriented PCM
systems.
Note : For correct ope ration NRZ data co ding/enco ding shou ld be used.
The receive and transmit clock are common for each channel and must be supplied
exter nally via p in RxCLK. The SCC re ceives and transm its only during fix ed time-sl ots.
Eith er one time-slot
–of progra m mable width (1 …512 bit, via TTSA and RTSA regist ers), and
–of programmable location with respect to the frame synchronization signal (via pin
FSC)
or up to 32 time-slots
–of const ant width (8 bit s) , and
–of programmable location with respect to the frame synchronization signal (via pin
FSC)
can be selected.
The time-slot locations can be programmed independently for receive and transmit
direct ion via TTSA / R TSA and PCM T X/ PCMRX registers.
Depen ding on the va lue prog rammed v ia th ose regi sters, the rec eive/tr ansm it time -slot
starts with a delay of 1 (minimum delay) up to 1024 clock periods following the frame
synchronization signal.
Figure 18 shows how to select a time-slot of programmable width and location and
Figure 19 shows how to select one or m ore time-slot s of 8-bit width.
If bit ’TOE’ in regi ster CCR0L is set, the selected transmit time-slot(s) is(are) indicated at
an o ut put s t at us signal via pin Tx C LK, which is driven to ‘low’ during the acti ve tran sm it
window.
Bit ’TSCM’ in register CCR1H determines whether the internal offset counters are
continuously running even if no synchronization pulse is detected at FSC signal or
stopping at their maximum value.
In the con t inuous case t he repetition rate of off s et co unt er operation is 1024 transmit or
receive clocks respectively. An FSC pulse detected earlier resets the counters and starts
operat ion again.
In the non-continuous case the time slot assigner offset counter is stopped after the
count er reached its maximum value and is started again if an F SC pulse is detec t ed.
PEB 20542
PEF 20542
Functional Overview
Data Sheet 58 2000-09-14
Figure 18 Selecting one time-slot of programmable delay and width
70
0
TTSN TCSTCC 0
RTSN RCSRCC 0
TTSA0..3: Transmit Time Slot Assignment Register
RTSA0..3: Receive Time Slot Assignment Register
TEPC M = '0' : TPCM Mask Di sabled
REPCM = '0': RPCM Mask Disabled
TS de lay (trans mi t ):
1 + TTSN*8 + TCS
(1...1024)
TS de lay (rec ei ve ) :
1 + RTSN*8 + RCS
(1...1024)
TS width (transmit):
TCC
(1...512 clocks)
TS width (receive):
RCC
(1..512)
FSC
RxCLK
active
time slot
TTSA1 7TTSA0 07 07
TTSA3 TTSA2
700RTSA1 7RTSA0 07 07
RTSA3 RTSA2
PEB 20542
PEF 20542
Functional Overview
Data Sheet 59 2000-09-14
Note: If time-slot 0 is to be selected, the DELAY has to be as long as the PCM frame
itself to achieve synchronization (at least for the 2nd and subsequent PCM
frames ): DELAY = PCM fra me lengt h = 1 + x TSN*8 + xC S. xTSN and xC S have
to be se t appropriately.
Exam ple: Time-slot 0 in E1 (2.048 Mbit/s) system has to be se lec ted.
PCM frame length is 256 clocks. 256 = 1+ xTSN*8 + xCS. => xTSN = 31, xCS = 7.
Note: In extended transparent mode the width xCC of the selected time-slot has to be
n´8 bit because of character synchronization (byte alignment). In all other modes
the width can be u s ed t o define windows down to a minimu m length of one bit .
PEB 20542
PEF 20542
Functional Overview
Data Sheet 60 2000-09-14
Figure 19 Selecting one or more time-slot s of 8-bit width
The common transmit and receive clock is supplied at pin RxCLK and the common frame
synchronisation signal at pin FSC. The "strobe signals" for active time slots are
generat ed internally by the time slot assigner b lock (TSA) in dependent in tr ansmit and
receive direction.
When t he tran sm it and rec e ive PC M ma sks are ena bled, bit field s ’TCC’ and ’RCC’ are
ignor ed because of the consta nt 8 -bit t i m e s l ot width.
TS delay (transmit):
1 + TTSN*8 + TCS
(1..1024)
TS delay (receive):
1 + RTSN*8 + RCS
(1..1024)
31 24 23 16 15 8 7 0
PCMTX0..3: Transmit PCM Mask Register
...
1
3
1
17
TS0 TS1 TS2 TS3 TS4 TS5 TS16 TS17
8 bit
REPCM = '1': TPCM Mask Enabled
31 24 23 16 15 8 7 0
PCMRX0..3: Rec eive PCM Mask Register
FSC
RxCLK
active
time slot
700
TTSN TCSTCC 1
TTSA0..3: Transmit Time Slot Assignment Register
TEPCM = '1': TPCM Mask Enabled
TTSA1 7TTSA0 07 07
TTSA3 TTSA2
PCMTX1 PCMTX0
PCMTX3 PCMTX2
RTSN RCS
RCC 1
RTSA0..3: Receive Time Slot As signment Register
70
0RTSA1 7RTSA0 07 07
RTSA3 RTSA2
PCMRX1 PCMRX0
PCMRX3 PCMRX2
PEB 20542
PEF 20542
Functional Overview
Data Sheet 61 2000-09-14
Figure 20 Cloc k Mode 5a Confi guration
Note: The transmit time slot delay and width is programmable via bit fields ’TTSN’, ’TCS’
and ’TCC’ in registers TTSA0..TTSA3.
The receive time slot delay and width is programmable via bit fields ’RTSN’, ’RCS’
and ’RCC’ in registers RTSA0..RTSA3.
RxCLK
CTS
, CxD, TCG
CD,
FSC
, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
clock supply
1
clo ck mode 5a
time slot indicator signal
Time Slot
Assigner
(TSA)
RxCLK
FSC
internal
tx strobe
TS delay TS width
TxCLK
TS-Control
TxD
internal
rx strobe
TS delay TS width
RxD
012n... 0n 1
Ctrl.
Ctrl.
PEB 20542
PEF 20542
Functional Overview
Data Sheet 62 2000-09-14
The following figures provide a more detailed description of the TSA internal counter
operation and exceptional cases:
Figure 21 Clock Mode 5a "Continuous Mode"
...
FSC
RxCLK,
TxCLK
active
time s lo t
load offset
ocnt:
ocnt := 1024 - TSdelay ocnt := 1024 ocnt := 0
load offset
ocnt:
ocnt := 1024 - TSdelay
load duration
dcnt:
ocnt := N,
N < TSdelay
dcnt := 0 dcnt := TSwidth - 1
dcnt := 0 dcnt := 255
active
tim e slots according
PCMTX/PCMRX
Mode TEPCM/REPCM = '0'
Mode TEPCM/REPCM = '1'
Exceptions:
a) F SC pulse period > 1024:
T h e o ffse t c o u n te r ocnt will a u to ma ic a lly re s ta rt a fte r 1 0 2 4 c lo c k cycles
and w ill b e re s ta rte d a g a in b y th e la te F SC p u ls e !
b) F SC pulse period < (TSdelay + TSwidth), i.e . F SC pu ls e de te c te d wh ile d u ra tio n c o u n te r s till a c tiv e :
T h e o ffse t c o u n te r ocnt will a u to ma ic a lly re s ta rt,
b u t du r a tio n c o u n te r dcnt continues operation (transm it/receive in active tim e slots)
clock mode 5a
bit TS CM='0' (continuou s mode )
ocnt
start
TSdelay + 1024 clock cycles
ocnt
restart
FSC
< 1024 clock cycles
FSC
dcnt
start
TSdelay = 1 + xTS N*8 + xCS
(1...1024)
ocnt
restart
ocnt
restart
ocnt
start
PEB 20542
PEF 20542
Functional Overview
Data Sheet 63 2000-09-14
Each fr ame sync pulse start s the internal offset cou nter with (10 24 - TSde lay) wher eas
TSdelay is the configur ed v alue definin g t he s t art pos ition. Whenever the offset coun t er
reaches its max imum value 1024, it trigg ers the duration counter to start ope rat ion.
If continuous mode is selected (bit CCR1H.TSCM=’0’) the offset counter continues
starting with value 0 until another frame sync puls is detected or again the maximum
value 10 24 is reached.
Once the duration counter is triggered it runs out independently from the offset counter,
i.e. an active time slot period may overlap with the next frame beginning (frame sync
even t, r efer to excepti on b) in Figure 21).
Figure 22 Clock Mode 5a "Non Continuous Mode"
If non-continuous mode is selected (bit CCR1H.TSCM=’1’) the offset counter is stopped
on its maximum value 1024 until another frame sync puls is detected. This allows frame
sync periods greater than 1024 clock cycles, but the accesible part is limited by the range
of TSdelay value (1..1024) plus TSwidth (1..512) or plus 256 clock cycles if the PCM
mask is selected.
ocnt := TSdelay - 1
Exceptions:
a) FSC pulse period > 1024:
The offset counter ocnt will stop on its maximum value 1024, which triggers the duration counter dcnt
and will be restarted again by the 'late' FSC pulse!
clock mode 5a
bit TSC M ='1' (non continuous mode)
ocnt
start
TSdelay + 1024 clock cycles
ocnt
stop ocnt
start
FSC
A different behavior to clock mode 5a continous mode is given only in
case of Exception a).
PEB 20542
PEF 20542
Functional Overview
Data Sheet 64 2000-09-14
3.2.3.7 Clock Mode 5b (Octet Sync Mode)
This operation mode has been designed for applications using Octet Synchronous PPP.
It is based on clock mode 5a, but only 8-bit (octet) wide time slot operation is supported,
i.e. bits TTSA1.TEPCM and RTSA1.REPCM must b e s et to ’1’. Clock mode 5b provides
octet alignment to time slots if Octet Synchronous PPP protocol mode or extended
trans parent mode is s e lected.
Note : For correct ope ration NRZ data co ding/enco ding shou ld be used.
The rec eive an d trans mit cl oc ks are se par ate and mus t be su pplied at pins Rx CLK an d
TxCLK. The SCC receives and transmits only during fixed octet wide time-slots of
programmable location with respect to the octet synchronization signals (via pins OSR
and OST)
The time-slot locations can be programmed independently for receive and transmit
direction via registers TTSA0..TTSA3 / RTSA0..RTSA3 and PCMTX0..PCMTX3 /
PCMRX0..PCMRX3.
Figure 23 s how s how to sele ct one or more octet wide time-s lot s.
Bit ’TSCM’ in register CCR1H determines whether the internal counters are continuously
running even if no synchronization pulse is detected at OST/OSR signals or stopping at
their maximum value.
In the continuous case the repetition rate of operation is 1024 transmit or receive clocks
respectively. An OST/OSR pulse detected earlier resets the corresponding offset
counter and starts operation again .
In the non-continuous case the transmit/receive time slot assigner offset counter is
stopped after the counter reached its maximum value and is started again if an OST/
OSR pulse is de t e c ted.
PEB 20542
PEF 20542
Functional Overview
Data Sheet 65 2000-09-14
Figure 23 Selecting one or more octet wide time-slots
The transmit and receive clocks are supplied at pins RxCLK and TxCLK. The Octet
synchronisation signals are supplied at pins OSR and OST. The "strobe signals" for
active time slots are generated internally by the time slot assigner blocks (TSA)
indep endent in tra n s m it and receive direction.
Bit fields ’TCC’ and ’RCC’ are ignored becaus e of the const ant 8-bit ti me slot wid th.
TS delay (transmit):
1 + TTSN*8 + TCS
(1...1024)
TS delay (receive):
1 + RTSN*8 + RCS
(1...1024)
...
TS0 TS1 TS2 TS3 TS4 TS5 TS16 TS17
8 bit
OSR
OST
RxCLK
TxCLK
active
time slot
31 24 23 16 15 8 7 0
PCMTX0..3: Transmit PCM Mask Register
1
3
1
17
700
TTSN TCS
TCC 1
TTSA0..3: Transmit Time Slot Assignment Register
TEPCM = '1': TPCM Mask Enabled
TTSA1 7TTSA0 0
707
TTSA3 TTSA2
PCMTX1 PCMTX0
PCMTX3 PCMTX2
REPCM = '1': TPCM Mask Enabled
31 24 23 16 15 8 7 0
PCM R X0. . 3: R eceive PCM Mask Reg i st er
RTSN RCSRCC 1
RTSA0..3: Receive Time Slot Assignment Register
700RTSA1 7RTSA0 07 07
RTSA3 RTSA2
PCMRX1 PCMRX0
PCMRX3 PCMRX2
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Data Sheet 66 2000-09-14
Figure 24 Clock Mode 5b Configuration
Note: The transmit time slot delay and width is programmable via bit fields ’TTSN’, ’TCS’
and ’TCC’ in registers TTSA0..TTSA3.
The receive time slot delay and width is programmable via bit fields ’RTSN’, ’RCS’
and ’RCC’ in registers RTSA0..RTSA3.
RxCLK
CTS, CxD, TCG,
OST
CD, FSC, RCG,
OSR
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
clock supply
1
clock mode 5b
Time Slot
Assigner
(RTSA)
RxCLK
TxCLK
OSR
OST
internal
tx strobe
TS delay TS width
TxD
internal
rx strobe
TS delay TS width
RxD
012n... 0n
Ctrl.
Ctrl.
Time Slot
Assigner
(TTSA)
2
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Functional Overview
Data Sheet 67 2000-09-14
3.2.3.8 Clock Mode 6 (6a/6b)
This cl ock mode is i dentical t o clock mode 2a/2b excep t that the clock sourc e of the BRG
is supplied at pin XTAL1.
The BRG is driv en by the int ernal osci llat or and deliv ers a referenc e clock for t he DPLL
which is 16 times the resulting DPLL output frequency which in turn supplies the internal
receive clock. Depending on the programming of register CCR0L bit ’SSEL’, the transmit
clock will be eithe r an external input clock signal pro vided at pin TxCLK in clock mode
6a or the clock deliv ered by the BRG divided by 16 in clock m ode 6b. In the latter cas e,
the transmit clock can be driven out to pin TxCLK if enabled via bit ’TOE’ in register
CCR0L.
Figure 25 Clock Mode 6a /6b Configuration
RxCLK
CTS
, CxD, TCG
CD
, FSC, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
clock supply
1
RxCLK
CTS
, CxD, TCG
CD
, FSC, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
(tx clock monitor output)
clock mode 6b
clock mode 6a
BRG
DPLL
BRG
DPLL 16:1
or
V
SS
V
SS
or
OSC
OSC
Ctrl.
Ctrl.
Ctrl.
Ctrl.
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Functional Overview
Data Sheet 68 2000-09-14
3.2.3.9 Clock Mode 7 (7a/7b)
This cl ock mode is i dentical t o clock mode 3a/3b excep t that the clock sourc e of the BRG
is supplied at pin XTAL1.
The BRG is driven by the internal oscillator. Depending on the value of bit ’SSEL’ in
register CCR0L the BRG delivers either a reference clock for the DPLL which is 16 times
the resulting DPLL output frequency (clock mode 7a) or delivers directly the receive and
transmit clock (clock mode 7b). In clock mode 7a the DPLL output clocks receive and
transmit data.
Figure 26 Clock Mode 7a /7b Configuration
RxCLK
CTS
, CxD, TCG
CD
, FSC, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
RxCLK
CTS
, CxD, TCG
CD
, FSC, RCG
TxCLK
RTS
RxD
TxD
XTAL1
XTAL2
(tx clock monitor output)
clock mode 7b
clock mode 7a
BRG
DPLL (tx clock monitor output)
BRG
or
V
SS
V
SS
OSC
OSC
or
Ctrl.
Ctrl.
Ctrl.
Ctrl.
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Functional Overview
Data Sheet 69 2000-09-14
3.2.4 Baud Rate Generator (BRG)
Each serial channel provides a baud rate generator (BRG) whose division factor is
cont rolled by re gist ers BRRL and BRRH. Whether the BRG is in the clocking path or not
depe nds on the selec ted clock m o de.
The clock division factor k is calculated by:
3.2.5 Clock Reco very (DPLL)
The SC C offers the adva ntage of recov ering th e received c lock from the rece ived data
by means of internal DPLL circuitry, thus eliminating the need to transfer additional clock
info rmation v ia a sep arate serial c lock lin e. For this pu rpose, the DP LL is s upplied with
a ‘r eference cloc k’ from the BR G which is 16 times the e xpected data clock rat e (clock
mode 2, 3a, 6, 7a). The transmit clock may be obtained by dividing the output of the BRG
by a constant fa ctor of 16 (clock mode 2b, 6b; bit ’SSEL’ in regis ter CCR0L set) or also
directly from the DPLL (clock mode 3a, 7a).
The main task of the DPLL is to derive a receive clock and to adjust its phase to the
inco m ing data str eam in order to enable optimal bit sam pling.
The m echan ism for clock recove ry depe nds on the s elected data encod ing (see “Data
Encoding” on Page 75).
The following functions have been implemented to facilitate a fast and reliable
synchronization:
Table 9 BRRL/BRRH Register and Bit-Fields
Register Bit-Fields
Offset Pos. Name Default Description
BRRL
38H/88H
5..0 BRN 0 Baud Rate Factor N
range N = 0.. 63
BRRH
39H/89H
11.. 8 BRM 0 Baud Rate Factor M,
range M = 0.. 15
kN1+()2M
´=
fBRG fin k¤=
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Data Sheet 70 2000-09-14
Interference Rejection and Spike Filtering
Two or more edges in the same directional data stream within a time period of 16
reference clocks are considered to be interference and consequently no additional clock
adjust m ent is perfo rm ed.
Phase Adjustment (PA)
Referring to Figure 27, Figure 28 and Figure 29, in the case where an edge appears in
the data stream within the PA fields of the time window, the phase will be adjusted by 1/
16 of the dat a.
Phase Shift (PS) (NRZ, NRZI only)
Referring to Figure 27 in the case where an edge appears in the data stream within the
PS field of the time window, a second sampling of the bit is forced and the phase is
shifted by 180 degrees.
Note : Edges in all other parts of th e time windo w will be ignored.
This operation facilitates a fast and reliable synchronization for most common
appli ca tions. Abov e all, it implies a very fast s y nchronizati on becaus e of t he phase sh ift
featur e: one edge o n the receiv ed data s tream is enou gh for the DPL L to synchro nize,
thereby eliminating the need for synchronization patterns, sometimes called preambles.
However, in case of extremely high jitter of the incoming data stream the reliability of the
clock recovery cannot be guaranteed.
The SCC offers the option to disable the Phase Shift function for NRZ and NRZI
encodings by setting bit ’PSD’ in register CCR0L to ’1’. In this case, the PA fields are
extended as shown in Figure 28.
Now, the DPLL is more insensitive to high jitter amplitudes but needs more time to reach
the optimal sampling position. To ensure correct data sampling, preambles should
precede the da ta information.
Figure 27, Figure 28 and Figure 29 explain the D PL L algorit hms use d fo r the d iffer ent
data encodings.
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Data Sheet 71 2000-09-14
Figure 27 DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Enable d)
Figure 28 DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Disabled)
012345678910 11 12 13 14 15
0 +PA PS -PA 0
Bit Cell
DPLL
Count
Output
DPLL
Correction
ITD01806
0123456789101112131415
0+PA -PA 0
Bit Cell
DPLL
Count
Output
DPLL
Correction
ITD04820
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Data Sheet 72 2000-09-14
Figure 29 DPLL Algorithm fo r FM0, FM1 and Manches ter Enc oding
To supervise correct function when using bi-phase encoding, a status flag and a
mask able inte rrupt inform about synchronous/ as ynchronous sta te of t he DPLL.
3.2.6 SCC Timer Operation
Each SCC provides a general purpose timer e.g. to support protocol functions. In all
operating modes the timer is clocked by the effective transmit clock. In clock mode 5
(time-slot oriented mode) the clock source for the timer can be optionally switched to the
frame sy nc c l oc k (input pin FSC) by s et ting bit ’SRC’ in register TIMR3.
The t imer i s co nt rolled b y t he CP U v ia a cce ss to reg iste rs CMDRL and TIMR0..TIMR3.
The timer can be started any time by setting bit ’STI’ in register CMDRL. After th e tim e r
has ex pired it generates a timer inte rrupt (’TIN’).
With bit field ’CNT(2..0)’ i n regist er TIMR3 the number of automatic timer restarts can be
programmed. If the maximum value ’111’ is entered, a timer interrupt is generated
periodically, with the time period determined by bit field ’TVALUE’ (registers
TIMR0..TIMR3).
The timer can be stopped any time by setting bit ’TRES’ in register CMDRL to ’1’.
In HDLC Automode the timer is used internally for autonomous protocol functions (refer
to the chapter “Automode” on Page 87). If this operating mode is selected, bit ’TMD’ in
register TIMR3 must be se t to ’1’.
01 2 3 4 5 6 7 8 9 101112131415
0 +PA - ignore - -PA 0
Bit Cell (FM Coding)
DPLL
Count
Clock
Transmit
Correction
ITD01807
76543210
Bit Cell (M anchester Coding)
+PA - ignore -
Receive
Clock
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Data Sheet 73 2000-09-14
3.2.7 SCC Serial B us Config uration Mo de
Beside the point-to -point conf iguration, the SCC effectiv ely supports point-to -multipoint
(pt-mpt, or bus) configuratio ns by means of internal idle and collision detection/collision
resolution methods.
In a pt-mpt configuration, comprising a central station (master) and several peripheral
stations (slaves), or in a multimaster configuration, data transmission can be initiated by
each station over a common transmit line (bus). In case more than one station attempts
to transmit data simultaneously (collision), the bus has to be assigned to only one
station. A collision -resolution pro cedure is implem ented in the SCC . Bus assignment is
based on a priority mechanism with rotating priorities. This allows each station a bus
access within a predetermined maximum time delay (deterministic CSMA/CD), no
matt er how many transmit ters are co nnected to the serial bus.
Prere quisite s f o r bus operat ion are:
•NRZ encodi n g
•‘OR’ing of data from every transmitter on the bus (this can be realized as a wired-OR,
using the TxD open drain ca pa bility)
•Feedback of bus information (CxD input).
The bus c onf iguration is se lected via bitfield SC(2:0) in register CCR0H.
Note: Central clock supply for each station is not necessary if both the receive and
transmit clock is re covered by t he DPLL (clock mod es 3a, 7a). This min imizes t he
phase shift between the individual transmi t clocks.
The bus configuration mode operates independently of the clock mode, e.g. also
together with clock mode 1 (receive and transmit strobe operation).
3.2.8 Serial Bus Acce ss Proc edure
The idle state of th e bus is ident ified by eight or more con secutive ‘1’s. When a device
starts trans mis sion of a frame , the bu s is rec ogniz ed to be bu sy by the oth er devi ce s at
the moment the first ‘zero’ is transmitted (e.g. first ‘zero’ of the opening flag in
HDLC mode).
After the frame has been transmitted, the bus becomes available again (idle).
Note : If t he bus is occ upied by other transm itters a nd/or t here is no tra nsmit re quest in
the SCC, logical ‘1’ will be continuously transmitted on TxD.
3.2.9 Serial Bus Collisions and Recovery
During the transmission, the data transmitted on TxD is compared with the data on CxD.
In case of a mismatch (‘1’ sent and ‘0’ detected, or vice versa) data transmission is
immedi ately aborted, and idle (logical ‘1’) is transmitted.
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Data Sheet 74 2000-09-14
HDLC/SDLC: Transmission will be initiated again by the SCC as soon as possible if the
first part of the frame is still present in the SCC transmit FIFO. If not, an XMR interrupt is
generated.
Since a ‘zero’ (‘low’) on the bus prevails over a ‘1’ (high impedance) if a wired-OR
connection is implemented, and since the address fields of the HDLC frames sent by
different station s norma lly differ from one an other, the fact that a collision has occurre d
will be detected prior to or at the latest within the address field. The frame of the
transmitter with the highest temporary priority (determined by the address field) is not
affected and is transmitted successfully. All other stations cease transmission
immediately and return to bus monitoring state.
Note: If a wired-OR connection has been realized by an external pull-up resistor without
decoupling, the data output (TxD) can be used as an open drain output and
connected direc tly to the CxD in put .
For correct identification as to which frame is aborted and thus has to be repeated
after an XMR interrupt has occurred, the contents of SCC transmit FIFO have to
be unique, i.e. SCC transmit FIFO should not contain data of more than one frame.
For this purpose new data may be provided to the transmit FIFO only after ’ALLS’
interrupt status is det ec t ed.
3.2.10 Serial Bus Access Priori ty Scheme
To ensure that all competing stations are given a fair access to the transmission medium,
a two-stage bus ac c e s s priority scheme is supported by SEROCCO- D :
Once a station has successfully completed the transmission of a frame, it is given a lower
level of priority. This priority mechanism is b ased on the req uire m ent tha t a station may
attempt transmitting only when a determined number of consecutive ‘1’s are detect ed on
the bus.
Norm ally, a t ran smis sion c an s tart whe n eight con sec utive ‘1’s on th e bus are de tec ted
(through pin CxD). When an HDLC frame has been successfully transmitted, the internal
priority class is decreased. Thus, in order for the same station to be able to transmit
anothe r frame, ten c onsecutiv e ‘1’s on the bu s must be d etected. T his guarant ees that
the transmission requests of other stations are satisfied before the same station is
allowed a second bus access. When ten consecutive ‘1’s have been detected,
transmission is allowed again and the priority class (of all stations) is increased (to eight
‘1’s).
Inside a priority class, the order of transmission (individual priority) is based on the HDLC
address, as explained in the preceding paragraph. Thus, when a collision occurs, it is
always the station transmitting the only ‘zero’ (i.e. all other stations transmit a ‘one’) in a
bit position of the address field that wins, all other stations cease transmission
immediately.
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Functional Overview
Data Sheet 75 2000-09-14
3.2.11 Serial Bus Configur ation Timing Modes
If a bus con figurati on has been selected, the SCC pr ovides tw o timing mode s, differin g
in the time interval between sending data and evaluation of the transmitted data for
collision detection.
•Timing mode 1 (CCR0H:SC(2:0) = ‘001’)
Data is output with the rising edge of the transmit clock via the TxD pin, and evaluated
1/2 a clock period later at the C xD pin with the falling clock edge.
•Timing mode 2 (CCR0H:SC(2:0) = ‘011’)
Data is output with the falling clock edge and evaluated with the next falling clock
edge. Thus o ne complete clock peri od is avail able betw een data output and collisio n
detection.
3.2.12 Functions Of Signal RTS in HDLC Mode
In clock modes 0 and 1, the RTS output can be programmed via register CCR1 (SOC
bits) to be active when data (frame or character) is being transmitted. This signal is
delayed by one clock period with respect to the data output TxD, and marks all data bits
that could be transmitted without collision (see Figure 30). In this way a configuration
may be implemented in which the bus access is resolved on a local basis (collision bus)
and where the data are sent one clock period la ter on a separate transmission line.
Figure 30 Request -to-Send in Bus Operation
Note: For details on the functions of the RTS pin refer to “Modem Control Signals
(RTS, CTS, CD)” on Page 78.
3.2.13 Data Encoding
The SCC supp or ts the fo ll owing coding schemes for serial da ta :
–Non-Return-To-Zero (NRZ)
–Non-Return-To-Zero-Inverted (NRZI)
–FM0 (a lso known as Bi-Phase Space)
–FM1 (a lso known as Bi-Phase M ark )
ITT00242
Collision
TxD
CxD
RTS
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Data Sheet 76 2000-09-14
–Manchester (also known as Bi-Phase)
The desired line coding scheme can be selected via bit field ’SC(2:0)’ in register CCR0H.
3.2.13.1 NRZ and NRZI Encoding
NRZ: The signal level corresponds to the value of the data bit. By programming bit ’DIV’
(CCR1L register), the SCC may invert the transmission and reception of data.
NRZI: A logical ‘0’ is indicated by a transition and a logical ‘1’ by no transition at the
begin ning of the bit cell.
Figure 31 NRZ and NRZI Data Encoding
3.2.13.2 FM0 and FM1 Encoding
FM0: An edge occurs at the beginning of every bit cell. A logical ‘0’ has an additional
edge in the center of the bit cell, whereas a logical ‘1’ has none. The transmit clock
precedes the rec eive cloc k by 90°.
FM1: An edge occurs at the beginning of every bit cell. A logical ‘1’ has an additional
edge in th e center of the bi t cel l , a lo gical ‘0’ has none. The transmit clock precedes the
receive clock by 90°.
0110010
ITD05313
Transmit/
Receive Clock
NRZ
NRZI
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Figure 32 FM0 and FM1 Data Enc oding
3.2.13.3 Manchester Encoding
Manchester: In the firs t half of the bit cell , the physi cal signal le vel corr esponds to the
logical value of the data bit. At the center of the bit cell this level is inverted. The transmit
clock precedes the receive clock by 90°. The bit cell is shifted by 180° in comparison with
FM coding.
Figure 33 Manchester Data Encoding
110010
ITD01809
Receive
Clock
FM0
FM1
Transmit
Clock
110010
ITD01810
Receive
Clock
Manchester
Transmit
Clock
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Functional Overview
Data Sheet 78 2000-09-14
3.2.14 Modem Control Signals (RTS, CTS, CD)
3.2.14.1 RTS/CTS Handshaking
The SCC provides two pins (RTS, CTS) per serial channel supporting the standard
request-to-send modem handshakin g procedure f or transmiss ion control.
A transmit request will be indicated by outputting logical ‘0’ on the request-to-send output
(RTS). It is also possible to control the RTS output by software. After having received the
permission to transmit (CTS) the SCC sta r ts dat a tra nsmiss i on.
In the case where permission to transmit is withdrawn in the course of transmission, the
frame is aborte d and IDL E is sent . After t ransmissio n is ena bled again b y re-activa tion
of CTS, and if the beginning of the frame is still available in the SCC, the frame will b e
re-transmitted (self-recove ry). However, if the permission to transmit is withdraw n after
the data available in the shadow part of the SCC transmit FIFO has been completely
transmitted and the pool is released, the transmitter and the SCC transmit FIFO are
reset, the RTS output is deac t iv at ed and an interr upt (XM R ) is generated.
Note: For correct identification as to which frame is aborted and thus has to be repeated
after an XMR interrupt has occurred, the contents of SCC transmit FIFO have to
be unique, i.e. SCC transmit FIFO should not contain data of more than one frame,
which could happen if transmission of a new frame is started by providing new
data to the transmitter too early. For this purpose the ’All Sent’ interrupt
(ISR1.ALLS ) ha s to be wai ted for before pro viding new transmit da ta.
Note: In the case where permission to transmit is not required, the CTS input can be
connected directly to VSS and/or bit ’FCTS’ (register CCR1H) may be set to ’1’.
Additionally, any transition on the CTS input pin, sampled with the transmit clock, will
generate an interrupt indicated via register ISR1, if this function is enabled by setting the
’CSC’ bit in register IMR1 to ’0’.
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Data Sheet 79 2000-09-14
Figure 34 RTS/CTS Hand shaking
Beyond this standard RTS function, signifying a transmission request of a frame
(Request To Send), in HDLC mode the RTS output may be programmed for a special
function via SOC1, SOC0 bits in the CCR1L register. This is only av ailable if th e serial
channel is operating in a bus configuration mode in clock mo de 0 or 1.
•If SOC1, SOC0 bits are set to ‘11’, the RTS output is active (= low) during the
reception of a fra m e.
•If SOC1, SOC0 bits are set to ‘10’, the RTS outpu t function is disab led and the RTS
pin remains always high.
3.2.14.2 Carrier Detect (CD) Receiver Control
Similar to the RTS/CTS control for the transmitter, the SCC supports the carrier dete ct
modem control function for the serial receiver if the Carrier Detect Auto Start (CAS)
function is programmed by setting the ’CAS’ bit in register CCR1H. This function is
always available in clock modes 0, 2, 3, 6, 7 via the CD pin. In clock mode 1 the CD
function is not supported. See Table 8 for an overview .
If the CAS function is selected, the receiver is enabled and data reception is started when
the CD input is detected to be high. If CD input is set to ‘low’, reception of the current
character (byte) is still completed.
3.2.15 Local Loop Te st Mode
To prov ide fast and efficient testing, t he SCC can be operated in a test mod e by setting
the ’TLP’ bit in register CCR2L. The on-chip serial data input and output signals (TxD,
ITT00244
Sampling
CTS
TxCLK
TxD
RTS
~
~~
~~
~~
~
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Data Sheet 80 2000-09-14
RxD) are connected, generating a local loopback. As a result, the user can perform a
self-tes t of the SC C.
Figure 35 SCC Test Loop
Transmit data can be disconnected from pin TxD by setting bit TLPO in register CCR2L.
Note: A sufficient clock mode must be used for test loop operation such that receiver and
transmitter operate with the same frequencies depending on the clock supply (e.g.
clock mode 2b or 6b).
3.3 Microprocessor Interface
The communication between the CPU and SEROCCO-D is done via a set of directly
acce ss ible registers. The inter fa ce may be co nf igured as Intel or M ot orola type (r ef er t o
description of pin ’BM’) with a selectable data bus width of 8 or 16 bit (refer to description
of pin ’WIDTH’).
The CPU transfers data to/from SEROCCO-D (via 64 byte deep FIFOs per direction and
channel), sets the operating modes, controls function sequences, and gets status
information by writing or reading control/status re gis ters.
All accesses can be done as byte or word accesses if enabled. If 16-bit bus width is
selec ted, acc ess to the lower/u pper part of the dat a bus is de termine d by signals BHE/
BLE as shown in Table 10 (Intel mode) or by the upper and lower data strobe signals
UDS/LDS as sh own in Table 11 (Motorola mode).
Table 10 Data Bus A c cess 16-bit Intel Mode
BHE BLE Register Access Data Pins Used
0 0 Word ac c es s (16 bit ) D(15: 0)
0 1 Byte acc es s (8 bit), odd add res s D(15: 8)
SCC transmit
logic
SCC receive
logic
TLP='0'
TLP='1'
RxD
TxD
TLPO='0'
TLPO='1'
IDLE '1'
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Data Sheet 81 2000-09-14
Each of the two serial channels of SEROCCO-D is controlled via an identical, but
completely independent register set (Channel A and B). Global functions that are
comm on to or independent from the tw o serial channels are locate d in global reg ist ers.
3.4 Internal DMA Controller
3.4.1 Arbitration for Bu s Control
Every time SEROCCO-D needs to access the bus in order to DMA transfer receive data
from the RFIFO to h os t me mory or transmit data from host memory to the XF IFO, it h a s
to request the bus arbiter for the bus mastership. This is achieved by asserting the open-
drain BREQ signal to low. When SERO C C O -D s amples the bus grant (BGNT ) active, it
1 0 Byte acc es s (8 bit), even address D(7: 0)
1 1 no data transfer -
Table 11 Data Bu s Access 16-bit Moto ro la Mode
UDS LDS Register Access Data Pins Used
0 0 Word ac c es s (16 bit ) D(15: 0)
0 1 Byte acc es s (8 bit), even address D(15: 8)
1 0 Byte access (8 bit), odd address D(7:0)
1 1 no data transfer -
Table 10 Data Bus A c cess 16-bit Intel Mode
BHE BLE Register Access Data Pins Used
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Data Sheet 82 2000-09-14
acknowledges bus owne rship by asserting the bus grant acknowledge (B GACK) line to
low.
Figure 36 SEROCCO-D requests and gets the bus
The BREQ si gnal becomes inactive one clock later and DMA transfer cycl es star t.
SEROCCO-D holds the BGACK line low for the time it performs DMA read or write cycles
on the bus.
3.4.2 Performing DMA Transfers
The maximum number of bus transfers in sequenc e is 16 (word transfers in 16- bit bus
modes) or 32 (byte transfers in 8-bit bus modes). Each DMA initiated read and write
cycle is performed in four clock cycles, see Figure 37 with numbering of the cycle
sectio ns i n Intel (T1/T2) an d Motorola (S0..S7) fashio n.
Figure 37 Un-interrupted Series of 32 DMA Bus Cycles
CLK
BREQ
BGNT
BGACK
Start
By te/ Word Trans f er
CLK
BGACK
Address
Strobe
Data
Strobe 1
st
bus cycle 2
nd
bus cycle
T1 T2 T1 T2
S0 S1 S2 S3 S4 S5 S6 S7
T2
32
nd
bus cycle
S0 S1 S2 S3 S4 S5 S6 S7 S5 S6 S7
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Data Sheet 83 2000-09-14
3.4.3 Bu s P r eemption
Figure 38 Bus Preemption and Re-gain of Bus Control
3.4. 4 E nding DM A Transfers
Figure 39 SEROCCO-D requests and gets the bus
3.5 Interru pt Architecture
For cer tain events in SER OCCO-D a n interrupt ca n be generat ed, reques ting the CPU
to read status information from SEROCCO-D. The interrupt line INT/INT is assert ed with
the output characteristics programmed in bit field ’IPC(1..0)’ in register “GMODE” on
Page 127 (open drain/push pull, active low/high).
CLK
BREQ
BGNT
BGACK
MISTRAL
requests the bus
again
Ex terna l arbi ter
interrupts
MISTRAL
DMA transfers
MISTRAL
completed curr ent
read/write cycle
as serted by
arbiter assert ed by
MISTRAL
CLK
BREQ
BGNT
BGACK Last Byte/Word
Transfer completed
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Data Sheet 84 2000-09-14
Since only one interrupt request output is provided, the cause of an interrupt must be
determined by the CPU by reading the interrupt status registers (GSTAR, ISR0, ISR1,
ISR2, DISR, GPIS).
Figure 40 Interrupt Status Registers
Each interrupt indication of registers ISR0, ISR1, ISR2, DISR and GPIS can be
selectively unmasked by resetting the corresponding bit in the corresponding mask
registers IMR0, IMR1, IMR2, DIMR and GPIM. Use of these registers depends on the
selected serial mode.
If bit ’VIS’ in regist er CCR0L is set to ’1’, masked interrupt status bits are visible in the
interr upt statu s regist ers ISR0..ISR2. Interrup ts masked in regi sters IMR0..IMR2 will not
generat e an interru pt though. A read access to the interrupt status registe rs clears the
bits.
A global interrupt mask bit (bit ’GIM’ in register GMODE) suppresses interrupt generation
at all. T o enable th e int errupt syst em after reset, this bit must be se t to ’0’.
The Global Interrupt Status Register (GSTAR) serves as pointer to pending channel
related interrupts and general purpose port int errupts.
GPIM
GPI DMI ISA2 ISA1 ISA0 ISB2 ISB1 ISB0
GPIS
IMR2 (ch A)
ISR2 (ch A)
IMR1 (ch A)
ISR1 (ch A)
IMR0 (ch A)
ISR0 (ch A)
Channel A
Channel B
GSTAR
DIMR
DISR
PEB 20542
PEF 20542
Functional Overview
Data Sheet 85 2000-09-14
3.6 General Purpose Port Pins
3.6.1 GPP Functional Descriptio n
General purpose pins are provided on pins GP0 ...GP2.
Every pin is separately programmable via the General Purpose Port Direction register
GPDIR to operate as an output (bit GPnDIR=’0’) or as an input (bit GPnDIR=’1’, reset
value).
If defined as output, the state of the pin is directly controlled via the General Purpose Port
Data register GPDAT. Read access to these registers delivers the current state of all
GPP pin s (i n put and output sig nals).
If defined as input, the state of the pin is monitored. The signal state of the corresponding
GP pin s is s a m pled with a rising edge of CLK and is read able via reg ist er GPDAT.
3.6.2 GPP Interrupt Indication
The GPP block generates interrupts for transitions on each input signal. All changes may
be indicated via interrupt (optional). To enable interrupt generation, the corresponding
inte rrupt mask bit in register GPIM must be rese t to ’0’.
Bit GPI in the gloabl interrupt status register (GSTAR) is set to ’1’ if an interrupt was
generated by any one or more of the the general purpose port pins. The GPP pin causing
the int errupt can be lo cated by reading th e GPIS register.
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 86 2000-09-14
4 Detailed Protocol Description
The fol lowing Table 12 provides an overview of all supported protocol modes and . The
desired protocol mode is selected via bit fields in the channel configuration registers
CCR0L, CCR0H, CCR2L and CCR3L.
Table 12 Protocol Mode Overview
All modes are discus sed in detail s in this c h apter.
Register CCR0H - Bit Field SM(1:0) = ’00’Register CCR2L - Bit Fie l d: CCR3L
(HDLC/SDLC/PPP protocol engine) MDS ADM PPPM ESS7
HDLC Automod e
(LAP D / LAP B / SDLC-NRM ) 16 bit ’00’’1’’00’’0’
8 bit ’00’’0’
HDLC Address Mode 2 16 bit ’01’’1’
8 bit ’01’’0’
HDLC Address Mode 1 ’10’’1’
HDLC Address Mode 0 ’10’’0’
Signaling System #7 (SS7) Operat ion ’10’’0’’00’’1’
Bit Synchronous PPP Mode ’10’’0’’11’’0’
Octet Synchronous PPP Mode ’01’
Asynchr on ous PPP Mode ’10’
Extended Tran sparent Mode1)
1) Extended transparent mode is a fully bit-transparent transmission/reception mode which is treated as sub-
mode of the HDLC/SDLC/PPP block.
’11’’1’’00’’0’
Register CCR0H - Bit Field SM(1:0) = ’11’Register CCR0L - Bit Fie l d:
(ASYNC protocol engine) BCR
Asynchronous Mode ’1’
Isochronous Mode ’0’
Register CCR0H - Bit Field SM(1:0) = ’10’Register CCR0L - Bit Fie l d:
(BISYNC protocol engine) EBIM
Bisynchrono us Mode ’1’
Monosynch ronous Mode ’0’
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 87 2000-09-14
4.1 HDLC/SDLC Protocol Modes
The HDLC controller of each serial channel (SCC) can be programmed to operate in
various modes, which are different in the treatment of the HDLC frame in receive
direction. Thus, the receive data flow and the address recognition features can be
performed in a very flexible way satisfying almost any application specific requirements.
There are 4 different HDLC operating modes which can be selected via register bits
CCR2L:MDS[1:0] and CCR2L:ADM.
4.1.1 HDLC Submodes Overview
The following table provides an overview of the different address comparison
mechanisms in H DLC operating mod es :
4.1.1.1 Automode
Characteristics: Wi ndow size 1, rand om message length , address recogn ition.
The SCC processes autonomously all numbered frames (S-, I-frames) of an HDLC
protocol. The HDLC control field, I-field data of the frames and an additional status byte
are te mporaril y s tored in the SCC rece iv e FI FO.
Table 13 Address Comparison Overview
Mode Address
Field Recognized Address Bytes for a Match:
High Address By te Low Address Byte
Address
Mode 2
-
Auto
Mode
16 bit FEH / FCH (1111 11 C/R 02)and RAL1
FEH / FCH (1111 11 C/R 02)and RAL2
RAH1 and RAL1
RAH1 and RAL2
RAH2 and RAL1
RAH2 and RAL2
8 bit RAL1 don’t care
RAL2 don’t care
Address
Mode 1 8 bit FEH / FCH (1111 11 C/ R 0 2)don’t care
RAH1 don’t care
RAH2 don’t care
Address
Mode 0 None don’t care don’t care
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 88 2000-09-14
Depending on the selected address mode, the SCC can perform a 2-byte or 1-byte
addre s s recognition.
If a 2-byte address field is selected, the high address byte is compared with the fixed
value FE H or FCH (group address) as well as with two individually programmable values
in RAH1 and RAH2 registers. According to the ISDN LAPD protocol, bit 1 of the high
byte address will be interpreted as COMMAND/RESPONSE bit (C/R), depending on the
setting of the CRI bit in RAH1, and will be exc luded from the address comparison.
Similarly, two comparison values can be programmed in special registers (RAL1, RAL2)
for the low address byte. A valid address will be recognized in case the high and low byte
of the address field correspond to one of the compare values. Thus, the SCC can be
called (addressed) with 6 different address combinations, however, only the logical
connec tion id entif ied thr ough the ad dress comb inat ion RAH1/RAL1 will be processed in
the auto-mode, all others in the non auto-mode. HDLC frames with address fields that
do not m at ch any of the address com binations , are ignore d by the SCC.
In the case of a 1-byte address, only RAL1 and RAL2 will be used as comparison values.
According to the X.25 LAPB protocol, the value in RAL1 will be interpreted as
COMMAND and the value in RAL2 as RESPONSE.
The address bytes can be masked to allow selective broadcast frame recognition. For
further informa t ion see “Receive Address Handl ing ” on Pag e 91.
4.1.1.2 Address Mode 2
Characteristics: address recognition, arbitrary window size.
All frames with valid addresses (address recognition identical to auto-mode) are
forwa rded directly to the RF IF O.
The HDL C con trol field , I-f ield dat a and an ad dition al s tatus byte are tem porar ily store d
in the SCC receive FIFO.
In address mode 2, all f r am es with a valid a ddress are treated sim ilarly.
The address bytes can be mas k ed to allow selec t iv e broadca s t fr am e recognit ion.
4.1.1.3 Address Mode 1
Characteristics: add res s rec ognition high byte.
Only the high byte of a 2-byte address field will be compared. The address byte is
compared with the fixed value FEH or FCH (group address) as well as with two
individually programmable values RAH1 and RAH2. The whole frame excluding the first
address b yte will be stor ed in the SCC receive FIFO.
The address bytes can be mas k ed to allow selec t iv e broadca s t fr am e recognit ion.
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 89 2000-09-14
4.1.1.4 Address Mode 0
Characteristics: no a ddress recogn it ion
No address recognition is performed and each complete frame will be stored in the SCC
receive FIFO.
4.1.2 HDLC Receive Data Processing
The following figures give an overview about the management of the received frames in
the different HDLC operating modes. The graphics show the actual HDLC frame and
how SEROCCO-D interprets the incoming octets. Below that it is shown which octets are
store d in the RFIFO and will thus be transf erred into memory.
Figure 41 HDLC Receive Data Processing in 16 bit Automode
Figure 42 HDLC Receive Data Processing in 8 bit Automode
CRC16
FLAGFLAG (high) (low)
16 bit ADDR
CTRL I-field (data)
/32
to RFIFO
RAH1,2 RAL1,2
option 1) option 2)
RSTA
RSTA
registers
involved
(address
compare)
Automode
16 bit
CRC16
FLAGFLAG (low)
8 bit
ADDR
CTRL I-f i eld (data)
/32
to RFIFO
RAL1,2
opt. 1) option 2)
RSTA
RSTA
registers
involved
(address
compare)
Automode
8 bit
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 90 2000-09-14
Figure 43 HDLC Receive Data Processing in Address Mode 2 (16 bit)
Figure 44 HDLC Receive Data Processing in Address Mode 2 (8 bit )
Figure 45 HDLC Receive Data Processing in Addres s Mode 1
CRC16
FLAGFLAG (high) (low)
16 bit ADDR
data
/32
to RFIFO
RAH1,2 RAL1,2
option 1) option 2)
RSTA
RSTA
registers
involved
(address
compare)
Address Mode 2
16 bit
CRC16
FLAGFLAG (low)
8 bit
ADDR
data
/32
to RFIFO
RAL1,2
opt. 1) option 2)
RSTA
RSTA
registers
involved
(address
compare)
Address Mode 2
8 bit
CRC16
FLAGFLAG
8 bit
ADDR
data
/32
to RFIFO
RAH1,2
opt. 1) option 2)
RSTA
RSTA
registers
involved
(address
compare)
Address Mode 1
16 bit ADDR
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 91 2000-09-14
Figure 46 HDLC Receive Data Processing in Addres s Mode 0
option 1)
The address field (8 bit address, 16 bit address or the high byte of a 16 bit address) can
optionally be forwarded to the RFIFO (bit 'RADD' in register CCR3H)
option 2)
The 16 bit or 32 bit CRC field can optionally be forwarded to the RFIFO (bit 'RCRC' in
register CCR3H)
4.1.3 Recei ve Addr ess Handling
The Receive Address Low/High Bytes (registers RAL1/RAH1 and RAL2/RAH2) can be
masked on a per bit basis by setting the corresponding bits in the mask registers
AMRAL1/AMRAH1 and AMRAL2/AMRAH2. This allows extended broadcast address
recognition. Masked bit positions always match in comparison of the received frame
addre s s w i t h t he respect iv e address fields in the Re ceive Addre ss Low/High registers .
This feature is applicable to all HDLC protocol modes with address recognition (auto
mode, address mode 2 and ad dress mode 1). It is disabled if all bits of mas k bit fields
AMRAL1/AMRAH1 a nd AMRAL2/AMRAH2 are set to ‘zero’ (which is th e reset value).
Dete ct ion of the fixed group address F EH or F CH, if a pplicable to the selected operating
mode, rem ains unchanged.
As an option in the auto mode, address mode 2 and address mode 1, the 8/16 bit
addre ss field of re ceiv ed fram es can be pus hed t o the rec ei ve data buffer (f irst o ne/tw o
bytes of the frame). This function is especially useful in conjunction with the extended
broadcast address recognition. It is enabled by setting control bit ’RADD’ in register
CCR3H.
4.1.4 HDLC Transmit Data Processing
Two different types of f rames can be transm itted:
–I-frames and
CRC16
FLAG
FLAG data
/32
to RFIFO
option 2)
RSTA
RSTA
registers
involved
Address Mode 0
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 92 2000-09-14
–trans parent fram es
as sho w n below.
Figure 47 SCC Transmit Data Flow (HDLC Modes)
For tra nsmis sion of I-fram es (select ed via t ransmi t comma nd ’XIF’ in re gister CMDRL),
the a ddress an d control f ields are generat ed autono m ously by the SC C and the data in
the cor respo nd ing tran sm it da ta buf fer is entere d into t he inform atio n fie ld of th e fr ame.
This is possible only if the SCC is operated in Automode.
For (address-) transparent frames, the address and the control fields have to be entered
in the transmit data buffer by software. This is possible in all operating modes and used
also in auto-mode for se nding U-fram es.
If bit ’XCRC’ in register CCR2H is set, the CRC checksum will not be generated
inte rnally . The che cksum ha s to be provide d vi a the tra nsm it dat a buffe r as th e last two
CRC16
FLAG
FLAG
8 bit
ADDR
data
/32
XFIFO
XAD1
option 2)
registers
involved
Frames with automatic 8 or 16 bit Address and Control Byte Generation
(Automode):
option 2)
Generation of the 16 or 32 bit CRC field can op tionally be disabled by setting bit 'XCRC' in
register CCR2H, in which case the CRC must be calc ulated and written into the last 2 or 4
bytes of the transmit FIFO, to immediately proceed closing flag.
16 bitADDR
XAD2
CRC16
FLAG
FLAG data
/32
XFIFO
option 2)
Frames without automatic Address and Control Byte Generation
(Address Mode 2/1/0):
CTRL
internally
generated
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 93 2000-09-14
or four bytes by software. The transmitted frame will be closed automatically only with a
(closing) flag.
Note: The SCC does not check whether the length of the frame, i.e. the number of bytes,
to be transmitted makes sense ac cording the H D L C protocol or not.
4.1.5 S hared Fl ags
If the ‘Shared Flag’ featu re is enabled by setting bit ’SFLG’ in register CCR1L the closing
flag of a previously transmitted frame simultaneously becomes the opening flag of the
follow i ng frame if there is one already availa ble in the SCC transmit FI F O.
In receive direction the SCC always expects and handles ’Shared Flags’. ’Shared
Zeroes’ of consecutive flags are also supported.
4.1.6 One Bit Insertion
Similar to the zero bit insertion (bit stuffing) mechanism, as defined by the HDLC
protocol, the SCC offers a feature of inserting/deleting a ’one’ after seven consecutive
‘zeros’ into the transmit/receive data stream, if the serial channel is operating in bus
confi guration mo de. This method is use fu l i f clock recovery is perfo r m ed by DPLL.
Since only NRZ data encoding is supported in a bus configuration, there are possibly
long sequences without edges in the receive data stream in case of successive ‘0’s
received, and the DPLL may lose synchronization.
Enabling the one bit insertion feature by setting bit ’OIN’ in register CCR2H, it is
guara nteed th at at least af ter
–5 consecutive ‘1’s a ‘0’ will appear (bit stuffing), and af ter
–7 consecutive ‘0’s a ‘1’ will appear (one insertion)
and thus a c orrect fun ct ion of the DPLL is ensure d.
Note: As with the bit stuffing, the ‘on e insertion’ is f ully tran sparent to the user, but it is
not in accordance with the HDLC protocol, i.e. it can only be applied in proprietary
systems using circuits that also implemen t this functi on, such as the PEB 20532
and PEB 20525.
4.1.7 Pream ble Tr ansmission
If en abled via bi t ’EPT’ in regi ster CCR2H, a programm able 8-bit pattern is transmit ted
with a selectable nu mber o f repetitions after Interfram e Timefill tran smission is stoppe d
and a new frame is ready to be sent out. The 8 bit preamble pattern can be programmed
in register PREAMB and the repe tition time in bit field ’PRE’ of register CCR2H.
Note: Zero Bit Insertion is disa bled during preamble transmission.
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 94 2000-09-14
4.1.8 CRC Generation and Checking
In HDLC/SDLC mode, error protection is done by CRC generation and checking.
In standard applications, CRC-CCITT algorithm is used. The Frame Check Sequence at
the end of each frame consists of two bytes of CRC checksum.
If required, the CRC-CCITT algorithm can be replaced by the CRC-32 algorithm,
enabled via bit ’C32’ in register CCR1L. In this case the Frame Check Sequence
consists of four bytes.
Optionally the internal handling of received and transmitted CRC checksum can be
influenced via control bits ’RCRC’, ’DRCRC’ in register CCR3H an d ’XCRC’ in re gister
CCR2H.
Receive direction:
If not disabled by setting bit ’DRCRC’ (register CCR3H), the rec eived CRC checksum is
always assumed to be in the 2 (CRC-CCITT) or 4 (CRC-32) last bytes of a frame,
immedia tely precedin g a closin g flag. If bit ’RCRC’ is set, the received CRC checksum
is treated as data and will be forwarded to the RFIFO, where it precedes the frame status
byte. Ne verthel ess t he re ceived CRC che cks um is add ition ally ch ecked for c orrectn ess.
If CRC c hecking i s disabl ed with bit CCR3H:DRCRC, the limits for ‘Valid Frame’ c heck
are modified accord ingly (refer to description of t he Receive Status Byte, RSTA:VFR).
Transmit direction:
If bit ’XCRC’ is set, the CRC che cksum is not generated inte rnally. The checksum ha s to
be provided via the transmit data buffer by software. The transmitted frame will only be
closed automati c a l ly with a ( closing) flag.
Note: The SCC does not check whether the length of the frame, i.e. the number of bytes,
to be transmitted makes sense or not according the HDLC protocol.
4.1.9 Receive Length Check Featur e
The SCC offers the possibility to supervise the maximum length of received frames and
to terminate data reception in t he case that t his length is exceeded.
This feature is controlled via the special Receive Length Check Registers RLCRL/
RLCRH.
The function is enabled by setting bit ’RCE’ (Receive Length Check Enable) and the
maximum frame length to be checked is programmed via bit field ’RL’. The maximum
receiv e length can be det ermined as a m ultiple of 32-b yt e blocks as follows:
MAX_LENGTH = (RL + 1) ´ 32 ,
where RL is the value written to bit field ’RL’. Thus, the maximum length of receive
frame s can be programmed bet ween 32 and 65536 bytes.
All fra mes exceed ing this lengt h are treate d as if they h ad been aborte d by the rem ote
station, i.e. the CPU is informed via
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 95 2000-09-14
–an ’RME’ interrupt ge nerated by the S CC, and
–the rec eiv e abort indication ’RAB’ in the Rece iv e St at us By t e (RSTA).
Additio nally an option al ’FLEX’ interrupt is gen erated prior to ’RME’, indicating that the
maximum receive frame length was exceeded.
Rece ive operatio n continues with the beginning of t he next rece iv e frame.
4.2 Point-to-Point Protocol (PPP) Modes
PPP (as described in RFC1662) can work over 3 modes: asynchronous HDLC,
synchronous HDLC, and octet synchronous. The SEROCCO-D supports asynchronous
HDLC PPP over ISDN or DDS circuits as well as bit and octet synchronous HDLC PPP
for use over dial-up connections. The octet synchronous mode of PPP protocol (RFC
1662) supports PPP over SON ET applications.
Both the asynchronous HDLC PPP mode, as well as the synchronous HDLC PPP
modes are submodes of the HDLC mode. Either mode is selected by configuring
SEROCCO-D for the standard HDLC mode. In addition the appropriate PPP mode is
selec te d via bit field ’PPPM’ in register CCR2L.
The SEROCCO-D provides logic to convert an HDLC frame to an ASYNC character
stream with the specified mapping functions. Layer 3 PPP functions are normally
implem ented in software.
The PPP-support hardware allows software to perform segmentation and reassembly of
PPP payloads, and allows SEROCCO-D to perform the asynchronous HDLC PPP or the
synchronous HDLC PPP protocol conversions as required for the network interface.
4.2.1 Bit Synchron ous PPP
The SEROCCO-D transmits a data block, inserts HDLC Header (Opening Flag), and
appends the HDLC Trailer (CRC, Ending Flag). Zero-bit stuffing algorithm is also
perform ed. No char acter mapping is perfo rmed. The bit -s ynchrono us PPP mode differs
from the HDLC mode (addres s m ode 0) only in th e abort sequence:
HDLC re quires at least 7 co n s e c utive ’1’ bits as abort sequence, whereas PPP requires
at least 15 ’1’ bits.
For rec eive oper ati on SERO CCO-D mo nito rs th e incomi ng da ta str eam fo r the Openi ng
Flag (7E Hex) to identify the beginning of a HDLC packet. Subsequent bytes are part of
data and are processed as normal HDLC packet including checking of CRC.
4.2.2 Octet Synchronous PPP
The SEROCCO-D transmits a data block, inserts HDLC Header (Opening Flag), and
appends the HDLC Trailer (CRC, Ending Flag). Beside this standard HDLC operation,
zero-bit stuffin g is not perfo rmed, but character mapping is perf ormed.
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 96 2000-09-14
For rec eive oper ati on S EROCCO-D monito rs the i ncomin g data stre am for t he Open ing
Flag (7E Hex) to identify the beginning of a HDLC packet. Subsequent bytes are part of
data and are processed as normal HDLC packet including checking of CRC. Received
mapped charac ters are unm apped.
The abort sequence consists of the control escape character 7DH followed by a flag
character 7E H (not stuffed). Between two frames, the interframe time fill character should
be programmed to 7EH by setting bit CCR2H:ITF to ’1’.
Octe t alignment is provide d through the synchronizati on pulses in cl oc k mode 5b.
4.2.3 Asynchronous PPP
For transmit operation, SEROCCO-D inserts the HDLC header (Opening Flag), and
appends the HDLC trailer (CRC, Ending Flag), surrounding the transmit data read from
the XFIFO. Each octet (including HDLC framing flags and idle flags) is converted into
async character format (1 start, 8 data bits, 1 stop bit) and then transmitted using the
asyn chron ous ch aracte r forma tter bl ock. C haracte r ma pping lik e in O ctet Synch ronous
PPP mode is perfo rmed.
In receive direction any async character is transferred into SEROCCO-D’s ASYNC
Character De-Formatting logic block, where it is translated back into the original
information octet. Mapped characters are unmapped and the information octets are then
transferred to the RFIFO (as in Octet Synchronous PPP mode).
4.2.4 Data Transparency in PPP Mode
When transporting bit-files (as opposed to text files), or compressed files, the characters
could easily represent MODEM control characters (such as CTRL-Q, CTRL-S) which the
MOD EM wou ld not pa ss th rough. SER OCCO -D main tains a n Asyn c Cont rol Char acter
Map (ACCM) for characters 00-1F Hex. Whenever there is a mapped character in the
data strea m, the tr ansmit ter prece des that character w ith a contro l-escap e character of
7DH. After the control-escape, the character itself is transmitted with bit 5 inverted.
charact er e. g. 13H is map ped to 7DH, 33H).
At the receive end, a 7DH character is discarded and the following character is modified
by inverting bit 5 (e.g. if 7DH, 33H is received, the 7DH is discarded and the 33H is
changed to 13H the original character). This character is received into RFIFO and
included in CRC calculation, even if it is not mapped.
The 32 look up octe t va lues ( 00H-1FH) are stored within the on-chip registers ACCM0..3.
In addition to the ACCM, 4 user programmable characters (especially outside the range
00-1F Hex) can also be ma pped using the contro l-escape sequence de scribed above.
These characters are specified in registers UDAC0..3.
The re ceiver d iscards all cha racters which are re ceived unmapp ed, but expect ed to b e
mapped becaus e of ACCM0..3 and UDAC0..3 register contents. If this occurs within an
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 97 2000-09-14
HDLC fram e, t he une x pecte d ch ara cte rs a re di sca rde d befo re f orwa rde d to the re ce ive
CRC checking unit.
7DH (control-escape) and 7EH (flag) octets in the data stream are mapped in general.
The se quence of map ping control logic is:
1. 7DH and 7EH octets,
2. ACCM0..3,
3. UDAC0..3.
This mechanism is applied to asynchronous HDLC PPP mode as well as to octet
synchronous HDLC PPP mode.
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 98 2000-09-14
Figure 48 PPP Mapping/Unmapping Example
ACCM0..3: Async Control Character Map Register
1F
0
00
0
3
1
13
1E
0
15
0
14
0
...
...
...
...
12
0
11
0
UDAC0..3: User Defined Asy nc Control Character Map Register
7Eh 7Eh 7Eh
20h
13
H
20
H
01
H
02
H
data in
transmit
FIFO:
HDLC
framing: 13
H
20
H
01
H
02
H
7E
H
7E
H
33
H
00
H
01
H
02
H
7E
H
7D
H
7D
H
7E
H
PPP
mapping:
33
H
00
H
01
H
02
H
7E
H
7D
H
7D
H
7E
H
received
character:
13
H
20
H
01
H
02
H
7E
H
7E
H
PPP
unmapping
:
13
H
20
H
01
H
02
H
data in
receive
FIFO:
serial
line
Note: CRC generation/checking is assumed to be disabled in this example; according the PPP mapping/
unmapping, CRC characters are treated as 'data' characters being mapped/unmapped if necessary .
UDAC1 UDAC0
UDAC3 UDAC2 70
070707
ACCM1 ACCM0ACCM3 ACCM2
70
070707
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 99 2000-09-14
4.3 Extended Transparent Mode
Characteristics: fu l l y transparent
When programmed in the extended transparent mode via the CCR2L register (bits
MDS1, MDS0, ADM = ‘111’) , t he SC C performs fully tra ns p arent data transm is sion and
recept ion with out HDLC fr aming, i.e. w ithout
•FLAG ins ertion and deletion
•CRC generation and checking
•bit stuffing.
This feat ure can be profit ably used e.g. f or:
•user specific protocol variations
•line state mo nit oring, or
•test purposes, in particular for monitoring or intentionally generating HDLC protocol
rule violations (e.g. w rong CRC)
Character or octet boundary synchronization can be achieved by using clock mode 5 or
clock mode 1 with a n ex t ernal receiv e st robe input t o pin C D.
Note: Data is transmit te d an d received with the least significant bit (LSB) first.
4.4 Asynchronous (ASYNC) Protocol Mode
4.4.1 C haracter Framin g
Character framing is achieved by start and stop bits. Each data character is preceded by
one S tart bit an d termin ated by one or two stop bits. The cha racter le ngth is selec table
from 5 up to 8 bits. Optionally, a parity bit can be added which complements the number
of ones to an even or odd quantity (even/odd parity). The parity bit can also be
progr am m ed to hav e a fixed v alue (Mark or Space ) . The character form at configuration
is performed via appropriate bit fields in registers CCR3L/CCR3H. Figure 49 shows the
asyn chronous character format.
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 100 2000-09-14
Figure 49 Asynchronous Character Frame
4.4.2 Data Reception
The SCC offers the flexibility to combine clock modes, data encoding and data sampling
in many different ways. However, only definite combinations make sense and are
recommended for correct operation:
4.4.2.1 Asynchronous Mode
Prerequisites:
•Bit clock rate 16 selected (register CCR0L, bit BCR = ‘1’)
•Clock m ode 0, 1, 3b, 4, or 7b selected (regist er CCR0L, bit field ’CM’)
•NRZ d at a encoding s elected (r egister CCR0H, bit field ’SC’)
The receiver which operates with a clock rate equal to 16 times the nominal (expected)
data bit rate, synchronizes itself to each character by detecting and verifying the start bit.
Since character length, parity and stop bit length is known, the ensuing valid bits are
sampled. Oversampling (3 samples) around the nominal bit center in conjunction with
majorit y dec ision is prov ided for ever y received bit (includi ng start bit).
The sy nch roniz ation lasts f or one c har acte r, the nex t inc omin g cha ract er cau ses a new
synchronization to be performed. As a result, the demand for high clock accuracy is
reduced. Two communication stations using the asynchronous procedure are clocked
independently, their clocks need not be in phase or locked to exactly the same frequency
but, in fac t , m ay differ f rom one anot her within a c ert ain range.
4.4.2.2 Isoch r onous Mode
Prerequisites:
•Bit clock rate 1 selected (register CCR0L bit BCR = ‘0’)
D1 D2 D3 D4 D5 D6 D7 Parity
Par. Par. Par.
D0
(LSB)
1
Start
Bit
5 to 8 Data Bits
(6 to 9 Bits with Parity)
1 or 2
Stop
Bits
Character Frame
ITD01804
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 101 2000-09-14
•Clock mode 2, 3a, 6, or 7a (DPLL mode) has to be used in conjunction with FM0, FM1
or Manchester encoding (register CCR0L/CCR0H bit fields ’CM’ and ’SC’).
The isochronous mode uses the asynchronous character format. However, each data bit
is only sampled once (no oversampling).
In clock modes 0 ,1 and 4, the input clock has to be externally phase locked to the data
stream. This mode allows much higher transfer rates. Clock modes 3b and 7b are not
recommended due to difficulties with bit synchronization when using the internal baud
rate generator.
In clock modes 2, 3a, 6, and 7a, clock recovery is provided by the internal DPLL. Correct
synchronization of the DPLL is achieved if there are enough edges within the data
stream, which is generally ensured only if Bi-Phase encoding (FM0, FM1 or Manchester)
is used.
4.4.2.3 Storage of Receive Data
If the receiv er is enabled, received data is stored in the SCC receive FIFO (the LSB is
received first). Moreover, the CD input may be used to control data reception. Character
length, number of stop bits and the optional parity bit are checked. Storage of parity bits
can b e disabled. E rrors are indicated via interrup ts. Additio nally, the character specific
error st at us (framing and parity) can optionally be s to red in the SCC rec eive FIF O.
Filling of the the SCC re ce ive FIFO is controlled by
•a progr am m able threshold level (bit field ’RFTH’ in register CCR3H),
•the sele cted data format ( bit ’RFDF’ in re gis t er CCR3H),
•the parity storage selection (bit ’DPS’ in regist er CCR3H),
•detec tion of the pr ogrammab le Te rmination C hara cter (bit ’TCDE’ in r egister CCR3L
and bit field ’TC’ in register TCR).
Additio nally, the tim e-out event int errupt as an opt ional status inf orm ation indicat es t hat
a certain time (refer to register TOLEN) has elapsed since the reception of the last
character.
4.4.3 Data Transmission
The selection of asynchronous or isochronous operation has no further influence on the
transmitter. The bit clock rate is solely a dividing factor for the selected clock so urce.
Transmission of the contents of the SCC transmit FIFO starts after the ’XF’ command i s
issue d (the LSB is sent out first) . Fur ther data is reques ted by an ’XPR’ interrupt (or by
DMA). The character frame for each character, consisting of start bit, the character itself
with defined character length, optionally generated parity bit and stop bit(s) is
assembled.
After finishing transmission (indicated by the ‘ALLS’ interrupt), IDLE sequence (logical
‘1’) is transm itted on pin T xD.
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 102 2000-09-14
Additionally, the CTS signal may be use d to control data transmission.
4.4.4 Special Functions
4.4.4.1 Break Detection/Generation
Break generation:
On issuing the transmit break command (bit ’XBRK’ in register CCR3L), the TxD pin is
immediately forced to physical ‘0’ level wit h the ne xt foll owing tr ansmit clock ed ge, and
released with the first transmit clo ck edge after this comman d is reset again b y software.
Brea k detectio n:
The S CC reco gnizes the break con dition upon receiving consecut ive (physic al) ‘0’s for
the defined character length, the optional parity and the selected number of stop bits
(‘zero’ character and framing error). The ‘zero’ character is not pushed to RFIFO. If
enabled, the ’Break’ interrupt (BRK) is generated.
The break condition will be present until a ‘1’ is received which is indicated by the ‘Break
Terminated’ interrupt (BRKT).
4.4.4.2 In-band Flow Control by XON/XOFF Characters
Programma ble XON and XOFF characters:
The XON/XOFF registers contain the programmable values for XON and XOFF
characters. The number of significant bits in a register is determined by the programmed
charac t er length via bi t f ield ’CHL’ in register CCR3L.
Additionally, two programmable eight-bit values in registers MXON and MXOFF serve
as masks fo r the characte rs XON and XOFF, respectively:
A ‘1’ in any mask bit position has the effect that no comparison is performed between the
corres ponding b its in the rece ived charac ters (‘don’t cares ’) and the XON /XOFF va lue.
At RES ET , the masks ar e z ero ’ed, i.e. all bit position s will be com pa red .
A rece iv ed c haracter is cons idered to be rec ognized as a valid XON or XOFF character
–if it is correctly framed (correct length),
–if its bits match the ones in the XON or XOFF registers over the programmed character
length,
–if it has correct parity (if applicable).
Received XON an d XOFF charact ers are stored in the SCC rec eiv e F I F O, as any oth er
characters, w hen bit ’DXS’ is set to ’0’ in regi s ter CCR3L. Otherwise they are not stored
in the receive FIFO.
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 103 2000-09-14
In-Band Flow Control of Transmitted Characters:
Recognition of an XON or XOFF character causes always a corresponding maskable
interrupt status to be generated.
Further action de pends on the se tt ing of contro l bit ’FLON’ (Flow Control On) in register
CCR2H:
0: No furt her action is automatically taken by the SCC .
1: The reception of an XOFF character automatically turns off the transmitter after the
currently transmitted character (if any) has been shifted out completely (entering
XOFF state). The reception of an XON character automatically makes the transmitter
resu m e t ransmitt ing (entering XON state).
After hardware RESET, bit CCR2H:FLON is ‘0’.
When bit CCR2H:FLON is programmed from ‘0’ to ‘1’, the transmitter is first in the
‘XON state’, until an XOFF character is received.
When bit CCR2H:FLON is programmed from ‘1’ to ‘0’, the transmitter alway s goes in the
‘XON s tate’, and transmission is only controlled by the user and by the CTS signal input.
The in-ba nd flow cont rol of the transm itter via rec eived XO N and XOF F characters can
be combined with control via CTS pin, i.e. the effect of the CTS pin is independent of
whether in-band control is used or not. The transmitter is enabled only if CTS is ‘low’ and
XON state has been reached.
Transmitter Status Bit:
The status bit ‘Flow Control Status’ (bit ’FCS’ in register STARL) indicates the current
state of the transmitter, as follows:
0: if th e transmit t er is in XON stat e,
1: if the transm it ter is in XOFF state.
Note: The transmitter cannot be turned off by software without disrupting data possibly
remaining in the transm it FIFO.
Flow Control for Received Data:
After writing a character value to register TICR (Transmit Immediate Character, ’TIC’) its
character contents is inserted into the outgoing character stream
•immediately upon writing this register by the microprocessor if the transmitter is in
IDLE state. If no further characters (transmit FIFO empty) are to be transmitted, i.e.
the tra nsmitter ret urns to ID LE state after transmis sion of th e ’TIC’ and an ALL S (All
Sent) interrupt w ill be generated.
•after the end of a character currently being transmitted if the transmitter is not in IDLE
state. This does not affect the contents of the transmit FIFO. Transmission of
characters from transmit FIFO is resumed after the ’TIC’ is s end out.
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 104 2000-09-14
Transmission via this register is possible even when the transmitter is in XOFF state
(howev er, CTS m us t be ‘low’).
The ’TIC’ value is an eight-bit value. The number of significant bits is determined by the
progr amm ed as ync h c har acte r leng th via b it field ’CHL’ in register CCR3L. Parity value
(if programmed) and selected number of stop bits are automatically appended, equal to
the characters provided via the transmit data buffer. The usage of ’TIC’ is ind ependent
of in-band flow control me chanism, i.e. is not affected by bit ’FLON’ in register CCR2H
anyway.
To control multiple accesses to register TICR, an addition al s ta tus bit STARL:TEC (TIC
Executing) is provided which signals that the transmission command of currently
programmed ’TIC’ is accepted but not yet completely executed. Further access to
register TICR is only allowed if bit STARL:TEC is ‘0’ again .
4.4.4. 3 Out-of-band Flow Control
Transmitter:
The t r ansmitter output is enabled if CT S signal is ‘LOW’ AND the XON state is reached
in case of in-band flow control is enabled. If the in-band flow control is disabled
(CCR2H:FLON = ‘0’), the transmitter is only contro lled by the CTS signal.
Nevertheless setting bit CCR1H:FCTS = ‘1’ allows the transmitter to send data
independent of the condition of the CTS signal, the in-band flow control (XON/XOFF)
mechanism w ould still be op erational if en abled via bit CCR2H:FLON = ‘1’.
Receiver:
For some applications it is desirable to provide means of out-of-band flow control to
indicate t o t he f ar end transmitt er t hat t he loc al receiver’s buffer is getting full.
This flow control can be used between two DTEs as shown in Figure 50 and between a
DTE and a DCE (MODEM) as shown in Figure 51 that supports this kind of bi-directional
flow control.
Setting bit CCR1H:FRTS = ‘1’ and CCR1H:RTS = ‘0’ invokes this out-of-band flow
control for the receiver. When the shadow part of the receive FIFO has reached a set
threshold of 28 bytes, the RTS signal is forced inactive (high). When the shadow part of
the receive FIFO is empty, the RTS is re-asserted (low). Note that the data is
immediately transferred from the shadow receive FIFO to the user accessible RFIFO (as
long as there is space available). So when the shadow receive FIFO reaches the 28
bytes t hreshol d, there is 4 more byte s torage ava ilable be fore o verflow c an occur. This
allows sufficie nt time for the far end tran smitter to react to th e ch an ge in th e RTS signal
and st op s ending mo re data.
Figure 50 shows the conn ec tion betw een t wo S CC devi ces as DTEs. The RTS of DT E-
A (SCC) feeds the CTS input of the second DTE-B (another SCC). For example while
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 105 2000-09-14
DTE-A is receiving data and its receive FIFO threshold is reached, the RTS signal goes
in-active ’HIGH’ forcing the CTS of DTE-B to become in-active indicating that
trans mis sion h as to stop aft er fin is hing t he curre nt c har acter. B oth D TE devic e s sh ou ld
als o be using t he CTS signal to flow control their transmitters. When the shadow receive
FIFO in D TE-A is cleared its RT S goes acti ve (low) and t his signals the far end DTE-B
to resume transmission . Data flow control from DTE -B to DTE-A works in the same way .
Figure 50 Out-of-Band DTE-DTE Bi-directional Flow Control
ITS08517
TxD
RxD
CTS
RTS RTS
CTS
RxD
TxD
RS232c Signal s
(driver s not shown)
DTE ABDTE
SEROCCO-D
SEROCCO-D
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 106 2000-09-14
Figure 51 shows an SCC as a DTE con nec t ed to a DCE (MO D EM equipment ).
The RTSA feeds the RTSB input of the DCE (MODEM equipment) that supports bi-
directional flow control. So when the DTE-A’s receiver threshold is reached, the RTSA
signal goes inactive ’HIGH’ which is sensed by the DCE and it stops transmitting.
Similarly if the DCE’s receiver threshold is reached, it deactivates the CTSB (’HIGH’) and
caus es the DTE t o stop tr ansmission . These t ypes of D CEs have fa irly deep buff ers to
ensure that it can continue to receive data from the line even though it is unable to pass
the dat a to the DT E for short periods of ti me. No te that a SC C can also be used in the
DCE equipme n t as sh own. Exchange of signa l s ( e.g . RTS to CTS) is necessarily inside
the DCE equipment.
Figure 51 Out-of-Band DTE-DCE Bi-directional Flow Control
RTS and CTS are used to indicate when the local receiver’s buffer is nearly full. This
alerts the far end transmitter to stop transmission.
The combination of transmitter and receiver out-of-band control features mentioned
above enables data to be exchanged between two devices without software intervention
for flow control.
4.5 BISYNC Protoc ol Mode
4.5.1 C haracter Framin g
Character oriented protocols achieve synchronization between transmitting and
receiving station by means of special SYN characters. Two examples are the
MONOSYNC and IBM’s BISYNC procedures. BISYNC has two starting SYN characters
TxD
RxD
CTS
RTS RTS
CTS
RxD
TxD
RS232c Signal s
(drivers not shown)
DTE A BDCE MODEM 1)
RTS
CTS
RxD
TxD
1) Some MODEMs support bi-directional flow control.
SEROCCO-D SEROCCO-D
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 107 2000-09-14
while MONOSYNC uses only one SYN. Figure 52 gives an example of the message
format.
Figur e 52 BISYN C Message Format
The SYN character, its length, the length of data characters and additional parity
generat ion are progr am m able:
•1 SYN character with 6 or 8 bit length (MONOSYNC), programmable via register
SYNCL.
•2 SYN chara cters with 6 or 8 b it length each (BI SYNC), p rogramma ble via re gisters
SYNCH/SYNCL.
•Data character length may vary from 5 to 8 bits (bit fiel d ’CHL’ in regist er CCR3L).
•Parity informat ion (eve n/odd p arity, mark, sp ace) may be a ppend ed to t he char acter
(bit ’PARE’ and bit field ’PAR’ in register CCR3H).
4.5.2 Data Reception
The rec eiver is g enerally a ctivate d by se tting bit ’RAC’ in register CCR3L. Additio nally,
the CD signal may be used to control data reception depending on the selected clock
mode. After issuing the HUNT command, the receiver monitors the incoming data
stream for the p resence of spe cified SYN character(s). However, data reception is st ill
disabled. If synchronization is gained by detecting the SYN character(s), an SCD
interrupt is generated and all following data is pushed to the receive FIFO, i.e. control
sequences, data characters and optional CRC frame checking sequence (the LSB is
received first). In normal operation, SYN characters are excluded from storage to receive
FIFO. SYN character length can be specified independently of the selected data
character length. If required, the character parity bit and/or parity status is stored
togethe r with each dat a byt e in the rece ive FIFO.
As an option, the loading of SYN cha r ac t ers in receiv e F IFO may be enabled by setting
the bit ’SLOAD’ in r egister CCR3L. Note that in this case SYN characters are treated as
data. Consequently, for correct operation it must be guaranteed that SYN character
SYN
(SYNL) (SYNH)
SYN SOH Header STX Text ETX CRC(Data)
2 Leading
SYN
Characters
Start
of
Header Text
of
Start End
of
Text
Frame
Checking
Sequence
ITD01805
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 108 2000-09-14
length equals the c haracter length + optional pa rity bit. This is the user’s responsibility
by appropriate softwar e settings.
Filling of the receive FIFO is controlled by a prog ramm able threshold level.
Reception is stopped if
1. the receiver is deac tivated by resett ing the bit CCR3L:RAC bit, or
2. the CD signal goes inactive (if Carrier Detect Auto Start is enabled in register CCR1H),
or
3. the CMDRH:HUNT comm and is issu ed again, or
4. the Receiver Reset command (CMDRH:RRES) is issued, or
5. a programmed Termination C haracter ha s been found (opt ional).
On actions 1. and 2., reception remains disabled until the receiver is activated again.
After this is done, and generally in cases 3. and 4., the receiver returns to the (non-
synchronized) Hunt state. In case 5. a HUNT command has to be issued. Reception of
data is internally disab led until syn chronization is regained.
Note: Further checking of frame length, extraction of text or data information and
verifying the Frame Checking Sequence (e.g. CRC) has to be done by the
microprocessor.
4.5.3 Data Transmission
Trans mis si on of data pro vided in th e memo ry is st arted af ter t he T ran smit Fra me ( ’XF’)
command is issued (the LSB is sent out first). Additionally, the CTS signal may be used
to control data transmission. The message frame is assembled by appending all data
characters to the specified SYN character(s) until Transmit Message End condition is
detected (’XME’ command in interrupt mode or, in DMA mode, when the number of
characters specified in XBC1L/XBC1H have been transferred). Internally generated
parity information may be added to each character (SYN, CRC and Preamble characters
are exc luded).
If enabled via CRC Append bi t (bit ’CAPP’ in re gister CCR2H), the internal ly calculated
CRC checksum (16 bit) i s added to the messag e frame. Selection between CRC-16 and
CRC-CCITT algorithms is provided.
Note: - Internall y generated SYN charact ers are always exclude d from CRC calculatio n,
- CRC checksum (2 bytes) is sent wi thout parity.
The internal CRC generator is automatically initialized before transmission of a new
frame starts. The initialization value is selectable.
After finishing data transmission, interframe-time-fill (SYN characters or IDLE) is
automaticall y sent.
A transmit data underrun condition in the XFIFO is indicated with an ’XDU’ interrupt.
Nevertheless, transmission continues inserting SYN characters into the data stream until
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 109 2000-09-14
new dat a is availabl e in the transm it FIFO. In serted SYN characte rs are not part of the
frame and thus not used for CRC calculation .
4.5.4 Special Functions
4.5.4. 1 Preamble Transmission
If enabled via register CCR2H, a programmable 8-bit pattern (register PREAMB) is
transmitted with a selectable number of repetitions after interframe-time-fill transmission
is stoppe d and a new frame is ready to be sent out.
Note: If the preamble pattern equals the SYN pattern, reception is triggered by the
preamble.
4.6 Procedur al Supp ort (Layer-2 Functions)
When operat in g in t he aut o m ode, the SCC of fers a hi gh degree of p rotoc ol s upport . In
addition to address recognition, the SCC autonomously processes all (numbered) S- and
I-frames (window size 1 only) with either normal or extended control field format
(modulo-8 or modulo-128 sequence numbers – selectable via register CCR2H bit
’MCS’).
The following functions will be performed:
–upda ting of trans m it and receiv e c ounter
–evaluation of transmit and receive counter
–processing of S commands
–flow control with RR/RNR
–generation of responses
–recognition of protocol errors
–trans mission of S comman ds , if acknowledgement is not receiv ed
–continuous status query of remote station after RNR has been received
–progr am mable tim er/ repeater functions .
In addit ion, all unnum bered frame s are forward ed directly to t he processor. The logical
link can be initialized by software at any time (Reset HDLC Receiver by RRES command
in register CMDRH).
Additional logical con nections can be operated in parallel by sof tware.
4.6.1 Full-Duplex LAPB/LAPD Operation
Initia lly ( i.e. after RESET), t he LAP co nt rollers of the two seria l c hannels a re configure d
to function as a combined (primary/secondary) station, where they autonomously
perform a subset of the balanced X.25 LAPB/ISDN LAPD protocol.
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 110 2000-09-14
Reception of Frames:
The logical processing of received S-frames is performed by the SCC without
interrupting th e host. The ho st is mere ly informed by interrupt of status changes in the
remote station (receiver ready / receiver not ready) and protocol errors (unacceptable
N(R), or S-frame with I-field).
I-frames are also processed autonomously and checked for protocol errors. The I-frame
will not be accepted in the case of sequence errors (no interrupt is forwarded to the host),
but is imm edi ately conf irmed by an S -resp on se. I f the ho st set s the SCC into a ‘receive
not ready’ status , an I-frame wi ll not be accept ed (no interrup t) and a n RNR respons e is
transmitted. U-frames are always stored in the RFIFO and forwarded directly to the host.
The logical sequence and the reception of a frame in auto mode is illustrated in
Figure 53.
Note: The state variables N(S), N(R) are evaluated within the window size 1, i.e. the
SCC checks only the least significant bit of the receive and transmit counter
rega rdless of the selected modulo count.
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 111 2000-09-14
Figure 53 Proces si ng of Recei ved Frames in Au to M ode
ITD00230
Command
with p=1
?
Y
?
Ready
Rec. N
f=p
Trm RR
ActivRec.
Set RRNR
Response
PCE
Int :
1
Response
Trm RNR
f=p
?
Overflow
Data
N
:Int RME
Set RDO
Response
Trm RR
f=p
RMEInt :
N
Y
Y
N
=V
Y
N(S) (R)+1
Rec. Ready :Int RME
N
Set RDO
Data
Overflow
?
N
Y
ALLSInt :
Acknowledge
RESET Wait for
+1
(S)=Y
=VN(R) (S)+1
Y
?
Acknowledge
Wait for
N
Y
:Int XMR
RESET Wait for
Acknowledge
Acknowledge
RESET Wait for
ALLSInt :
Response
f=1
?
N
(S)+1N(R)=V
N
Y
Wait for
Acknowledge
?
NN
Y
?
CRC Error
Set CRCE
N
N
Set RAB
Aborted
?
Y
U Frame
1
YProt. Erro r
?
N
PCEInt:
:Int RME
Set CRCE N
?
CRC Error
Y
Set RAB
Aborted
?N
Y
I Frame
N
1
YProt. Error
?
N
or Abort
CRC Error
Y
RNR
?
1
RESET RRNR
?
,
YCRC Error
or Abort
N
?
Prot. Erro r
Y
N
:Int PCE
SREJREJRR,
1
Y
(R)+1(R) =VV
V(S)
V
V(S)
V=
(S) +1 Y
??
ALLS:Int
?
?
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 112 2000-09-14
Transmission of Fram es:
The SCC autonomously transmits S commands and S responses in the auto mode.
Either transparent or I-frames can be transmitted by the user. The software timer has to
be operated in the internal timer mode to transmit I-frames. After the frame has been
transmitted, the timer is self-started, the XFIFO is inhibited, and the SCC waits for the
arrival of a positive acknowledgement. This acknowledgement can be provided by
means of an S- or I-frame.
If no positive acknowledgement is received during time t1, the SCC transmits an S-
command (p = ‘1’), which must be answered by an S-response (f = ‘1’). If the S-response
is not received, the process is performed n1 times (in HDLC known as N2, refer to
register TIMR3).
Upon the arrival of an acknowledgement or after the completion of this poll procedure
the XF IFO is enable d and an interrupt is generated . Interrupts ma y be trigger ed by the
following:
•message has been positively ac k nowledged (ALLS interru pt )
•message must be repeated (XMR interrupt)
•resp onse has not been rece iv ed (T IN interrupt ).
In automode, only when the ALLS interrupt has been issued data of a new frame may
be provided to the XFIFO!
Upon arrival of an RNR frame, the software timer is started and the status of the remote
station is polled periodically after expiration of t1, until the s tatus ‘receive ready’ has been
detect ed. The user is informed via the appro priate interrupt. If no response is received
after n1 times, a TIN interrupt, and t1 clock periods thereafter an ALLS interrupt is
gener ated and the process is termi n ated.
Note : The int ernal timer mode should only be used in the auto mode.
Trans parent fram es c an be transmitted in all operating m odes.
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 113 2000-09-14
Figure 54 Time r Proc e dure / P oll Cyc l e
ITD00231
Wait for
Acknowledge
Set
?
?
2
?
with f=1
Response
Wait for
Acknowledge
?
RRNR
N
NN
Y Y
N
2
YY
=?
(R) (S)+1VN
Y
N
1tLoad
Rec.RNRRec.RRIRec. Frame
T Proc. Activ
TINInt :
1
Load t1
Y
?
Ready
Rec. N
Command p=1
Trm RR
,,
Trm RNR
Command p=1
n1 n1-1=
N
?
Y
Y
?
N
n1= 7
n1= 0
Run Out
1 2
2
Load t1
Trm RR/RNR
CMDR ; STI
Command p=1
Trm I Fr ame
Acknowledge
Set wa it fo r
InactivT Proc. 1
RNR
Set RRNR
Rec.
1t
Load n1
Load n1
11.06.1996 B/R
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 114 2000-09-14
Examples
The interaction between SCC and the host during transmission and reception of I-frames
is illustrated in the following two figures. The flow cont rol with RR/RNR of I-frames during
transmission/reception is illustrated in Figure 55. Both, the sequence of the poll cycle
and protocol errors are shown in Figure 56.
Figure 55 Transmission/Reception of I-Frames and Flow Control
Figure 56 Flow Control: Reception of S-Commands and Protocol Errors
RME
RME
WFA
Transmit with
FrameI
Confirm I Frame
ALLS
ALLS WFA
Reception FrameI
Transmit FrameI
RR(1)
(0.0)
I
RR(1)
I(0.1)
(1.1)
I
(1.2)
I
RR(2)
RR(0)f=1
RNR
RSC
(RNR)
RSC(RR)
XMR
WFA
t1
t1 RR(0)p=1
RNR(0)f=1
RNR(0)
I(0.0)
RR(0)p=1
ALLS
WFA = Wait For Acknow ledge (see Status Register)
RNR
RME
XRNR
RNR(0)
RR
(0.0)
I
RR(0)p=1
RR(0)f=1
RR(0)p=1
RR(0)f=1
I(0.0)
RR(1)
t1
t1
t1
RRp=1
Poll Cycle
Protocol Error
I
RR(0)p=1
RR(1)
RR(2)
ALLS
PCE
TIN
WFA
ALLS
RR(0)
WFA
RRp=1
(0.0)
WFA = Wait For Acknowledge (see Status Regist er)
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 115 2000-09-14
Protocol Error Handling:
Depen ding on the error ty pe, erroneous frames are han dled according to Table 14.
Note: The station variables ( V(S), V(R) ) are not changed.
4.6.2 H al f-D uplex SDLC-NRM Operation
The LAP controllers of the two serial channels can be configured to function in a half-
duplex Normal Response Mode (NRM), where they operate as a slave (secondary)
station, by setting t he NRM bit in th e CCR2L re gis t er of the corres ponding ch annel.
In contrast to the full-duplex LAP B/LAP D operation, where the combined
(primary + secondary) station transmits both commands and responses and may
trans mit data a t any time, th e NRM mode all ows only res ponses to be transm itted and
the secondary station may transmit only when instructed to do so by the master (primary)
station. The SCC gets the permission to transmit from the primary station via an S-, or I-
frame with the poll bit (p) set.
The NRM mode can be profitably used in a point-to-multipoint configuration with a fixed
master-slave relationship, which guarantees the absence of collisions on the common
transmit line. It is the responsibility of the master station to poll the slaves periodically
and to ha ndle error situat ions .
Prerequisite for NRM operation is:
–auto m ode with 8-bit address fie ld selected
Register CCR2L bit fields ’MDS1’, ’MDS0’, ’ADM’ = ‘000’
–Register TIMR3 bit ’TMD’ = ‘0’
–same transmit and receive ad dresses, since only re s ponses can be t ransmitted, i.e.
Register XAD1 = XAD2 and register RAL1 = RAL2 (address of secondary).
Table 14 Error Handling
Frame Type Error Type Generated
Response Generated
Interrupt Rec. Status
ICRC error
Aborted
Unex pected N(S)
Unexpected N(R)
–
–
S-frame
–
RME
RME
–
PCE
CRC error
Abort
–
–
SCRC error
Aborted
Unexpected N(R)
With I-field
–
–
–
–
–
–
PCE
PCE
–
–
–
–
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 116 2000-09-14
Note: The broadcast address may be programmed in register RAL2 if broadcasting is
required.
In this case registers RAL1 and RAL2 are not equal.
The pri mary station has to op erate in trans pa rent HDLC mode.
Recepti on of Frames:
The reception of frames functions similarly to the LAPB/LAPD operation (see “Full-
Duplex LAPB/LAPD Operation” on Pag e 109).
Trans mission of Frames:
The SCC does not transmit S-, or I-frames if not instructed to do so by the primary station
via an S-, or I-fram e w i t h t he poll bit set.
The SCC can be told to send an I-fram e issuing t he trans mit comman d ’XIF’ in regis ter
CMDRL. The transmission of the frame, however, will not be initiated by the SCC until
recept ion of either an
•RR, or
•I-frame
with poll bit set (p = ‘1’).
After the frame has been transmit ted (with the final bit set), the h ost has to wait for an
ALLS or XMR interrupt .
A secondary does not poll the primary for acknowledgements, thus timer supervision
must be done by the primary station.
Upon the arrival of an acknowledgement the SCC transmit FIFO is enabled and an
interrupt is forwarded to the host, either the
–message has been positive ly ac k nowledged (ALLS interr upt ), or the
–message must be repeated (XMR interrupt).
Additionally, the on-chip timer can be used under host control to provide timer recovery
of the sec ondary if no acknowledgements are re c eiv ed at all.
Note: A secondary will transmit transparent frames only if the permission to send is
given by receiv ing an S-fram e or I -frame wit h poll bit set (p = ‘1’).
Examples:
A few examples of SCC/host interaction in the case of normal response mode (NRM)
mode are shown in Figure 57 and Figure 58.
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 117 2000-09-14
Figure 57 No Data to Send: Data Reception/Transmission
Figure 58 Data Transmission (without error), Data Transmi ssion (with error)
4.6.3 Signaling System #7 (SS7) Operation
The SEROCCO-D supports the signaling system #7 (SS7) which is described in ITU-
Q.703. SS7 supp ort m ust be activ at ed by setting bi t ’ESS7’ in register CCR3L.
RR(0)f=1
RR(0)p=1
Secondary Primary
ITD01800
(0,1)f=1
(0,0) p=1
ITD00237
(1,1) p=1
RR(2)f=1
ALLS
RME
XIF I
I
I
(0,0)f=1
RR(0)p=1
ITD00238
RR(1)p=0
ALLS
XIF
I (0,0 )f =1
RR(0)p=1
ITD01801
RR(0)p=1
XMR
XIF
I
RR(0)f=1
t
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 118 2000-09-14
Receive
The SS7 protoco l is supporte d by the following hardware featur es in receive direc t ion:
•Reco gnit i on of Signaling Unit type
•Discard of repeatedly received FISUs and optionally of LSSUs if content is unchanged
•Check if the length of the received signaling unit is at least six octets (including the
opening f lag)
•Check if the signal information field of a received signaling unit consists of more than
272 octets (enabled with bit CCR3L.ELC). In this case, reception of the current
signaling unit will be aborted.
•Count ing and proces s ing of errored s ignaling units
In order to reduce the microprocessor load, Fill In Signaling Units (FISUs) are processed
automatically. By examining the length indicator of a received Signal Unit (SU)
SEROCCO-D decides whether a FISU has been received. Consecutively received
FISUs will be compared and not stored in the RFIFO, if the content is equal to the
previous one. The same applies to Link Status Si gnaling Un it s (LSSUs) , if enabled wit h
bit CCR3L.CSF. The different types of Signaling Units as Message Signaling Unit
(MSU), Link Status Signaling Unit (LSSU) and Fill-In Signaling Units (FISU) are indicated
in the RSTA byte (bit field ’SU’), which is automatically added to the RFIFO with each
received Signaling Unit. The complete Signaling Unit except start and end flags is stored
in the receive FIFO. The functions of bits CCR3H.RCRC and CCR3H.RADD are also
valid in SS7 mode, with bit ’RADD’ related to BSN (backward sequence number) and
FSN (forward seq uence numb er).
Errored signaling units are counted and processed according to ITU-T Q.703. The SU
counter and errored-SU counter are reset by setting CMDRH.RSUC to ’1’. The error
thres hold c an b e select ed t o be 6 4 ( defau lt) o r 32 by c le aring/ setti ng bit CCR3L.SUET.
If the defined error limit is exceeded, an interrupt (ISR1.SUEX) is generated, if not
masked by bit IMR1.SUEX.
Transmit
In tran smit direc ti on, following features are supported:
•single or repetitive transmission of signal ing units
•automatic generation of Fill-In Signaling U ni ts (FISU)
Each Signaling Unit (SU) written to the transmit FIFO (XFIFO) will be sent once or
repeatedl y including f lags, CRC checksu m and st uf fed bi ts. A fter e .g. an MSU ha s be en
transmitted comple tely, SEROCCO -D option ally starts sending of Fill In Sig naling Uni ts
(FISUs) containing the forward sequence number (FSN) and the backward sequence
number (BSN) of the previously trans mitted si gnaling unit. Setting bit CCR3L.AFX to ’1’
causes FISUs to be sent continuously if no Signaling Unit is to be transmitted from
XFIFO. After a new signaling unit has been written to the XFIFO and a transmission has
been initiated, the current FISU is completed and the new SU is sent. After this,
PEB 20542
PEF 20542
Detailed Protocol Desc ription
Data Sheet 119 2000-09-14
transmission of FISUs continues. The internally generated FISUs contain FSN and BSN
of the la st transmitt ed signaling unit written to XFIFO.
Using CMDRL.XREP=’1’, the contents of XFIFO (1..32 bytes) can be sent continuously.
Thi s cyclic transmission can b e stopped with th e CMDRL.XR ES command.
PEB 20542
PEF 20542
Register Description
Data Sheet 120 2000-09-14
5 Register Description
5.1 R egister Overv i ew
The SEROCCO-D global registers are used to configure and control the Serial
Communicatio n C ont rollers (SCCs ), General Purpose Pins (GPP) and DMA o peration.
All reg isters are 8-bit o rganiz ed regist ers, b ut groupe d and o ptimiz ed for 16 b it ac cess.
16 bit ac c es s is supported to even addresses on ly .
Table 15 provides an overv iew about all on-chip regis t ers :
Table 15 Register Overvi ew
Offset Ch Register Res
Val Meaning Page
A B read write
Global registers:
00HGCMDR 00HGlobal Command R egister 1 26
01HGMODE 0BHGloba l M ode Register 127
02HDBSR 00HDMA Buffer Status Register 130
03HGSTAR 00HGlobal St at us R egister 131
04HReserved
05HGPDIR FFHGPP Direction Register 133
06HReserved
07HGPDAT - GPP Data Register 134
08HReserved
09HGPIM FFHGPP Interrupt M as k Re gis ter 135
0AHReserved
0BHGPIS 00HG PP I nt errupt Status R egister 136
0CHDCMDR 00HDMA Command Register 137
0DHDMODE 00HDMA Mode Register 139
0EHDISR 00HDMA Int errupt Status Register 140
0FHDIMR 77HDMA Interrupt Mask Re gister 142
Chan n e l specific registers:
10H60HRFIFO XFIFO - Receive/Transmit FI FO (Low By t e) 143
11H61H- R eceive/Transmit FIFO (Hig h By t e ) 143
PEB 20542
PEF 20542
Register Description
Data Sheet 121 2000-09-14
12H62HSTARL 00HStatus Register (Low Byte) 145
13H63HSTARH 10HStatus Register (High Byte) 145
14H64HCMDRL 00HCommand Register (Low Byte) 150
15H65HCMDRH 00HCommand Register (High Byte) 150
16H66HCCR0L 00HChannel Configuration R egister 0 (Low
Byte) 155
17H67HCCR0H 00HChannel Conf iguration Register 0 (High
Byte) 155
18H68HCCR1L 00HChannel Configuration R egister 1 (Low
Byte) 159
19H69HCCR1H 00HChannel Conf iguration Register 1 (High
Byte) 159
1AH6AHCCR2L 00HChannel Configuration R egister 2 (Low
Byte) 164
1BH6BHCCR2H 00HChannel Conf iguration R egister 2 (Hi gh
Byte) 164
1CH6CHCCR3L 00HChannel Conf iguration Register 3 (Low
Byte) 171
1DH6DHCCR3H 00HChannel Configuration R egister 3 (Hi gh
Byte) 171
1EH6EHPREAMB 00HPreamble Register 179
1FH6FHTOLEN 00HTime Out Length Regist er 180
20H70HACCM0 00HPPP ASYNC Control Charac ter Map 0 181
21H71HACCM1 00HPPP ASYNC Control Charac ter Map 1 181
22H72HACCM2 00HPPP ASYNC Control Charac ter Map2 182
23H73HACCM3 00HPPP ASYNC Control Charac ter Map 3 182
24H74HUDAC0 7EHUser Defined PPP ASYNC Control
Character Map 0 184
25H75HUDAC1 7EHUser Defined PPP ASYNC Control
Character Map 1 184
26H76HUDAC2 7EHUser Defined PPP ASYNC Control
Character Map 2 185
Table 15 Register Over vi ew (cont’d)
Offset Ch Register Res
Val Meaning Page
A B read write
PEB 20542
PEF 20542
Register Description
Data Sheet 122 2000-09-14
27H77HUDAC3 7EHUser Defined PPP ASYNC Control
Character Map 3 185
28H78HTTSA0 00HTransmit Time Slot Assignment Register 0 187
29H79HTTSA1 00HTransmit Time Slot Assignment Register 1 187
2AH7AHTTSA2 00HTransmit Time Slot Assignment Register 2 188
2BH7BHTTSA3 00HTransmit Time Slot Assignment Register 3 188
2CH7CHRTSA0 00HReceive Time Slot Assignment Register 0 190
2DH7DHRTSA1 00HReceive Time Slot Assignment Register 1 190
2EH7EHRTSA2 00HReceive Time Slot Assignment Register 2 191
2FH7FHRTSA3 00HReceive Time Slot Assignment Register 3 191
30H80HPCMTX0 00HPCM Mask Transmit Direction Re gister 0 193
31H81HPCMTX1 00HPCM Mask Transmit Direction Re gister 1 193
32H82HPCMTX2 00HPCM Mask Transmit Direction Re gister 2 194
33H83HPCMTX3 00HPCM Mask Transmit Direction Re gister 3 194
34H84HPCMRX0 00HPCM Mask Receive Direction Register 0 196
35H85HPCMRX1 00HPCM Mask Receive Direction Register 1 196
36H86HPCMRX2 00HPCM Mask Receive Direction Register 2 197
37H87HPCMRX3 00HPCM Mask Receive Direction Register 3 197
38H88HBRRL 00HBaud Rate Register (Low Byte) 199
39H89HBRRH 00HBaud Rate Register (High Byte) 199
3AH8AHTIMR0 00HTimer Register 0 201
3BH8BHTIMR1 00HTimer Register 1 201
3CH8CHTIMR2 00HTimer Register 2 202
3DH8DHTIMR3 00HTimer Register 3 202
3EH8EHXAD1 00HTransmit Address 1 Register 205
3FH8FHXAD2 00HTransmit Address 2 Register 205
40H90HRAL1 00HReceive Address 1 Low Register 207
41H91HRAH1 00HReceive Address 1 High Register 207
42H92HRAL2 00HReceive Address 2 Low Register 208
43H93HRAH2 00HReceive Address 2 High Register 208
Table 15 Register Over vi ew (cont’d)
Offset Ch Register Res
Val Meaning Page
A B read write
PEB 20542
PEF 20542
Register Description
Data Sheet 123 2000-09-14
44H94HAMRAL1 00HMask Receive Address 1 Low Register 210
45H95HAMRAH1 00HMask Receive Ad d re ss 1 Hi gh Register 210
46H95HAMRAL2 00HMask Receive Address 2 Low Register 211
47H96HAMRAH2 00HMask Receive Ad d re ss 2 Hi gh Register 211
48H98HRLCRL 00HRec eive Len gt h C h eck Regi st er (Low
Byte) 213
49H99HRLCRH 00HRe c eive Len gt h C h eck Reg ist er (High
Byte) 213
4AH9AHXON 00HXON In-Band Flow C ontrol Cha r ac t er
Register 215
4BH9BHXOFF 00HXOF F In- Band Flow Control Char ac ter
Register 215
4CH9CHMXON 00HXO N In-Band F low Contr ol M a s k Register 217
4DH9DHMXOFF 00HXOFF In- Band Flow Control Mask
Register 217
4EH9EHTCR 00HTermination Character Register 219
4FH9FHTICR 00HTran s m it I mmediat e C haracter Register 220
50HA0HISR0 00HInterrupt Status Register 0 222
51HA1HISR1 00HInterrupt Status Register 1 222
52HA2HISR2 00HInterrupt Status Register 2 223
53HA3HReserved
54HA4HIMR0 FFHInterrupt Mask Register 0 2 30
55HA5HIMR1 FFHInterrupt Mask Register 1 2 30
56HA6HIMR2 03HInt errupt Mask Re gis t er 2 231
57HA7HReserved
58HA8HRSTA 00HRece ive Status By t e 233
59HA9HReserved
5AHAA
H
SYNCL 00HSYN Character Register (Low Byte ) 237
5BHAB
H
SYNCH 00HSYN Character Register (H igh Byte) 237
Table 15 Register Over vi ew (cont’d)
Offset Ch Register Res
Val Meaning Page
A B read write
PEB 20542
PEF 20542
Register Description
Data Sheet 124 2000-09-14
5CHAC
H
... Reserved
5FHAFH
Channel specific DMA registers:
B0HCA
H
TBADDR1L 00HPr imary Transmit Base Address (Low
Byte) 239
B1HCB
H
TBADDR1M 00HPrimary Transmit Base Address (Mid
Byte) 239
B2HCC
H
TBADDR1H 00HPrimary Transmit Base Address (High
Byte) 240
B3HCD
H
Reserved
B4HCE
H
TBADDR2L 00HSecondary Transmit Ba s e Address (Lo w
Byte) 241
B5HCF
H
TBADDR2M 00HSe c ondary Transmit Base Address (Mid
Byte) 241
B6HD0HTBADDR2H 00HSecondary Tran sm it Base Add res s (High
Byte) 242
B7HD1HReserved
B8HD2HXBC1L 00HPrimary Transmit Byte Count (Low Byte) 243
B9HD3HXBC1H 00HPrimary Transm it Byte Cou nt ( Hi gh By t e) 243
BAHD4HXBC2L 00HSecondary Transmi t By t e C ount (Low
Byte) 245
BBHD5HXBC2H 00HSecondary Transmit Byt e C o unt (High
Byte) 245
BCHD6HRBADDR1L 00HPrimary Receive Base Address (Low
Byte) 247
BDHD7HRBADDR1M 00HPrimary Receive Base Address 1 (Mid
Byte) 247
BEHD8HRBADDR1H 00HPrimary Receive Base Ad dress 1 (High
Byte) 248
BFHD9HReserved
Table 15 Register Over vi ew (cont’d)
Offset Ch Register Res
Val Meaning Page
A B read write
PEB 20542
PEF 20542
Register Description
Data Sheet 125 2000-09-14
C0HDA
H
RBADDR2L 00HSecondary Rec eive Base A ddress (Low
Byte) 249
C1HDB
H
RBADDR2M 00HSec ondary Receiv e Base Addre s s (M id
Byte) 249
C2HDC
H
RBADDR2H 00HSecondary Receive Base Address2 (High
Byte) 250
C3HDD
H
Reserved
C4HDE
H
RMBSL 00HReceive Maximum Buffer Size (Low Byte) 251
C5HDF
H
RMBSH 00HReceiv e Maximum Buffe r Size (High By te) 25 1
C6HE0HRBCL 00HR eceive By te Count (Low Byte) 253
C7HE1HRBCH 00HReceive Byte Count (H igh Byte) 253
C8HE2HReserved
C9HE3HReserved
Miscellaneous:
E4H
... Reserved
EBH
ECHVER0 03HVersion Register 0 255
EDHVER1 E0HVersion Register 1 255
EEHVER2 05HVersion Register 2 256
EFHVER3 20HVersion Register 3 256
Table 15 Register Over vi ew (cont’d)
Offset Ch Register Res
Val Meaning Page
A B read write
PEB 20542
PEF 20542
Register Description (GCMDR)
Data Sheet 5-126 2000-09- 14
5.2 Detailed Register Description
5.2.1 G l obal Registers
Each register desc ription is org anized in three parts:
•a head with general information about reset value, access type (read/write), offset
address and usual handling;
•a table c ontaining th e bit inf orm ation (name of bit positions );
•a section containing the detailed description of each bit.
Register 1 GCMDR
Global Command Register
CPU Accessibility: read/write
Reset Value : 00H
Offs et Address: 00H
typica l us age: written by C PU ,
eval uated by SEROCCO-D
Bit76543210
Global Command Bits
0000000SWR
SWR Softw are Reset Command
Self clearing command bit:
bit=’0’No software reset command is issu ed .
bit=’1’Causes SEROCCO-D to perform a complete reset
identical to hardware reset.
PEB 20542
PEF 20542
Register Description ( GMODE)
Data Sheet 5-127 2000-09- 14
Register 2 GMODE
Global Mode Register
CPU Accessibility: read/write
Reset Value : 0BH
Offs et Address: 01H
typica l us age: written by C PU
eval uated by SEROCCO-D
Bit76543210
DMA and Global Control
IDMA 0 IPC(1:0) OSCPD BRC DSHP GIM
IDMA Enable Internal DMA
This bit field contr ols the DMA op erat ion mode:
IDMA=’0’The internal DMA controller functions are disabled.
SEROCCO-D is operated in standard register access
controlled mode.
IDMA=’1’The internal DMA controller is enabled.
Sing le Buffer or Sw it c hed Buffer op eration mode is
selected with register DMODE.
IPC(1:0) Interrupt Pin Characteristic
These bits control the characteristic of interrupt output pin INT/INT:
IPC(1:0) Output Function:
’00’Open Drain active low
’01’Push/Pull active low
’10’Reserved.
’11’Push/Pull active high
PEB 20542
PEF 20542
Register Description ( GMODE)
Data Sheet 5-128 2000-09- 14
OSCPD Oscillator Power Down
Setting this bit to ’0’ enables the internal oscillator. For power saving
purpo s es (e s c pec ially if clock mo des are used which do n ot need the
internal oscillator) this bit may remain se t to ’1’.
OSCPD=’0’The internal oscillator is active.
OSCPD=’1’The internal oscillator is in power down mode.
Not e: After rese t this bit is set t o ’1’, i.e. t he oscillat or is in pow er down
mode!
BRC Bus Request Pin Characteristic
This bit c ont rols the ch arac teristic of output pi n BR EQ:
BRC=’0’Open Dra i n active low (res e t value)
BRC=’1’Push/Pull active low
Note: If bus preemption as shown in Chapter 3.4.3 is not needed,
enabling the push/pull output characteristic makes a strong pull-up
resistor for pin BREQ obsolete.
DSHP Disable Shaper
This bit has to be set to ’0’ if the shaping function in the oscillator unit is
desired. The shape r am plifies the oscillator sign al and improves th e
slope of the clock edges .
DSHP=’0’Shaper is en abled. Recom mended setting if a cry s t al is
connected to pins XTAL1/XTAL2.
DSHP=’1’Shaper is disabled (byp assed). Recomme nded setting if
- a TTL level cloc k signal is su pplied to pin XT AL1
- the oscillator unit is unused
Note: After reset this bit is set to ’1’, i.e. the shaper is disa bled!
PEB 20542
PEF 20542
Register Description ( GMODE)
Data Sheet 5-129 2000-09- 14
GIM Global Interrupt Mask
This bits disables all interrupt indications via pin INT/INT. Internal
operation (interrupt generation, interrupt status register update,...) is not
affected.
If set, pin INT/INT immediately changes or re mai n s in in active state.
GIM=’0’Global interrupt mask is cleared. Pin INT/INT is controlled
by the internal interrupt control logic and activated as long
as at le as t one unmas ked interrupt indication is pending
(not yet confirmed by read access to corresponding
interrupt status register).
GIM=’1’Global interrupt mask is set. Pin INT/INT remains inactive.
Note: After reset this bit is set to ’1’, i. e. all int errupts are dis abled!
PEB 20542
PEF 20542
Register Description (DBSR)
Data Sheet 5-130 2000-09- 14
Register 3 DBSR
DMA Buffer Status Register
CPU Accessibility: read/write
Reset Value : 00H
Offs et Address: 02H
typical usage: writ te n by SER OCCO-D ev aluated by CP U
Bit76543210
Internal DMAC Status Information
DTBB 0 DRBB 0 DTBA 0 DRBA 0
DTBB DMA Transmit Buffer Channel B
DRBB DMA Receive Buffer Channel B
DTBA DMA Transmit Buffer Channel A
DRBA DMA Receive Buffer Channel A
Only valid in internal DMA controll er modes.
These bits indicate on which buffer the corresponding DMA channel is
currently operating on.
These st at us bits are for debug purposes only.
bit = ’0’b as e address 1 is ac t iv e address
bit = ’1’b as e address 2 is ac t iv e address
PEB 20542
PEF 20542
Register Des cr iption (GSTAR)
Data Sheet 5-131 2000-09- 14
Register 4 GSTAR
Glob al Status Re g i ster
CPU Accessibility: read only
Reset Value : 00H
Offs et Address: 03H
typical usage: writ te n by SER OCCO-D ev aluated by CP U
Bit76543210
Global Interrupt Stat us Info rm at ion
GPI DMI ISA2 ISA1 ISA0 ISB2 ISB1 ISB0
GP I Gener al Purpos e Po r t In d ication (-)
This bit indicates, tha t a GPP port interrupt indica tion is pending:
GPI=’0’No general purpose port interrupt indication is pending.
GPI=’1’General purpose port interrupt indication is pending. The
sourc e f or t h is int errupt can be further de termined by
reading register GPIS (refer to page 5-13 6).
DMI DMA Interrupt Indication (-)
This bit indicates, that a DMA interrup t indicatio n is pend ing :
DMI=’0’No DMA interrupt indication is pending.
DMI=’1’DMA interrupt indication is pending. The source for this
interrupt (chan nel A/B, receive/transmi t ) c an be further
determined by read ing register DISR (refer to page 5-
140).
PEB 20542
PEF 20542
Register Des cr iption (GSTAR)
Data Sheet 5-132 2000-09- 14
ISA2 Channel A Interrupt Status Register 2
ISA1 Channel A Interrupt Status Register 1
ISA0 Channel A Interrupt Status Register 0
ISB2 Channel B Interrupt Status Register 2
ISB1 Channel B Interrupt Status Register 1
ISB0 Channel B Interrupt Status Register 0
These bit s indicate, t hat an interrup t indic ation is pending in the
corres ponding interrupt sta tu s register(s) ISR0/ISR1/ISR2 of th e serial
communication controller (SCC):
bit=’0’No interrupt indication is pending.
bit=’1’An interrupt indicat i on is pending.
PEB 20542
PEF 20542
Register Description (GPDIR)
Data Sheet 5-133 2000-09- 14
Register 5 GPDIR
GPP Directi on Regis t er
CPU Accessibility: read/write
Reset Value : FFH
Offs et Address: 05H
typica l us age: written by C PU ev aluated by SER OC C O-D
Bit76543210
GPP I/O Direction Contr ol
11111GP2DIR GP1DIR GP0DIR
GPnDIR GPP Pin n Direction Control (-)
This bit selects between input and output func tion of the co rresponding
GPP pin:
bit = ’0’output
bit = ’1’in put (reset value)
PEB 20542
PEF 20542
Register Des cription (GPDAT)
Data Sheet 5-134 2000-09- 14
Register 6 GPDAT
GPP Data Regist er
CPU Accessibility: read/write
Reset Value : -
Offs et Address: 07H
typical usage: writ te n by C PU(outputs ) and SEROCC O -D (inputs),
evaluat ed by SEROCCO-D(out put s ) and CPU(inp ut s )
Bit76543210
GPP Data I/O
-0---GP2DAT GP1DAT GP0DAT
GPnDAT GPP Pin n Data I/O Value (-)
This bit indicates the value of the corresponding GPP pin:
bit = ’0’If direction is input: inpu t le vel is ’low’;
if direc ti on is out put: output level is ’low’.
bit = ’1’If direction is input: inpu t le vel is ’high’;
if direc ti on is out put: output level is ’high’.
PEB 20542
PEF 20542
Register Descri p t i on (GPIM )
Data Sheet 5-135 2000-09- 14
Register 7 GPIM
GPP Interrupt Mas k Regi ste r
CPU Accessibility: read/write
Reset Value : FFH
Offs et Address: 09H
typical usage: w rit te n by CPU, eva luated by SE ROCCO- D
Bit76543210
GPP Interru pt Mask Bits
11111GP2IM GP1IM GP0IM
GPnIM GPP Pin n Interrupt Ma sk (-)
This bit c ont rols the interrupt mask of the c orresponding GPP pin:
bit = ’0’Interrupt generation is enabled. An interrupt is generated
on an y s t at e transition of the corresponding port pin
(inputs).
bit = ’1’Int errupt gene rat i on is disabled (res et value).
PEB 20542
PEF 20542
Register Description (GPIS)
Data Sheet 5-136 2000-09- 14
Register 8 GPIS
GPP Interrupt Status Register
CPU Accessibility: read only
Reset Value : 00H
Offs et Address: 0BH
typica l us age: written by SER OCCO-D, read and evalu at ed by CPU
Bit76543210
GPP Interrupt Status Bits
00000GP2I GP1I GP0I
GPnI GPP Pin n Interrupt Indiction (-)
This bit indicates if an interrupt event occured on the corresponding GPP
pin:
bit = ’0’No interrupt indication is pending at this pin (no state
transition has occured).
bit = ’1’A n int errupt indication is pending (a st at e t ransitio n
occured). The int errupt indication is cleared afte r read
access.
PEB 20542
PEF 20542
Register Des cr iption (DCMDR)
Data Sheet 5-137 2000-09- 14
Register 9 DCMDR
DMA Command Register
CPU Accessibility: read/write
Reset Value : 00H
Offs et Address: 0CH
typical usage: w rit te n by CPU, eva luated by SE ROCCO- D
Bit76543210
DMA Controller Reset Command Bits
RDTB DTACK
TB RDRB DTACK
RB RDTA DTACK
TA RDRA DTACK
RA
RDTB Reset DMA Transmit Channel B
RDRB Reset DMA Receive Channel B
RDTA Reset DMA Transmit Channel A
RDRA Reset DMA Receive Channel A
Self-clearing command bit.
These bi ts bring the corre spo nding DMA channel to the reset st ate:
bit=’0’No reset is performed.
bit=’1’Reset is perfor me d.
PEB 20542
PEF 20542
Register Des cr iption (DCMDR)
Data Sheet 5-138 2000-09- 14
DTACKTB DMA Transfer Ack Transmit Channel B
DTACKRB DMA Transfer Ack Receive Channel B
DTACKTA DMA Transfer Ack Transmit Channel A
DTACKRA DMA Transfer Ack Receive Channel A
Only valid in internal DMA controll er modes.
bit = ’0’The data tran s fe r acknowledge signa l on pin DTACK/
READY p in is igno red for data tran sfer cycle s initiate d by
the SEROCCO-D DMA controller .
bit = ’1’For data transfer cycles initiated by the internal DMA
cont roller the hands hake signa l DTAC K/READY is
evaluated by SER OCCO-D. T his can be used t o ex t e nd
the duration of read or write cycles.
PEB 20542
PEF 20542
Register Description (DMODE)
Data Sheet 5-139 2000-09- 14
Register 10 DMODE
DMA Mode Register
CPU Accessibility: read/write
Reset Value : 00H
Offs et Address: 0DH
typical usage: w rit te n by CPU, eva luated by SE ROCCO- D
Bit76543210
DMA Controller Operation M ode
0 TMODEB 0 RMODEB 0 TMODEA 0 RMODEA
TMODEB Transmit DMA Mode Channel B
RMODEB Receive DMA Mode Channel B
TMODEA Transmit DMA Mode Channel A
RMODEA Receive DMA Mode Channel A
These bit s select the operating mode of the corres ponding DM A
channel:
’0’Sing le Buffer Mo de (s t andard mode)
Used base address registers are TBADDR1L/M/H
(transmit) and RBADDR1L/M/H (receive).
’1’Swit ched Buffe r Mode
Base address registers sw itch alternating fr om
TBADDR1L/M/H and RBADDR1L/M/H to
TBADDR2L/M/H and RBADDR2L/M/H.
Afte r reset, trans m it and rece iv e buffers #1 are selected.
PEB 20542
PEF 20542
Register Description (DISR)
Data Sheet 5-140 2000-09- 14
Note: Interrupt indications are stored even if masked in register DIMR. Pending
interrupts get presented to the system as soon as they get unmasked.
Register 11 DISR
DMA Interrupt St atus Register
CPU Accessibility: read only
Reset Value : 00H
Offs et Address: 0EH
typica l us age: written by SER OCCO-D, ev aluated by CPU
Bit76543210
DMA Interrupt Status Register
0 RBFB RDTEB TDTEB 0 RBFA RDTEA TDTEA
RBFB Receive Buffer Full Channel B
RBFA Receive Buffer Full Channel A
If a receive buffer size is defined in registers RMBSL/RMBSH and during
reception the end of the receive buffer is reached this interrupt is
gene rated indicatin g that the rece ive buffer is full. The corresponding
DMA channel suspends the write transfers to memory until a new b uffer
is allocated and res umes the reception.
RDTEB Receive DMA Transfer End Channel B
RDTEA Receive DMA Transfer End Channel A
This bit set to ’1’ indicates that a DMA transfer of receive data is finished
and the rec eive data is completely mo v ed to the corre s ponding receiv e
buffer in host m e m ory.
If this completed DMA transfer filled up the receive buffer (i.e. the receive
byte count RBC matches the buffer size RMBS), bit RBFA/B is also set.
PEB 20542
PEF 20542
Register Description (DISR)
Data Sheet 5-141 2000-09- 14
TDTEB Transmit DMA Transfer End Channel B
TDTEA Transmit DMA Transfer End Channel A
This bit set to ’1’ indicates that a DMA transfer of transmit data is finished
and the data is completely moved from the transmit buffer to the on-chip
transmit FIFO.
PEB 20542
PEF 20542
Register Description (DIMR)
Data Sheet 5-142 2000-09- 14
Register 12 DIMR
DMA Interrupt Mask Register
CPU Accessibility: read/write
Reset Value : 77H
Offs et Address: 0FH
typical usage:
Bit76543210
DMA Interrupt Mask Register
0 MRBFB MRDTEB MTDTEB 0 MRBFA MRDTEA MTDTEA
MRBFB Mask Receive Buffer Full Interrupt Channel B
MRBFA Mask Receive Buffer Full Interrupt Channel A
MRDTEB Mask Receive DMA Transfer End Interrupt Channel B
MRDTEA Mask Receive DMA Transfer End Interrupt Channel A
MTDTEB Mask Transmit DMA Transfer End Interrupt Channel B
MTDTEA Mask Transmit DMA Transfer End Interrupt Channel A
If a bit in this interrupt mask register is set to ’1’, the corresponding
inte rrupt is not generated and no t indicated in the corresponding bit
position in the DISR register. After reset all inte rrupts are masked.
PEB 20542
PEF 20542
Register Description (FIFOL)
Data Sheet 5-143 2000-09- 14
5.2.2 Channel Specific SCC Registers
Each register desc ription is org anized in three parts:
•a hea d with ge neral infor mation about res et value , acce ss type (r ead/wr ite), ch annel
spec ific offset addresses and usual hand ling;
•a table containing the bit information (name of bit positions) distinguished for the three
major protocol m od es HDLC /PPP (H ), ASYNC (A) and BISYNC (B);
•a section containing the detailed description of each bit; the corresponding modes, the
bit is v alid for, are ma rk ed again by a bracket term right beside the full bit nam e.
Register 13 FIFOL
Receive/Transmit FIFO (Low Byte)
CPU Accessibility: read/write
Reset Value : -
Channel A Channel B
Offs et Address: 10H60H
typical usage: XFIFO: written by CPU, evaluated by SEROCCO-D
RFIFO: w ritten by SE ROCCO- D , evaluated by CPU
Bit76543210
RFIFO/XFIFO Access Low Byte
FIFO(7:0)
Register 14 FIFOH
Receive/Transmit FIFO (High Byte)
CPU Accessibility: read/write
Reset Value : -
Channel A Channel B
Offs et Address: 11H61H
typical usage: XFIFO: written by CPU, evaluated by SEROCCO-D
RFIFO: w ritten by SE ROCCO- D , evaluated by CPU
Bit76543210
RFIFO/XFIFO Access High Byte
FIFO(15:8)
PEB 20542
PEF 20542
Register Description (FIFOH)
Data Sheet 5-144 2000-09- 14
Receive FIFO (RFIFO)
Reading data from the RFIFO can be done in 8-bit (byte) or 16-bit (word) accesses,
depending on the selected microprocessor bus width using signal ’WIDTH’. In 16-bit bus
mode on ly 16 -bit a cce sse s to R FIFO a re allow e d. O nly for a f ram e wit h odd b yte coun t
the last access can be an 8-bit access.
The size of the accessible part of RFIFO is determined by programming the RFIFO
threshold level in bit field CCR3H.RFTH(1:0). If the HDLC/PPP protocol machine is
selected, the threshold can be adjusted to 32 (reset value), 16, 4 or 2 bytes. With the
ASYNC and BISYNC protocol machines following threshold levels can be selected: 1
(reset value), 4, 16 or 32 bytes.
•Interrupt Controlled Data Transfer (GMODE.IDMA=’0’)
Up to 32 bytes/16 words of received data can be read from the RFIFO following an RPF
or an RME interrupt (see ISR0 register). The address provided during an RFIFO read
access is not incremental; it is always 10H for channel A or 60H f or c hannel B.
RPF Interrupt: This interrupt indicates that the adjusted receive threshold level is
reach ed. The m essage is not y et complet e. A fix numb er of bytes, depende nt from the
threshold level, has to be r ead.
RME Interrupt: The message is completely received. The number of valid bytes is
determined by reading the RBCL, RBCH registers.
The content of the RFIFO is released by issuing the “Receive Message Complete”
command (CMDRH.RMC).
•DMA Controlled Data Transfer (GMODE.IDMA=’1’)
If DMA operation is enabled, the SEROCCO-D takes over control of the receive FIFO
accesses. Refer to “Internal DMA Controller” on Page 81 for details.
Transmit FIFO (XFIFO)
Writing data to the XFIFO can be done in 8-bit (byte) or 16-bit (word) accesses,
depending on the selected microprocessor bus width using signal ’WIDTH’. In 16-bit bus
mode only 16-bit acces ses to XFIF O are allowe d. Only for a f rame with od d byte co unt
the last access must be an 8-bit access.
•Interrupt Controlled Data Transfer (GMODE.IDMA=’0’)
Follow ing an XP R ( or an AL LS) interru pt, u p t o 32 by tes /16 wo rds of ne w tra nsm it data
can b e written into the XFIFO. Transmit data can be released for transmission with an
XTF command. The address provided during an XFIFO write access is not incremental;
it is always 10H for channe l A or 60H for channel B.
•DMA Controlled Data Transfer (GMODE.IDMA=’1’)
If DM A operatio n is enabled , the S EROCCO-D takes over contro l of the tran smit FIF O
accesses. Refer to “Internal DMA Controller” on Page 81 for details.
PEB 20542
PEF 20542
Register Description (STARL)
Data Sheet 5-145 2000-09- 14
Register 15 STARL
Status Register (Low Byte)
CPU Accessibility: read only
Reset Value : 00H
Channel A Channel B
Offs et Address: 12H62H
typical usage: updated by SEROCCO-D
read and ev aluated by CPU
Bit76543210
Mode
Command Status Tra nsmitter Status
HXREPE 0 0CEC 0 XDOV XFW CTS
AXREPE 0 TEC CEC FCS XDOV XFW CTS
BXREPE 0 0 CEC 0 XDOV XFW CTS
Register 16 STARH
Status Register (High Byte)
CPU Accessibility: read only
Reset Value : 10H
Channel A Channel B
Offs et Address: 13H63H
typical usage: updated by SEROCCO-D
read and ev aluated by CPU
Bit76543210
Mode
Receiver Status Automode Status
H0 0 CD RLI DPLA WFA XRNR RRNR
A0RFNECD0DPLA000
B0 RFNE CD SYNC DPLA 0 0 0
PEB 20542
PEF 20542
Register Description (STARH)
Data Sheet 5-146 2000-09- 14
XREPE Transmit Repetition Executing (all mode s)
XREPE=’0’No transmit rep etition command is i n exe cution.
XREPE=’1’A XREP command (register CMDRL) is currently in
execution.
TEC TIC Executing (async mode)
TIC=’0’No TIC (transmit im m ediate chara c ter) is curren tly in
transmission. Access to register TICR is allowed to initiate
a TIC transmission.
TIC=’1’A TIC co mmand (write access to register TICR) is
accepted but not completel y executed. No further write
access to register TICR is allowed until ’TIC’ bit is clea red
by SEROCCO-D.
CEC Command Executing (all mode s)
CEC=’0’No comma nd is currently in ex ec ution. The c om m and
registers CMDRL/CMDRH can be written by CPU.
CEC=’1’A comm and (writte n previously to registers CMDRL/
CMDRH) is currently in execution. No further command
can be wr it t en t o registers CMDRL/CMDRH by CPU.
Note: CEC will stay active if the SCC is in power-down mode or if no
serial c loc k , n eeded for comm and execut ion, is av ailable.
FCS Flow Control Status (async mode)
If (in-band) flow control mechanism is enabled via bit ’FLON’ in register
CCR2H this bit indicates the current state of transmitter:
FCS=’0’Transmitter is ready (always after transmitter reset
command or XON-character detected).
FCS=’1’Transmitter is stopped (XOFF-character detected).
PEB 20542
PEF 20542
Register Description (STARH)
Data Sheet 5-147 2000-09- 14
XDOV Transmit FIFO Data Overflow (all mode s)
XDOV=’0’Less than or equal to 32 bytes have been written to the
XFIFO.
XDOV=’1’More than 32 bytes have been written to the XFIFO. This
bit is reset by:
–a transmi tter reset command ’XRES’
–or when all bytes in the accessible half of the XFIFO
have be en m ov ed into the inac cessible half .
XFW Transmit FIFO Write Enable (all modes)
XFW=’0’The XFIFO is not able to accept further transmit data.
XFW=’1’Transmit data can be written to the XFIFO.
CTS CTS (Clear To Send) Input Signal State (all modes)
CTS=’0’CTS input signal is inactiv e (high level)
CTS=’1’CTS input signal is active (low level)
Note: A transmit clock is necessary to dete ct the input level of CTS.
Optionally this inpu t can be pro gramm ed to genera te an inte rrupt
on signal level changes.
RFNE Receive FIFO Not Empty (async/bisync modes)
This st atus bit i s set if the SCC recei ve FIFO (RFI FO) ho lds at least one
valid byte.
RFNE=’0’The receive FIFO is empty.
RFNE=’1’The receive FIF O is not empty.
CD CD (Carrier Detect) Input Signal State (all modes)
This status bit gives the signal state of CD inpu t. This bit value is
indep endent of the programmed polarity of th e C arrier Detec t function
(bit ’ICD’ in register CCR1H).
CD=’0’CD input signal is low.
CD=’1’CD input signal is high.
Note: Option ally this input can be progra mmed to gen erate an int errupt
on signal level changes.
PEB 20542
PEF 20542
Register Description (STARH)
Data Sheet 5-148 2000-09- 14
SYNC Synchronization Status (bisync mode)
This bit indicates whether the receive r is in synchronized sta te. After a
’HUNT’ command ’SYNC’ bit is cleared and the receiver starts searching
for a SYN C ch aracter. When found th e ’SYNC’ status bit is set
immediately, an SCD-interrupt is generated (if enabled) and receive data
is forw arded to the re ceiver FIFO.
SYNC=’0’Synchronization is lost or not yet achieved.
(after reset or after new ’HUNT’ comm and has be en
issue d and befo re SYNC charac t er is found)
SYNC=’1’The receiver is in synchronized state.
RLI Receive Line Inactive (hdlc mode)
This bit indicates that neither flags as interframe time fill nor data are
being received via the receive line.
RLI=’0’Receive line is active, no consta nt high level is detected.
RLI=’1’Receive line is inactive, i.e. more than 7 consec utive ’1’
are de tected on the line.
Note: A receive clock must be provided in order to detect the receive line
state.
DPLA DPLL Asynchronous (all mode s)
This bit is only valid if the receive clock is recovered by the DPLL and
FM0, FM1 or Manchester data enc oding is selected. It is se t when the
DPLL has lost s yn c hronization . In this case reception is dis a bled
(receiv e abort cond ition) until sy nchroniz at ion has been regained. In
addition transm ission is interrupte d in all c ases where transm it clock is
derived from the DPLL (clock mode 3a, 7a). Interruption of transmission
is performed the same way as on deactivation of the CTS s ignal.
DPLA=’0’DPLL is s yn c hronized.
DPLA=’1’DPLL is as y nchronous (re-s ynchron ization proc es s is
started aut om atically).
PEB 20542
PEF 20542
Register Description (STARH)
Data Sheet 5-149 2000-09- 14
WFA Wait For Acknowledgement (hdlc mode)
This status bit is significan t in Au to mod e only. It ind i cates whether the
Automode state machine expects an acknowledging I- or S-Frame for a
previously sent I-Fram e.
WFA=’0’No acknowledge I/S-Frame is expected.
WFA=’1’The Automode st at e m ac hine is waiting for an
achnowledging S- or I-Frame.
XRNR Transmit RNR Status (hdlc mode)
This status bit is significan t in Auto mod e only. It in d i cates the receive r
status of the local station (SCC).
XRNR=’0’The receiver is read y and will automatically answer poll-
frames with a S-Frame with ’receiver-ready’ indication.
XRNR=’1’The receiver is NOT ready and will automatically answer
poll- frames with a S-Frame with a ’receiver-not-ready’
indication.
RRNR Received RNR (Receiver Not Ready) Status (hdlc mode)
This status bit is significan t in Auto mod e only. It in d i cates the receive r
status of the remote station.
RRNR=’0’The remote station receive r i s re ady .
RRNR=’1’The remote receiver is NOT ready.
(A ’receiver-not -ready’ indic at ion was rece iv ed f r om t he
remot e s t at ion)
PEB 20542
PEF 20542
Register De scription (CMDRL)
Data Sheet 5-150 2000-09- 14
The c ommand re gister co ntains se lf-clearing c ommand bits. T he comma nd bits re ad a
’1’ until the cor responding c om mand is exec ut ed completely.
Register 17 CMDRL
Command Regist er (Low Byte)
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 14H64H
typical usage: w rit te n by CPU, eva luated by SE ROCCO- D
Bit76543210
Mode
Timer Transmitter Commands
HSTI TRES XIF XRES XF XME XREP 0
ASTI TRES TXON XRES XF XME XREP TXOFF
BSTI TRES 0 XRES XF XME XREP 0
Register 18 CMDRH
Command Regist er (High Byte )
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 15H65H
typical usage: w rit te n by CPU, eva luated by SE ROCCO- D
Bit76543210
Mode
Receiver Commands
HRMC RNR 0 0 RSUC 0 0 RRES
ARMC 0 0 0 0 0 RFRD RRES
BRMC 0 0 0 HUNT 0 RFRD RRES
PEB 20542
PEF 20542
Register Des cr iption (CMDRH)
Data Sheet 5-151 2000-09- 14
For a write access to the register, the new value gets OR’ed with the current register
contents.
The ’CEC’ bit in register STARL/STARH is the OR -f unction ov er all command bits.
STI Start Timer Command (all modes)
Self-clearing command bit:
HDLC Automode:
In HDLC Automode the timer is used internally for the autonomous
protocol support functions. The timer is started automatically by the SCC
when an I-Frame is sent o ut a nd needs to be acknow ledged.
If the ’STI’ comm and is issu ed by software:
STI=’1’A n S-Frame wi t h poll bit set is sent out and the internal
timer is started expecting an acknowledge from the
remo t e station via an I- or S- F rame.
The tim er is stopped after rec eiv ing an ackn ow ledge
otherwise the timer expires generating a timer interrupt.
Note: In HDLC Automode, bit ’TMD’ in register TIMR3
must be set to ’1’
All protocol modes except HDLC Automode:
In thes e m odes the t im er is operating as a general purp os e t i m er.
STI=’1’This commands starts timer operation.
The tim er can be stopped by se tt ing bit ’TRES’.
Note: Bit ’TMD’ in register TIMR3 must be cleared for
proper operation
TRES Timer Reset (all modes)
Self-clearing command bit.
This bit deactivates tim er operation:
TRES=’0’Timer operation ena bled.
TRES=’1’Timer operation st opped.
XIF Transmit I-Frame (hdlc mode)
Self-clearing command bit.
This command bit is significant in HDLC Autom od e only.
XIF=’1’Initiates the transmission of an I-frame in auto-mode.
Additional to the opening flag , the addr ess an d con t r ol
fields of the frame are added by SEROCCO-D.
PEB 20542
PEF 20542
Register Des cr iption (CMDRH)
Data Sheet 5-152 2000-09- 14
TXOFF Transmit Off Command (async mode)
Self-clearing command bit:
This command bit is significant if in-band flow-control is selected.
TXOFF=’1’Forces the transmitter to enter its ’transmit off’ state. This
is equal to receiving an XO FF character.
TXON Transmit On Command (async mode)
Self-clearing command bit:
This command bit is significant if in-band flow-control is selected.
TXON=’1’Forces the transmitter to enter its ’transmit on’ state. This
is equal to receiving an XO N character .
XRES Transmitter Rese t C ommand (all modes)
Self-clearing command bit:
XRES=’1’T he SCC tr ansmit FIF O is cleared and t he transm itt er
protoc ol engines are reset to their initial state.
A transmitte r reset command is recommended after all
changes in protoc ol m ode configurations ( e. g. swit ching
betw een the protocol engines HDLC / ASYNC/BI SYNC or
sub-modes of HDLC).
XF Transmit Frame (all modes)
This self-clearing command bit is significant in interrupt driven operation
only (GMODE.IDMA=’0’).
XF=’1’After having written up to 32 bytes to the XFIFO, this
com mand initiate s transmis s ion. In pack et oriented
protocols like HDLC/PPP the opening flag is automatically
added by SEROCCO-D. If the end of the packet is part of
the transmit data, bit ’XME’ should be set in addition.
DMA Mode
After having written the lengt h of the data bl oc k to be
tra nsmitted to regi sters XBC1L an d XBC1H, this
command initiates the data transfer from host memory to
SEROCCO-D by DMA. Transmission on the serial side
starts as soon as 32 bytes are transferred to the XFIFO or
the transmit byte coun ter value is reac hed.
PEB 20542
PEF 20542
Register Des cr iption (CMDRH)
Data Sheet 5-153 2000-09- 14
XME Transmit Message End (hdlc/bisyn c mod es)
Self-clearing command bit:
XME=’1’Indicates that the data block written last to the XFIFO
contains the end of the packet. This bit should always be
set in conjunction with a transmit command (’XF’ or ’XIF’).
XREP Transmission Repeat Command (hdlc mode)
Self-clearing command bit:
XREP=’1’If bit ’XREP’ is set together with bit ’XME’ and ’XF’,
SEROCCO-D repeatedly transmits the co nt ents of the
XFIFO (1..32 bytes).
The cy c lic transmis sion can be stopped wit h the ’XRES’
command.
RMC Receive Message Complete (all modes)
Self-clearing command bit:
RMC=’1’With this bit the CPU indicates to SEROCCO-D that the
current receive data has been fe tched out of the RFIFO.
Thus th e corresp onding spac e in t he RFIFO c an be
released and re-used by SEROCCO-D fo r further
incoming data.
RNR Receiver Not Ready Command (hdlc mode)
NON self-clearin g com m an d bit:
This command bit is significant in HDLC Autom od e only.
RNR=’0’Forces the receiver to enter its ’receiver-ready’ state. The
receiv er acknowledges received poll or I -Frames wit h a
’receiver-ready’ indication.
RNR=’1’Forces th e re ceiver to enter its ’receiver-not-ready’ state.
The receiver acknowledges received poll or I-Frames with
a ’receiver-not-ready’ indication.
RSUC Reset Signaling Unit Counter (hdlc mode)
Self-clearing command bit:
This command bit is significant if HDLC SS7 mode is selected .
RSUC=’1’The Signaling System #7 (SS7) unit counter is reset.
PEB 20542
PEF 20542
Register Des cr iption (CMDRH)
Data Sheet 5-154 2000-09- 14
HUNT Enter Hunt State Command (bisync mode)
Self-clearing command bit:
HUNT=’1’This command forces the receive r to enter its ’HUNT’
state im m ediately. T hus synchro nization is ’lost’ an d t he
receiv er starts searching fo r new SYNC c haracters .
RFRD Receive FIFO Read Enable Command (async/bisync modes)
Self-clearing command bit:
RFRD=’1’This command forces insertion of a ’block end’ condition
into the RFIFO before the receive FIFO threshold is
exceeded or a block end condition (termination character
detected or time-out) is fulfilled . The execution of this
command is reported with a TCD interrupt.
RRES Receiver Re set Command (all modes)
Self-clearing command bit:
RRES=’1’The SCC rec eive FIFO is cleared an d the receiver
protoc ol engines are reset to their initial state.
The SCC receive FIFO accepts new receive data from the
protoc ol engine im mediatel y after receiver rese t
procedure.
It is recommended to disabl e data reception before
issuing a receiv er reset command by setting bit
CCR3L.RAC = ’0’ and enabling data reception afterwards.
A ’receiver reset’ command is recommended after all
changes in protoc ol mode conf igurations (swit c hing
betw een the proto c ol engines HDLC / ASYNC/BI SYNC or
sub-modes of HDLC).
PEB 20542
PEF 20542
Register Description (CCR0L)
Data Sheet 5-155 2000-09- 14
Register 19 CCR0L
Channel Configuration Register 0 (Low Byte)
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 16H66H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
misc. Clock Mode Selection
HVIS PSD BCR TOE SSEL CM(2:0)
AVIS PSD BCR TOE SSEL CM(2:0)
BVIS PSD 0 TOE SSEL CM(2:0)
Register 20 CCR0H
Channel Configuration Register 0 (High Byte)
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 17H67H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Power Line Coding Protocol Mode
HPU SC(2:0) 0 0 SM(1:0)
APU SC(2:0) 0 0 SM(1:0)
BPU SC(2:0) 0 0 SM(1:0)
PEB 20542
PEF 20542
Register Description (CCR0H)
Data Sheet 5-156 2000-09- 14
VIS Masked Interr u pts Visible (all modes)
VIS=’0’M asked inte rrupt status bits ar e not dis p layed in the
interrupt status registers (ISR0..ISR2).
VIS=’1’Masked inte rrupt stat us bits ar e visible a n d automatical ly
cleared after interrupt statu s regis ter (ISR0..ISR2) rea d
access.
Note: Interrupts masked in registers IMR0..IMR2 will not generate an
interrupt.
PSD DPLL Ph ase Shift Disab l e (all modes)
This option is only applicable in the case of NRZ or NRZI line encod ing
is selected.
PSD=’0’N ormal DPLL operation.
PSD=’1’T he phase s h if t f unction of the DPLL is dis abled. Th e
windows for phas e adjustment are extended.
BCR Bit Clock Rate (asyn c P PP, ASYNC mode s)
This bit is only valid in asyn c h ronous PPP and ASYNC protocol mode
and on ly in clock mod es not using the DPLL (0, 1, 3b, 7b). It is also
invalid in clock mode 4.
BCR=’0’Selects isochronou s operation wit h bit clock rat e 1. Data
bits are sampled once.
BCR=’1’Selects standa rd asynch ronous operat ion with bit clock
rate 16. Using 16 samples per bit, data bits are sampled 3
time s around th e nominal bit center. The resulting bit
value is determined by majority decision of the 3 samples.
For correct ope rat i on NRZ da ta encod i ng has to be
selected.
PEB 20542
PEF 20542
Register Description (CCR0H)
Data Sheet 5-157 2000-09- 14
TOE Transmit Clock Out Enable (all modes)
For clock modes 0b, 2b, 3a, 3b, 6b, 7a and 7b, the internal transmit clock
can be monitored on pin TxCLK as an output signal. In clock mode 5, a
time slot control signal marking the active transmit time slot is output on
pin TxC LK.
Bit ’TOE’ is invalid for all other clock modes.
TOE=’0’TxCLK pin is input.
TOE=’1’TxCLK pin is switched to output function if applicable for
the selected clock mode.
SSEL Cl ock Source Select (all modes)
Distinguishes between the ’a’ and ’b’ option of clock modes 0, 2, 3, 5, 6
and 7.
SSEL=’0’Option ’a’ is selected.
SSEL=’1’Option ’b’ is selected.
CM(2:0) C lock Mode (all modes)
This bit field selec ts one of main cloc k modes 0..7 . F or a detailed
descri ption of the clock modes refer to Chapter 3.2.3
CM = ’000’clock mode 0
CM = ’001’clock mode 1
CM = ’010’clock mode 2
CM = ’011’clock mode 3
CM = ’100’clock mode 4
CM = ’101’clock m ode 5 (time-slot oriente d clocking modes)
CM = ’110’clock mode 6
CM = ’111’clock mode 7
PU Power Up (all modes)
PU=’0’The SCC is in ’power-down’ mode. The protocol engines
are switched off (standby) and no operation is performed.
This may be used to save power when SCC is not in use.
Note: The SCC tr ansmit FIFO acce pts transmi t data even
in ’power-down’ mode.
PU=’1’Th e SC C is in ’power-up’ mode.
PEB 20542
PEF 20542
Register Description (CCR0H)
Data Sheet 5-158 2000-09- 14
SC(2:0) Serial Port Configuration (all modes)
This bit field selec ts t he line coding of the seria l port .
Note, that special operation modes and settings may require or exclude
operation in special line coding modes. Refer to the ’prerequisites’ in the
dedicat ed mode descriptions.
SC = ’000’NRZ data encoding
SC = ’001’B us configu rat ion, timing mode 1 (NRZ dat a enc oding)
SC = ’010’NRZI data encoding
SC = ’011’B us configu rat ion, timing mode 2 (NRZ dat a enc oding)
SC = ’100’FM0 data encodi ng
SC = ’101’FM1 data encodi ng
SC = ’110’Manchester data encoding
SC = ’111’Reserved
Note: If b us co nfigurat ion mo de is s elected, only NRZ data encoding is
supported.
SM(1:0) Serial Port Mode (all modes)
This bit field selec ts one of the th ree protocol engines.
Depend ing on the selected protocol engine the SCC related registers
change or special bit positions within the registers change their meaning.
SM = ’00’HDLC/PPP protocol engine
SM = ’01’Reserved
(do no t use)
SM = ’10’B IS YN C protocol engine
SM = ’11’ASYNC protocol engine
PEB 20542
PEF 20542
Register Description (CCR1L)
Data Sheet 5-159 2000-09- 14
Register 21 CCR1L
Channel Configuration Register 1 (Low Byte)
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 18H68H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
misc.
HCRL C32 SOC(1:0) SFLG DIV ODS 0
A00000DIVODS0
B00000DIVODS0
Register 22 CCR1H
Channel Configuration Register 1 (High Byte)
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 19H69H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
misc.
H0 ICD 0 RTS FRTS FCTS CAS TSCM
A0 ICD 0 RTS FRTS FCTS CAS TSCM
B0 ICD 0 RTS FRTS FCTS CAS TSCM
PEB 20542
PEF 20542
Register Description (CCR1H)
Data Sheet 5-160 2000-09- 14
CRL CRC Reset Value (hdlc mode)
This bit defines the initial value of the internal transmit/receive CRC
generators:
CRL=’0’Initial value is 0xFFFFH (16 bit CRC), 0xFFFFFFFFH
(32 bit CRC).
This is the default value for most HDLC/PPP applications.
CRL=’1’Initial value is 0x0000H (16 bit CRC), 0x00 0 0000 0H
(32 bit CRC).
C32 CRC 32 Select (hdlc mode)
This bit enables 32-bit CRC operation for transmit and receive.
C32=’0’16-bit CRC-CCITT generation/checking.
C32=’1’32-bit CRC generation/checking.
Note: The internal ’valid frame’ criteria is updated depending on the
selected number of CRC-bytes.
SOC(1:0) Serial Output Control (hdlc mode)
This bit field selec ts t he R TS signal outp ut function.
(This bit field is only valid in bus configuration modes selected via bit field
SC(2:0) in register CCR0H).
SOC = ’0X’RTS ouput signal is active during transmission of a frame
(active low).
SOC = ’10’RTS ouput signal is alw ays inactive (high).
SOC = ’11’RTS ouput signal is active during reception of a frame
(active low).
SFLG Shar ed Fla g s Tra nsmission (hdlc mode)
This bit en ables ’share d flag transmis s ion’ in HDLC protocol mode. If
another transmit frame begin is stored in the SCC transmit FIFO, the
closing flag of the preceding frame becomes the opening flag of the next
frame ( s ha red flags):
SFLG = ’0’Shared flag transmission disabled.
SFLG = ’1’Shared flag transmission enabled.
Note: The receiver always supports shared flags and shared zeros of
consecutive flags.
PEB 20542
PEF 20542
Register Description (CCR1H)
Data Sheet 5-161 2000-09- 14
DIV Data Inver sion (all mode s)
This bit is only valid if NRZ data encoding is selected via bit field SC(2:0)
in register CCR0H.
DIV=’0’No Data Inversion.
DIV=’1’Data is t ransmitte d/received inverted (on a per bit basis ).
In HDLC and HDLC Sync hronous PPP modes the
continuous ’1’ idle sequence is NOT inverted. Thus it is
recomme nd ed to sel e ct the flag sequence fo r interfra me
time fill transmission (CCR2H:ITF = ’1’), which is inverted.
ODS Outpu t D river Select (all modes)
The transmit data output pin TxD can be configured as push/pull or open
drain o ut put c hrac t eristic.
ODS=’0’TxD pin is op en drain output.
ODS=’1’TxD pin is pu sh/pull o ut put .
ICD Invert Carrier Detect Pin Polarity (all modes)
ICD=’0’Carrier Dete ct (CD) input pin is active high.
ICD=’1’Carrier Detect (CD) input pin is active low.
RTS Request To Send Pin Control (all modes)
The request to send pin RTS can be controlled by SEROCCO-D as an
outp ut aut onomou s ly or via se t ting/clear ing bit ’RTS’.
This bit is not valid in clock mode 4.
RTS=’0’Pin RTS (output) pin is controlled by SEROCCO-D
autonomously.
HDLC Mode:
RTS is activated during transmission. In bus configuration
mode t he functionality depends on bi t f ield ’SOC’ setting.
Note: For autono mous RTS pin cont rol a transmit clock is
necessary.
ASYNC/BISYNC Mode:
The functionality depe nds on se tt ing of bit ’FRTS’
RTS=’1’Pin RTS can be controlled by software. The output level of
this pi n depends on bit ’FRTS’.
PEB 20542
PEF 20542
Register Description (CCR1H)
Data Sheet 5-162 2000-09- 14
FRTS Flow Control (using signal RTS)(a ll m odes)
Bit ’FRTS’ together with bit ’RTS’ determine the fu nc tion of sign al RTS:
RTS, FRTS
0, 0 P in RT S is cont rolled by SEROC C O-D auton omously.
RTS is activated (low) as soon as tran smit data is
available w ithin the SC C transm it FIFO.
0, 1 P in RT S is cont rolled by SEROC C O-D auton omously
supporting bi-dire c tional data flow control.
RTS is activated (low) if the shadow part of the SCC
receiv e F I FO is empty and de-activat ed (high) when the
SCC receive FIFO fill level reaches its receive FIFO
threshold.
1, 0 Forces pin RTS to active state (low).
1, 1 Forces pin RTS to inactive state (high).
FCTS Flow Control (using signal CTS) (a ll m ode s)
This bit controls the function of pin CTS.
FCTS = ’0’The tr ansmitter is stopped if CTS input signa l is inactive
(high) and enabled if ac t iv e (low).
Note : In the c haracter oriented pro tocol mo des (ASYNC ,
BISYNC, asynchronous PPP), the current byte is
completely sent even if CTS becomes inactive
during transmission.
FCTS = ’1’The transmitter is enabled, disregarding CTS input si gnal.
PEB 20542
PEF 20542
Register Description (CCR1H)
Data Sheet 5-163 2000-09- 14
CAS Carrier Detect Auto Start (all modes)
CAS = ’0’The CD pin is us ed as general input.
In clock mode 1, 4 and 5, clock mode specific contr ol
signals must be provided at this pin (re ce i v e strobe,
receiv e gating RCG, frame sync clock FSC).
A pull- up/ down resistor is recomme nded if unuse d.
CAS = ’1’The CD pin enables/disables the receiver for data
recept ion. (Polarity of CD pin can be con fig ured via bit
’ICD’.)
Note: ( 1) In clock mode 1, 4 and 5 this bit m ust be set to ’0’.
(2) A receive clock must be provided for the autonomous receiver
control function of the CD input pin.
(3) In ASYNC mode the transmitter is additionally controlled by in-
band flow control mechani sm (i f en abled).
TSCM Time Slot Control Mode (all modes)
This bit controls internal counter operation in time slot oriented clock
mode 5:
TSCM=’0’The intern al c ounter keep s running, restarting with zero
after being expired.
TSCM=’1’The internal counter stops at its maximum value and
resta rt s wit h t he next frame sync pulse again.
PEB 20542
PEF 20542
Register Description (CCR2L)
Data Sheet 5-164 2000-09- 14
Register 23 CCR2L
Channel Configuration Register 2 (Low Byte)
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 1AH6AH
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
misc.
HMDS(1:0) ADM NRM PPPM(1:0) TLPO TLP
A000000TLPOTLP
B0000SLENBISNCTLPOTLP
Register 24 CCR2H
Channel Configuration Register 2 (High Byte)
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 1BH6BH
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
misc.
HMCS EPT NPRE(1:0) ITF 0 OIN XCRC
A0000000FLON
B0 EPT NPRE(1:0) ITF 0 CAPP CRCM
PEB 20542
PEF 20542
Register Description (CCR2H)
Data Sheet 5-165 2000-09- 14
MDS(1 : 0) Mod e Select (hdlc modes)
This bit field selects the HDLC pro to c ol sub-mode inc luding the
’extended transparent mode’.
MDS = ’00’Automode.
MDS = ’01’Address Mod e 2.
MDS = ’10’Address Mod e 0/1.
(Option ’0’ or ’1’ is selected via bit ’ADM’.)
MDS = ’11’Extended transparent mode (bit transparent transmission/
reception).
Note: ’MDS(1:0)’ must be set to ’10’ if any PPP mode is enabled via bit
field ’PPPM’ or if SS7 is enabled via bit ’ESS7’ in register CCR3L.
ADM Address Mode Selec t (hdlc modes)
The meaning of this bit dep ends on th e selected prot ocol sub-m ode:
Automode, Address Mode 2:
Determines the address f ield length o f an HDLC fra me.
ADM = ’0’8-bit address field.
ADM = ’1’16-bit addr es s field.
Address Mode 0/1:
Determines wheth er address mod e 0 or 1 is s elec t ed.
ADM = ’0’Address Mode 0 (no address recognition).
ADM = ’1’Address Mod e 1 ( high byte address recognit i on).
Extended Transparent Mode:
ADM = ’1’recommended setting
NRM Normal Response Mode (hdlc modes)
This bit is va lid in HDLC Automode operation only and dete rm ines the
function of the Automode LAP-Controller:
NRM = ’0’Full-duplex LAP-B / LAP-D operation.
NRM = ’1’Half-duplex normal res ponse mode (N RM) opera tio n.
PEB 20542
PEF 20542
Register Description (CCR2H)
Data Sheet 5-166 2000-09- 14
PPPM(1:0) PPP M o d e Select (hdlc modes)
This bit field enab les and select s t h e HDLC P PP protocol modes:
PPPM = ’00’No PPP pr o t o c ol operation. The HDLC sub-mode is
determined by bit field ’MDS’.
PPPM = ’01’Octe t s y nchronous PPP proto col operation.
PPPM = ’10’Asynchronous PPP protocol operation.
Bit ’BCR’ in register CCR0L must be set to ensure proper
asynchronous reception.
PPPM = ’11’Bit synchronous PP P protocol operat ion.
Note: ’Address Mode 0’ must be selected by setting bit fiel d ’MDS(1:0)’
to ’10’ and bit ’ADM’ to ’0’ if any PPP mode is enabled.
TLPO Test Loop Out Function (all modes)
This bit is only valid if test loop is enabled and controls whether test loop
transmit data is driven on pin TxD:
TLPO = ’0’Test loo p transmit dat a is driven to TxD pin .
TLPO = ’1’Test loop transmit data is NOT driven to TxD pin. TxD pin
is idle ’1’. Depending on the selected output characteristic
the pin is high impedance (bit CCR1L.ODS =’0’) or driving
high (CCR1L.ODS =’1’).
TLP Test Loop (all modes)
This bit controls the internal test loop between transmit and receive data
signals . The test loo p is closed at the f ar end of serial transmit and
receive line just before the respective TxD and RxD pins:
TLP = ’0’Test loop disabled.
TLP = ’1’Test loop enable d.
The soft ware is resp onsib le t o select a clock mo de which
allows correct reception of transmit data depending on the
extern al clock supply. Tran smit data is sent out via pin
TxD if not disabled with bit ’TLPO’. The receive input pin
RxD is internally dis c onnected du ring test loop operation.
PEB 20542
PEF 20542
Register Description (CCR2H)
Data Sheet 5-167 2000-09- 14
SLEN SYNC Character Length (bisync mod e)
This bit selects the SYNC character length in BISYNC/MONOSYNC
operati on mode:
SLEN = ’0’6 bit (MONOSYNC), 12 bit (BISYNC).
SLEN = ’1’8 bit (MONOSYNC), 16 bit (BISYNC).
BISNC Select MONOSYNC/BISYNC Mode (bisync mode)
This bit s elec t s BISYNC or MONOSYNC operation mo de:
BISN C = ’0’MONOSYNC mode.
BISN C = ’1’BISYNC mode.
MCS Modulo Count Select (hdlc modes)
This bit is va lid in HDLC Automode operation only and dete rm ines the
control field format:
MCS = ’0’Basic operation, one byte control field (modulo 8 counter
operation).
MCS = ’1’Exte nded opera tio n, two bytes contro l field (modulo 128
counter operation).
EPT Enable Preamble Transmis sion (hdlc/bisyn c mod e)
This bit enables preamble tran smission . The preamble is started af ter
interframe time fill (ITF) transmission is stopped because a new frame is
ready to be transmitted. The preamble pattern consists of 8 bits defined
in register PREAMB, which is sent repetitively. The number of repetitions
is deter m ined by bit field ’PRE(1:0)’:
EPT=’0’Preamble transmis sion is disab led.
EPT=’1’Preamble transmis sion is enabled.
Note: Preamble operation does NOT influence HDLC shared flag
transmission if enabled.
PEB 20542
PEF 20542
Register Description (CCR2H)
Data Sheet 5-168 2000-09- 14
NPRE(1:0) Number of Preamble Repetitions (hdlc/bisync mod e)
This bit field determ ines the number of preamb les transm it ted:
NPRE = ’00’1 preamble.
NPRE = ’01’2 preambles.
NPRE = ’10’4 preambles.
NPRE = ’11’8 preambles.
ITF I n t er frame Tim e Fill (hdlc/bisync mod e)
This bit s elec ts the idle stat e of the transm i t pin TxD:
ITF=’0’Continuous logical ’1’ is sent during idle phase.
ITF=’1’HDLC Mode:
Continuous flag sequences are s ent (’01111110’ flag
pattern).
BISYNC Mode:
Continuous SYN ch aracters are output.
Note: It is recommended to clear bit ’ITF’ in bus configuration modes, i.e.
continuous ’1’s are sent as idle sequence and data encoding is
NRZ.
OIN One Insertion (hdlc mode)
In HDLC m ode a one-insertion mechanism sim ilar to the zero-insertion
can be activated:
OIN=’0’The ’1’ insertion m echanism is dis abled.
OIN=’1’In transmit direction a logic al ’1’ is inserted to the seri al
data str eam after 7 con se c ut iv e z eros .
In receive direction a ’1’ is deleted from the receive data
stream after receivi ng 7 consecutive zer o s.
Thi s enables clock in f o r m ation to b e r ecovered from the
receive data stream by means of a DPLL, even in the case
of NRZ dat a encoding, bec ause a tran sition at bit ce ll
bound ar y occurs at least every 7 bits.
PEB 20542
PEF 20542
Register Description (CCR2H)
Data Sheet 5-169 2000-09- 14
XCRC Transmit CRC Checking Mode (hdlc mode)
XCRC=’0’The tr ansmit checksum (2 or 4 bytes) is generated and
app ended to the tr ansmit da ta automatically .
XCRC=’1’The transmit ch ec k s um is not gen erat ed automa t ically.
The checksum is expe cted to be prov ided by softwar e as
the last 2 or 4 byte s in the tr ans m i t data buffe r.
FLON Flow Control Enable (async mode)
In ASYN C mode, in-band flow cont rol is suppor ted:
FLON=’0’No automatic in-band flow-control is performed. However
recognition of a flow c ont rol charact er (XON/XOF F )
caus es alw ay s a maskab l e int errupt event.
FLON=’1’Automa tic in-band f low-contr ol is performed.
Reception of a XOFF character (defined in register XNXF)
turns off the transmitte r af te r th e curre ntly transmit ted
charac t er has been shifted ou t c o m pletely (XO F F st at e).
Reception of a XON character (defined in register XNXF)
resume s the transmit ter from XOF F into XON s tate read y
to sen d av ailable tra ns m it data bytes .
The current flow control state is indicated via bit ’FCS’ in
register Star.
Any transmitter rese t s witches the flow-control logic to
XON state.
CAPP CRC Append (bisync mode)
In BISYNC mode the CRC generator can be activated:
CAPP = ’0’No CRC generation/checking is active in BISYNC mode.
CAPP = ’1’The CRC generator is activated:
1. The CRC generator is initialized every time the
transmission of a new ’frame’ starts. The CRC
initialization value can be selected via bit ’CRL’ in
register CCR2 (for BISYNC operation).
2. The CRC is automati cally to th e last transmit ted data of
a ’frame’.
PEB 20542
PEF 20542
Register Description (CCR2H)
Data Sheet 5-170 2000-09- 14
CRCM CRC Mode Select (bisync mode)
In BISYNC mode th e CRC generator can be configured for tw o differen t
generat or polynoms:
CRCM = ’0’CRC-16:
The polynominal is x16+x15+x2+1.
CRCM = ’1’CRC-CCITT:
The polynominal is x16+x15+x5+1.
PEB 20542
PEF 20542
Register Description (CCR3L)
Data Sheet 5-171 2000-09- 14
Register 25 CCR3L
Channel Configuration Register 3 (Low Byte)
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 1CH6CH
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
misc.
HELC AFX CSF SUET RAC 0 0 ESS7
ATCDE 0 CHL(1:0) RAC DXS XBRK STOP
BTCDE SLOAD CHL(1:0) RAC 0 0 STOP
Register 26 CCR3H
Channel Configuration Register 3 (High Byte)
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 1DH6DH
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
misc.
H0 DRCRC RCRC RADD 0 0 RFTH(1:0)
APAR(1:0) PARE DPS RFDF 0 RFTH(1:0)
BPAR(1:0) PARE DPS RFDF 0 RFTH(1:0)
PEB 20542
PEF 20542
Register Description (CCR3H)
Data Sheet 5-172 2000-09- 14
ELC Enable Length Check (hdlc mode)
This bit is only valid in HDLC SS7 mode:
If the nu m ber of receiv ed octets ex c e eds 272 + 7 wit hin one Sign aling
Unit, reception is abort ed and bit RSTA.RAB is set.
ELC=’0’Length Check disabled.
ELC=’1’Length Chec k enabled.
TCDE Terminatio n Charact er Detection En able (async/bisync modes)
This bit is valid in ASYNC/BISYNC modes only and enables/disables the
termination character detection mechanism:
TCDE = ’0’No receive terminati on character detection is performed.
TCDE = ’1’The termination character detection is enabled. The
receiv e data stream is monitored f or t he oc curence of a
termination character (TC) programmed via register TCR.
When this character is detected, a ’TCD’ interrupt is
gener ated to the CPU (unle ss masked).
Note: If the programmed character length (bit field
’CHL(1:0)’) is less than 8 bits, the most significant
unused bits in register TCR must be set to ’0’.
Otherwise no termination character will be
detected.
AFX Automatic FISU Transmission (hdlc mode)
This bit is only valid in HDLC SS7 mode:
After the co ntents of the transmit FIFO (X FIFO ) ha s be en tra n smi tted
comp let ely , FISUs are transmited a utomatically. These FI SU s contain
the FSN and BSN of the last transm itted Sign aling Unit (pro vided in
XFIFO).
AFX=’0’Automatic FISU transmission disabled.
AFX=’1’Automatic FISU transmission enabled.
PEB 20542
PEF 20542
Register Description (CCR3H)
Data Sheet 5-173 2000-09- 14
SLOAD Enable SYN Character Load (bisync mode)
In BISYNC mode, SYN chara cte rs might be filtere d ou t or store d to the
SCC receive FIFO.
SLOAD=’0’SYN c haracters are filtered ou t and not stored in th e
receive FIFO.
SLOAD=’1’All recei ve d characte rs , inc luding SYN ch aracters, are
stored in the receive FIFO.
CSF Compare Statu s Field (hdlc mode)
This bit is only valid in HDLC SS7 mode:
If the status fields of consecutive LSSUs are equal, only the first will be
stored and every fo llow ing is ignored
CSF=’0’Compare is disabled, all received LSSUs are stored in the
receive FIFO.
CSF=’1’Compar e is e nabled, only th e first one of co nsecutive
equal LSSU s is stored in the rece ive FIFO.
SUET Signalling Unit Counter Threshold (hdlc mode)
This bit is only valid in HDLC SS7 mode:
Defines the number of signaling units received in error that will cause an
error rate high indication (ISR1.SUEX).
SUET=’0’threshold is 64 errored signaling units.
SUET=’1’threshold is 32 errored signaling units.
CHL(1:0) Character Length (async/bisync modes)
This bit field selec ts t he number of da t a bits within a c haracter:
CHL = ’00’8-bit data.
CHL = ’01’7-bit data.
CHL = ’10’6-bit data.
CHL = ’11’5-bit data.
RAC Receiver active (all modes)
Switches the receiver between operational/inoperational states:
RAC=’0’Receiver inactive , rece ive line is ignored.
RAC=’1’Receiv er active.
PEB 20542
PEF 20542
Register Description (CCR3H)
Data Sheet 5-174 2000-09- 14
DXS Disab l e Storage of XON/XOFF Char acters (async mode)
In ASYN C mode, X O N / XOFF cha r ac t e rs m i ght be filter ed out or stored
to the SC C receive FIF O:
DXS=’0’All received c haracters inc luding XON/XOFF charac t ers
are stored in the rec eive FIFO .
DXS=’1’XO N/X OFF ch ar acters are fil tered out and not stor ed in
the receive FIFO.
XBRK Transmit Break (async mode)
XBRK=’0’N ormal tran sm it operatio n.
XBRK=’1’F orces the TxD pin to ’low’ level imme diat ely (break
condition), regardless of any character being currently
transmitted. This command is executed immediately with
the nex t r is ing edge of the transmit cloc k and furt her
trans m ission is disabled. The currently s ent charact er is
lost.
Data stored in the SCC transmit FIFO will be sent as soon
as the bre ak co ndition is cle ar ed (XBRK=’0’). A transmit
reset command (bit ’XRES’ in register CMDRL) does NOT
clear t he break cond it ion automatic ally.
ESS7 Enable SS7 Mode (hdlc mode)
This bit is only valid in HDLC mode only.
ESS7=’0’Disable signaling system #7 (SS7) supp ort .
ESS7=’1’Enable signaling system #7 (SS7) support .
Note: If SS7 mode is enabled, ’Address Mode 0’ must be selected by
setting bit field CCR2L:MDS(1:0) to ’10’ and bit CCR2L:ADM to ’0’.
STOP Stop Bi t number (async mode)
This bit s elec t s the number of s to p bit s per ASYNC c haracter:
STOP=’0’1 stop bit per character.
STOP=’1’2 stop bits per character.
PEB 20542
PEF 20542
Register Description (CCR3H)
Data Sheet 5-175 2000-09- 14
PAR(1:0) Parity Format (async/bisync modes)
This bit field selec ts t he parity gene rat ion/check ing mode:
PAR = ’00’SPACE (’0’), a constant ’0’ is inse r t e d as pari ty bit.
PAR = ’01’Odd pa rity.
PAR = ’10’Even parit y .
PAR = ’11’MARK (’1’), a constant ’1’ is inserted as parity bit.
The received parity bit is stored in the SCC receive FIFO depending on
the sele c ted charac ter format :
•as leadin g bit imme diately prec eding the d ata bits if c haracter len gth
is 5, 6 or 7 bi ts and bit ’DPS’ is cleared (’0’).
•as LSB of the status byte belonging to the character if character length
is 8 bits and the corresponding rece ive FIFO data format is selected
(bit ’RFDF’ = ’1’).
A parity error is indicated in the MSB of the status byte belonging to each
character if enabled. In addition, a parity error interrupt can be
generated.
DRCRC Disable Receive CRC Checking (hdlc mode)
DRCRC=’0’The receiver expects a 16 or 32 bit C R C w ithin a HDL C
frame. CRC processing depends on the setting of bit
’RCRC’.
Frames sh orte r th an ex pecte d ar e mar ked ’invalid’ or are
discarded (refer to RSTA description).
DRCRC=’1’The receiver doe s not expect any CRC within a HDLC
frame. The criteria for ’val id frame’ in dic at i on is updated
accordin gly (re fe r to RSTA description).
Bit ’RCRC’ is ignored.
RCRC Receive CRC Checking Mode (hdlc mode)
RCRC=’0’The received checksum is evalua ted, but NOT forwa rded
to the receive FIFO.
RCRC=’1’The received checksum (2 or 4 bytes) is evaluated and
forw arded to the rec eive FIFO as data.
PARE Par ity En ab l e (async/bisync modes)
PARE=’0’Parity generation/checking is disabled.
PARE=’1’Parity gen eration/checking is enabled.
PEB 20542
PEF 20542
Register Description (CCR3H)
Data Sheet 5-176 2000-09- 14
RADD Receive Address Forward to RFIFO (hdlc mode)
This bit is only valid
–if an HDLC sub-mode with address field support is selected
(Autom ode, Add res s Mode 2, Addr es s Mo de 1)
–in SS7 mode
RADD=’0’The recei ve d H D LC address fie ld (either 8 or 16 bit ,
depen ding on bit ’ADM’) is evaluated, but NOT forwarded
to the receive FIFO.
In SS7 mode, the signaling unit fields ’FSN’ and ’BSN’ are
NOT forwarded to the receive FIFO.
RADD=’1’The recei ve d H D LC address fie ld (either 8 or 16 bit ,
depending on bit ’ADM’) is evaluated and forwarded to the
receive FIFO.
In SS7 mode, the signaling unit fields ’FSN’ and ’BSN’ are
forw arded to the rec eive FIFO .
DPS Data Parity Storage (async/bisync modes)
Only valid if parity ge neration/checking is enabled via bit ’PARE’:
DPS=’0’The parity bit is stored.
DPS=’1’The parity bit is not stored in the dat a by t e c ont aining
character data.
The parity bit is alw a y s st ored in the st at us by te.
PEB 20542
PEF 20542
Register Description (CCR3H)
Data Sheet 5-177 2000-09- 14
RFDF Receive FIFO Data Format (async/bisyn c mod e)
In ASYNC mode, the character format is determined as follows:
Char5P
Data Byte:
0457
Char6
P
0657
Char7
P
0
6
7
Char8
07
RFDF='0'
(no parity bit stored)
Char5P
Data Byte (DB):
0457
Char6
P
0657
Char7
P
0
6
7
Char8
07
RFDF='1'
(no parity bit stored)
Status Byte (SB):
PE
0
6
7
FE P
PE
067
FE P
PE
0
6
7
FE P
PE
067
FE P
P: Parity bit stored in data byte (can be disabled via bit ' DPS' )
PE: Parity Error
FE: Frame Error
P: Parity bit stored in status byte
PEB 20542
PEF 20542
Register Description (CCR3H)
Data Sheet 5-178 2000-09- 14
RFTH(1:0) Re ceiv e FIFO Thres hold (all modes)
This bit field defines the level up to which the SCC receive FIFO is filled
with valid data before an ’RPF’ interrupt is generated.
(In case of a ’frame end / block end’ condition the SEROCCO-D notifies
the CP U immediately, disregarding this threshold.)
The me aning depends on the selected protocol en gine:
HDLC Modes:
RFTH (1:0) Thres hold level in number of da ta bytes.
’00’32 byte
’01’16 byte
’10’4 byt e
’11’2 byt e
ASYNC/BIS YNC Mode:
RFTH (1:0) Thres hold level in num ber of data bytes (DB) and status
bytes (SB) de pending on bit ’RFDF’:
RFDF = ’0’ RFDF = ’1’
’00’1 DB 1 DB + 1 SB
’01’4 DB 2 DB + 2 SB
’10’16 DB 8 DB + 8 SB
’11’32 DB 16 DB + 16 SB
PEB 20542
PEF 20542
Register Des cr iption (PREAMB)
Data Sheet 5-179 2000-09- 14
Register 27 PREAMB
Preamble Register
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 1EH6EH
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Preamble Pattern
HPRE(7:0)
A00000000
BPRE(7:0)
PRE(7:0) Preamble (hd l c/b i syn c modes)
This bit field determ ines the pre am ble pattern wh ic h is send out du ring
preamble transm ission.
Note: In HDLC-mode, zero-bit insertion is disabled during preamble
transmission.
PEB 20542
PEF 20542
Register Descri p t i on (TOL EN)
Data Sheet 5-180 2000-09- 14
Register 28 TOLEN
Time Out Length Register
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 1FH6FH
typical usage: w rit te n by CPU; read and ev aluate d by SER OCCO-D
Bit76543210
Mode
Time Out Length
H00000000
ATOIE TOLEN(6:0)
B00000000
TOIE Time Out Indication Enable (async mode)
If this bit is set to ’1’ in ASYNC mode, any time out even t will
automatically generate an ’RFRD’ command thus insertin g a ’block end’
indication into the RFIFO. This time-out co ndition is indic ated wi th the
’TIME’ interrupt (if unmasked).
TOIE = ’0’Aut om atic Time Out process ing disabled.
TOIE = ’1’Aut om atic Time Out process ing enabled.
TOLEN(6:0) Time Out Length (async mode)
This bit field determ ines the time out period. I f there is no recei ve line
activity for the confi gured period of time, a time out indication is
generat ed if enabled via bit ’TOIE’.
The period of time is programmable in multip les of character frame
length <CFL> time equivalents including start, parity and stop bits (refer
to Figure 49):
TOLEN T = ((TOLEN + 1) * 4) * <CFL>
PEB 20542
PEF 20542
Register Description (ACCM0)
Data Sheet 5-181 2000-09- 14
Register 29 ACCM0
PPP ASYNC Control Character Map 0
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 20H70H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
ASYNC Charac te r Cont rol Map 07..00
H07 06 05 04 03 02 01 00
A00000000
B00000000
Register 30 ACCM1
PPP ASYNC Control Character Map 1
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 21H71H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
ASYNC Character Control Map 0F..0 8
H0F 0E 0D 0C 0B 0A 09 08
A00000000
B00000000
PEB 20542
PEF 20542
Register Description (ACCM2)
Data Sheet 5-182 2000-09- 14
Register 31 ACCM2
PPP ASYNC Contr o l Character Map2
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 22H72H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
ASYNC Charac te r Cont rol Map 17..10
H17 16 15 14 13 12 11 10
A00000000
B00000000
Register 32 ACCM3
PPP ASYNC Control Character Map 3
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 23H73H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
ASYNC Character Control Map 1F..1 8
H1F 1E 1D 1C 1B 1A 19 18
A00000000
B00000000
PEB 20542
PEF 20542
Register Description (ACCM3)
Data Sheet 5-183 2000-09- 14
ACCM ASYNC Character Control Map (hdlc modes)
This bit field is valid in HDLC asynchronous and octet-synchronous PPP
mode only:
Each bit selects the co rres ponding cha rac ter (indicated as hex value
1FH..00H in the register description table) as control character which has
to be mapped into the transmit data stream.
PEB 20542
PEF 20542
Register Description (UDAC0)
Data Sheet 5-184 2000-09- 14
Register 33 UDAC0
User Defined PP P ASY NC Con tr ol Ch ara c t er Map 0
CPU Accessibility: read/write
Reset Value : 7EH
Channel A Channel B
Offs et Address: 24H74H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
ASYNC Character 0
HAC0
A00000000
B00000000
Register 34 UDAC1
User Defined PP P ASY NC Con tr ol Ch ara c t er Map 1
CPU Accessibility: read/write
Reset Value : 7EH
Channel A Channel B
Offs et Address: 25H75H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
ASYNC Character 1
HAC1
A00000000
B00000000
PEB 20542
PEF 20542
Register Description (UDAC2)
Data Sheet 5-185 2000-09- 14
Register 35 UDAC2
User Defined PP P ASY NC Con tr ol Ch ara c t er Map 2
CPU Accessibility: read/write
Reset Value : 7EH
Channel A Channel B
Offs et Address: 26H76H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
ASYNC Character 2
HAC2
A00000000
B00000000
Register 36 UDAC3
User Defined PP P ASY NC Con tr ol Ch ara c t er Map 3
CPU Accessibility: read/write
Reset Value : 7EH
Channel A Channel B
Offs et Address: 27H77H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
ASYNC Character 3
HAC3
A00000000
B00000000
PEB 20542
PEF 20542
Register Description (UDAC3)
Data Sheet 5-186 2000-09- 14
AC3..0 User Defined ASYNC Character Control Map (hdlc mode)
This bit field is valid in HDLC asynchronous and octet-synchronous PPP
mode only:
These bit fields define user determined characters as control characters
which hav e to be mappe d int o t he transmit data stre am .
In registe r ACCM only characters 00 H..1FH can be selected as control
characters. Register UDAC allows to specify any four characters in the
range 00H..FFH .
The default value is a 7EH flag which must be always mapped. Thus no
additional charact er is mapped if 7EH ’s are programed to bit fields
AC3...0 (reset value).
(7EH is ma pped automatically, even if not defined via a AC b it f ield.)
PEB 20542
PEF 20542
Register Description (TTSA0)
Data Sheet 5-187 2000-09- 14
Register 37 TTSA0
Transmit Time Slot Assignment Register 0
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 28H78H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Tx Clock Shift
H00000 TCS(2:0)
A00000 TCS(2:0)
B00000 TCS(2:0)
Register 38 TTSA1
Transmit Time Slot Assignment Register 1
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 29H79H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Tx Time Slot Number
HTEPCM TTSN(6:0)
ATEPCM TTSN(6:0)
BTEPCM TTSN(6:0)
PEB 20542
PEF 20542
Register Description (TTSA2)
Data Sheet 5-188 2000-09- 14
Register 39 TTSA2
Transmit Time Slot Assignment Register 2
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 2AH7AH
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Transmit Chan nel Capacit y
HTCC(7:0)
ATCC(7:0)
BTCC(7:0)
Register 40 TTSA3
Transmit Time Slot Assignment Register 3
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 2BH7BH
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Transmit Chan nel Capacit y
H0000000TCC8
A0000000TCC8
B0000000TCC8
PEB 20542
PEF 20542
Register Description (TTSA3)
Data Sheet 5-189 2000-09- 14
The following register bit fields allow flexible assignment of bit- or octet-aligned transmit
time-slots to the serial channel. For more detailed information refer to chapters “Clock
Mode 5a (Time Slo t Mode)” on Page 57 and “Clock Mode 5b (Octet Sync Mode)”
on Page 64.
TCS(2:0) Transmit Clock Shift (all modes)
This bit field dete rm ines the transmit clock shift .
TEPCM Enable PCM Mask Transmit (all modes)
This bit s elec t s th e additional Transmit PCM Mask (refer to register
PCMTX0..PCMTX3):
TEPCM=’0’St an dard time-slot configura tion.
TEPCM=’1’The ti me-sl ot wi dt h is con stan t 8 bit , bi t fie lds ’TTSN’ and
’TCS’ determine the offset of the PCM mask and ’TCC’ is
ignored. Each time-slot selected via register
PCMTX0..PCMTX3 is an activ e transmit timeslot.
TTSN(6:0) Trans mit Time Slot Number (all modes)
This bit fi eld selects the start position of the timeslot in time-slot
configuration mode (clock mode 5a/5b):
Offset = 1+ T T SN * 8 + T CS (1..1024 clocks)
TCC(8:0) Transmit Channel Capacity (all modes)
This bit field determines the transmit time-slot width in standard time-slot
config uration (bit TEPCM=’0’):
Number of bits = TCC + 1, (1..512 bits/time-slot)
PEB 20542
PEF 20542
Register Description (RTSA0)
Data Sheet 5-190 2000-09- 14
Register 41 RTSA0
Recei ve Time Slot Assign ment Regis ter 0
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 2CH7CH
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Rx Clock Shift
H00000 RCS(2:0)
A00000 RCS(2:0)
B00000 RCS(2:0)
Register 42 RTSA1
Recei ve Time Slot Assign ment Regis ter 1
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 2DH7DH
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Rx Time Slot Number
HREPCM RTSN(6:0)
AREPCM RTSN(6:0)
BREPCM RTSN(6:0)
PEB 20542
PEF 20542
Register Description (RTSA2)
Data Sheet 5-191 2000-09- 14
Register 43 RTSA2
Recei ve Time Slot Assign ment Regis ter 2
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 2EH7EH
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Receive Channel Capacity
HRCC(7:0)
ARCC(7:0)
BRCC(7:0)
Register 44 RTSA3
Recei ve Time Slot Assign ment Regis ter 3
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 2FH7FH
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Receive Channel Capacity
H0 0 0 0 0 0 0 RCC8
A0 0 0 0 0 0 0 RCC8
B0 0 0 0 0 0 0 RCC8
PEB 20542
PEF 20542
Register Description (RTSA3)
Data Sheet 5-192 2000-09- 14
The following register bit fields allow flexible assignment of bit- or octet-aligned receive
time-slots to the serial channel. For more detailed information refer to chapters “Clock
Mode 5a (Time Slo t Mode)” on Page 57 and “Clock Mode 5b (Octet Sync Mode)”
on Page 64.
RCS(2:0) Receive Clock Shift (all modes)
This bit field determ ines the receive clock shif t .
REPCM Enable PCM Mas k Rece iv e (all modes)
This bit s elec t s th e additional R ec eiv e PCM Mask (refer to regist er
PCMRX0..PCMRX3):
REPCM=’0’St an dard time-slot configura tion.
REPCM=’1’The ti me-slo t width i s constan t 8 bit , bit fiel ds ’RTSN’ and
’RCS’ determine the offset of the PCM mask and ’RCC’ is
ignored. Each time-slot selected via register
PCMRX0..PCMRX3 is an active receive timeslot.
RTSN(6:0) Receive Time Slot Number (all modes)
This bit fi eld selects the start position of the timeslot in time-slot
configuration mode (clock mode 5a/5b):
Offset = 1+RTSN*8 + RCS (1..1024 clocks)
RCC(8:0) Receive Channel Capacity (all modes)
This bit field determines the receive time-slot width in standard time-slot
config uration (bit REPCM=’0’):
Number of bits = RCC + 1, (1..512 bits/time-slot)
PEB 20542
PEF 20542
Register Description (PCMTX0)
Data Sheet 5-193 2000-09- 14
Register 45 PCMTX0
PCM Mask Transm it Direc tion Regi ster 0
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 30H80H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
PCM Mask for Transmit Di re c tio n
HT07 T06 T05 T04 T03 T02 T01 T00
AT07 T06 T05 T04 T03 T02 T01 T00
BT07 T06 T05 T04 T03 T02 T01 T00
Register 46 PCMTX1
PCM Mask Transm it Direc tion Regi ster 1
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 31H81H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
PCM Mask for Transmit Di re c tio n
HT15 T14 T13 T12 T11 T10 T09 T08
AT15 T14 T13 T12 T11 T10 T09 T08
BT15 T14 T13 T12 T11 T10 T09 T08
PEB 20542
PEF 20542
Register Description (PCMTX2)
Data Sheet 5-194 2000-09- 14
Register 47 PCMTX2
PCM Mask Transm it Direc tion Regi ster 2
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 32H82H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
PCM Mask for Transmit Di re c tio n
HT23 T22 T21 T20 T19 T18 T17 T16
AT23 T22 T21 T20 T19 T18 T17 T16
BT23 T22 T21 T20 T19 T18 T17 T16
Register 48 PCMTX3
PCM Mask Transm it Direc tion Regi ster 3
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 33H83H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit151413121110 9 8
Mode
PCM Mask for Transmit Di re c tio n
HT31 T30 T29 T28 T27 T26 T25 T24
AT31 T30 T29 T28 T27 T26 T25 T24
BT31 T30 T29 T28 T27 T26 T25 T24
PEB 20542
PEF 20542
Register Description (PCMTX3)
Data Sheet 5-195 2000-09- 14
PCMTX PCM Mask for Transmit Direction (all mode)
This bit field is valid in cloc k m ode 5 only and t he PC M mask must be
enab led v ia bit ’TEPCM’ in register TTSA1.
Each bit selects one of 32 (8-bit) transmit time-slots. The offset of time-
slot zero to the frame sync pulse can be programmed via register TTSA1
bit field ’TTSN’.
PEB 20542
PEF 20542
Register Description (PCMRX0)
Data Sheet 5-196 2000-09- 14
Register 49 PCMRX0
PCM Mask Receive Direction Register 0
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 34H84H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
PCM Mask for Receive Direction
HR07 R06 R05 R04 R03 R02 R01 R00
AR07 R06 R05 R04 R03 R02 R01 R00
BR07 R06 R05 R04 R03 R02 R01 R00
Register 50 PCMRX1
PCM Mask Receive Direction Register 1
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 35H85H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit151413121110 9 8
Mode
PCM Mask for Receive Direction
HR15 R14 R13 R12 R11 R10 R09 R08
AR15 R14 R13 R12 R11 R10 R09 R08
BR15 R14 R13 R12 R11 R10 R09 R08
PEB 20542
PEF 20542
Register Description (PCMRX2)
Data Sheet 5-197 2000-09- 14
Register 51 PCMRX2
PCM Mask Receive Direction Register 2
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 36H86H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
PCM Mask for Receive Direction
HR23 R22 R21 R20 R19 R18 R17 R16
AR23 R22 R21 R20 R19 R18 R17 R16
BR23 R22 R21 R20 R19 R18 R17 R16
Register 52 PCMRX3
PCM Mask Receive Direction Register 3
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 37H87H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit151413121110 9 8
Mode
PCM Mask for Receive Direction
HR31 R30 R29 R28 R27 R26 R25 R24
AR31 R30 R29 R28 R27 R26 R25 R24
BR31 R30 R29 R28 R27 R26 R25 R24
PEB 20542
PEF 20542
Register Description (PCMRX3)
Data Sheet 5-198 2000-09- 14
PCMRX PCM M ask for Recei ve Direc t i on (all mode)
This bit field is valid in cloc k m ode 5 only and t he PC M mask must be
enab led v ia bit ’REPCM’ in register RTSA1.
Each bit selects one of 32 (8-bi t) re ceive time -s lots. The of fset of tim e-
slot zero to the frame sync pulse can be programmed via register RTSA1
bit field ’RTSN’.
PEB 20542
PEF 20542
Register Des cr iption (BRRL)
Data Sheet 5-199 2000-09- 14
Register 53 BRRL
Baud Rate Register (Low Byte)
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 38H88H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Baud Rate G enerator Factor N
H0 0 BRN(5:0)
A0 0 BRN(5:0)
B0 0 BRN(5:0)
Register 54 BRRH
Baud Rate Register (High Byte)
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 39H89H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Baud Rate Generat or Fact or M
H0000 BRM(3:0)
A0000 BRM(3:0)
B0000 BRM(3:0)
PEB 20542
PEF 20542
Register Des cr iption (BRRH)
Data Sheet 5-200 2000-09- 14
BRM(3:0) Baud Rate Factor ’M’ (all m odes)
BRN(5:0) Baud Rate Factor ’N’ (all modes)
These bit fields determine the division fact or of the internal b aud rate
generator. The baud rate genera to r input clock an d the usage of baud
rate generator output depends on the selected clock mode.
The division factor k is calculated by:
with M=0. . 15 and N=0..63.
kN1+()2M
´=
fBRG fin k¤=
PEB 20542
PEF 20542
Register Des c ription (TIMR0)
Data Sheet 5-201 2000-09- 14
Register 55 TIMR0
Timer Register 0
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 3AH8AH
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Timer Value
HTVALUE(7:0)
ATVALUE(7:0)
BTVALUE(7:0)
Register 56 TIMR1
Timer Register 1
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 3BH8BH
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Timer Value
HTVALUE(15:0)
ATVALUE(15:0)
BTVALUE(15:0)
PEB 20542
PEF 20542
Register Des c ription (TIMR2)
Data Sheet 5-202 2000-09- 14
Register 57 TIMR2
Timer Register 2
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 3CH8CH
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Timer Value
HTVALUE(23:16)
ATVALUE(23:16)
BTVALUE(23:16)
Register 58 TIMR3
Timer Register 3
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 3DH8DH
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Timer Configur atio n
HSRC 0 0 TMD 0 CNT(2:0)
ASRC 0 0 0 0 CNT(2:0)
BSRC 0 0 0 0 CNT(2:0)
PEB 20542
PEF 20542
Register Des c ription (TIMR3)
Data Sheet 5-203 2000-09- 14
SRC Clock Sourc e (valid in clock mode 5 only) (all modes)
This bit s e lec t s the clock source of the internal t im e r:
SRC = ’0’The timer is clocked by th e effective transmit clock.
SRC = ’1’The tim er is clocked by the frame-sy nc s ynchroniz ation
signal supplied via t he FSC pin in cloc k mo de 5.
TMD Timer Mode (hdlc modes)
This bit must be set to ’1’ if HDLC Automode operation is selected. In all
other pro to col modes it mus t remain ’0’:
TMD=’0’The timer is controlled by the CPU via access to registers
CMDRL and TIMR0..TIMR3.
The tim er can be start ed any time by setting bit ’STI’ in
register CMDRL. After th e t i m er has expi red it generat es
a timer interrupt. The timer can be stopped any time by
setting bit ’TRES’ in regis t er CMDRL to ’1’.
TMD=’1’The timer is used by the SE R O C C O-D for prot oc ol
specific time-out and retry transactions in HDLC
Automode.
CNT(2:0) Counter (all modes)
The me aning of this bi t fie ld depends on t he s elected pro to c ol m ode.
In HDLC Automode, with bit TMD=’1’:
•Retry Counter (in H DLC proto c ol k nown as ’N2’):
Bit field ’CNT’ indic ates the numb er of S-Comm and frames (with poll
bit set) which are transmitted autonomously by SEROCCO-D after
every expiration of the time out period ’t’ (determined by ’TVALUE’), in
case an I-Fra me ge ts no t ack no wled ged by the opp osit e sta tion. The
maximum value is 6 S-command frames. If ’CNT’ is set to ’7’, the
number of S-commands is unlimited in case of no acknowledgement.
In all other modes, with bit TMD=’0’:
•Restart Counte r :
Bit field ’CNT’ indicates the number of automatic restarts which are
performed by SEROCCO-D after every expiration of the time-out
period ’t’, in case the timer is not stopped by setting bit ’TRES’ in
register CMDRL to ’1’. The maximum value is 6 restarts. If ’CNT’ is set
to ’7’, a timer interrupt is generated periodically with time period ’t’
dete rm ined by bit fie ld ’TVALUE’.
PEB 20542
PEF 20542
Register Des c ription (TIMR3)
Data Sheet 5-204 2000-09- 14
TVALUE
(23:0) Timer Expiration Value (all modes)
This bit field determines the timer expirat ion period ’t’:
(’CP’ is the clock period , dependin g on bit ’SRC’.)
tTVALUE1+()CP×=
PEB 20542
PEF 20542
Register Des cr iption (XAD1)
Data Sheet 5-205 2000-09- 14
Register 59 XAD1
Transmit Addres s 1 R eg i ster
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 3EH8EH
typical usage: w rit te n by CPU; read and ev aluate d by SER OCCO-D
Bit76543210
Mode
Transmit Address (high)
HXAD1 (high byte) 0 XAD1_0
or XAD1 (COMMAND)
A00000000
B00000000
Register 60 XAD2
Transmit Addres s 2 R eg i ster
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 3FH8FH
typical usage: w rit te n by CPU; read and ev aluate d by SER OCCO-D
Bit76543210
Mode
Transm it Address (low)
HXAD2 (low byte)
or XAD2 (RESP ONS E)
A00000000
B00000000
PEB 20542
PEF 20542
Register Des cr iption (XAD2)
Data Sheet 5-206 2000-09- 14
XAD1 and XA D2 bi t fields are valid in HDLC mod es with aut oma ti c address field
handling only (Automode, Addre ss Mode 1, A ddress Mode 2). They can be
programmed with one individual address byte which is inserted automatically into the
address field (8 or 16 bit ) of a HDLC tr ans mit fram e. The function depend s on the
select ed protoco l mo de and addre ss f ield size (bit ’ADM’ in regist er CCR2L).
XAD1 Transmit Address 1 (hdlc modes)
–2-byte address field:
Bit field XAD1 constitutes the high byte of the 2-byte address field. Bit
1 must be set to ’0’. According to the ISDN LAP-D protocol, bit 1 is
interpreted as the C/R (COMMAND/RESPONSE) bit. This bit is
manipulated automatically by SEROCCO-D according to the setting
of bit ’CRI’ in re gister RAH1. The following is the C/R value (on bit 1),
when:
- transmitting COMMANDs: ’1’ (if ’CRI’=’1’) ; ’0’ (if ’CRI’=’0’)
- transm i t t ing RESPON SEs: ’0’ (if ’CRI’=’1’) ; ’1’ (if ’CRI’=’0’)
(In ISDN LAP-D, the high byte is known as ’SAPI’.)
In accord ance with the H DLC pro tocol, bit ’XAD1_0’ should be set to
’0’, to i ndicate that the ad dress f ield co ntain s (at l east) on e more byte.
–1-byte address field:
According to the X.25 LAP-B protocol, XAD1 is the address of a
’COMMAND’ frame.
XAD2 Transmit Address 2 (hdlc modes)
–2-byte address field:
Bit field XAD2 constitutes the low byte of the 2-byte address field.
(In ISDN LAP-D, the low byte i s known as ’TEI’.)
–1-byte address field:
According to the X.25 LAP-B protocol, XAD2 is the address of a
’RESPONSE’ frame.
PEB 20542
PEF 20542
Register Description (RAL1)
Data Sheet 5-207 2000-09- 14
Register 61 RAL1
Recei ve Addres s 1 Low Register
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 40H90H
typical usage: w rit te n by CPU; read and ev aluate d by SER OCCO-D
Bit76543210
Mode
Receive Address 1 (low)
HRAL1
RAL1
A00000000
B00000000
Register 62 RAH1
Recei ve Addres s 1 High Register
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 41H91H
typical usage: w rit te n by CPU; read and ev aluate d by SER OCCO-D
Bit76543210
Mode
Receive Address 1 (high)
HRAH1 CRI RAH1_0
or RAH1
A00000000
B00000000
PEB 20542
PEF 20542
Register Description (RAL2)
Data Sheet 5-208 2000-09- 14
Register 63 RAL2
Recei ve Addres s 2 Low Register
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 42H92H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Receive Address 2 (low)
HRAL2
A00000000
B00000000
Register 64 RAH2
Recei ve Addres s 2 High Register
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 43H93H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Receive Address 2 (high)
HRAH2
A00000000
B00000000
PEB 20542
PEF 20542
Register Description (RAH2)
Data Sheet 5-209 2000-09- 14
In operating modes that provide address recognition, the high/low byte of the received
address is compared with the individua lly programma ble values in regis t er RAH2/
RAL2/RAH1/RAL1.
This add resses can be masked on a per bit ba sis by set t ing t h e correspo nding bits in
registers AMRAL1/AMRAH1/AMRAL2/AMRAH2 to allow extended broadcast address
recognition. This feature is applicable to all HDLC sub-modes with address recognition.
RAH1 Receive Address 1 Byte High (hdlc modes)
In HDLC Automode bit ’1’ is reserved for ’CRI’ (Command R es ponse
Interpretation ). In all othe r mode s RAH1 is an 8 bit address.
CRI Command/Response Interpretation
The se tting of this bit ef fects the meaning of the ’C/R’ bit in the receive
status byte (RSTA). This status bit ’C/R’ should be interpre ted after
recept i o n as follows:
’0’ (if ’CRI’=’1’) ; ’1’ (if ’CRI’=’0’) : COMMAND received
’1’ (if ’CRI’=’1’) ; ’0’ (if ’CRI’=’0’) : RESPONSE received
Note: If 1-byte address field is selected in HDLC Auto mode, RAH1 must
be set to 0x00H.
RAL1 Receive Address 1 Byte Low (hdlc modes)
The general functio n and its mea ning depends on t he selected H DL C
operati ng mode:
•Automode / Address Mode 2 (16-bit address)
RAL1 can be programmed with the value of the first individual low
address byte.
•Automode / Address Mode 2 (8-bit addr es s)
According to X.25 LAP-B protocol, the address in RAL1 is considered
as the address of a ’COMMAND’ frame.
RAH2 Receive Address 2 Byte High (hdlc modes)
RAL2 Receive Address 2 Byte Low (hdlc modes)
Value of the second individually programmable high/low address byte. If
a 1-byte address field is selected, RAL2 is considered as the address of
a ’RESPONSE’ frame according to X.2 5 LAP-B protocol.
PEB 20542
PEF 20542
Register Description (AMRAL1)
Data Sheet 5-210 2000-09- 14
Register 65 AMRAL1
Mask R eceive Addr ess 1 Low Reg is ter
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 44H94H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Rece i ve Mask Address 1 (low)
HAMRAL1
A00000000
B00000000
Register 66 AMRAH1
Mask R eceive Addr ess 1 High Regi ster
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 45H95H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Receive Mask Address 1 (high)
HAMRAH1
A00000000
B00000000
PEB 20542
PEF 20542
Register Description (AMRAL2)
Data Sheet 5-211 2000-09- 14
Register 67 AMRAL2
Mask R eceive Addr ess 2 Low Reg is ter
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 46H96H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Rece i ve Mask Address 2 (low)
HAMRAL2
A00000000
B00000000
Register 68 AMRAH2
Mask R eceive Addr ess 2 High Regi ster
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 47H97H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Receive Mask Address 2 (high)
HAMRAH2
A00000000
B00000000
PEB 20542
PEF 20542
Register Description (AMRAH2)
Data Sheet 5-212 2000-09- 14
AMRAH2 Receive Mask Addres s 2 Byte High (hdlc modes)
AMRAL2 Receiv e Mas k Addr es s 2 Byt e Low (hdlc modes)
AMRAH1 Receive Mask Addres s 1 Byte High (hdlc modes)
AMRAL1 Receiv e Mas k Addr es s 1 Byt e Low (hdlc modes)
Setting a bit in this registers to ’1’ m asks th e corresponding bit in
registers RAH2/RAL2/RAH1/RAL1. A masked bi t positi on always
matches when comparing the received frame address w i t h registers
RAH2/RAL2/RAH1/RAL1, allowing extended broad c ast mechanism.
bit = ’0’The dedicated bit posit i on is N OT masked. T his bit
position in the received address must match with the
corresponding bit position in registers RAH2/RAL2/RAH1/
RAL1 to accept the frame.
bit = ’1’The dedicated bit posit ion is masked. This bit position in
the received address NEED NOT match with the
corresponding bit position in registers RAH2/RAL2/RAH1/
RAL1 to accept the frame.
PEB 20542
PEF 20542
Register Description (RLCRL)
Data Sheet 5-213 2000-09- 14
Register 69 RLCRL
Recei ve Leng th Ch eck Register (Low By te)
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 48H98H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Receive Lengt h Limit
HRL(7:0)
A00000000
B00000000
Register 70 RLCRH
Recei ve Lengt h Check Register (High By te)
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 49H99H
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Receive Length Check Control Receive Length Limit
HRCE 0 0 0 0 RL(10:8)
A00000000
B00000000
PEB 20542
PEF 20542
Register De scription (RLCRH)
Data Sheet 5-214 2000-09- 14
RCE Receive Length Check Enable (hdlc modes)
This bit is valid in HDLC m ode only an d enables/d isables th e rec eive
length check function:
RCE = ’0’No rec eiv e length check on rec eiv ed HDLC frames is
performed.
RCE = ’1’The receive length check is enabled. All bytes of a HDLC
fram e which are transferred t o the receive FIFO
(dep ending on the selected pro to col sub-mo de and
receiv e CRC handling) are coun te d and chec ked against
the maxim um length check limit which is programme d in
bit field ’RL’.
A frame exceeding the maximum length is treated as if it
were aborted on the receive line (’RME’ inter r upt and bit
’RAB’ (receive abort) set in the RSTA byte).
In addit ion a ’FLEX’ interrupt is generated prior to ’RME’,
if enabl ed.
Note: The Receive Status Byte (RSTA) is part of the
frame length checking.
RL(10:0) Recei v e Length C h eck Limit (hdlc modes)
This bit-f ield defines th e receive leng th check limi t (32 ..65536 by t es ) if
chec ki ng is en ab led via bit ’RCE’:
RL(10: 0) T he receive l ength limit is calculated by :
Limit RL 1+()32×=
PEB 20542
PEF 20542
Register Description (XON)
Data Sheet 5-215 2000-09- 14
Register 71 XON
XON In-Band Flow Control Character Register
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 4AH9AH
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
XON Character
H00000000
AXON(7:0)
B00000000
Register 72 XOFF
XOFF In-Band Flow Control Character Register
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 4BH9BH
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
XOFF Character
H00000000
AXOFF(7:0)
B00000000
PEB 20542
PEF 20542
Register Description (XOFF)
Data Sheet 5-216 2000-09- 14
XON(7:0) XON Character (async mode)
This bit field spec ifies the XON c haracter for in-band fl ow control in
ASYNC protocol mode. The numb er of significa nt bi t s st art ing with the
LSB de pends on the ch aracter leng th (5..8 bits ) s elected vi a bit field
’CHL(1:0)’ in register CCR3L.
A received character is recognize d as a valid XON-character, if
•the characte r was c orrectly fr amed (character l ength a s programmed
and co rrect parity if checking is en abled)
•each bit position of the received character which is not masked via
register MXON matches wit h t he corresponding bit in register XO N .
Received characters recognized as XON character are stored in the
receive FIFO as normal receive data unless disabled with bit
CCR3L:DXS. An appropriate ’XON’ interrupt is generated (if enabled)
and the t ransm itt er is switc he d into ’XON’ state if in-band f low control is
enab led v ia bit ’FLON’ in register CCR2H.
XOFF(7:0) XOFF Character (async mode)
This bit field spec ifies the XOF F c haracter for in-band flow control in
ASYNC protocol mode. The numb er of significa nt bi t s st art ing with the
LSB de pends on the ch aracter leng th (5..8 bits ) s elected vi a bit field
’CHL(1:0)’ in register CCR3L.
A receiv ed character is rec ognized as a valid XOFF-character, if
•the characte r was c orrectly fr amed (character l ength a s programmed
and co rrect parity if checking is en abled)
•each bit position of the received character which is not masked via
register MXOFF matches with the corresponding bit in register XOFF.
Received characters recognized as XOFF character are stored in the
receive FIFO as normal receive data unless disabled with bit
CCR3L:DXS. An appropriate ’XOFF’ interrupt is generated (if enabled)
and the transmitter is switched into ’XOFF’ state if in-band flow control is
enab led v ia bit ’FLON’ in register CCR2H.
PEB 20542
PEF 20542
Register Des c ription (MXON)
Data Sheet 5-217 2000-09- 14
Register 73 MXON
XON In-Band Flow Control Mask Register
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 4CH9CH
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
XON Character Mask
H00000000
AMXON(7:0)
B00000000
Register 74 MXOFF
XOFF In-Band Flow Control Mask Register
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 4DH9DH
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
XOFF Character Mask
H00000000
AMXOFF(7:0)
B00000000
PEB 20542
PEF 20542
Register Description (MXOFF)
Data Sheet 5-218 2000-09- 14
MXON(7:0) XON Character Mask (async mod e)
Setting a bit in this bit field to ’1’ masks the corresponding bit in bit field
’XON(7:0)’ of register XON. A masked bit position always matches when
comp aring the rece iv ed character w i t h bit field ’XON(7:0)’.
bit = ’0’The dedicated bit posit ion is NOT mas k ed. T his bit
posi t ion in the rece ived character m us t match wi t h the
corres p onding b i t position in bit field ’XON’ to recogniz e
the received character as an XON character.
bit = ’1’The dedicated bit posit ion is m asked. This bit pos it ion in
the received character NEED NOT match with the
corres p onding b i t position in bit field ’XON’ to recognize
the received character as an XON character.
MXOFF(7:0) XOFF Charact er Mask (async mode)
Setting a bit in this bit field to ’1’ masks the corresponding bit in bit field
’XOFF(7:0)’ of register XOFF. A masked bit position always matches
when comparing the received character with bit fiel d ’XOFF(7:0)’.
bit = ’0’The dedicated bit posit ion is NOT mas k ed. T his bit
posi t ion in the rece ived character m us t match wi t h the
corresponding bit position in bit field ’XOFF’ to rec ognize
the received character as an XOFF character.
bit = ’1’The dedicated bit posit ion is m asked. This bit pos it ion in
the received character NEED NOT match with the
corresponding bit position in bit field ’XOFF’ to rec ognize
the received character as an XOFF character.
PEB 20542
PEF 20542
Register Description (TCR)
Data Sheet 5-219 2000-09- 14
Register 75 TCR
Terminati on Character Register
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 4EH8 9EH
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Termination C ha r a cter
H00000000
ATC(7:0)
BTC(7:0)
TC(7:0 ) Term ination Char acter (async mode)
This bit-field defines the termination character which is monitored on the
rece iv e data strea m if enabled v ia bit ’TCDE’ in register CCR3L.
PEB 20542
PEF 20542
Register Description (TICR)
Data Sheet 5-220 2000-09- 14
Register 76 TICR
Transmit Immediate Ch ar acter Regi ster
CPU Accessibility: read/write
Reset Value : 00H
Channel A Channel B
Offs et Address: 4FH9FH
typica l us age: written by C PU ;
read and ev aluated by SER OCCO-D
Bit76543210
Mode
Transmit Immediate Character
H00000000
ATIC(7:0)
B00000000
PEB 20542
PEF 20542
Register Description (TICR)
Data Sheet 5-221 2000-09- 14
TIC Transmit Immediate Character (async mod e)
On write access to this register, the ASYNC protocol e ngine will
automatically insert the char a cte r defin ed by bit field ’TIC’ into the
tran sm it data stream.
This happens
•immed iately aft er write acces s to regis ter TIC R if the tran smitter is in
IDLE state (no other character is currently transmitted). The
transmitter retu rns to IDLE state after transmission of the TIC.
•immediately after the character which is currently in transmission is
completed. After transmission of the TIC, the transmitter continues
with transmission of characters which are still stored in the transmit
FIFO. Thus the TIC is inserted into the data stream between the
characters provided via the transmit FIFO.
The TIC transmission is independent of in-band flow control. Thus the
TIC is sent out even if the transmitter is in ’XOFF’ state. However the
transm itter mus t be enabled v i a signal CT S (dep ending on bit ’FCTS’ in
register CCR1H).
The number of significant bits (starting with the LSB) depends on the
character length programmed in bit field ’CHL(1:0)’ in register CCR3L.
All character fra ming related settings in registers CCR3L/CCR3H (start
bit, parity generation, number of stop bits) also apply to the TIC character
framing.
As long as the TIC character is not completely sent, status bit TIC
Exec ution (’TEC’) i n stat us r egister STARL is set to ’1’ b y SEROCCO-D.
No further write access to register TICR is allowed until ’TEC’ status
indication is cleared by SEROCCO-D.
PEB 20542
PEF 20542
Register Description (ISR0)
Data Sheet 5-222 2000-09- 14
Register 77 ISR0
Interrupt Status Register 0
CPU Accessibility: read only
Reset Value : 00H
Channel A Channel B
Offs et Address: 50HA0H
typical usage: updated by SEROCCO-D
read and ev aluated by CPU
Bit76543210
Mode
ISR0
HRDO RFO PCE RSC RPF RME RFS FLEX
A0 RFO FERR PERR RPF TCD TIME 0
B0 RFO SCD PERR RPF TCD 0 0
Register 78 ISR1
Interrupt Status Register 1
CPU Accessibility: read only
Reset Value : 00H
Channel A Channel B
Offs et Address: 51HA1H
typical usage: updated by SEROCCO-D
read and ev aluated by CPU
Bit76543210
Mode
ISR1
HTIN CSC XMR XPR ALLS XDU SUEX 0
ATIN CSC XOFF XPR ALLS XON BRK BRKT
BTIN CSC XMR XPR ALLS XDU 0 0
PEB 20542
PEF 20542
Register Description (ISR2)
Data Sheet 5-223 2000-09- 14
Register 79 ISR2
Interrupt Status Register 2
CPU Accessibility: read only
Reset Value : 00H
Channel A Channel B
Offs et Address: 52HA2H
typical usage: updated by SEROCCO-D
read and ev aluated by CPU
Bit76543210
Mode
ISR2
H000000PLLACDSC
A000000PLLACDSC
B000000PLLACDSC
PEB 20542
PEF 20542
Register Description (ISR2)
Data Sheet 5-224 2000-09- 14
RDO Receive Data Ov erflow Interrupt (hdlc mode)
This bit is set to ’1’, if re ceive data o f the c u rrent fram e got lost because
of a SCC receive FIFO full condition. However the rest of the frame is
receiv ed an d disca rded as long as the receive FIFO remain s full and i s
stored as soon as FIFO space is available again. The receive status byte
(RSTA) of such a frame contains an ’RDO’ indica tion. In DMA operation
the ’RDO’ indication is also set in the receive byte count register RBCH.
RFO Receive FIFO Ov erflow Interrupt (all modes)
HDLC Mode:
This bit is set to ’1’, if the SCC receive FIFO is full and a complete frame
must be discarded. This interrupt can be used for statistical purposes,
indicating that the host was not able to service the SCC receive FIFO
quickly enough, e.g. due to high bus latency.
ASYNC/BIS YNC Mode:
This bit is set to ’1’, if the SCC receive FIFO is full and another received
charact er has been discarded. This interrupt can be used for statistical
purposes and might indicate that the host was not able to service the
SCC re ceive FIFO quickly enough, e .g . bus latenc ies are too hig h.
PCE Protocol Error Interrupt (hdlc mode)
This bit is valid in HDLC Automode only.
It is set to ’1’, if the receiver has detected a protocol error, i.e. one of the
following events occured:
•an S- or I- frame was received with wron g N(R) count er value ;
•an S-frame contain i ng an In for m a t i on field was recei ved.
FERR Framing Error Interrupt (async mode)
This bit is s et to ’1’, if a character framing error is detected, i.e. a ’0’ was
samp led at a position where a stop bit ’1’ w a s ex pected due to the
selected characte r format.
PEB 20542
PEF 20542
Register Description (ISR2)
Data Sheet 5-225 2000-09- 14
SCD Sync Char acter Detect ed (bisync mode)
Only valid in Hunt Mode.
This bit is set to ’1’ if a SYN c haracter is found in th e rec eived da ta
stream after the ’HUNT’ command has been issued in register CMDRH.
The rece i v e r no w is in the s ynchronous st ate .
RSC Receive Status Change Interrupt (hdlc mode)
This bit is valid in HDLC Automode only.
It is set to ’1’, if a status change of the remote station receiver has been
detected by receiving a S-frame with receiver ready (RR) or receiver not
ready (RNR) indication. Because only a status change is indicated via
this interrupt, the current status can be evaluated by reading bit ’RRNR’
in status register STARH.
PERR Parity Error Inte r ru pt (async/bisync modes)
This bit is only v alid if parity checking/gen eration is enabled via bit
’PARE’ in register CCR3H.
It is set to ’1’, if a character with wrong parit y has been rec eived. If
enab led v ia bit CCR3H:RFDF, t hi s error status is additionally stored in
the rec eiv e status by te generated for each receive c haracter.
RPF Receive Pool Full Interrup t (all mode s)
This bit is set to ’1’ if the RFIFO threshold level, set with bit field
’RFTH(1:0)’ in register CCR3H, is reached. Default threshold level is 32
data bytes in HDLC/PPP modes, 1 data byte in ASYNC/BISYNC modes.
PEB 20542
PEF 20542
Register Description (ISR2)
Data Sheet 5-226 2000-09- 14
RME Rec ei ve Message End Interrupt (hdlc mode)
This bit set to ’1’ indicates that the recept ion of one me ssage is
comp let ed, i.e. either
–one message which fits into RFIFO not exceeding the receive FIFO
threshold, or
–the last part of a message, all in all exceeding the receive FIFO
threshold
is stored in the RFIFO.
The complete message length can be determined by reading the RBCL/
RBCH registers. The number of bytes stored in RFIFO is given by the 5,
4, 2 or 1 leas t sig nif ic ant bit s of register RBCL, dependi ng on the
selected RFIFO threshold (bit field ’RFTH(1:0)’ in register CCR3H).
Additional frame status information is available in the RSTA by te, stored
in the RFIFO as the last byte of each frame.
Note: After the RFIFO contents have been read, an CMDRH:RMC
command must be issued to free the RFIFO for new receive data.
TCD Termination C h aracter De tected Int errupt (async /bisync mode)
This bit is set to ’1’, if a term ination chara cter ( TCR) has been d etected
in the receive data stream or an ’RFRD’ command, issued in the CMDRH
register, has been completed. The SCC will insert a ’block end’ indication
to the RFIFO. The actual block length can be determined by reading
register RBCL.
Note: After the RFIFO contents have been read, an CMDRH:RMC
command must be issued to free the RFIFO for new receive data.
RFS Receive Frame Start Interrupt (hdlc mode)
This bit is set to ’1’, if the beginning of a valid frame is detected by the
receiver. A vali d frame start is detec ted either if a valid address field i s
recognized (in all operating modes with address recognition) or if a start
flag is recognized (in all operating modes w it h no address rec ognition).
TIME Time Out Interrupt (async mode)
This bit is set to ’1’, if the time out limit is exceeded, i.e. no new character
was received in a programmable period of time (refer to register TOLEN
bit fields ’TOIE’ and ’TOLEN’ for more information).
PEB 20542
PEF 20542
Register Description (ISR2)
Data Sheet 5-227 2000-09- 14
FLEX Fram e Length Exceeded Interrupt (hdlc mode)
This bi t is set to ’1’, if the frame length check feature is enabled and the
current received frame is aborted because the programmed frame length
limit was exceeded (refer to registers RLCRL/RLCRH for detailed
description).
TIN Timer Interrupt (all modes)
This bit is set to ’1’, if the internal timer was activated and has expired
(refer also to descrip t ion o f timer reg isters TIMR0..TIMR3).
CSC CTS Status Change (all modes)
This bit is set to ’1’, if a transition occurs on signal CTS. The current state
of signal CTS is monitored by st atus bit ’CTS’ in st at us register STARL.
Note: A transmit clock must be pr ovi d ed to detect a transition of CTS.
XMR Transmit Mess age Repe at (hdlc/b i syn c mod es)
This bit is set to ’1’, if tra nsmiss ion of the last fram e has to be repea ted
(by sof tware), because
•the SCC has received a negative acknowledge to an I-frame (in HDLC
Auto m ode operation);
•a collision occured after at least 14.5 bytes of data have been
completely sent out, i.e. automatic re-transmission cannot be
perf ormed by the SCC;
•CTS signal was deasserted after at least 14.5bytes of data have been
completely se nt out .
Note: For easy recovery from a collision event (in bus configuration
only), the SCC transmit FIFO should not contain more than one
complete frame. This can be achieved by using the ’ALLS’
interrupt to control the corresponding transmit channel forwarding
a new frame on all sent (ALLS) event onl y.
XOFF XOFF Character Dete c t ed Interrupt (async mode)
ASYNC Mode:
This bit is set to ’1’, if the currently received character matched the XOFF
character programmed in register XOFF and indicates, that the
transmitter is switched to ’XOFF’ state if in- band f lo w co ntro l is en abled
via bi t ’FLON’ in register CCR2H.
PEB 20542
PEF 20542
Register Description
Data Sheet 228 2000-09-14
XPR Transmit Pool Ready Interrupt (all modes)
This bit is set to ’1’, if a transmitter reset command was executed
successfully (command bit ’XRES’ in register CMDRL) and whenever
the XFI FO is able to accept ne w t r ans mit data again.
An ’XPR’ interrupt is not generated, if no sufficient transmit clock is
available (depending on t he s elected cloc k mo de).
ALLS ALL Sent Interrupt (all modes)
HDLC Mode:
This bit is set to ’1’:
•if the last bit of the current HDLC frame is sent out via pin TxD and no
further frame is stored in the SCC transmit FIFO, i.e. the transmit FIFO
is empty (Address Mode 2/1/0);
•if an I-frame is sent out completely via pin TxD and either a valid
acknowledge S-frame has been received or a time-out condition
occured because no valid acknowledge S-frame has been received in
time (Automode).
ASYNC/BISYNC Mode:
This bit is set to ’1’, if the last c haracter is com pletely s ent via pin TxD
and no further data is stored in the SCC transmit FIFO, i.e. the transmit
FIFO is empty.
XDU Transmit Data Underrun Interrupt (hdlc/bisync modes)
This bit is set to ’1’, if the current frame was terminated by the SCC with
an abort sequence, because neither a ’frame end / blo ck e nd’ indication
was detected in the FIFO (to complete the current frame) nor more data
is available in the SCC transmit FIFO.
Note: The transmitter is stopped if this condition occurs. The XDU
condition MUST be cleared by reading register ISR1, thus bit
’XDU’ shou l d no t be masked vi a register IMR1.
XON XON Character Detected Interrupt (async mode)
This bit is set to ’1’, if the currently received character matched the XON
character programmed in register XON and indicates, that the
transmitter is switched to ’XON’ state if in-band flow control is enabled
via bit ’FLON’ in register CCR2H.
PEB 20542
PEF 20542
Register Description
Data Sheet 229 2000-09-14
SUEX Signalling Unit Counter Exceeded Interrupt (hdlc mode)
This bit is set to ’1’, if 256 correct or incorrect SU’s have been receive d
and th e int ernal counter is reset to 0.
BRK Break Inte rrupt (async mode)
This bit is set to ’1’, if a break condition was detected on the receive line,
i.e. a low level for a time equal to (character length + parity bit + stop
bit(s)) bits depending on t he s elected AS YN C character format.
BRKT Break Terminate d Interrupt (async mode)
This bit is set to ’1’, if a previously detected break condition on the
receive line is termin at ed by a low to high tr ans it ion.
PLLA DPLL Asynchronous Interrupt (all modes)
This bit is only valid, if the receive clock is derived from the internal DPLL
and FM 0, FM 1 or Man ches ter data enco ding is se lect ed (de pen ding o n
the selected clock mode and d ata encoding mode). It is set to ’1’ if the
DPLL has lost synchronization. Reception is disabled until
synchronization has been regained again. If the transmitter is supplied
with a clock deriv ed from the DPLL, t ransmiss ion is also int errupted.
CDSC Carrier Detect Stat us Cha nge Inte rrupt (all modes)
This bit is set to ’1’, if a st ate tra nsit ion h as bee n de tec ted at si gna l CD.
Beca us e only a state t r ansition is indicated via this interrupt, t he c u rrent
status can be evalua t e d by reading bit ’CD’ in status reg i st er STARH.
Note: A receive clock must be provided to detect a tran sition of C D.
PEB 20542
PEF 20542
Register Description
Data Sheet 230 2000-09-14
Register 80 IMR0
Interrupt Mask Register 0
CPU Acce ssib ility: read/write
Reset Value: FFH
Chann el A Channel B
Offset Address: 54HA4H
typica l us ag e: written by CPU;
read and evaluated by SEROCCO-D
Bit76543210
Mode
IMR0
HRDO RFO PCE RSC RPF RME RFS FLEX
A1 RFO FERR PERR RPF TCD TIME 1
B1 RFO SCD PERR RPF TCD 1 1
Register 81 IMR1
Interrupt Mask Register 1
CPU Acce ssib ility: read/write
Reset Value: FFH
Chann el A Channel B
Offset Address: 55HA5H
typica l us ag e: written by CPU;
read and evaluated by SEROCCO-D
Bit76543210
Mode
IMR1
HTIN CSC XMR XPR ALLS XDU SUEX 1
ATIN CSC XOFF XPR ALLS XON BRK BRKT
BTIN CSC XMR XPR ALLS XDU 1 1
PEB 20542
PEF 20542
Register Description
Data Sheet 231 2000-09-14
Register 82 IMR2
Interrupt Mask Register 2
CPU Acce ssib ility: read/write
Reset Value: 03H
Chann el A Channel B
Offset Address: 56HA6H
typica l us ag e: written by CPU;
read and evaluated by SEROCCO-D
Bit76543210
Mode
IMR2
H000000PLLACDSC
A000000PLLA CDSC
B000000PLLA CDSC
PEB 20542
PEF 20542
Register Description
Data Sheet 232 2000-09-14
(IM) Interrupt Mask Bits
Each SCC interrupt event can generate an interrupt signal indication via
pin INT/INT . Each bit position of registers IMR0..IMR2 is a mas k f or th e
corresponding int errupt even t in the interru pt st at us registers
ISR0..ISR2. Maske d int errupt events never generate an in terrupt
indication via pin INT/INT .
bit = ’0’The corresponding interrupt event is NOT masked and will
gene rat e an interrupt indicatio n via pin INT / IN T.
bit = ’1’The corresponding interrupt event is masked and will
NEITHER generate an interrupt vector NOR an interrupt
indicat ion via pin INT / I NT.
Moreover, masked interrupt events are:
•not dis play ed in the interrupt s ta t us registers ISR0..ISR2 if b it ’VIS’ in
register CCR0L is programmed to ’0’.
•displayed in interrupt status registers ISR0..ISR2 if bit ’VIS’ in register
CCR0L is programmed to ’1’.
Note: After RESET, all interrupt events are masked. Undefined bits must
not b e cleared to ’0’.
For detailed interrupt event description refer to the corresponding bit
position in registers ISR0..ISR2.
PEB 20542
PEF 20542
Register Description
Data Sheet 233 2000-09-14
The Receive Status Byte ’RSTA’ contains co mprehensive status informatio n about the
last rec eived frame (HDLC/P P P) or th e las t received ASYNC/BI SYNC cha r ac t er.
The SCC attaches this status byte to the receive data and thus it should be read from
the RFIFO.
In HDLC/PPP modes the RSTA value can optionally be read from this register address;
in ASYNC and BISYNC modes a read to this register is not specified. In extended
trans parent mode this status field does not apply.
Register 83 RSTA
Receiv e Status Byte
CPU Acce ssib ility: read only
Reset Value: 00H
Chann el A Channel B
Offset Address: 58HA8H
typical usage: written by SEROCCO-D to RFIFO;
read from RFIFO and evaluated by CPU
Bit76543210
Mode
Receive Status Byte
HVFR RDO CRCOK RAB HA(1:0)/
SU(1:0) C/R LA
APEFE00000P
BPE000000P
PEB 20542
PEF 20542
Register Description
Data Sheet 234 2000-09-14
VFR Valid Frame (hdlc modes)
Determines whethe r a valid frame has been received.
VFR=’0’The received frame is invalid .
An invalid frame is either a frame which is not an integer
number of 8 b its (n * 8 bits) in length (e.g. 25 bits), or a
frame which is too short, taking into account the operation
mode selected via CCR2L (MDS1, MDS0, ADM) and the
selected CRC algorithm (CCR1L:C32) as follows:
for CCR3H:DRCRC = ’0’ (CRC recepti o n en a ble d):
•auto m o de / addre ss mode 2 (16-bit ad dress)
4 bytes (CRC-CCITT) or 6 (CRC-32)
•auto m ode / addre ss mode 2 (8-bit addres s )
3 bytes (CRC-CCITT) or 5 (CRC-32)
•address mode 1:
3 bytes (CRC-CCITT) or 5 (CRC-32)
•address mode 0:
2 bytes (CRC-CCITT) or 4 (CRC-32)
for CCR3H:DRCRC = ’1’ (CRC recepti o n di sa b l ed ):
•auto m o de / addre ss mode 2 (16-bit ad dress):
2bytes
•auto m ode / addre ss mode 2 (8-bit addres s ) :
1byte
•address mode 1:
1byte
•address mode 0:
1byte
Note: Shorter frames are not reported at all.
VFR=’1’The received fram e is valid.
RDO Recei ve D ata Overflow (hdlc modes)
RDO=’0’No receive data overflow has occurred .
RDO=’1’A data over flow has occ u rred during rec ept ion of the
frame. Additionally, an interrupt can be generated (refer to
ISR0:RDO/IMR0:RDO).
PEB 20542
PEF 20542
Register Description
Data Sheet 235 2000-09-14
CRCOK CRC Compare/Check (hdlc modes)
CRCOK=’0’CRC check failed, received frame contains errors.
CRCOK=’1’CRC check OK; the received frame does not contain CRC
errors.
RAB R eceive Message Aborted (hdlc modes)
RAB=’0’No abort cond it ion was dete c ted during rec ept ion of the
frame.
RAB=’1’The received frame was aborted from t he transmitt ing
station. Accor ding to the HD LC protoc ol, this frame must
be disc arded by the receiver station.
This bit is also set to ’1’ if the maximum receive byte count
(set in regis t ers RLCRL/RLCRH) is reached.
HA(1:0) High Byte Address Compare (hdlc modes)
Significant only if an address mode with automatic address handling has
been selected. In op erating mod es which provide high byte address
recognit ion, SER OCCO-D compares the high byte of a 2-byte addre s s
with the contents of two indiv i dually programmable address es (RAH1,
RAH2) and the fixed values FEH an d F CH (broadcast address).
Dependent on the result of this comparison, the following bit
combinations are possible:
HA(1:0)=’10’RAH1 has be en recogni zed.
HA(1:0)=’00’RAH2 has be en recogni zed.
HA(1:0)=’01’broadca st address has been re cognized.
If RAH1 and RAH2 cont ain identica l values, a match is indicated by
HA(1:0)=’10’.
SU(1:0) SS7 Signaling Unit Type (hdlc modes)
If Signaling System #7 support is activated (see CCR3L register, bit
’ESS7’), the bit funct i on s ar e defined as follo ws:
SU(1:0)=’00’not valid
SU(1:0)=’01’Fill In Signaling U nit (FISU) detected
SU(1:0)=’10’Link Status Signaling Unit (LSS U ) detected
SU(1:0)=’11’Message Signaling Unit (MSU) detected
PEB 20542
PEF 20542
Register Description
Data Sheet 236 2000-09-14
C/R Command/Response (hdlc modes)
Sign i f i c a nt onl y i f 2- byte address mode has been selected.
Value o f the C / R bit (bit 1 of high address byte) in the received fram e.
The interpreta t ion depends on the setting of th e ’CRI’ bit in the RAH1
register (See “RAH1” on page 207.).
LA Low Byte Addres s Compare (hdlc modes)
Signific ant in automode and addres s mode 2 only.
The low byte address of a 2-byte address field, or the single address byte
of a 1-byte address field is compared with two addresses (RAL1, RAL2).
LA=’0’RAL2 has been recognized.
LA=’1’RAL1 has been recognized.
According to the X.25 LAPB protocol, RAL1 is interpreted as the address
of a COMM AN D f rame and RAL2 is interpr e ted as the address of a
RESPONSE frame.
PParity (async/bisync mode )
’1’This bit ca rries the parity bit of the last received character.
FE Framing Error (async mode)
’1’A charac t er framing error was det ec t ed, i. e. a ’0’ was sam pled at a bit
posi tion wh ere a st op bi t ’1’ was expected due to the selected character
format.
PE Parity Error (async/bisync mode)
’1’The calculated parity did not match the received parity bit. Optionally the
interrupt PERR can be ge nerated.
PEB 20542
PEF 20542
Register Description
Data Sheet 237 2000-09-14
Register 84 SYNCL
SYN Character Register (Low Byte)
CPU Acce ssib ility: read/write
Reset Value: 00H
Chann el A Channel B
Offset Address: 5AHAAH
typica l us ag e: written by CPU;
read and evaluated by SEROCCO-D
Bit76543210
Mode
SYN Character Low
H00000000
A00000000
BSYNCL(7:0)
Register 85 SYNCH
SYN Character Register (High Byte)
CPU Acce ssib ility: read/write
Reset Value: 00H
Chann el A Channel B
Offset Address: 5BHABH
typica l us ag e: written by CPU;
read and evaluated by SEROCCO-D
Bit76543210
Mode
SYN Character High
H00000000
A00000000
BSYNCH(7:0)
PEB 20542
PEF 20542
Register Description
Data Sheet 238 2000-09-14
SYNCH(7:0) Syn chr oniza tion Character (high) (bisync mode)
SYNCL(7:0) Synchronization Character (low) (bisync mode)
This register is only valid in BISYNC protocol mode .
The synchroniza tion (SYN) character format depends on the setting of
bit ’BISNC’ and ’SLEN’ in register CCR2L:
•MONOSYNC Mode (CCR2L.BISNC = ’0’)
The SYN character is defined by register ’SYNCL’:
a) SLEN = ’0’: the 6 bit SYN c h aracter is specified b y bi t s (5 ..0)
b) SLEN = ’1’: the 8 bit SYN c h aracter is specified b y bi t s (7 ..0).
•BISYNC M ode (CCR2L.BISNC = ’1’)
The SYN character is defined by registers ’SYNCL’ and ’SYNCH’:
a) SLEN = ’0’: the 12 bit SYN character is specified by bits (5..0) of
each register, i.e. SYN(11..0) = SYNCH(5:0), SYNCL(5:0)
b) SLEN = ’1’: the 16 bit SYN character is specified by bits (7..0) of
each register, i.e. SYN(15..0) = SYNCH(7:0), SYNCL(7:0).
In transmit direction the SYN character is sent continuously if no data
has to be transmitted and interframe timefill control is enabled by setting
bit ’ITF’ to ’1’ in register CCR2H.
In receive direction the receiver monitors the data stream for occurence
of the specified S YN pattern if operating in ’HUNT’ mode (bit ’HUNT’ in
register CMDRH).
PEB 20542
PEF 20542
Register Description
Data Sheet 239 2000-09-14
5.2.3 Channel Specific DMA Registers
Each register desc ription is organized in three parts:
•a head with gen eral inf ormati on about re set va lue, a ccess t ype (read /write ), cha nnel
speci fic of f set address and usual ha ndling;
•a table c ont aining the bit inf orm ation (name of bit position s );
•a section containi ng t he detailed descripti on of each bit.
Register 86 TBADDR1L
Prim ar y T ra nsmit Bas e A ddress (Low Byte)
CPU Acce ssib ility: read/write
Reset Value: 00H
Chann el A Channel B
Offset Address: B0HCAH
typical usage: written by CPU, evaluated by SEROCCO-D
Bit76543210
TBADDR1(7:0)
Register 87 TBADDR1M
Prim ar y T ransmit Base Addre ss (M id Byte)
CPU Acce ssib ility: read/write
Reset Value: 00H
Chann el A Channel B
Offset Address: B1HCBH
typical usage: written by CPU, evaluated by SEROCCO-D
Bit151413121110 9 8
TBADDR1(15:8)
PEB 20542
PEF 20542
Register Description
Data Sheet 240 2000-09-14
Register 88 TBADDR1H
Prim ar y T ra n smit Base A d d re ss (High Byte)
CPU Acce ssib ility: read/write
Reset Value: 00H
Offset Address: B2HCCH
typical usage: written by CPU, evaluated by SEROCCO-D
Bit76543210
TBADDR1(23:16)
TBADDR1
(23:0) Primary Tr an smit Base Ad d ress
Only valid in internal DMA controller modes.
This bit field dete rm ines the bas e address of t he primary DMA transmi t
buffer (buffer 1).
•If single-buffer operation is selected, this base address is the only one
used; the secondary base address TBADDR2(23:0) is "don’t care " in
this case.
•If switched-buffer operation is selected (refer to register DMODE),
transm ission takes place ba sed on two tr ansmit buffe rs that a re s ent
alternating.
Note: If 16-bit bus operation is selected, the base address must be word
aligne d, i.e. bit TBADDR1 ( 0) must be set to ’0’.
PEB 20542
PEF 20542
Register Description
Data Sheet 241 2000-09-14
Register 89 TBADDR2L
Secondary Transmit Base Addres s (Low Byte)
CPU Acce ssib ility: read/write
Reset Value: 00H
Chann el A Channel B
Offset Address: B4HCEH
typical usage: written by CPU, evaluated by SEROCCO-D
Bit76543210
TBADDR2(7:0)
Register 90 TBADDR2M
Secondary Transmit Base Addre s s (Mid Byte)
CPU Acce ssib ility: read/write
Reset Value: 00H
Chann el A Channel B
Offset Address: B5HCFH
typical usage: written by CPU, evaluated by SEROCCO-D
Bit151413121110 9 8
TBADDR2(15:8)
PEB 20542
PEF 20542
Register Description
Data Sheet 242 2000-09-14
Register 91 TBADDR2H
Secondary Transmit Base Addre s s (High Byte)
CPU Acce ssib ility: read/write
Reset Value: 00H
Chann el A Channel B
Offset Address: B6HD0H
typical usage: written by CPU, evaluated by SEROCCO-D
Bit76543210
TBADDR2(23:16)
TBADDR2
(23:0) Secondary Transmit Base Address
Only val id in s w itc hed-buff er D M A c ontroller mo de.
This bit field dete rmines the ba s e address of the secon dary DMA
transm it buffer (buffer 2) in switched-buffer operation.
•If single-buffer operation is selected, this base address is "don’t care".
Only address TBADDR1(23:0) is used in this case.
•If switched-buffer operation is selected (refer to register DMODE),
transmission takes place based on both transmit buffers (TBADDR1
and TBADDR2). Data from these transmit buffers is sent alternatin g.
Note: If 16-bit bus operation is selected, the base address must be word
aligne d, i.e. bit TBADDR2 ( 0) must be set to ’0’.
PEB 20542
PEF 20542
Register Description
Data Sheet 243 2000-09-14
Register 92 XBC1L
Primary Transmit Byte Count (Low Byte)
CPU Acce ssib ility: read/write
Reset Value: 00H
Chann el A Channel B
Offset Address: B8HD2H
typical usage: written by CPU, evaluated by SEROCCO-D
Bit76543210
XBC1(7:0)
Register 93 XBC1H
Primary Transmit Byte Count (High Byte)
CPU Acce ssib ility: read/write
Reset Value: 00H
Chann el A Channel B
Offset Address: B9HD3H
typical usage: written by CPU, evaluated by SEROCCO-D
Bit76543210
XME XF XIF 0 XBC1(11:8)
PEB 20542
PEF 20542
Register Description
Data Sheet 244 2000-09-14
XBC1
(11:0) Primary Transmit Byte Count
Only valid in internal DMA controller modes.
This bit field determines the size in number of bytes of the primary
transmit buffer (with base address TBADDR1(23:0)).
•If single-buffer operation is selected, the primary buffer is the only one
used; the secondary transmit byte c ount bit fiel d XBC2(11 :0 ) is "don’t
care" in this case.
•If switched-buffer operation is selected (refer to register DMODE),
transm ission take s plac e based on two trans mit bu ffer s (prima ry and
secondary) that are sent alternating.
XME Tra nsmit Message End Command
Only valid in internal DMA controller mode.
This bit is identical to ’XME’ command bit (refer to register “CMDRL” on
Page 150).
XF Tra n smit Fram e C o mmand
Only valid in internal DMA controller mode.
This bit is identical to ’XF’ comm and bit (refer to register “CMDRL” on
Page 150).
XIF Transmit I-Frame Command
Only valid in internal DMA controller mode.
This bit is identical to ’XIF’ command bit (refer to register “CMDRL” on
Page 150).
PEB 20542
PEF 20542
Register Description
Data Sheet 245 2000-09-14
Register 94 XBC2L
Secondary Transmit Byte Count (Low Byte)
CPU Acce ssib ility: read/write
Reset Value: 00H
Chann el A Channel B
Offset Address: BAHD4H
typical usage: written by CPU, evaluated by SEROCCO-D
Bit76543210
XBC2(7:0)
Register 95 XBC2H
Secondary Transm it Byte Count (High Byte)
CPU Acce ssib ility: read/write
Reset Value: 00H
Chann el A Channel B
Offset Address: BBHD5H
typical usage: written by CPU, evaluated by SEROCCO-D
Bit76543210
XME XF XIF 0 XBC2(11:8)
PEB 20542
PEF 20542
Register Description
Data Sheet 246 2000-09-14
XBC2
(11:0) Secondary Transmit Byte Count
Only val id in s w itc hed-buff er D M A c ontroller mo de.
This bit field dete rmines the size in numb er of by tes of the secondary
transmit buffer (with base address TBADDR2(23:0)).
•If single-buffer ope ration is selected, this bit fie ld is "don’t care". The
primary transmit buffer with transmit byte count XBC1(11:0) is the only
one used in this case.
•If switched-buffer operation is selected (refer to register DMODE),
transm ission take s plac e based on two trans mit bu ffer s (prima ry and
secondary) that are sent alternating.
XME Tra nsmit Message End Command
Only valid in internal DMA controller modes.
This bit is identical to ’XME’ command bit (refer to register “CMDRL” on
Page 150).
XF Tra n smit Fram e C o mmand
Only valid in internal DMA controller modes.
This bit is identical to ’XF’ comm and bit (refer to register “CMDRL” on
Page 150).
XIF Transmit I-Frame Command
Only valid in internal DMA controller modes.
This bit is identical to ’XIF’ command bit (refer to register “CMDRL” on
Page 150).
PEB 20542
PEF 20542
Register Description
Data Sheet 247 2000-09-14
Register 96 RBADDR1L
Prim ar y R eceive Bas e Address (L o w B yte)
CPU Acce ssib ility: read/write
Reset Value: 00H
Chann el A Channel B
Offset Address: BCHD6H
typical usage: written by CPU, evaluated by SEROCCO-D
Bit76543210
RBADDR1(7:0)
Register 97 RBADDR1M
Prim ar y R eceive Bas e Address 1 (M i d Byte)
CPU Acce ssib ility: read/write
Reset Value: 00H
Chann el A Channel B
Offset Address: BDHD7H
typical usage: written by CPU, evaluated by SEROCCO-D
Bit151413121110 9 8
RBADDR1(15:8)
PEB 20542
PEF 20542
Register Description
Data Sheet 248 2000-09-14
Register 98 RBADDR1H
Prim ar y R eceive Bas e A d dr ess 1 (High By te)
CPU Acce ssib ility: read/write
Reset Value: 00H
Chann el A Channel B
Offset Address: BEHD8H
typical usage: written by CPU, evaluated by SEROCCO-D
Bit76543210
RBADDR1(23:16)
RBADDR1
(23:0) Primary Receive Base Address
Only valid in internal DMA controller modes.
This bit field determines the ba s e address of the primary DMA receive
buffer (buffer 1).
•If single-buffer operation is selected, this base address is the only one
used; the secondary base address RBADDR2(23:0) is "don’t care" in
this case.
•If switched-buffer operation is selected (refer to register DMODE),
reception takes place based on two receive buffers that are filled
alternating.
Note: If 16-bit bus operation is selected, the base address must be word
aligne d, i.e. bi t RBADDR1(0) must be set to ’0’.
PEB 20542
PEF 20542
Register Description
Data Sheet 249 2000-09-14
Register 99 RBADDR2L
Secondary Receiv e Bas e Addr es s (Low Byte )
CPU Acce ssib ility: read/write
Reset Value: 00H
Chann el A Channel B
Offset Address: C0HDAH
typical usage: written by CPU, evaluated by SEROCCO-D
Bit76543210
RBADDR2(7:0)
Register 100 RBADDR2M
Secondary Receive Base Address (Mid Byte)
CPU Acce ssib ility: read/write
Reset Value: 00H
Chann el A Channel B
Offset Address: C1HDBH
typical usage: written by CPU, evaluated by SEROCCO-D
Bit151413121110 9 8
RBADDR2(15:8)
PEB 20542
PEF 20542
Register Description
Data Sheet 250 2000-09-14
Register 101 RBADDR2H
Secondary Receive Base Address2 (High Byte)
CPU Acce ssib ility: read/write
Reset Value: 00H
Chann el A Channel B
Offset Address: C2HDCH
typical usage: written by CPU, evaluated by SEROCCO-D
Bit76543210
RBADDRA2(23:8)
RBADDR2
(23:0) Secondary Receive Base Address
Only val id in s w itc hed-buff er D M A c ontroller mo de.
This bit field determines the base address of the secondary DMA receive
buffer (buffer 2) in sw it ched-buffer operation.
•If single-buffer operation is selected, this base address is "don’t care".
Only address RBADDR1(23:0) is used in this case.
•If switched-buffer operation is selected (refer to register DMODE),
recepti on take s place base d on bot h rece ive buf fers (RBA DDR1 and
RBADDR2). Data is received into these buffers alternating.
Note: If 16-bit bus operation is selected, the base address must be word
aligne d, i.e. bi t RBADDR2(0) must be set to ’0’.
PEB 20542
PEF 20542
Register Description
Data Sheet 251 2000-09-14
Register 102 RMBSL
Receive Maximum Buffer Size (Low Byte)
CPU Acce ssib ility: read/write
Reset Value: 00H
Chann el A Channel B
Offset Address: C4HDEH
typical usage: written by CPU, evaluated by SEROCCO-D
Bit76543210
Receive Maximum Buffer Size
RMBS(7:0)
Register 103 RMBSH
Receive Max imum Buffer Size (High Byte)
CPU Acce ssib ility: read/write
Reset Value: 00H
Chann el A Channel B
Offset Address: C5HDFH
typical usage: written by CPU, evaluated by SEROCCO-D
Bit151413121110 9 8
Receive Maximum Buffer Size
RE 0 0 0 RMBS(11:8)
PEB 20542
PEF 20542
Register Description
Data Sheet 252 2000-09-14
RE Recei ve D M A En ab le
Only valid in internal DMA controller modes.
Self-clearing c om m and bit:
RE=’0’The DMA controll er is not set up to for wa r d receive data
into a bu ffe r in memor y.
RE=’1’If this bit is set to ’1’, the DMA cont roller is activat ed for
transferring receive data into a buffer in memory. This
buffer in memory ha s to be set up with a valid base
address RBADDRi(23:0) and the maximum buffer size
RMBS (11:0) in advanc e.
RMBS(11:0) R eceive Maximum Buffe r Si z e
Only valid in internal DMA controller modes.
This bit field dete rm ines the reserved size (0..4095 byte) for a receive
buffer in memory. With the base address RBADDRi(23:0), the location
of the rec eive buffer is defined.
PEB 20542
PEF 20542
Register Description
Data Sheet 253 2000-09-14
Register 104 RBCL
Receive Byte Count (Low Byte)
CPU Acce ssib ility: read only
Reset Value: 00H
Chann el A Channel B
Offset Address: C6HE0H
typica l us ag e: written by SEROCCO-D, evaluate d by CPU
Bit76543210
RBC(7:0)
Register 105 RBCH
Receive Byte Count (High Byte)
CPU Acce ssib ility: read only
Reset Value: 00H
Chann el A Channel B
Offset Address: C7HE1H
typica l us ag e: written by SEROCCO-D, evaluate d by CPU
Bit76543210
RBCO 0 0 0 RBC(11:8)
PEB 20542
PEF 20542
Register Description
Data Sheet 254 2000-09-14
RBC(11:0) Receive Byte Count
This bit field determines the receive byte count (1..4095) of the currently
received frame/block.
RBCO Receive Byte Counter Overflow
Only valid in DMA controller mode.
This bit indicate s an ov erf l ow of the receive byte c ont er RBC(11:0), i.e.
the receive fram e length exceeded 409 5 by t es.
PEB 20542
PEF 20542
Register Description
Data Sheet 255 2000-09-14
5.2.4 Miscellaneous Registers
Register 106 VER0
Ver sion Register 0
CPU Acce ssib ility: read only
Reset Value: 83H
Offset Address: ECH
typical u sa ge: evalua t ed by CPU
Bit76543210
Manufacturer Code Fix ’1’
VER(7:0)
Register 107 VER1
Ver sion Register 1
CPU Acce ssib ility: read only
Reset Value: E0H
Offset Address: EDH
typical u sa ge: evalua t ed by CPU
Bit76543210
Device Code (bits 3 .. 0) Manufacturer Code
VER(15:8)
PEB 20542
PEF 20542
Register Description
Data Sheet 256 2000-09-14
Register 108 VER2
Ver sion Register 2
CPU Acce ssib ility: read only
Reset Value: 05H
Offset Address: EEH
typical u sa ge: evalua t ed by CPU
Bit76543210
Device Code (bits 11 .. 4)
VER(23:16)
Register 109 VER3
Ver sion Register 3
CPU Acce ssib ility: read only
Reset Value: 20H
Offset Address: EFH
typical u sa ge: evalua t ed by CPU
Bit76543210
Version Number Device Code (bits 15 .. 12)
VER(31:24)
PEB 20542
PEF 20542
Register Description
Data Sheet 257 2000-09-14
VER(31:0) Version Register
Iden tic al to 32 bit boundary scan ID str ing.
The 32 bit string consis t s of the bit fields:
VER(31:28) 2HVersio n Number
VER(27:12) 005EHDevice Code
VER(11:0) 083HManuf ac turer Code (LSB fixed to ’1’)
PEB 20542
PEF 20542
Programming
Data Sheet 258 2000-09-14
6Programming
6.1 Initialization
After Reset the CPU has to write a minimum set of registers and an optional set
depe nding on the required fe at ures and operating modes.
First, the following initialization st eps must be ta k en:
•Select serial protocol mode (refer to Table 12 "Protocol Mode Overview" on
Page 86),
•Select encoding of the serial data (refer to Chapter 3.2.13 “Data Encoding” on
Page 75),
•Progr am the output characteristics of
- pin TxD (selected with bit ’ODS’ in “Channel Configuration Register 1 (Low
Byte)” on Page 159) and
- interrupt pin INT/INT (selected with bit field ’IPC(1:0)’ in “Global Mode Register” on
Page 127),
•Choos e a c lock mode (r ef er t o Table 7 "Overview of Clock Modes" on Page 48).
•Power- up the oscill ator unit (with or wi thout shaper ) by re- setting bi t GMODE:OSCPD
to ’0’, if appropriate (GMODE:DSHP=’0’ enables the shaper).
The clock mode must be set before power-up (CCR0H.PU). The CPU may switch the
SEROCCO-D between power-up and power-down mode. This has no influence upon the
contents of the registers, i.e. the internal state remains stored. In power-down mode
however, all internal clocks are disabled, no interrupts from the cor responding channel
are forwarded to the CPU. This state can be used as a standby mode, when the channel
is (temporarily) not us ed, thus subs t antially reduc ing power con s um pt ion.
The SEROC C O-D should usually be initialized in Power-Down mo de .
The need for programming further registers depends on the selected features (serial
mode, clock mode s pecific features, operating mode, address m ode, user dem ands).
6.2 I nt errupt Mo de
6.2.1 Data Transm ission (Interrupt Driven)
In transmit direction 2 ´ 32 byte FIFO buffers (transmit pools) are provided for each
channel. After checking the XFIFO status by polling the Transmit FIFO Write Enable bit
(bit ’XFW’ in STARL regi st er) or a fter a Tr ansm it P ool Re ady ( ’XPR’) interrupt, up to 32
bytes may be ente red by the CP U int o the XFIFO.
PEB 20542
PEF 20542
Programming
Data Sheet 259 2000-09-14
HDLC/SDLC/PPP
The transmission of a packet can be started by issuing an ’XF’ or ’XIF’ command via the
CMDRL register. If enabled, a specified number of preambles (refer to registers CCR2H
and PREAMB) are sen t o ut o pt ionally before transmiss ion of the current packet start s.
If the transmit command does not include an end of message indication (CMDRL.XME),
SEROCCO-D will repeatedly request for the next data block by means of an ’XPR’
interrup t as soon as n o m ore t han 32 by tes ar e sto red in th e XFIF O, i. e. a 32-by te po ol
is accessible to the CPU.
This process will be repeated until the CPU indicates the end of message per ’XME’
comma nd, afte r which p acket trans mission is finishe d correct ly by ap pending th e CRC
and closing flag sequence. Consecutive packets may be transmitted as back-to-back
packet s and may even s hare a flag (e nabled via CCR1L.SFLG), if service of XFIFO is
quick en ough.
In case no more data is available in the XFIFO prior to the arrival of the end-of-message
indiction (’XME’), the transmission of the packet is terminated with an abort sequence
and the CPU is notified per interrupt (ISR1.XDU, transmit data underrun). The packet
may also be aborted per s o f t ware at any t i m e ( CMDRL.XRES).
The data transmission sequence, from the CPU’s point of view, is outlined in Figure 59.
ASYNC
The transmission of character(s) can be started by issuing a ’XF’ command via the
CMDRL register. SEROCCO-D will repeatedly request for the next data block by means
of an ’XPR’ interrupt as soon as no more than 32 by tes are stored in t he XFIFO, i.e. a
32-byte pool is accessible to the CPU. Transmission may be aborted per software
(CMDRL.XRES).
BISYNC
The transmission of a block can be started by issuing an ’XF’ command via the CMDRL
register. Further handling of data transmission with respect to preamble transmission
and command ’XME’ is similar to HDLC/SDLC mode. After ’XME’ command has been
issued, th e block is finis hed by appending th e internall y generated CRC if en abled (refer
to descri pt ion of register CCR2H).
In case no more data is available in the XFIFO prior to the arrival of ’XME’, the
transmission of the block is terminated with IDLE and the CPU is notified per interrupt
(ISR1.XDU). The block may also be aborted per software (CMDRL.XRES). The data
transmission flow, from the CPU ’s point of v i ew , is outlined in Figure 59.
PEB 20542
PEF 20542
Programming
Data Sheet 260 2000-09-14
Figure 59 Interrupt Driven Data Transmis sion (Flow Diagram)
6.2.2 Data Reception (Interrupt Driven)
Also 2 ´3 2 byte FIFO buffe rs (rec eive po ols) ar e provi ded for each c hannel in rece ive
direction.
There are differe nt interrupt indic ations concerned with the rec eption of data :
HDLC/SDLC/PPP
•’RPF’ (Receive Pool Full) interrupt, indicating that a specified number of bytes (limited
with the receive FIFO threshold in register CCR3H, bit field ’RFTH(1..0)’; default is 32
bytes) can be read from RFIF O and the received message is not y e t co mplete.
•’RME’ (Receive Message End) interrupt, indicating that the reception of one message
is completed, i.e. either
- one mes s age which f its int o R F I FO not excee d ing the receive FIFO thre shold, or
- the last part of a mess age, all in all exceeding the re ceive FIFO threshol d
is stored in the RFIFO.
In addition to the message end (’RME’) interrupt the following information about the
received packet is stored by SEROCCO-D in speci al registers and/or RFIFO:
START
XFIFO
READY
'XPR' Interrupt
Reset Transmitter
(CMDRL.XRES)
Write Data to
XFIFO
(up t o 32 byt e s)
End of M e ssage
?
Yes
No
Is s u e Co m mand
CMDRL.XF+.XME
or
CMDRL.XIF+.XME
Issue Command
CMDRL.XF
or
CMDRL.XIF
Action taken
by CPU
Interrupt
indication to CPU
Transmit serial
dat a an d
append trailer
Transmit serial
data
Action taken
by the SCC
PEB 20542
PEF 20542
Programming
Data Sheet 261 2000-09-14
ASYNC, BISYNC
•’RPF’ (Receiv e Pool Full) int errupt, indi cating t hat a specified n umber of b ytes (refer
to register CCR3H, bit field ’RFTH(1..0)’) c an be read from R F I FO.
•’TCD’ (Termina tion Charac ter Detec ted) interrupt, indicat ing that recepti on has been
terminated by reception of a specified character (refer to register TCR and bit
CCR3L.TCDE).
Additionally, the CPU can have access to contents of RFIFO without having received an
interrupt (and thereby causing ’TCD’ to occur) by issuing the RFIFO Read command
(CMDRH.RFRD).
In addition to every received character the assigned status information Parity bit (0/1),
Parity Error (yes/no), Framing Error (yes/no, ASYNC only!) is optionally stored in RFIFO.
With an end conditi on (’TCD’ interrupt or after ’RFRD’ command) th e length of the la st
received data block is stored in register RBCL. The number of bytes to read from RFIFO
is det ermi ned b y the 1, 2, 4 or 5 leas t sign ifi cant bits o f re gist er RBCL, depending on the
selected RFIFO thr eshold (bit field ’RFTH(1..0)’ in regis t er CCR3H).
Note : (Fo r all serial modes) After the received da ta has been read from the RFIFO, this
must be explicitly acknowledged by the CPU issuing an ’RMC’ (Receive Messa ge
Complete) command. The CPU has to handle the ’RPF’ interrupt before the
complete 2 x 32-byte FIFO is filled up with receive data which would cause a
“Receive Data Overflow” condition.
The da t a reception sequenc e, from the CPU’s point of view, is out lined in Figure 60.
Table 16 Status Information after RME interupt
Status Information Location
Length of received message registers RBCH, RBCL
CRC result (good/bad) RSTA regist er (or l ast byte of r eceived dat a)
Valid frame (yes/no) RSTA regi ster (or l ast byte o f received d ata)
ABO RT sequence recogniz ed (yes/n o) RSTA re gister ( or last byt e of receiv ed data)
Data overflow (yes/no) RSTA regi ster (or l ast byte o f received d ata)
Results from ad dress comparison
(with aut om at ic address handling) RSTA re gister ( or last byt e of receive d data)
Type of frame (COMMAND/RESPONSE)
(with aut om at ic address handling) RSTA re gister ( or last byt e of receive d data)
Type of Signaling Unit
(in SS7 mode) RSTA regi ster (or l ast byte o f received d ata)
PEB 20542
PEF 20542
Programming
Data Sheet 262 2000-09-14
1) A receive threshold of 32 bytes is the default for HDLC/PPP mode. It can be programmed with bit field
RFTH(1:0) in register CCR3H.
2) The number of bytes stored in RFIFO can be determined by evaluating the lower bits in register RBCL
(depending on the selected receive threshold RFTH(1:0)).
Figure 60 Interrupt Driven Data Reception (Flow Diagram)
START
WAIT FOR
INTERRUPT
Reset Receiver
(CMDRH.RRES)
Activate Receiver
(CCR3L.RAC)
Action taken
by CPU
Interrupt
indication to CPU
'RPF'
Interrupt
Read
[32]
1)
bytes from RFIFO
Release RFIFO
(CMDRH.RMC)
Read registers
RBCL, RBCH
(Rc Byte Count)
'RME'/'TCD'
Interrupt
Read
[RBCL % 32]
1), 2)
bytes from RFIFO
PEB 20542
PEF 20542
Programming
Data Sheet 263 2000-09-14
6.3 Internal DMA Mode
The following table provides a definition of terms used in this chapter to describe the
operat ion of the DMA controller.
6.3.1 Data Transm ission (DMA Controlled)
Standard Transfer Mode:
Any packet transmission is prepared by writing the transmit buffer start address into
registers TBADDR1L/M/H and the packet size in number of bytes to registers XBC1L/
XBC1H.
Now the r e are two possible s c enarios:
•If the prepared transmit buffer in memory contains a complete packet, the start
command for DMA transmission is issued by setting bits ’XF’ and ’XME’ in register
XBC1H to ’1’. The DMA controller will request the external bus and then read transmit
data beginning at address TBADDR1. The data is immediately transferred into the
XFIFO. After the last byte has been transmitted, the protocol machine appends the
Table 17 DMA Terminology
Packet A "Packet" is a connected block of data bytes. This can be
an HDLC/PPP fra me as wel l as a number of ASYNC/
BISYNC characters up to a specific limit (rece ived
termination character, CMDRH:RFRD command). If a
receive stat us by t e (RSTA) is attached to data bytes, it is
also con si dered as part of the packet.
Buffer A "Buffer" is a limited space in memory that is reserved for
DMA reception/transmission. Every t im e the DMA
controller completes a buf f er t ransfer, it not if ies t he C PU
with an appropriate int errupt.
A packet can go into one single buffer, or it can go
fragmented into multiple buffers.
Block A "Block" is the amount of data that is transfered from the
memory to the XFIFO (transmit DMA transfer) or from the
RFIFO to the memory. In HDLC/PPP modes the block size
is 32 bytes by default. It can be lowered with the receive
FIFO threshold in register CCR3H, bit field ’RFTH(1..0)’.
Bus Cycle A "Bus Cy cle" correspon ds to a single byte/word transfer.
Multipl e bus cycles ma ke up a block transfer.
DMA Transfer A "DMA Tra nsfer" is the moveme nt of complete buffers
and/or packets between t he XFIFO/R F IFO and th e
memory.
PEB 20542
PEF 20542
Programming
Data Sheet 264 2000-09-14
trailer (e.g. CRC and Flag in HDLC), if applicable. The Transmit DMA Transfer End
(TDTE) interrup t is ge nerated (refer to Figure 61).
•If a transmit p acket is distributed over m ore than one tra nsmit buff er in mem ory, th e
’XF’ command (without setting the ’XME’ bit)starts transmission of a buffer. A Transmit
DMA Transfer End (TDTE) interrupt is generated whenever a block of <XBC1> bytes
is completely transferred. For the last buffer, containing the end of the transmit packet,
the ’XF’ command is issued together with bit ’XME’ set (refer to Figure 62).
After transmission is complete, the optional generation of the ALLS interrupt indicates
that all tr ansmit data has been sent on pi n TxD.
Any ’XF’ command resets the transmit DMA controller for new operation starting with
TBADDR1 an d XBC1 again.
Note: In HDLC Automode, the ’XF’ command may be replaced by the ’XIF’ command in
the same regis te r , wh en transmission of an I -f r am e is desired.
Figur e 61 DMA T r an smit (Single Buffer per Pa cket)
CPU / ME M ORY MIST RAL
TBADDR1
XBC1
(write transmit buffer start address)
(write transmit byte count with
com m and bit 'XF'+'XME')
...
TFIFO
TFIFO
TFIFO
DMA transfer of
<XBC1> transmit
data bytes
TDTE interrupt
ALL S interrupt (optional)
TBADDR1
XBC1
(write transmit buffer start address)
(write transmit byte count with command
bit 'X F '+ 'XM E ')
...
Packe t n:
Packe t (n+1):
PEB 20542
PEF 20542
Programming
Data Sheet 265 2000-09-14
Figure 62 Fragmented DMA Transmission (Multiple Buffers per Packet)
CPU / ME MORY MIS TR AL
TBADDR1
XBC1
(write transmit buffer start address)
(write transmit byte count with
com mand bit 'XF')
...
TFIFO
TFIFO
TFIFO
DMA transfer of
<XB C1> tran s mi t
data bytes
TDTE interrupt
ALLS interrupt (optional)
TBADDR1
XBC1
(write transmit buffer start address)
(write transmit byte count with command
bit 'X F ')
...
TFIFO
TFIFO
TFIFO
DMA transfer of
<XB C1> tran s mi t
data bytes
TDTE interrupt
TBADDRi1
XBC1
(write transmit buffer start address)
(write transmit byte count with command
bit 'X F '+ 'XME')
...
TFIFO
TFIFO
TFIFO
DMA transfer of
<XB C1> tran s mi t
data bytes
TDTE interrupt
Packe t n, Bu ffer 0:
Packe t n, Bu ffer 1:
Packe t n, Bu ffer m:
PEB 20542
PEF 20542
Programming
Data Sheet 266 2000-09-14
The data transmission fl ow, from the CPU’s point of view, is outlined in Figure 67.
Figure 63 DMA Controlled Data Transmission (Flow Diagram)
6.3.2 Data Reception (DMA Controlled)
The re ceive D MA co ntrolle r h as to be prepa red by writing an appro pria te a ddres s to i ts
RBADDR1L/M/H registers and the maximum buffer size to register RMBSL/RMBSH. If
a new packet is received by the SCC, the DMA controlle r will req uest the external bus
and then move receive data out of the RFIFO. The receive data is directly written on the
external bus, beginning at address RBADDR1.
Now the DMA has to face two possible scenarios:
•If the maximum buffer size programmed in register RMBSL/RMBSH has been
transferred, DMA transfer stops and a Receive Buffer Full (RBF) interrupt is
generated. The CPU now updates the receive buffer base address in the appropriate
registers RBADDR1L/M/H and restarts the DMA receiver by setting the ’RE’ bit in
register RMBSH. Optional ly the max imum bu ffer si ze value c an be upd ated with the
same register write access.
START
TX DMA
READY
'TDTE' Interrupt
Enable DMA
(set bit 'IDMA' in
register GMODE)
Set TxBuffer Base
Address
(TBADDR1H/M/L)
End of M essage
in TxBuffer
?
Yes
No
Set Tx Byte Count
('XBC') a nd issu e
'XF'+'XME'
command
(register XBC1L/H)
Action taken
by CPU
Interrupt
indication to CPU
Set Tx Byte Count
('XBC') and issue
'XF'
command
(register XBC1L/H)
'TDTE' Interrupt
Action taken by
internal DMA
DMA Controller
reads <XBC> bytes
of transmit data
DMA Controller
reads <XBC>
bytes of transmit
data (incl. end of
message)
Transmit
Data available
?
Yes
No
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Programming
Data Sheet 267 2000-09-14
•If the end of a received packet/block is contained in the current receive buffer, the
DMA controller generates a Receive DMA Transfer End (RDTE) interr upt and stops
opera tion. Th e CPU now re ads th e rec eived b yte c ount fr om reg isters RBCL/RBCH.
The rec eive DM A controller will not continue operation unt il it is set up again with the
’RE’ command in register RMBSH. The software should update RBADDR1L/M/H
registers if necess ary bef ore issuing th e ’RE’ command.
If in packet oriented protocol modes (HDLC, PPP) the maximum receive buffer size
RMBS is chosen to be larger than the expected receive packets, each buffer will contain
the whole pac ket (see Figure 64). In this case a Receive Buffer Full (RBF) interrupt will
never occur, simplifying the software. To ensure that no packets exceeding the
maximum buffer size are forwarded from the SCC to the RFIFO, the receive packet
length should be limited with registers RLCRL/RLCRH.
Figure 64 DMA Receive (Single Buffer per Packet)
CPU / MEMORY MISTRAL
RBADDR1
RMBS
(w rite receive buffer start address)
...
RFIFO
RFIFO
RFIFO
DM A transfer of all
receive data bytes
RDTE interrupt
...
Packet 0:
Packet 1:
RBC
(read R BC register)
(w rite receive buffer start address)
RBADDR1
(set m ax. receive buffer size
and issue 'R E' comm and)
(issu e 'R M C' comm and)
CMDR
PEB 20542
PEF 20542
Programming
Data Sheet 268 2000-09-14
Figure 65 shows an example for fragmented reception of a packet larger than the
prepared receive buffers in memory. In this case the length of the received packet is 199
bytes, each of the buffers in host memory is 128 bytes deep:
Figure 65 Fragmented Reception pe r DMA (Example)
After the D M A controller is initialized wit h the base address of receive buf f er #1 and the
maximum buffer size RMBS, simultaneously activated with the ’RE’ command, DMA
trans fer from t he RFIFO to the receive b uffer ta kes place in blocks of 32 b ytes (u nless
changed with bit field ’RFTH’ in register CCR3H).
After four 32-byte-blocks have been transferred, the first receive buffer is filled up
complet ely with receiv e data. The DMA controller in dicates this b y generatin g the RBF
interrupt.
Now the CPU has to provide the base address of the second receive buffer to th e DMA
controller and issue the ’RE’ command again. This allows the DMA controller to continue
data transfers into the second receive buffer. After another two 32-byte-blocks have
been transferred, the remaining 7 bytes (including the RSTA byte) are written to the
buffer, follwed by the generation of the RDTE interrupt. Now the DMA transfer is
completed and software has to read the number of received bytes from the Receive Byte
Count registers RBCL/RBCH.
The following figure (Figure 66) gives the sequence of actions from both, the internal
DMA controller of SEROCCO-D and the CPU for this example (fragmented reception of
199 bytes into two receive buffers):
32 32 32 32 32 32 7
128
1
...
199 By tes Payl oad
128
1
1st pac ket
fragment 2nd packet
fragment
...
Receive Buffers
in Memory
Packet
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Programming
Data Sheet 269 2000-09-14
Figure 66 Fragmented Reception Sequence (Example)
Performance:
In sing le buffer operat ion, only 2 regis ter accesses are required f or transmissio n and 4
for reception for each buffer besides first initialization:
•update TBADDR1, upd ate XBC1 (including co mmand ’XF’)
•update RBADDR1 , issue ’RE’ command (in RMBS register), read register RBC, issue
’RMC’ comman d (in register CMDRH).
CPU / MEMORY MISTRAL
RBADDR1
RMBS
(write receive buffer start address)
(issue 'R E' com m and)
RFIFO
RFIFO
RFIFO
DM A transfer of 128
re c eiv e da ta b yte s
RBF interrupt
...
Packet 1, Fragment 1:
Packet 2, Fragment 1:
RBC
(read RBC register)
(write receive buffer start address)
RBADDR1
RBADDR1
(write receive buffer start address)
RFIFO
RFIFO
RFIFO
DM A transfer of 71
re c eiv e da ta b yte s
R DTE in te rru p t
Packet 1, Fragment 2:
RFIFO
32
32
32
32
32
32
7
RMBS
(set m ax. receive buffer size to 128 bytes
and issue 'RE' com m and)
CMDR
(issue 'R M C ' com m and )
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Programming
Data Sheet 270 2000-09-14
The data reception flow, from the CPU’s point of view, is outlined in Figure 67.
Figure 67 DMA Controlled Data Reception (Flow Diagram)
6.3.3 Bu ffer Switched Mode
In buffer switched mode, operation will be similar but the DMA controller will
autonomously switch between buffer base addresses TBADDR1/RBADDR1 and
TBADDR2/RBAD DR2 after any buffer completion.
START
RX DMA READY
Action taken by
CPU
Interrupt
indication to CPU
'RBF'
Interrupt
Release RFIFO
(CMDRH.RMC)
'RDTE'
Interrupt
Enable DMA
(set bit 'IDMA' in
register GMODE)
RX DMA ACTI VE
Set Base Address
of current R xBu ff er
(RBADDR1H/M/L)
Set Max Bu ffer
Size ('RMBS') and
Enable Re ceive
('RE') in register
RMBSL/H
The 'RDTE' interrupt
indi cat es th at the end of the
packet curren tly re ceive d is
containe d in t he curren t
RxBuffer.
The 'R BF ' int er rup t
indicates that the DMA
control ler f ille d th e curren t
RxBuffer to the maximum
level (<RMBS> bytes).
The end of the packet is not
containe d in this RxBuf fer.
Read Receive
Byte Count
(RBCL/H)
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Programming
Data Sheet 271 2000-09-14
A reset command will force the DMAC to begin with base addresses TBADDR1/
RBADDR1. Setting bit ’XF’ (and ’XME’) in the XBC1H register will start transmission.
Sett i ng bit ’RE’ in register RMBSH enables reception. The DMA controller automatically
reloads the configuration values (base address TBADDRi/RBADDRi and byte count
XBCi/ RMBS) from th e alternate regi ster set. T ransmis sion can be sto pped by reset ting
the ’XF’ bit back to ’0’.
Status bits in register DBSR indicate which buffer is currently in operation (for debug
purposes).
A TDTE interrupt indicates completion of a transmit buffer, an RDTE/RBF interrupt
indicat e s c o m pletion of a receive buffer.
Thus DMA operation is completely autonomous with no additional register access during
operation.
In case of HDLC/PPP packet oriented protocol mode, the buffer size is assumed to
contain complete transmit/receive packets (single buffer operation).
Furtherm or e thi s mode supp orts con tinuou s trans miss ion (no H DLC/ PPP f ram ing) v ery
effectively.
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Electrical Characteristics
Data Sheet 272 2000-09-14
7 Electrical Characteristics
7.1 Absolute Maximum Ratings
Note:Stresses above those listed here may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended
peri o ds may affect device r el i ability.
7.2 Operating Range
Note : In the operating range, the fu nc tions give n in t he c i rc uit descripti on are fulfilled.
Parameter Symbol Limit Values Unit
Ambient temperature under bias PEB
PEF TA
TA
0 to 70
– 40 to 85 °C
°C
Storage temperature Tstg – 65 to 125 °C
IC supply voltage VDD3 – 0.3 to 3. 6 V
Voltage on any sig nal pin with respect to
ground VS– 0. 4 to 5.5 V
ESD robustness1)
HBM: 1.5 kW, 100 pF
1) According to MIL-Std 883D, me thod 3015.7 and ESD Ass. Standard EOS/ESD-5.1-1993.
VESD,HBM 2000 V
Parameter Symbol Limit Values Unit Test Condition
min. max.
Ambient temperaturePEB
PEF TA
TA
0
-40 70
85 °C
°C
Junction temperature TJ0125°C
Supply voltage VDD3 3.0 3.6 V
Ground VSS 00V
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Electrical Characteristics
Data Sheet 273 2000-09-14
7.3 DC Characteristics
Parameter Symbol Limit Values Unit Notes
min. max.
Input low voltage VIL – 0.4 0.8 V
Input hi gh voltage VIH 2.0
2.1 5.5
5.5 V
VVDD =3.3V
VDD =3.6V
Output low voltage VOL 0.45 V IOL =7mA
1)
IOL =2mA
2)
1) Apply to the next pins: TxDA, TxDB.
2) Apply to all the I/O and O pins that do not appear in the list in note 1), excep t XTAL2.
The listed characteristics are ensured over the operating range of the integrated
circu it. Typical characteristics spec ify mean values ex pected over the pr oduction
sprea d. If not othe rwise specif ied, typical characteris tics apply at TA = 25 °C and
the given supply voltage.
Output high voltage VOH 2.4 V IOH =–1.0 mA
Power
supply
current
operational
(average) ICC (AV) 50 mA VDD =3.3V,
TA=25°C,
CLK = 33 MHz,
XTAL = 20 MHz,
inpu ts at VSS/VDD,
no ou tput loads
power do wn
(no clocks) ICC (PD) 0.01 mA VDD =3.3V,
TA=25°C
Power dissipation P150 mW VDD =3.3V,
TA=25°C,
CLK = 33 MHz,
XTAL = 20 MHz,
inpu ts at VSS/VDD,
no ou tput loads
Input leakage current ILI 1mAVDD =3.3V,
GND = 0 V;
inpu ts at VSS/VDD,
no ou tput loads
Output leakage current ILO 1mAVDD =3.3V,
GND = 0 V ;
VOUT =0V,
VDDP +0.4
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Electrical Characteristics
Data Sheet 274 2000-09-14
7.4 AC Characteristics
Interface Pins
TA = 0 to + 70 °C; VDD3 = 3.3 V ± 0.3 V
Inputs are driven to 2.4 V for a logical “1” and to 0.4 V for a logical “0”. Timing
meas urements are ma de at 2. 0 V for a logical “1” and at 0.8 V for a logic al “0”.
The AC testing input/output waveforms are shown below.
Figure 68 Input/Output Waveform for AC Tests
7.5 Capacitances
Interfa ce Pins
Table 18 Capacitances
TA = 25 °C; VDD3 = 3. 3 V ± 0. 3 V, VSS = 0 V
Parameter Symbol Limit Values Unit Test Condition
min. max.
Input capa citance CIN 5pF
Outp ut capaci tance COUT 10 pF
I/O-capacitance CIO 15 pF
ITS09800
= 50 pF
Load
C
Test
Under
Device
0.45
2.4 2.0
0.80.8
2.0 Test Points
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Electrical Characteristics
Data Sheet 275 2000-09-14
7.6 Thermal Package Characteristics
Table 19 Thermal Packa ge Characteristics P-TQFP-144-10
Parameter Symbol Value Unit
Thermal Pa ck age Resistan ce Junc ti on to Ambi ent
Airflow: Ambient Temperature:
without airflow TA=-40°CqJA(0,-40) 43.0 K/W
without airflow TA=+25°CqJA(0,25) 38.9 K/W
airflow 1 m /s (~200 lfpm) TA=+25°CqJA(1,25) 37.0 K/W
airflow 2 m /s (~400 lfpm) TA=+25°CqJA(2,25) 36.4 K/W
airflow 3 m /s (~600 lfpm) TA=+25°CqJA(3,25) 36.0 K/W
PEB 20542
PEF 20542
Electrical Characteristics
Data Sheet 276 2000-09-14
7.7 Timing Diagrams
7.7.1 Microprocessor Interface Timing
7.7.1.1 Microprocessor Interface Clock Timing
Figure 69 Micr oproc e ss or Interface Clock Timing
Table 20 Mi cr oproc e sso r Interface Cloc k Tim ing
No. P ar ameter Limit Va l ue s Unit
min. max.
1 CLK clock period 30 ¥
1) A clock supply is needed for read access to the on-chip interrupt status registers (I SR , DISR) and for general
purpose port (GPP) operation.
ns
CLK frequency 0 33 MH z
2 CLK high time 11 ¥ns
3 CLK low time 11 ¥ns
CLK
1
32
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Electrical Characteristics
Data Sheet 277 2000-09-14
7.7.1.2 Infineon/Intel Bus Interface Timing (Slave Access)
Figure 70 Infineon/Intel Read Cycle Timing (Slave Access)
Figure 71 Infineon/Intel Write Cycle Timing ( Slave Access)
A(7:0)
BHE
1)
CS
D(7:0)
D(15:8)
1)
RD
READY
4657
8
14a 15a
17
11a
11
INT
2)
16
10
14 15
(1) Signals BHE and D(15:8) only available in 16-bit Infineon/Intel bus mode.
(2) Interrupt signal shown is push-pull, act ive high. Same timings apply to push-pull, active low interrupt
signal. In case of open-drain output the timing depends on external components.
A(7:0)
BHE
1)
CS
D(7:0)
D(15:8)
1)
WR
READY
4657
12 13
9
14a 15a
17
14 15
(1) Signals BHE and D(15:8) only available in 16-bit Infineon/Intel bus mode.
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Electrical Characteristics
Data Sheet 278 2000-09-14
Table 21 Infineon/Intel Bus Interface Timing (Slave Access)
No. Parameter Limit Values U nit
min. max.
4 activ e address to act iv e R D /WR setup time 8 ns
5 inactive RD/WR to inactiv e address ho ld time 0 ns
6active CS
to active RD/WR setup time 2 ns
7 inactive RD/WR to inactive CS hold ti me 0 ns
8RD
active pulse width 301)
1) At least one rising CLK edge must appear during read pulse active for interrupt status register (ISR, DISR)
read.
ns
9WR
active pulse width 30 ns
10 active RD to vali d data del ay 20 ns
11 inactive RD to invalid data hold time 5 ns
11a inactive RD to data high impedance delay 25 ns
12 valid dat a t o inactive WR setup time 6 ns
13 inactive WR to invalid data hold time 5 ns
14 active RD/WR to active READY delay 20 ns
14a active CS to driven READY delay 20 ns
15 inactive RD/WR to inactive READY delay 15 ns
15a inactive CS to READY high im pedance de lay 15 ns
16 inactive RD to inactive INT/INT delay 1 TCLK2)
2) TCLK is the system clock (C LK) period.
17 RD/WR inactive pulse width 30 ns
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Electrical Characteristics
Data Sheet 279 2000-09-14
7.7.1.3 Motorola Bus Interface Timing (Slave Access)
Figure 72 Motorola Read Cycle Timing (Slave Access)
Figur e 73 Motoro l a W rite Cycle Timing (Slave Access)
A(7:0)
A(7:1)
1)
CS
R/W
D(7:0)
D(15:8)
1)
DS
LDS, UDS
1)
DTACK
40
42
41
43
44 45
46
52a 53a
55
INT
2)
49a
49
48
54
52 53
(1) Signals LDS, UDS and D(15:8) only available in 16-bit Motorola bus mode
(2) Interrupt signal shown is push-pull, active high. Same timings appl y to push-pull, active low i nterrupt
signal. In case of open-drain output the timing depends on external components.
A(7:0)
A(7:1)
1)
CS
R/W
D(7:0)
D(15:8)
1)
DS
LDS, UDS
1)
DTACK
40
42
41
43
44 45
50 51
47
52a 53a
55
52 53
(1) Signals LDS, UDS and D(15:8) only available in 16-bit Motorola bus mode
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Electrical Characteristics
Data Sheet 280 2000-09-14
Tabl e 22 Mot or ola Bus Interface Timin g (Slave A c cess)
No. P ar ameter Lim it V al u es Unit
min. max.
40 active address to active DS setup time 0 ns
41 inactive DS to inactive add res s hold time 0 ns
42 active CS to active DS setup time 0 ns
43 inactive DS to inactive CS hold time 0 ns
44 active R/W to active DS setup time 0 ns
45 inactive DS to inactive R/W hold time 0 ns
46 DS active pulse width (read acce ss ) 301)
1) At least one rising CLK edge must appear during read data strobe active for interrupt status register (ISR,
DISR) read.
ns
47 DS active pulse width (writ e ac c es s ) 30 ns
48 active DS (read) to valid data delay 20 n s
49 inactive DS (rea d) t o inv alid data hold tim e 5 ns
49a inactive DS (read) t o dat a high impeda nc e delay 20 ns
50 valid dat a t o inactive DS (write) setup tim e 10 n s
51 inactive DS (write) to invalid data hold time 10 ns
52 active DS to active DTACK delay 20 ns
52a active CS to driving DTACK de lay 20 ns
53 inactive DS to inactive DTACK delay 1 5 ns
53a inactive CS to DTA CK high impedance dela y 15 ns
54 inactive DS (read) to inactive INT/ INT delay 1 TCLK
55 DS inactive pulse width 30 ns
56 active DS (read) to inactive DRR delay 22 ns
57 active DS (write) to inac tive DRT delay 22 ns
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Electrical Characteristics
Data Sheet 281 2000-09-14
7.7.1.4 Infineon/Intel B us Interface Timing (Master Access)
Figure 74 Infineon/Intel Read Cycle Timing (Master Access)
A(23:0)
BHE
1)
ADS
D(7:0)
D(15:8)
1)
RD
READY
60a
61a
60b
6766
62a
6463
CLK
62b
W/R
61b
T1 T2 T1 T2
BGACK
68a
68a
68a
68a
68a
68b
68b
68b
68b
68b
(1) Signals BHE and D(15:8) only available in 16-bit Infineon/Intel bus m ode
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Electrical Characteristics
Data Sheet 282 2000-09-14
Figure 75 Infineon/Intel Write Cycle Timing (Master Acc e ss )
Table 23 Infineon/Intel Bus Interface Timing (Master Access)
No. P ar ameter Limit Va l ue s Unit
min. max.
60a clock to valid address delay 22 ns
60b clock to invalid addre ss de lay 22 ns
61a c l o ck to a ctive ADS delay 15 ns
61b clock to inactive ADS delay 15 ns
62a c l o ck to a ctive RD / WR delay 20 ns
62b clock to inactive RD / WR delay 20 ns
63 valid dat a t o inactive RD setup time 5 ns
64 inactive RD to invalid data hold time 5 n s
65a active WR to va l id data de l ay 20 ns
65b inactive WR to invalid da ta dela y 20 ns
66 active READY to clock setup time 5 ns
67 clock to inactive READY hold time 5 ns
A(23:0)
BHE
1)
ADS
D(7:0)
D(15:8)
1)
WR
READY
60a
61a
60b
6766
62a
65b
CLK
62b
W/R
61b
T1 T2 T1 T2
BGACK
68a
68a
68a
68a
68a
68a
65a
68b
68b
68b
68b
68b
68b
(1)Signals BHE and D(15:8) only available in 16-bit Infineon/Intel bus mode
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Electrical Characteristics
Data Sheet 283 2000-09-14
7.7.1. 5 Motorola Bus Interf ac e Ti min g (Mast er Acce ss)
Figure 76 Motorola R ead C ycle Timing (M aster Access)
68a clock to driving bus de lay 22 ns
68b clock to bus high im pedance delay 22 ns
Table 23 Infineon/Intel Bus Interface Timing (Master Access) (cont’d)
No. P ar ameter Limit Va l ue s Unit
min. max.
D(7:0)
D(15:8)
1)
70a
71a
70b
7776
72a
7473
CLK
72b
71b
BGACK
78a
78a
78a
78a
78a
78b
78b
78b
78b
78b
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7
A(23:0)
A(23:1)
1)
AS
DS
LDS, UD S
1)
DTACK
R/W
(1) Signals LDS, UDS and D(15:8) only available in 16-bit Motorola bus m ode
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Electrical Characteristics
Data Sheet 284 2000-09-14
Figure 77 Motorola Write Cycle Timing (Master Access)
Tabl e 24 Mot or o la Bus Interface Ti ming (Master Access)
No. P ar ameter Limit Va l ue s Unit
min. max.
70a clock to valid address delay 22 ns
70b clock to invalid addre ss de lay 22 ns
71a c l o ck to a ctive AS delay 20 ns
71b clock to inactive AS delay 20 ns
72a c l o ck to a ctive DS / LDS/UDS delay 20 ns
72b clock to inactive DS / LDS/UDS delay 20 ns
73 valid dat a t o inactive DS (read) set up t i m e 5 ns
74 inactive DS (rea d) t o inv alid data hold tim e 5 ns
75a active DS (write) to valid data delay 20 n s
75b inactive DS (write) t o inv alid data delay 20 ns
76 active DTACK to clock setup time 5 ns
77 clock to inactive DTACK hold time 5 n s
A(23:0)
A(23:1)
1)
AS
D(7:0)
D(15:8)
1)
DS
LDS, UDS
1)
DTACK
70a
71a
70b
7776
72a
75b
CLK
72b
R/W
71b
S0
BGACK
78a
78a
78a
78a
78a
78a
75a
78b
78b
78b
78b
78b
78b
S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7
(1) Signals LDS, UDS and D(15:8) only available in 16-bit Motorola bus mode
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Electrical Characteristics
Data Sheet 285 2000-09-14
7.7.1.6 Bus Arbitration Timing
Figure 78 Bus Arbitrat ion Timing
78a clock to driving bus de lay 22 ns
78b clock to bus high im pedance delay 22 ns
Table 25 Bus Arbitra t ion Timing
No. P ar ameter Limit Va l ue s Unit
min. max.
200 cl o c k to ac ti ve BREQ delay 2 2 ns
201 clock to i nactive BREQ delay 24 ns
202 c l o ck to a ctive BG ACK delay 22 ns
203 BREQ i nacti ve time 7 TCLK
204 inactive BGNT to active BREQ delay 2 TCLK
205 active BGNT to active BGACK del ay 4 TCLK
Tabl e 24 Mot or ola Bus In terface Timing (Master A ccess) (cont’d)
No. P ar ameter Limit Va l ue s Unit
min. max.
CLK
BREQ
BGNT
BGACK
200 203
202
201
204
205
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Electrical Characteristics
Data Sheet 286 2000-09-14
7.7.2 PCM Serial Interface Timing
7.7.2.1 Clock Input Timing
Figure 79 Cloc k Input Timing
Table 26 C loc k Input Timi ng
No. P ar ameter Limit Va l ue s Unit
min. max.
81 RxCLK clock period 62 ¥ns
82 RxCLK high time 25 ¥ns
83 RxCLK low time 25 ¥ns
84 TxCLK clock period 62 ¥ns
85 TxCLK high time 25 ¥ns
86 TxCLK low time 25 ¥ns
87 XTAL1 clock period (intern al oscillator used) 25 100 n s
XTAL1 clock period (TTL clock signal supplied) 25 ¥ns
88 XTAL1 high time (internal oscillator used) 12 46 ns
XTAL1 high time (TTL clock signal su pplied) 12 ¥ns
89 XTAL1 low time (internal oscillator used) 12 46 ns
XTAL1 low time (TTL clock signal supplied) 12 ¥ns
RxCLK
TxCLK
XTAL1
81,84,87
82,85,88 83,86,89
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Electrical Characteristics
Data Sheet 287 2000-09-14
7.7.2.2 Receive Cycl e Ti ming
Figure 80 Receiv e Cycle Timing
Table 27 Receive Cycle Timing
No. Paramete r Limit Values U n it
min. max.
Receive
data rate s externally clocked
(HDLC) 016 Mbit/s
internally clocked
(DPLL modes) 02Mbit/s
internally clocked
(non DP LL modes) 016 Mbit/s
90 Clock
period externally clocked 62 ¥ns
internally clocked
(DPLL modes) 480 ¥ns
internally clocked
(non DP LL modes) 62 ¥ns
91 RxD to RxCLK setup time 5ns
92 RxD to RxCLK hold time 5ns
90
91 92
91 92
93 94
Receive Clock
(Note 1)
RxD
(Note 2)
RxD
(Note 3)
CD
(Note 4)
91 92
(1)Whichever supplies the receive clock depending on the selected clock mode:
externally clocked via RxCLK or XTAL1 or
internally clocked via DPLL, BCR or BRG.
(No edge relation can be measured if the internal receive clock is derived from the external clock
source by division stages (BRG, BCR) or DPLL)
(2)NRZ, NRZI and Manchester data encoding
(3) FM0 and FM1 data encoding
(4)If Carrier Detect auto start feature enabled (not for clock modes 1, 4 and 5)
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Electrical Characteristics
Data Sheet 288 2000-09-14
7.7.2. 3 Transmit Cycl e Ti min g
Figure 81 Transmit Cycle Timing
93 CD to RxCLK rising edge setup time 5ns
94 CD to RxCLK falling edge hol d time 5ns
Table 27 Receive Cycle Timing (cont’d)
No. Paramete r Limit Values U n it
min. max.
100
101
Transmit Clock
(Note1)
TxD
(Note2,5)
TxD
(Note3)
TxCLK
(Note4)
106
102
103
104 105
106
102
103
CxD
CTS
RTS
(Note5)
(1)Whichever supplies the transmit clock depending on the sel ected clock mode:
externally clocked via TxCLK, RxCLK or XTAL1 or
internally clocked via DPLL, BCR or BRG.
(No edge relation can be measured if the internal transmit clock is derived from the external clock
source by division stages (BRG, BCR) or DPLL)
(2)NRZ, NRZI and Manchester data encoding
(3) FM0 and FM1 data encoding
(4)If TxCLK output feature is enabled (only in some clock modes)
(5)The timing is valid for non bus configuration modes and bus configuration mode 1. In bus configuration
mode 2, TxD and RTS are right shifted for 0.5 TxCLK periods i.e. driven by the falling TxCLK edge.
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Data Sheet 289 2000-09-14
Table 28 Transmit Cycle Timing
No. Parameter Limit Values Unit
min. max.
Transmit
data rates externally clocked 0 16 Mbit/s
internally clocked
(DPLL modes) 02Mbit/s
internally clocked
(non DPLL modes) 016Mbit/s
100 Clock
period externally clocked 62 ¥ns
internally clocked
(DPLL modes) 480 ¥ns
internally clocked
(non DPLL modes) 62 ¥ns
101 TxD to TxCLK delay (NRZ, NRZI encoding) 25 ns
102 TxD to T x CLK dela y (F M0, FM1, Manches te r
encoding) 25 ns
103 TxD to Tx CLK(out) de lay (output function e nabled) 10 25 ns
104 CxD to TxCLK setup t i me 5 ns
CTS to TxCLK setup time 5 ns
105 CxD to TxCLK hold ti me 5 ns
CTS to TxCLK hold time 5 ns
106 RTS to TxCLK de lay (not bus configuration mo de) 20 ns
RTS to TxCLK delay (bus configuration mode) 2 0 ns
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Electrical Characteristics
Data Sheet 290 2000-09-14
7.7.2.4 Clock Mode 1 Strobe Timing
Figure 82 Clock Mode 1 Str obe Ti ming
Table 29 Clock Mode 1 Strobe Ti ming
No. P ar ameter Limit Values Un i t
min. max.
110 Receive strobe to RxCLK setup 5ns
111 Receive strobe to RxCLK hold 5ns
112 Transmit strobe to RxCLK se tup 5ns
113 Transmit strobe to RxCLK hold 5ns
114 TxD to RxCLK de lay 10 25 ns
115 TxD to RxCLK high imped ance delay 10 25 ns
110 111
valid
112 113
114
114
115
115
RxCLK
CD
(RxStrobe)
RxD
(Note1)
TxCLK
(TxStrobe)
TxD
(Note1,3)
TxD
(Note2,3)
(1) No bus configuration mode and bus configuration mode 1
(2) Bus configuration mode 2
(3) TxD Idle is either active high or high impedance if ’open drain’ output type is selected.
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Electrical Characteristics
Data Sheet 291 2000-09-14
7.7.2.5 Clock Mode 4 Gating Timing
Figure 83 Cloc k Mode 4 Rec eive Gating Timing
Figure 84 Clock Mode 4 Tra n sm it Gating Ti ming
Table 30 Clock Mode 4 Gating Timing
No. P ar ameter Limit Values Un i t
min. max.
140 RCG setup time 5ns
141 RCG hold time 5ns
142 RxD setup time 5ns
143 RxD hold time 5ns
145 TCG setup time 0ns
146 TCG hold time 6ns
147 TxCLK to TxD delay1)
1) Note that the TxD output is delayed for one additional clock with respect to the gating signal TCG!
10 25 ns
RxCLK
RCG
RxD
140
141
142
143
TxCLK
TCG
TxD
145
146
147
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Electrical Characteristics
Data Sheet 292 2000-09-14
7.7.2.6 Clock Mode 5 Frame Synchronisation Timing
Figure 85 Clock Mode 5 Fra me Synchronisation Timing
Table 31 Clock Mode 5 Frame Synchronis ation Timing
No. P ar ameter Limit Values Un i t
min. max.
130 Sync pulse to RxCLK setup time 10 ns
131 Sync pulse to RxCLK hold time 0ns
132 TxCLKou t to RxCL K delay (time slot monitor) 10 27 ns
132
132
132
132
130 131
RxCLK
CD
(FSC)
TxCLK
Note1
TxCLK
Note2
(1) Normal operation and bus configuration mode 1
(2) Bus configuration mode 2
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Electrical Characteristics
Data Sheet 293 2000-09-14
7.7.3 Reset Timing
Figure 86 Reset Timing
Note: RESET may be assert ed and deass ert ed async hronous to CLK at any tim e.
Table 32 Reset Timi ng
No. Parameter Limit Values Unit
min. max.
150 RESET pulse width 500 ns
151 Number of CLK cycles after
RESET inac t iv e 2CLK
cycles
power-on
VDD3
CLK
RESET
150
151
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Electrical Characteristics
Data Sheet 294 2000-09-14
7.7.4 JTAG-Boundary Scan Timing
Figure 87 JTAG-Boundary Scan Timing
Table 33 JTAG-Boundary Sc an Timing
No. P ar ameter Limit Values Un i t
min. max.
160 T C K period 166 ¥ns
161 T CK high time 80 ns
162 TCK low time 80 ns
163 TMS setup time 30 ns
164 TMS hold time 10 ns
165 TDI setup time 30 ns
166 TDI hold time 20 ns
167 TDO valid delay 60 ns
160
161 162
163 164
165 166
167
TCK
TMS
TDI
TRST
TDO
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Test Modes
Data Sheet 295 2000-09-14
8 Test Modes
8.1 JTAG Boundary Scan Interface
In the SERO CCO- D a Tes t Acc ess Port (TAP ) c ontro ller is impl emen te d. Th e ess enti al
part of the TAP is a finite state machine (16 states) controllin g the different operational
modes of the boundary scan. Both, TAP controller and boundary scan, meet the
requirements given by the JTAG standard: IEEE 1149.1. Figure 88 gives an overview
abou t t he TAP cont roller.
Figure 88 Block Diagram of Test Access Port and Boundary Scan Unit
If no boundary scan operation is planned TRST has to be connected with VSS. TMS, TCK
and TD I do not need to be connected since pull-up transisto rs ensure high inp ut levels
in this case. Nevertheless it would be a good practice to put these unused inputs to
define d levels, using pull-up resistors .
Test handling (boundary scan operation) is performed via the pins TCK (Test Clock),
TMS ( Test Mo de Select), T DI (Test Data Inpu t) and TD O (Test Dat a Outpu t) when th e
TAP controller is not in its reset state, i.e. TRST is connected to VDD or it remains
unco nnec ted due to its in te rna l pull -up. T est da ta at TDI are loaded w ith a 4- M Hz c lock
Clock Generation
Test Access Port (TAP)
TAP Controller
- Finite State Machine
- Instruction Register (3 bit)
- Test Signal Generator
CLOCK
TCK
TRST
TMS
Reset
Data in
TDI
Test
Control
TDO
Enable
Data out
CLOCK
BS Data IN
Identification Sc an (32 bit)
Boundary Scan (n bit)
6
Control
Bus
ID Data out
SS Data
out n
.
.
.
.
.
.
1
2
Pins
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Test Modes
Data Sheet 296 2000-09-14
signal c onnec ted to TCK. ‘1’ or ‘0’ on TMS caus es a trans itio n fro m one con troller state
to anot her; constant ’1’ on TMS leads t o normal operat ion of the ch ip.
Table 34 Boundary Scan Sequence of SEROCCO-D
Seq.
No. Pin I/O Numbe r of
Boundary Scan Cells Const ant Value
In, Out, Enable
TDI ->
1CTSB I1 0
2CTSA I1 0
3CDA I1 1
4RxDA I1 0
5RxCLKA I1 0
6TxDA 2 00
7TxCLKA 3 000
8RTSA O1 0
9 RESET I1 0
10 INT O2 01
11 A15 I/O 3 011
12 A14 I/O 3 110
13 A13 I/O 3 000
14 A12 I/O 3 010
15 A11 I/O 3 000
16 A10 I/O 3 001
17 A9 I/O 3 100
18 A8 I/O 3 000
19 A7 I/O 3 000
20 A6 I/O 3 000
21 A5 I/O 3 000
22 A4 I/O 3 000
23 A3 I/O 3 000
24 A2 I/O 3 000
25 A1 I/O 3 000
26 A0 I/O 3 000
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Data Sheet 297 2000-09-14
27 BM I 1 0
28 CS I1 0
29 BHE I/O 3 000
30 W/R I/O 3 000
31 A16 O 2 00
32 A17 O 2 00
33 A18 O 2 00
34 A19 O 2 00
35 A20 O 2 00
36 A21 O 2 00
37 A22 O 2 00
38 A23 O 2 00
39 RD I/O 3 000
40 WR I/O 3 000
41 READY I/O 3 000
42 CLK I 1 0
43 D0 I/O 2 00
44 D1 I/O 2 00
45 D2 I/O 2 00
46 D3 I/O 2 00
47 D4 I/O 2 00
48 D5 I/O 2 00
49 D6 I/O 2 00
50 D7 I/O 3 000
51 D8 I/O 2 00
52 D9 I/O 2 00
53 D10 I/O 2 00
54 D11 I/O 2 00
55 D12 I/O 2 00
56 D13 I/O 2 00
Table 34 Boundary Scan Sequence of SEROCCO-D
Seq.
No. Pin I/O Numbe r of
Boundary Scan Cells Const ant Value
In, Out, Enable
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Test Modes
Data Sheet 298 2000-09-14
An input pin (I) uses one boundary scan cell (data in), an output pin (O) us es two cells
(data ou t, e nable) a nd a n I/O- pin (I /O) us es th ree c ells (d ata in , dat a ou t, en able). Not e
that some functional output and input pins of SEROCCO-D are tested as I/O pins in
boundary scan, hence using three cells. The boundary scan unit of SEROCCO-D
conta ins a t ot al of n = 158 scan cells.
The ri ght colum n of Table 34 gives the initialization values of the cells.
The desired test mode is selected by serially loading a 3-bit instruction code into the
instruction register via TDI (LS B first); see Table 35.
57 D14 I/O 2 00
58 D15 I/O 3 000
59 BREQ I/O 3 000
60 BGNT I1 0
61 BGACK I/O 3 000
62 GP1 I/O 3 000
63 GP0 I/O 3 000
64 GP2 I/O 3 000
65 RTSB O1 0
66 RxDB I 1 0
67 RxCLKB I 1 0
68 TxDB O 2 00
69 TxCLKB I/O 3 000
70 CDB I 1 0
71 ADS O2 00
-> TDO
Table 34 Boundary Scan Sequence of SEROCCO-D
Seq.
No. Pin I/O Numbe r of
Boundary Scan Cells Const ant Value
In, Out, Enable
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Test Modes
Data Sheet 299 2000-09-14
EXTEST is used to examine the interconnection of the devices on the board. In this test
mode at first all input pins capture the current level on the corresponding external
interconnection line, whereas all output pins are held at constant values (‘0’ or ‘1’,
according to Table 34). Then the contents of the boundary scan is shifted to TDO. At
the same time the next scan vector is loaded from TDI. Subsequently all output pins are
updated according to t he new bo undary scan content s and all input pins again c apt ure
the cu rrent external level afte rw ards, and so on.
INTEST supports internal testing of the chip, i.e. the output pins capture the current level
on the corresponding internal line whereas all input pins are held on constant values (‘0’
or ‘1’, according to Table 34). The resulting boundary scan vector is shifted to TDO. The
next test vector is serially loaded via TDI. Then all input pins are updated for the
following test cycle.
Note: In capture IR-state the code ‘001’ is automatically loaded into the instruction
regist er, i.e. if INTEST is wa nt ed the shift IR-state does not need to be passed.
SAMPLE/PRELOAD is a test mode which provides a snap-shot of pin levels during
normal operation.
IDCODE: A 32-bit identification register is serially read out via TDO. It contains the
versio n number (4 bits), t he device code (16 bits) and the m anufacture r code (11 bits).
The LSB is fixed to ‘1’.
Note: Since in test logic reset state the code ‘011’ is automatically loaded into the
instruction register, the ID code can easily be read out in shift DR state which is
reached by TMS = 0, 1, 0, 0.
BYPASS: A bit entering TDI is shifted to TDO after one TCK clock cycle.
Table 35 Boundary Scan Test Modes
Instruction (Bit 2 … 0) Test Mode
000
001
010
011
111
others
EXTE ST (ex t ernal testing)
INTE ST (int ernal testi ng)
SAMPLE/PRELOAD (snap-shot testing)
IDCODE (reading ID code)
BYPA SS (bypass operation)
handled lik e BYPASS
TDI -> 0010 000 0 0000 0101 1110 0000 1000 001 1 -> TDO
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Package Outlines
Data Sheet 300 2000-09-14
9 Package Outlines
P-TQFP-144-10
(Plastic Th in Quad Flat Package)
GPP09243
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package In fo rm at ion” . Dim ensions in mm
