LTC2185/LTC2184/LTC2183 16-Bit, 125/105/80Msps Low Power Dual ADCs Features n n n n n n n n n n n n n Description The LTC(R)2185/LTC2184/LTC2183 are two-channel simultaneous sampling 16-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 76.8dB SNR and 90dB spurious free dynamic range (SFDR). Ultralow jitter of 0.07psRMS allows undersampling of IF frequencies with excellent noise performance. Two-Channel Simultaneously Sampling ADC 76.8dB SNR 90dB SFDR Low Power: 370mW/308mW/200mW Total 185mW/154mW/100mW per Channel Single 1.8V Supply CMOS, DDR CMOS, or DDR LVDS Outputs Selectable Input Ranges: 1VP-P to 2VP-P 550MHz Full Power Bandwidth S/H Optional Data Output Randomizer Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Serial SPI Port for Configuration 64-Pin (9mm x 9mm) QFN Package DC specs include 2LSB INL (typ), 0.5LSB DNL (typ) and no missing codes over temperature. The transition noise is 3.4LSBRMS. The digital outputs can be either full rate CMOS, Double Data Rate CMOS, or Double Data Rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V. Applications n n n n n n The ENC+ and ENC- inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. Communications Cellular Base Stations Software Defined Radios Portable Medical Imaging Multi-Channel Data Acquisition Nondestructive Testing L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application 1.8V VDD 2-Tone FFT, fIN = 70MHz and 69MHz 1.8V OVDD 0 -10 CH 2 ANALOG INPUT -20 D1_15 * * * D1_0 16-BIT ADC CORE S/H 16-BIT ADC CORE S/H OUTPUT DRIVERS D2_15 * * * D2_0 -30 CMOS, DDR CMOS OR DDR LVDS OUTPUTS AMPLITUDE (dBFS) CH 1 ANALOG INPUT -40 -50 -60 -70 -80 -90 -100 -110 -120 125MHz CLOCK CONTROL CLOCK 0 10 20 30 40 FREQUENCY (MHz) 50 60 218543 TA01b 218543 TA01a GND OGND 218543f 1 LTC2185/LTC2184/LTC2183 Absolute Maximum Ratings (Notes 1, 2) Supply Voltages (VDD, OVDD)........................ -0.3V to 2V Analog Input Voltage (AIN+, AIN-, PAR/SER, SENSE) (Note 3)........... -0.3V to (VDD + 0.2V) Digital Input Voltage (ENC+, ENC-, CS, SDI, SCK) (Note 4)..................................... -0.3V to 3.9V SDO (Note 4)............................................. -0.3V to 3.9V Digital Output Voltage................. -0.3V to (OVDD + 0.3V) Operating Temperature Range LTC2185C, 2184C, 2183C......................... 0C to 70C LTC2185I, 2184I, 2183I........................ -40C to 85C Storage Temperature Range.................... -65C to 150C Pin ConfigurationS FULL-RATE CMOS OUTPUT MODE DOUBLE DATA RATE CMOS OUTPUT MODE TOP VIEW 64 VDD 63 SENSE 62 VREF 61 SDO 60 OF1 59 OF2 58 D1_15 57 D1_14 56 D1_13 55 D1_12 54 D1_11 53 D1_10 52 D1_9 51 D1_8 50 D1_7 49 D1_6 64 VDD 63 SENSE 62 VREF 61 SDO 60 OF2_1 59 DNC 58 D1_14_15 57 DNC 56 D1_12_13 55 DNC 54 D1_10_11 53 DNC 52 D1_8_9 51 DNC 50 D1_6_7 49 DNC TOP VIEW VDD 1 VCM1 2 GND 3 AIN1+ 4 AIN1- 5 GND 6 REFH 7 REFL 8 REFH 9 REFL 10 PAR/SER 11 AIN2+ 12 AIN2- 13 GND 14 VCM2 15 VDD 16 65 GND 48 D1_4_5 47 DNC 46 D1_2_3 45 DNC 44 D1_0_1 43 DNC 42 OVDD 41 OGND 40 CLKOUT+ 39 CLKOUT- 38 D2_14_15 37 DNC 36 D2_12_13 35 DNC 34 D2_10_11 33 DNC VDD 17 ENC+ 18 ENC- 19 CS 20 SCK 21 SDI 22 DNC 23 D2_0_1 24 DNC 25 D2_2_3 26 DNC 27 D2_4_5 28 DNC 29 D2_6_7 30 DNC 31 D2_8_9 32 65 GND 48 D1_5 47 D1_4 46 D1_3 45 D1_2 44 D1_1 43 D1_0 42 OVDD 41 OGND 40 CLKOUT+ 39 CLKOUT- 38 D2_15 37 D2_14 36 D2_13 35 D2_12 34 D2_11 33 D2_10 VDD 17 ENC+ 18 ENC- 19 CS 20 SCK 21 SDI 22 D2_0 23 D2_1 24 D2_2 25 D2_3 26 D2_4 27 D2_5 28 D2_6 29 D2_7 30 D2_8 31 D2_9 32 VDD 1 VCM1 2 GND 3 AIN1+ 4 AIN1- 5 GND 6 REFH 7 REFL 8 REFH 9 REFL 10 PAR/SER 11 AIN2+ 12 AIN2- 13 GND 14 VCM2 15 VDD 16 UP PACKAGE 64-LEAD (9mm x 9mm) PLASTIC QFN TJMAX = 150C, JA = 20C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB UP PACKAGE 64-LEAD (9mm x 9mm) PLASTIC QFN TJMAX = 150C, JA = 20C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB 218543f 2 LTC2185/LTC2184/LTC2183 Pin ConfigurationS DOUBLE DATA RATE LVDS OUTPUT MODE 64 VDD 63 SENSE 62 VREF 61 SDO 60 OF2_1+ 59 OF2_1- 58 D1_14_15+ 57 D1_14_15- 56 D1_12_13+ 55 D1_12_13- 54 D1_10_11+ 53 D1_10_11- 52 D1_8_9+ 51 D1_8_9- 50 D1_6_7+ 49 D1_6_7- TOP VIEW VDD 1 VCM1 2 GND 3 AIN1+ 4 AIN1- 5 GND 6 REFH 7 REFL 8 REFH 9 REFL 10 PAR/SER 11 AIN2+ 12 AIN2- 13 GND 14 VCM2 15 VDD 16 48 D1_4_5+ 47 D1_4_5- 46 D1_2_3+ 45 D1_2_3- 44 D1_0_1+ 43 D1_0_1- 42 OVDD 41 OGND 40 CLKOUT+ 39 CLKOUT- 38 D2_14_15+ 37 D2_14_15- 36 D2_12_13+ 35 D2_12_13- 34 D2_10_11+ 33 D2_10_11- VDD 17 ENC+ 18 ENC- 19 CS 20 SCK 21 SDI 22 D2_0_1- 23 D2_0_1+ 24 D2_2_3- 25 D2_2_3+ 26 D2_4_5- 27 D2_4_5+ 28 D2_6_7- 29 D2_6_7+ 30 D2_8_9- 31 D2_8_9+ 32 65 GND UP PACKAGE 64-LEAD (9mm x 9mm) PLASTIC QFN TJMAX = 150C, JA = 20C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2185CUP#PBF LTC2185CUP#TRPBF LTC2185UP 64-Lead (9mm x 9mm) Plastic QFN 0C to 70C LTC2185IUP#PBF LTC2185IUP#TRPBF LTC2185UP 64-Lead (9mm x 9mm) Plastic QFN -40C to 85C LTC2184CUP#PBF LTC2184CUP#TRPBF LTC2184UP 64-Lead (9mm x 9mm) Plastic QFN 0C to 70C LTC2184IUP#PBF LTC2184IUP#TRPBF LTC2184UP 64-Lead (9mm x 9mm) Plastic QFN -40C to 85C LTC2183CUP#PBF LTC2183CUP#TRPBF LTC2183UP 64-Lead (9mm x 9mm) Plastic QFN 0C to 70C LTC2183IUP#PBF LTC2183IUP#TRPBF LTC2183UP 64-Lead (9mm x 9mm) Plastic QFN -40C to 85C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 218543f 3 LTC2185/LTC2184/LTC2183 Converter Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) LTC2185 PARAMETER CONDITIONS Resolution (No Missing Codes) MIN l LTC2184 TYP MAX MIN 2 7.5 -7.5 16 LTC2183 TYP MAX MIN 2 7.5 -7.5 16 TYP MAX UNITS 2 7.5 LSB 16 Bits Integral Linearity Error Differential Analog Input (Note 6) l -7.5 Differential Linearity Error Differential Analog Input l -0.9 0.5 0.9 -0.9 0.5 0.9 -0.9 0.5 0.9 LSB Offset Error (Note 7) l -7 1.5 7 -7 1.5 7 -7 1.5 7 mV Gain Error Internal Reference External Reference l -2.3 1.5 -0.9 0.3 -2.1 1.5 -0.8 0.4 -1.8 1.5 -0.5 0.8 %FS %FS Offset Drift 10 10 10 V/C 30 10 30 10 30 10 ppm/C ppm/C Gain Matching 0.3 0.3 0.3 %FS Offset Matching 1.5 1.5 1.5 mV Transition Noise 3.4 3.5 3.2 LSBRMS Full-Scale Drift Internal Reference External Reference Analog Input The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Analog Input Range (AIN+ - AIN-) 1.7V < VDD < 1.9V l Differential Analog Input (Note 8) l 0.7 VCM 1.25 V l 0.625 1.250 1.300 V 1 to 2 VP-P VIN(CM) Analog Input Common Mode (AIN+ + AIN-)/2 VSENSE External Voltage Reference Applied to SENSE External Reference Mode IINCM Analog Input Common Mode Current Per Pin, 125Msps Per Pin, 105Msps Per Pin, 80Msps IIN1 Analog Input Leakage Current (No Encode) 0 < AIN+, AIN- < VDD l -1.5 1.5 A IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l -3 3 A IIN3 SENSE Input Leakage Current 0.625 < SENSE < 1.3V l -3 3 A tAP Sample-and-Hold Acquisition Delay Time tJITTER Sample-and-Hold Acquisition Delay Jitter CMRR Analog Input Common Mode Rejection Ratio BW-3B Full-Power Bandwidth 200 170 130 0 Single-Ended Encode Differential Encode Figure 6 Test Circuit 0.07 0.09 A A A ns psRMS psRMS 80 dB 550 MHz 218543f 4 LTC2185/LTC2184/LTC2183 Dynamic Accuracy The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 5) LTC2185 SYMBOL PARAMETER CONDITIONS SNR Signal-to-Noise Ratio 5MHz Input 70MHz Input 140MHz Input SFDR S/(N+D) MIN TYP l 74.8 Spurious Free Dynamic Range 5MHz Input 2nd Harmonic 70MHz Input 140MHz Input l Spurious Free Dynamic Range 5MHz Input 3rd Harmonic 70MHz Input 140MHz Input Spurious Free Dynamic Range 5MHz Input 4th Harmonic or Higher 70MHz Input 140MHz Input Signal-to-Noise Plus Distortion Ratio 5MHz Input 70MHz Input 140MHz Input Crosstalk 10MHz Input LTC2184 MAX MIN TYP 76.8 76.6 76.1 74.8 79 90 89 84 l 82 l l LTC2183 MIN TYP 76.7 76.5 76 75.1 77.1 76.9 76.4 dBFS dBFS dBFS 81 90 89 84 81 90 89 84 dBFS dBFS dBFS 90 89 84 81 90 89 84 82 90 89 84 dBFS dBFS dBFS 89 95 95 95 89 95 95 95 89 95 95 95 dBFS dBFS dBFS 73.3 76.6 76.2 75.1 73.9 76.5 76.1 75 74.4 76.9 76.5 75.3 dBFS dBFS dBFS -110 dBc -110 MAX -110 MAX UNITS Internal Reference Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) PARAMETER CONDITIONS VCM Output Voltage IOUT = 0 MIN TYP MAX 0.5 * VDD - 25mV 0.5 * VDD 0.5 * VDD + 25mV VCM Output Temperature Drift 25 VCM Output Resistance -600A < IOUT < 1mA VREF Output Voltage IOUT = 0 VREF Output Temperature Drift 1.250 25 VREF Output Resistance -400A < IOUT < 1mA VREF Line Regulation 1.7V < VDD < 1.9V 7 0.6 V ppm/C 4 1.225 UNITS 1.275 V ppm/C mV/V 218543f 5 LTC2185/LTC2184/LTC2183 Digital Inputs and Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ENCODE INPUTS (ENC+, ENC-) Differential Encode Mode (ENC- Not Tied to GND) VID Differential Input Voltage (Note 8) l 0.2 VICM Common Mode Input Voltage Internally Set Externally Set (Note 8) l 1.1 l 0.2 V 1.2 1.6 V V 3.6 V VIN Input Voltage Range ENC+, ENC- to GND RIN Input Resistance (See Figure 10) 10 k CIN Input Capacitance (Note 8) 3.5 pF Single-Ended Encode Mode (ENC- Tied to GND) VIH High Level Input Voltage VDD = 1.8V l VIL Low Level Input Voltage VDD = 1.8V l 1.2 V VIN Input Voltage Range ENC+ to GND l RIN Input Resistance (See Figure 11) 30 k CIN Input Capacitance (Note 8) 3.5 pF 0.6 0 3.6 V V DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode) VIH High Level Input Voltage VDD = 1.8V l VIL Low Level Input Voltage VDD = 1.8V l IIN Input Current VIN = 0V to 3.6V l CIN Input Capacitance (Note 8) 1.3 V -10 0.6 V 10 A 3 pF 200 SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used) ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V IOH Logic High Output Leakage Current SDO = 0V to 3.6V COUT Output Capacitance (Note 8) l -10 10 A 3 pF 1.790 V DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE) OVDD = 1.8V VOH High Level Output Voltage IO = -500A l VOL Low Level Output Voltage IO = 500A l 1.750 0.010 0.050 V OVDD = 1.5V VOH High Level Output Voltage IO = -500A 1.488 V VOL Low Level Output Voltage IO = 500A 0.010 V OVDD = 1.2V VOH High Level Output Voltage IO = -500A 1.185 V VOL Low Level Output Voltage IO = 500A 0.010 V DIGITAL DATA OUTPUTS (LVDS MODE) VOD Differential Output Voltage 100 Differential Load, 3.5mA Mode 100 Differential Load, 1.75mA Mode l 247 350 175 454 VOS Common Mode Output Voltage 100 Differential Load, 3.5mA Mode 100 Differential Load, 1.75mA Mode l 1.125 1.250 1.250 1.375 RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 mV mV V V 218543f 6 LTC2185/LTC2184/LTC2183 Power Requirements The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 9) LTC2185 SYMBOL PARAMETER CONDITIONS LTC2184 LTC2183 MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS CMOS Output Modes: Full Data Rate and Double Data Rate VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.1 1.8 1.9 1.1 1.8 1.9 1.1 1.8 1.9 V IVDD Analog Supply Current DC Input Sine Wave Input l 206 209 228 171 173 188 111 113 124 mA mA IOVDD Digital Supply Current Sine Wave Input, OVDD = 1.2V 10 PDISS Power Dissipation l DC Input Sine Wave Input, OVDD = 1.2V 370 388 410 8 6 308 321 339 mA 200 211 223 mW mW LVDS Output Mode VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode l 211 213 233 175 177 193 115 117 128 mA mA Digital Supply Current (0VDD = 1.8V) Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode l 40 76 86 40 75 85 39 75 84 mA mA Power Dissipation Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode l 452 520 574 387 454 500 277 346 382 mW mW IOVDD PDISS All Output Modes PSLEEP Sleep Mode Power 1 1 1 mW PNAP Nap Mode Power 16 16 16 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled (No increase for Nap or Sleep Modes) 20 20 20 mW Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) LTC2185 SYMBOL PARAMETER CONDITIONS MIN fS Sampling Frequency (Note 10) l 1 tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 3.8 2 tH ENC High Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 3.8 2 tAP Sample-and-Hold Acquisition Delay Time SYMBOL PARAMETER TYP LTC2184 MAX MIN 125 1 4 4 500 500 4.52 2 4 4 500 500 4.52 2 0 TYP LTC2183 MAX MIN 105 1 4.76 4.76 500 500 5.93 2 4.76 4.76 500 500 5.93 2 0 CONDITIONS TYP MAX UNITS 80 MHz 6.25 6.25 500 500 ns ns 6.25 6.25 500 500 ns ns 0 ns MIN TYP MAX UNITS Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate) tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD - tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency Full Data Rate Mode Double Data Rate Mode 6 6.5 Cycles Cycles 218543f 7 LTC2185/LTC2184/LTC2183 timing characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (LVDS Mode) tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.8 3.2 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.5 2.7 ns tSKEW DATA to CLKOUT Skew tD - tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency 6.5 Cycles SPI Port Timing (Note 8) tSCK SCK Period tS Write Mode Readback Mode, CSDO = 20pF, RPULLUP = 2k l l 40 250 ns ns CS to SCK Setup Time l 5 ns tH SCK to CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP = 2k Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup. Note 5: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTC2185), 105MHz (LTC2184), or 80MHz (LTC2183), LVDS outputs, differential ENC+/ENC- = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. l ns 125 ns Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Offset error is the offset voltage measured from -0.5 LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2's complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: VDD = 1.8V, fSAMPLE = 125MHz (LTC2185), 105MHz (LTC2184), or 80MHz (LTC2183), CMOS outputs, ENC+ = single-ended 1.8V square wave, ENC- = 0V, input range = 2VP-P with differential drive, 5pF load on each digital output unless otherwise noted. The supply current and power dissipation specifications are totals for the entire IC, not per channel. Note 10: Recommended operating conditions. 218543f 8 LTC2185/LTC2184/LTC2183 Timing Diagrams Full-Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels tAP CH 1 ANALOG INPUT A+4 A+2 A A+3 tAP CH 2 ANALOG INPUT A+1 B+4 B+2 B B+3 tH tL B+1 ENC- ENC+ tD D1_0 - D1_15, OF1 A-6 A-5 A-4 A-3 A-2 D2_0 - D2_15, OF2 B-6 B-5 B-4 B-3 B-2 tC CLKOUT + CLKOUT - 218543 TD01 Double Data Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels tAP CH 1 ANALOG INPUT A+3 tAP CH 2 ANALOG INPUT A+4 A+2 A A+1 B+4 B+2 B B+3 tH tL B+1 ENC- ENC+ tD tD BIT 0 A-6 BIT 1 A-6 BIT 0 A-5 BIT 1 A-5 BIT 0 A-4 BIT 1 A-4 BIT 0 A-3 BIT 1 A-3 BIT 0 A-2 D1_14_15 BIT 14 A-6 BIT 15 A-6 BIT 14 A-5 BIT 15 A-5 BIT 14 A-4 BIT 15 A-4 BIT 14 A-3 BIT 15 A-3 BIT 14 A-2 D2_0_1 BIT 0 B-6 BIT 1 B-6 BIT 0 B-5 BIT 1 B-5 BIT 0 B-4 BIT 1 B-4 BIT 0 B-3 BIT 1 B-3 BIT 0 B-2 BIT 14 B-6 BIT 15 B-6 BIT 14 B-5 BIT 15 B-5 BIT 14 B-4 BIT 15 B-4 BIT 14 B-3 BIT 15 B-3 BIT 14 B-2 OF B-6 OF A-6 OF B-5 OF A-5 OF B-4 OF A-4 OF B-3 OF A-3 OF B-2 D1_0_1 ** * ** * D2_14_15 OF2_1 CLKOUT+ CLKOUT - tC tC 218543 TD02 218543f 9 LTC2185/LTC2184/LTC2183 timing DIAGRAMS Double Data Rate LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels tAP CH 1 ANALOG INPUT A+4 A+2 A A+3 tAP CH 2 ANALOG INPUT A+1 B+4 B+2 B B+3 tH B+1 tL ENC- ENC+ tD D1_0_1+ D1_0_1- ** * D1_14_15+ D1_14_15- D2_0_1+ D2_0_1- ** * D2_14_15+ D2_14_15- OF2_1+ OF2_1- tD BIT 0 A-6 BIT 1 A-6 BIT 0 A-5 BIT 1 A-5 BIT 0 A-4 BIT 1 A-4 BIT 0 A-3 BIT 1 A-3 BIT 0 A-2 BIT 14 A-6 BIT 15 A-6 BIT 14 A-5 BIT 15 A-5 BIT 14 A-4 BIT 15 A-4 BIT 14 A-3 BIT 15 A-3 BIT 14 A-2 BIT 0 B-6 BIT 1 B-6 BIT 0 B-5 BIT 1 B-5 BIT 0 B-4 BIT 1 B-4 BIT 0 B-3 BIT 1 B-3 BIT 0 B-2 BIT 14 B-6 BIT 15 B-6 BIT 14 B-5 BIT 15 B-5 BIT 14 B-4 BIT 15 B-4 BIT 14 B-3 BIT 15 B-3 BIT 14 B-2 OF B-6 OF A-6 OF B-5 OF A-5 OF B-4 OF A-4 OF B-3 OF A-3 OF B-2 tC tC CLKOUT+ CLKOUT - 218543 TD03 SPI Port Timing (Readback Mode) tDS tS tDH tSCK tH CS SCK tDO SDI SDO R/W A6 A5 A4 A3 A2 A1 A0 XX D7 HIGH IMPEDANCE XX D6 XX D5 XX D4 XX D3 XX D2 XX XX D1 D0 SPI Port Timing (Write Mode) CS SCK SDI SDO R/W HIGH IMPEDANCE A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 218543 TD04 218543f 10 LTC2185/LTC2184/LTC2183 Typical Performance Characteristics LTC2185: Integral Non-Linearity (INL) LTC2185: Differential Non-Linearity (DNL) 4.0 3.0 1.0 0 0.8 -10 -20 0.6 1.0 0 -1.0 -2.0 -30 0.4 AMPLITUDE (dBFS) DNL ERROR (LSB) 2.0 INL ERROR (LSB) LTC2185: 64k Point FFT, fIN = 5MHz, -1dBFS, 125Msps 0.2 0 -0.2 -0.4 -0.8 -4.0 -1.0 0 16384 32768 49152 OUTPUT CODE 65536 0 16384 32768 49152 OUTPUT CODE 218543 G01 -70 -80 65536 -110 -120 0 -10 -20 -20 -20 -30 -30 -30 -70 -80 AMPLITUDE (dBFS) 0 -10 AMPLITUDE (dBFS) 0 -60 -40 -50 -60 -70 -80 -60 -70 -80 -90 -100 -110 -120 -110 -120 -110 -120 20 30 40 FREQUENCY (MHz) 50 60 0 10 20 30 40 FREQUENCY (MHz) 218543 G04 LTC2185: 64k Point 2-Tone FFT, fIN = 69MHz, 70MHz, -7dBFS, 125Msps 60 77 8000 5000 4000 3000 -90 -100 -110 -120 6000 SNR (dBFS) COUNT -80 20 30 40 FREQUENCY (MHz) 50 60 218543 G07 0 32750 74 DIFFERENTIAL ENCODE 73 71 1000 10 75 72 2000 0 60 SINGLE-ENDED ENCODE 76 7000 -70 50 LTC2185: SNR vs Input Frequency, -1dBFS, 125Msps, 2V Range 78 -60 20 30 40 FREQUENCY (MHz) LTC2185: Shorted Input Histogram 9000 -40 10 218543 G06 10000 -30 0 218543 G05 0 -20 AMPLITUDE (dBFS) 50 -10 -50 60 -40 -90 -100 10 50 -50 -90 -100 0 20 30 40 FREQUENCY (MHz) LTC2185: 64k Point FFT, fIN = 140MHz, -1dBFS, 125Msps -10 -50 10 218543 G03 LTC2185: 64k Point FFT, fIN = 70MHz, -1dBFS, 125Msps -40 0 218543 G02 LTC2185: 64k Point FFT, fIN = 30MHz, -1dBFS, 125Msps AMPLITUDE (dBFS) -60 -90 -100 -0.6 -3.0 -40 -50 32756 32762 32768 OUTPUT CODE 32774 218543 G08 70 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300 218543 G09 218543f 11 LTC2185/LTC2184/LTC2183 Typical Performance Characteristics LTC2185: 2nd, 3rd Harmonic vs Input Frequency, -1dBFS, 125Msps, 1V Range 100 95 95 90 3RD 85 80 2ND 75 70 65 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 130 120 85 2ND 80 75 60 50 40 30 0 80 50 100 150 200 250 INPUT FREQUENCY (MHz) 20 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 300 3.5mA LVDS OUTPUTS IOVDD (mA) 200 LTC2185: SNR vs SENSE, fIN = 5MHz, -1dBFS 78 3.5mA LVDS 70 77 60 76 50 1.75mA LVDS 40 30 160 1.8V CMOS 10 0 25 50 75 100 SAMPLE RATE (Msps) 0 125 74 73 71 1.2V CMOS 0 25 50 75 100 SAMPLE RATE (Msps) 218543 G13 70 125 1.0 0 3.0 0.8 -10 -4.0 0.2 0 -0.2 -0.4 -0.8 0 16384 32768 49152 OUTPUT CODE 65536 218543 G16 -1.0 1.3 -40 -50 -60 -70 -80 -90 -100 -0.6 -3.0 1.2 -30 0.4 AMPLITUDE (dBFS) DNL ERROR (LSB) -2.0 0.9 1 1.1 SENSE PIN (V) -20 0.6 2.0 -1.0 0.8 LTC2184: 64k Point FFT, fIN = 5MHz, -1dBFS, 105Msps 4.0 0 0.7 218543 G15 LTC2184: Differential Non-Linearity (DNL) 1.0 0.6 218543 G14 LTC2184: Integral Non-Linearity (INL) INL ERROR (LSB) 75 72 20 170 0 218543 G12 SNR (dBFS) 210 CMOS OUTPUTS dBc 70 LTC2185: IOVDD vs Sample Rate, 5MHz, -1dBFS Sine Wave Input on Each Channel 220 IVDD (mA) 90 80 218543 G11 LTC2185: IVDD vs Sample Rate, 5MHz, -1dBFS Sine Wave Input on Each Channel 180 100 70 218543 G10 190 dBFS 110 3RD 90 65 300 LTC2185: SFDR vs Input Level, fIN = 70MHz, 125Msps, 2V Range SFDR (dBc AND dBFS) 100 2ND AND 3RD HARMONIC (dBFS) 2ND AND 3RD HARMONIC (dBFS) LTC2185: 2nd, 3rd Harmonic vs Input Frequency, -1dBFS, 125Msps, 2V Range 0 16384 32768 49152 OUTPUT CODE 65536 218543 G17 -110 -120 0 10 20 30 40 FREQUENCY (MHz) 50 218543 G18 218543f 12 LTC2185/LTC2184/LTC2183 Typical Performance Characteristics 0 0 -10 -20 -20 -20 -30 -30 -30 -40 -50 -60 -70 -80 AMPLITUDE (dBFS) -10 -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -100 -90 -100 -90 -100 -110 -120 -110 -120 -110 -120 0 10 20 30 40 FREQUENCY (MHz) 50 0 10 20 30 40 FREQUENCY (MHz) 218543 G19 LTC2184: 64k Point 2-Tone FFT, fIN = 69MHz, 70MHz, -7dBFS, 105Msps 77 8000 5000 4000 3000 -90 -100 10 20 30 40 FREQUENCY (MHz) 0 32790 50 32796 32802 32808 OUTPUT CODE 100 95 95 2ND AND 3RD HARMONIC (dBFS) 100 80 2ND 75 70 65 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300 218543 G25 50 100 150 200 250 INPUT FREQUENCY (MHz) LTC2184: SFDR vs Input Level, fIN = 70MHz, 105Msps, 2V Range 130 120 110 3RD 90 85 2ND 80 75 dBFS 100 90 80 70 dBc 60 50 40 70 65 300 218543 G24 LTC2184: 2nd, 3rd Harmonic vs Input Frequency, -1dBFS, 105Msps, 1V Range 3RD 0 218543 G23 LTC2184: 2nd, 3rd Harmonic vs Input Frequency, -1dBFS, 105Msps, 2V Range 90 DIFFERENTIAL ENCODE 73 70 32814 218543 G22 85 74 71 1000 0 75 72 2000 SFDR (dBc AND dBFS) -110 -120 6000 SNR (dBFS) COUNT -80 SINGLE-ENDED ENCODE 76 7000 -70 50 LTC2184: SNR vs Input Frequency, -1dBFS, 105Msps, 2V Range 9000 -60 20 30 40 FREQUENCY (MHz) LTC2184: Shorted Input Histogram 78 -50 10 218543 G21 10000 -40 0 218543 G20 0 -30 AMPLITUDE (dBFS) 50 -10 -20 2ND AND 3RD HARMONIC (dBFS) LTC2184: 64k Point FFT, fIN = 140MHz, -1dBFS, 105Msps LTC2184: 64k Point FFT, fIN = 70MHz, -1dBFS, 105Msps -10 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 0 LTC2184: 64k Point FFT, fIN = 30MHz, -1dBFS, 105Msps 30 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 300 218543 G26 20 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 0 218543 G27 218543f 13 LTC2185/LTC2184/LTC2183 Typical Performance Characteristics LTC2184: IVDD vs Sample Rate, 5MHz, -1dBFS Sine Wave Input on Each Channel LTC2184: IOVDD vs Sample Rate, 5MHz, -1dBFS Sine Wave Input on Each Channel 180 80 3.5mA LVDS OUTPUTS CMOS OUTPUTS 150 70 77 60 76 50 1.75mA LVDS 40 30 1.8V CMOS 10 0 25 50 75 SAMPLE RATE (Msps) 0 100 73 0 25 50 75 SAMPLE RATE (Msps) 70 100 1.0 0 3.0 0.8 -10 -4.0 0.2 0 -0.2 -0.4 -0.8 0 16384 32768 49152 OUTPUT CODE 65536 -1.0 0 16384 32768 49152 OUTPUT CODE -40 -50 -60 -70 -80 65536 -110 -120 0 -10 -20 -20 -20 -30 -30 -30 -70 -80 AMPLITUDE (dBFS) 0 -10 AMPLITUDE (dBFS) 0 -60 -40 -50 -60 -70 -80 -50 -60 -70 -80 -90 -100 -90 -100 -110 -120 -110 -120 -110 -120 10 20 30 FREQUENCY (MHz) 40 218543 G34 0 10 20 30 FREQUENCY (MHz) 40 -40 -90 -100 0 20 30 FREQUENCY (MHz) LTC2183: 64k Point FFT, fIN = 140MHz, -1dBFS, 80Msps -10 -50 10 218543 G33 LTC2183: 64k Point FFT, fIN = 70MHz, -1dBFS, 80Msps -40 0 218543 G32 218543 G31 LTC2183: 64k Point FFT, fIN = 30MHz, -1dBFS, 80Msps 1.3 -90 -100 -0.6 -3.0 1.2 -30 0.4 AMPLITUDE (dBFS) DNL ERROR (LSB) -2.0 0.9 1 1.1 SENSE PIN (V) -20 0.6 2.0 -1.0 0.8 LTC2183: 64k Point FFT, fIN = 5MHz, -1dBFS, 80Msps 4.0 0 0.7 218543 G30 LTC2183: Differential Non-Linearity (DNL) 1.0 0.6 218543 G29 LTC2183: Integral Non-Linearity (INL) INL ERROR (LSB) 74 71 1.2V CMOS 218543 G28 AMPLITUDE (dBFS) 75 72 20 140 130 78 3.5mA LVDS SNR (dBFS) 160 IOVDD (mA) IVDD (mA) 170 LTC2184: SNR vs SENSE, fIN = 5MHz, -1dBFS 40 218543 G35 0 10 20 30 FREQUENCY (MHz) 40 218543 G36 218543f 14 LTC2185/LTC2184/LTC2183 Typical Performance Characteristics LTC2183: 64k Point 2-Tone FFT, fIN = 69MHz, 70MHz, -7dBFS, 80Msps LTC2183: Shorted Input Histogram 0 10000 78 -10 9000 -20 77 8000 -30 -60 -70 6000 5000 4000 -80 3000 -90 -100 2000 10 20 30 FREQUENCY (MHz) 0 32817 40 32823 32829 32835 OUTPUT CODE 100 100 95 95 85 80 2ND 75 70 65 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 2ND 80 75 IOVDD (mA) IVDD (mA) 3.5mA LVDS OUTPUTS 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 90 80 60 50 LTC2183: SNR vs SENSE, fIN = 5MHz, -1dBFS 78 70 77 60 76 50 1.75mA LVDS 40 30 218543 G43 0 0 218543 G27 3.5mA LVDS 75 74 73 72 1.8V CMOS 10 80 dBc 70 20 -80 -70 -60 -50 -40 -30 -20 -10 INPUT LEVEL (dBFS) 300 20 90 20 40 60 SAMPLE RATE (Msps) 100 30 SNR (dBFS) 120 dBFS 40 70 80 0 LTC2183: SFDR vs Input Level, fIN = 70MHz, 80Msps, 2V Range 218543 G41 130 300 218543 G39 LTC2183: IOVDD vs Sample Rate, 5MHz, -1dBFS Sine Wave Input on Each Channel CMOS OUTPUTS 100 150 200 250 INPUT FREQUENCY (MHz) 110 3RD 85 LTC2183: IVDD vs Sample Rate, 5MHz, -1dBFS Sine Wave Input on Each Channel 100 50 120 90 65 300 110 0 130 218543 G40 80 70 32841 LTC2183: 2nd, 3rd Harmonic vs Input Frequency, -1dBFS, 80Msps, 1V Range 2ND AND 3RD HARMONIC (dBFS) 2ND AND 3RD HARMONIC (dBFS) LTC2183: 2nd, 3rd Harmonic vs Input Frequency, -1dBFS, 80Msps, 2V Range 3RD 73 218543 G38 218543 G37 90 DIFFERENTIAL ENCODE 74 71 1000 0 75 72 SFDR (dBc AND dBFS) -110 -120 SNR (dBFS) -50 SINGLE-ENDED ENCODE 76 7000 -40 COUNT AMPLITUDE (dBFS) LTC2183: SNR vs Input Frequency, -1dBFS, 80Msps, 2V Range 71 1.2V CMOS 0 20 40 60 SAMPLE RATE (Msps) 80 218543 G44 70 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 218543 G45 218543f 15 LTC2185/LTC2184/LTC2183 Pin Functions Pins that are the same for all Digital Output Modes VDD (Pins 1, 16, 17, 64): Analog Power Supply, 1.7V to 1.9V. Bypass to ground with 0.1F ceramic capacitors. Adjacent pins can share a bypass capacitor. VCM1 (Pin 2): Common Mode Bias Output, nominally equal to VDD/2. VCM1 should be used to bias the common mode of the analog inputs to channel 1. Bypass to ground with a 0.1F ceramic capacitor. GND (Pins 3, 6, 14): ADC Power Ground. AIN1+ (Pin 4): Channel 1 Positive Differential Analog Input. AIN1- (Pin 5): Channel 1 Negative Differential Analog Input. REFH (Pins 7, 9): ADC High Reference. See the Applications Information section for recommended bypassing circuits for REFH and REFL. REFL (Pins 8, 10): ADC Low Reference. See the Applications Information section for recommended bypassing circuits for REFH and REFL. PAR/SER (Pin 11): Programming Mode selection pin. Connect to ground to enable the Serial Programming Mode. CS, SCK, SDI, SDO become a serial interface that control the A/D operating modes. Connect to VDD to enable the Parallel Programming Mode where CS, SCK, SDI, SDO become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or VDD and not be driven by a logic signal. AIN2+ (Pin 12): Channel 2 Positive Differential Analog Input. AIN2- (Pin 13): Channel 2 Negative Differential Analog Input. VCM2 (Pin 15): Common Mode Bias Output, nominally equal to VDD/2. VCM2 should be used to bias the common mode of the analog inputs to channel 2. Bypass to ground with a 0.1F ceramic capacitor. ENC+ (Pin 18): Encode Input. Conversion starts on the rising edge. ENC- (Pin 19): Encode Complement Input. Conversion starts on the falling edge. Tie to GND for single-ended encode mode. CS (Pin 20): In Serial Programming Mode, (PAR/SER = 0V), CS is the Serial Interface Chip Select Input. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In the Parallel Programming Mode (PAR/SER = VDD), CS controls the Clock Duty Cycle Stabilizer (See Table 2). CS can be driven with 1.8V to 3.3V logic. SCK (Pin 21): In Serial Programming Mode, (PAR/SER = 0V), SCK is the Serial Interface Clock Input. In the Parallel Programming Mode (PAR/SER = VDD), SCK controls the Digital Output Mode (See Table 2). SCK can be driven with 1.8V to 3.3V logic. SDI (Pin 22): In Serial Programming Mode, (PAR/SER = 0V), SDI is the Serial Interface Data Input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In the Parallel Programming Mode (PAR/SER = VDD), SDI can be used together with SDO to power down the part (see Table 2). SDI can be driven with 1.8V to 3.3V logic. OGND (Pin 41): Output Driver Ground. Must be shorted to the ground plane by a very low inductance path. Use multiple vias close to the pin. OVDD (Pin 42): Output Driver Supply. Bypass to ground with a 0.1F ceramic capacitor. SDO (Pin 61): In Serial Programming Mode, (PAR/SER = 0V), SDO is the optional Serial Interface Data Output. Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO is an open-drain NMOS output that requires an external 2k pull-up resistor to 1.8V - 3.3V. If read back from the mode control registers is not needed, the pull-up resistor is not necessary and SDO can be left unconnected. In the Parallel Programming Mode (PAR/SER = VDD), SDO can be used together with SDI to power down the part (see Table 2). When used as an input, SDO can be driven with 1.8V to 3.3V logic through a 1k series resistor. VREF (Pin 62): Reference Voltage Output. Bypass to ground with a 2.2F ceramic capacitor. The output voltage is nominally 1.25V. 218543f 16 LTC2185/LTC2184/LTC2183 Pin Functions SENSE (Pin 63): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a 1V input range. Connecting SENSE to ground selects the internal reference and a 0.5V input range. An external reference between 0.625V and 1.3V applied to SENSE selects an input range of 0.8 * VSENSE. Ground (Exposed Pad Pin 65): The exposed pad must be soldered to the PCB ground. FULL-RATE CMOS OUTPUT MODE All Pins Below Have CMOS Output Levels (OGND to OVDD) D2_0 to D2_15 (Pins 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38): Channel 2 Digital Outputs. D2_15 is the MSB. CLKOUT- (Pin 39): Inverted version of CLKOUT+. CLKOUT+ (Pin 40): Data Output Clock. The Digital Outputs normally transition at the same time as the falling edge of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the Digital Outputs by programming the mode control registers. D1_0 to D1_15 (Pins 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58): Channel 1 Digital Outputs. D1_15 is the MSB. OF2 (Pin 59): Channel 2 Over/Under Flow Digital Output. OF2 is high when an overflow or underflow has occurred. OF1 (Pin 60): Channel 1 Over/Under Flow Digital Output. OF1 is high when an overflow or underflow has occurred. DOUBLE DATA RATE CMOS OUTPUT MODE All Pins Below Have CMOS Output Levels (OGND to OVDD) D2_0_1 to D2_14_15 (Pins 24, 26, 28, 30, 32, 34, 36, 38): Channel 2 Double Data Rate Digital Outputs. Two data bits are multiplexed onto each output pin. The even data bits (D0, D2, D4, D6, D8, D10, D12, D14) appear when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13, D15) appear when CLKOUT+ is high. DNC (Pins 23, 25, 27, 29, 31, 33, 35, 37, 43, 45, 47, 49, 51, 53, 55, 57, 59): Do not connect these pins. CLKOUT- (Pin 39): Inverted version of CLKOUT+. CLKOUT+ (Pin 40): Data Output Clock. The Digital Outputs normally transition at the same time as the falling and rising edges of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the Digital Outputs by programming the mode control registers. D1_0_1 to D1_14_15 (Pins 44, 46, 48, 50, 52, 54, 56, 58): Channel 1 Double Data Rate Digital Outputs. Two data bits are multiplexed onto each output pin. The even data bits (D0, D2, D4, D6, D8, D10, D12, D14) appear when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13, D15) appear when CLKOUT+ is high. OF2_1 (Pin 60): Over/Under Flow Digital Output. OF2_1 is high when an overflow or underflow has occurred. The over/under flow for both channels are multiplexed onto this pin. Channel 2 appears when CLKOUT+ is low, and Channel 1 appears when CLKOUT+ is high. DOUBLE DATA RATE LVDS OUTPUT MODE All Pins Below Have LVDS Output Levels. The Output Current Level Is Programmable. There Is an Optional Internal 100 Termination Resistor Between the Pins of Each LVDS Output Pair. D2_0_1-/D2_0_1+ to D2_14_15-/D2_14_15+ (Pins 23/24, 25/26, 27/28, 29/30, 31/32, 33/34, 35/36, 37/38): Channel 2 Double Data Rate Digital Outputs. Two data bits are multiplexed onto each differential output pair. The even data bits (D0, D2, D4, D6, D8, D10, D12, D14) appear when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13, D15) appear when CLKOUT+ is high. CLKOUT-/CLKOUT+ (Pins 39/40): Data Output Clock. The Digital Outputs normally transition at the same time as the falling and rising edges of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the Digital Outputs by programming the mode control registers. 218543f 17 LTC2185/LTC2184/LTC2183 Pin Functions D1_0_1-/D1_0_1+ to D1_14_15-/D1_14_15+ (Pins 43/44, 45/46, 47/48, 49/50, 51/52, 53/54, 55/56, 57/58): Channel 2 Double Data Rate Digital Outputs. Two data bits are multiplexed onto each differential output pair. The even data bits (D0, D2, D4, D6, D8, D10, D12, D14) appear when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13, D15) appear when CLKOUT+ is high. OF2_1-/OF2_1+ (Pins 59/60): Over/Under Flow Digital Output. OF2_1+ is high when an overflow or underflow has occurred. The over/under flow for both channels are multiplexed onto this pin. Channel 2 appears when CLKOUT+ is low, and Channel 1 appears when CLKOUT+ is high. Functional Block Diagram OVDD CH 1 ANALOG INPUT OF1 16-BIT ADC CORE S/H OF2 CORRECTION LOGIC CH 2 ANALOG INPUT 16-BIT ADC CORE S/H D1_15 * * * D1_0 OUTPUT DRIVERS CLKOUT + CLKOUT - VREF 2.2F D2_15 * * * D2_0 1.25V REFERENCE RANGE SELECT SENSE VCM1 0.1F OGND REFH REF BUF VDD/2 REFL INTERNAL CLOCK SIGNALS VDD DIFF REF AMP CLOCK/DUTY CYCLE CONTROL MODE CONTROL REGISTERS VCM2 0.1F GND REFH REFL ENC+ 2.2F 0.1F ENC- PAR/SER CS SCK SDI SDO 218543 F01 0.1F Figure 1. Functional Block Diagram 218543f 18 LTC2185/LTC2184/LTC2183 Applications Information Converter Operation The LTC2185/LTC2184/LTC2183 are low power, two-channel, 16-bit, 125Msps/105Msps/80Msps A/D converters that are powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially, or single ended for lower power consumption. The digital outputs can be CMOS, double data rate CMOS (to halve the number of output lines), or double data rate LVDS (to reduce digital noise in the system.) Many additional features can be chosen by programming the mode control registers through a serial SPI port. The two channels are simultaneously sampled by a shared encode circuit (Figure 2). Single-Ended Input For applications less sensitive to harmonic distortion, the AIN+ input can be driven single-ended with a 1VP-P signal centered around VCM. The AIN- input should be connected to VCM. With a single-ended input the harmonic distortion and INL will degrade, but the noise and DNL will remain unchanged. Input Drive Circuits Analog Input Input filtering The analog inputs are differential CMOS sample-and-hold circuits (Figure 2). The inputs should be driven differentially around a common mode voltage set by the VCM1 or VCM2 output pins, which are nominally VDD/2. For the 2V input range, the inputs should swing from VCM - 0.5V to VCM + 0.5V. There should be 180 phase difference between the inputs. If possible, there should be an RC lowpass filter right at the analog inputs. This lowpass filter isolates the drive circuitry from the A/D sample-and-hold switching, and also limits wideband noise from the drive circuitry. Figure 3 shows an example of an input RC filter. The RC component values should be chosen based on the application's input frequency. Transformer Coupled Circuits LTC2185 VDD AIN+ RON 15 10 CPARASITIC 1.8pF VDD AIN- CSAMPLE 5pF RON 15 10 CSAMPLE 5pF CPARASITIC 1.8pF Figure 3 shows the analog input being driven by an RF transformer with a center-tapped secondary. The center tap is biased with VCM, setting the A/D input at its optimal DC level. At higher input frequencies a transmission line balun transformer (Figure 4 to Figure 6) has better balance, resulting in lower A/D distortion. 50 VDD VCM 0.1F 0.1F ANALOG INPUT 1.2V 10k T1 1:1 25 25 AIN+ LTC2185 0.1F 12pF ENC+ 25 ENC- 25 T1: MA/COM MABAES0060 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 10k 1.2V 218543 F02 Figure 2. Equivalent Input Circuit. Only One of the Two Analog Channels Is Shown AIN- 218543 F03 Figure 3. Analog Input Circuit Using a Transformer. Recommended for Input Frequencies from 5MHz to 70MHz 218543f 19 LTC2185/LTC2184/LTC2183 Applications Information Amplifier Circuits Reference Figure 7 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is ACcoupled to the A/D so the amplifier's output common mode voltage can be optimally set to minimize distortion. The LTC2185/LTC2184/LTC2183 has an internal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE to VDD. For a 1V input range using the internal reference, connect SENSE to ground. For a 2V input range with an external reference, apply a 1.25V reference voltage to SENSE (Figure 9). At very high frequencies an RF gain block will often have lower distortion than a differential amplifier. If the gain block is single-ended, then a transformer circuit (Figure 4 to Figure 6) should convert the signal to differential before driving the A/D. 50 VCM 0.1F 0.1F ANALOG INPUT 12 T2 T1 25 AIN+ LTC2185 0.1F 8.2pF 0.1F 25 12 The input range can be adjusted by applying a voltage to SENSE that is between 0.625V and 1.30V. The input range will then be 1.6 * VSENSE. The VREF, REFH and REFL pins should be bypassed as shown in Figure 8. A low inductance 2.2F interdigitated capacitor is recommended for the bypass between REFH and REFL. This type of capacitor is available at a low cost from multiple suppliers. AIN- 50 0.1F 218543 F04 T1: MA/COM MABA-007159-000000 T2: COILCRAFT WBC1-1TL RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 0.1F ANALOG INPUT T1 25 25 25 VCM 4.7nH AIN- 218543 F06 Figure 6. Recommended Front-End Circuit for Input Frequencies Above 250MHz LTC2185 0.1F 25 LTC2185 0.1F VCM 1.8pF 0.1F AIN+ T1: MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE AIN+ T2 T1 0.1F 0.1F 0.1F 4.7nH ANALOG INPUT Figure 4. Recommended Front-End Circuit for Input Frequencies from 5MHz to 150MHz 50 VCM HIGH SPEED DIFFERENTIAL 0.1F AMPLIFIER AIN- 218543 F05 T1: MA/COM MABA-007159-000000 T2: COILCRAFT WBC1-1TL RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 5. Recommended Front-End Circuit for Input Frequencies from 150MHz to 250MHz ANALOG INPUT + + - - 200 200 25 0.1F AIN+ 12pF 0.1F 25 LTC2185 AIN- 12pF 218543 F07 Figure 7. Front-End Circuit Using a High Speed Differential Amplifier 218543f 20 LTC2185/LTC2184/LTC2183 Applications Information in some vendors' capacitors. In Figure 8d the REFH and REFL pins are connected by short jumpers in an internal layer. To minimize the inductance of these jumpers they can be placed in a small hole in the GND plane on the second board layer. LTC2185 VREF 1.25V 5 2.2F 1.25V BANDGAP REFERENCE 0.625V TIE TO VDD FOR 2V RANGE; TIE TO GND FOR 1V RANGE; RANGE = 1.6 * VSENSE FOR 0.625V < VSENSE < 1.300V RANGE DETECT AND CONTROL SENSE BUFFER INTERNAL ADC HIGH REFERENCE C2 0.1F + REFH - REFL - + REFH + - REFL - + Figure 8c. Recommended Layout for the REFH/REFL Bypass Circuit in Figure 8a 0.8x DIFF AMP C1 C3 0.1F INTERNAL ADC LOW REFERENCE C1: 2.2F LOW INDUCTANCE INTERDIGITATED CAPACITOR TDK CLLE1AX7S0G225M MURATA LLA219C70G225M AVX W2L14Z225M OR EQUIVALENT 218543 F08a Figure 8d. Recommended Layout for the REFH/REFL Bypass Circuit in Figure 8b. Figure 8a. Reference Circuit At sample rates below 110Msps an interdigitated capacitor is not necessary for good performance and C1 can be replaced by a standard 2.2F capacitor between REFH and REFL (see Figure 8b). The capacitors should be as close to the pins as possible (not on the back side of the circuit board). Figure 8c and Figure 8d show the recommended circuit board layout for the REFH/REFL bypass capacitors. Note that in Figure 8c, every pin of the interdigitated capacitor (C1) is connected since the pins are not internally connected REFH C3 0.1F REFL C1 2.2F C2 0.1F LTC2185 REFH REFL CAPACITORS ARE 0402 PACKAGE SIZE 218543 F08b VREF 2.2F 1.25V EXTERNAL REFERENCE LTC2185 SENSE 1F 218543 F09 Figure 9. Using an External 1.25V Reference Encode Input The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals - do not route them next to digital traces on the circuit board. There are two modes of operation for the encode inputs: the differential encode mode (Figure 10), and the single-ended encode mode (Figure 11). The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figure 12 and Figure 13). The encode inputs are internally biased to 1.2V Figure 8b. Alternative REFH/REFL Bypass Circuit 218543f 21 LTC2185/LTC2184/LTC2183 Applications Information LTC2185 through 10k equivalent resistance. The encode inputs can be taken above VDD (up to 3.6V), and the common mode range is from 1.1V to 1.6V. In the differential encode mode, ENC- should stay at least 200mV above ground to avoid falsely triggering the single ended encode mode. For good jitter performance ENC+ and ENC- should have fast rise and fall times. VDD DIFFERENTIAL COMPARATOR VDD 15k ENC+ ENC- The single-ended encode mode should be used with CMOS encode inputs. To select this mode, ENC- is connected to ground and ENC+ is driven with a square wave encode input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V to 3.3V CMOS logic levels can be used. The ENC+ threshold is 0.9V. For good jitter performance ENC+ should have fast rise and fall times. 30k 218543 F10 Figure 10. Equivalent Encode Input Circuit for Differential Encode Mode LTC2185 If the encode signal is turned off or drops below approximately 500kHz, the A/D enters nap mode. ENC+ 1.8V TO 3.3V 0V ENC- 30k CMOS LOGIC BUFFER Clock Duty Cycle Stabilizer 218543 F11 Figure 11. Equivalent Encode Input Circuit for Single-Ended Encode Mode 0.1F ENC+ T1 50 LTC2185 100 50 0.1F 0.1F ENC- 218543 F12 T1 = MA/COM ETC1-1-13 RESISTORS AND CAPACITORS ARE 0402 PACKAGE SIZE Figure 12. Sinusoidal Encode Drive 0.1F PECL OR LVDS CLOCK For applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. If the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50% (5%) duty cycle. The duty cycle stabilizer should not be used below 5Msps. Digital Outputs ENC+ LTC2185 0.1F For good performance the encode signal should have a 50% (5%) duty cycle. If the optional clock duty cycle stabilizer circuit is enabled, the encode duty cycle can vary from 30% to 70% and the duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the encode signal changes frequency, the duty cycle stabilizer circuit requires one hundred clock cycles to lock onto the input clock. The duty cycle stabilizer is enabled by mode control register A2 (Serial Programming Mode), or by CS (Parallel Programming Mode). ENC- 218543 F13 Figure 13. PECL or LVDS Encode Drive Digital Output Modes The LTC2185/LTC2184/LTC2183 can operate in three digital output modes: full rate CMOS, double data rate CMOS (to halve the number of output lines), or double data rate LVDS (to reduce digital noise in the system.) The output mode is set by mode control register A3 (Serial Programming 218543f 22 LTC2185/LTC2184/LTC2183 Applications Information Mode), or by SCK (Parallel Programming Mode). Note that double data rate CMOS cannot be selected in the Parallel Programming Mode. Full Rate CMOS Mode In Full Rate CMOS Mode the data outputs (D1_0 to D1_15 and D2_0 to D2_15), overflow (OF2, OF1), and the data output clocks (CLKOUT+, CLKOUT-) have CMOS output levels. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. OVDD can range from 1.1V to 1.9V, allowing 1.2V through 1.8V CMOS logic outputs. For good performance the digital outputs should drive minimal capacitive loads. If the load capacitance is larger than 10pF a digital buffer should be used. Double Data Rate CMOS Mode In Double Data Rate CMOS Mode, two data bits are multiplexed and output on each data pin. This reduces the number of digital lines by seventeen, simplifying board routing and reducing the number of input pins needed to receive the data. The data outputs (D1_0_1, D1_2_3, D1_4_5, D1_6_7, D1_8_9, D1_10_11, D1_12_13, D1_14_15, D2_0_1, D2_2_3, D2_4_5, D2_6_7, D2_8_9, D2_10_11, D2_12_13, D2_14_15), overflow (OF2_1), and the data output clocks (CLKOUT+, CLKOUT-) have CMOS output levels. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. OVDD can range from 1.1V to 1.9V, allowing 1.2V through 1.8V CMOS logic outputs. Note that the overflow for both ADC channels is multiplexed onto the OF2_1 pin. For good performance the digital outputs should drive minimal capacitive loads. If the load capacitance is larger than 10pF a digital buffer should be used. When using Double Data Rate CMOS at sample rates above 100Msps the SNR may degrade slightly, about 0.2dB to 0.5dB depending on load capacitance and board layout. Double Data Rate LVDS Mode In Double Data Rate LVDS Mode, two data bits are multiplexed and output on each differential output pair. There are eight LVDS output pairs per ADC channel (D1_0_1+/ D1_0_1- through D1_14_15+/D1_14_15- and D2_0_1+/ D2_0_1- through D2_14_15+/D2_14_15-) for the digital output data. Overflow (OF2_1+/OF2_1-) and the data output clock (CLKOUT+/CLKOUT-) each have an LVDS output pair. Note that the overflow for both ADC channels is multiplexed onto the OF2_1+/OF2_1- output pair. By default the outputs are standard LVDS levels: 3.5mA output current and a 1.25V output common mode voltage. An external 100 differential termination resistor is required for each LVDS output pair. The termination resistors should be located as close as possible to the LVDS receiver. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. In LVDS mode, OVDD must be 1.8V. Programmable LVDS Output Current In LVDS Mode, the default output driver current is 3.5mA. This current can be adjusted by serially programming mode control register A3. Available current levels are 1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. Optional LVDS Driver Internal Termination In most cases using just an external 100 termination resistor will give excellent LVDS signal integrity. In addition, an optional internal 100 termination resistor can be enabled by serially programming mode control register A3. The internal termination helps absorb any reflections caused by imperfect termination at the receiver. When the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. Overflow Bit The overflow output bit outputs a logic high when the analog input is either over-ranged or under-ranged. The overflow bit has the same pipeline latency as the data bits. In Full-Rate CMOS mode each ADC channel has its own overflow pin (OF1 for channel 1, OF2 for channel 2). In DDR CMOS or DDR LVDS mode the overflow for both ADC channels is multiplexed onto the OF2_1 output. 218543f 23 LTC2185/LTC2184/LTC2183 Applications Information Phase Shifting the Output Clock Data Format In Full Rate CMOS mode the data output bits normally change at the same time as the falling edge of CLKOUT+, so the rising edge of CLKOUT+ can be used to latch the output data. In Double Data Rate CMOS and LVDS Modes the data output bits normally change at the same time as the falling and rising edges of CLKOUT+. To allow adequate set-up and hold time when latching the data, the CLKOUT+ signal may need to be phase shifted relative to the data output bits. Most FPGAs have this feature; this is generally the best place to adjust the timing. Table 1 shows the relationship between the analog input voltage, the digital data output bits and the overflow bit. By default the output data format is offset binary. The 2's complement format can be selected by serially programming mode control register A4. The LTC2185/LTC2184/LTC2183 can also phase shift the CLKOUT+/CLKOUT- signals by serially programming mode control register A2. The output clock can be shifted by 0, 45, 90, or 135. To use the phase shifting feature the Clock Duty Cycle Stabilizer must be turned on. Another control register bit can invert the polarity of CLKOUT+ and CLKOUT-, independently of the phase shift. The combination of these two features enables phase shifts of 45 up to 315 (Figure 14). Table 1. Output Codes vs Input Voltage AIN+ - AIN- (2V Range) OF D15-D0 (OFFSET BINARY) D15-D0 (2's COMPLEMENT) >1.000000V 1 1111 1111 1111 1111 0111 1111 1111 1111 +0.999970V 0 1111 1111 1111 1111 0111 1111 1111 1111 +0.999939V 0 1111 1111 1111 1110 0111 1111 1111 1110 +0.000030V 0 1000 0000 0000 0001 0000 0000 0000 0001 +0.000000V 0 1000 0000 0000 0000 0000 0000 0000 0000 -0.000030V 0 0111 1111 1111 1111 1111 1111 1111 1111 -0.000061V 0 0111 1111 1111 1110 1111 1111 1111 1110 -0.999939V 0 0000 0000 0000 0001 1000 0000 0000 0001 -1.000000V 0 0000 0000 0000 0000 1000 0000 0000 0000 <-1.000000V 1 0000 0000 0000 0000 1000 0000 0000 0000 ENC+ D0-D15, OF CLKOUT+ MODE CONTROL BITS PHASE SHIFT CLKINV CLKPHASE1 CLKPHASE0 0 0 0 0 45 0 0 1 90 0 1 0 135 0 1 1 180 1 0 0 225 1 0 1 270 1 1 0 315 1 1 1 218543 F14 Figure 14. Phase Shifting CLKOUT 218543f 24 LTC2185/LTC2184/LTC2183 Applications Information Digital Output Randomizer CLKOUT Interference from the A/D digital outputs is sometimes unavoidable. Digital interference may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can cause unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude. The digital output is randomized by applying an exclusiveOR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied - an exclusive-OR operation is applied between the LSB and all other bits. The LSB, OF and CLKOUT outputs are not affected. The output randomizer is enabled by serially programming mode control register A4. Alternate Bit Polarity Another feature that reduces digital feedback on the circuit board is the alternate bit polarity mode. When this mode is enabled, all of the odd bits (D1, D3, D5, D7, D9, D11, D13, D15) are inverted before the output buffers. The even bits (D0, D2, D4, D6, D8, D10, D12, D14), OF and CLKOUT are not affected. This can reduce digital currents in the circuit board ground plane and reduce digital noise, particularly for very small analog input signals. When there is a very small signal at the input of the A/D that is centered around mid-scale, the digital outputs toggle between mostly 1's and mostly 0's. This simultaneous switching of most of the bits will cause large currents in the ground plane. By inverting every other bit, the Alternate Bit Polarity Mode makes half of the bits transition high while half of the bits transition low. This cancels current flow in the ground plane, reducing the digital noise. The digital output is decoded at the receiver by inverting the odd bits (D1, D3, D5, D7, D9, D11, D13, D15.) The Alternate Bit Polarity Mode is independent of the Digital Output Randomizer - either, both or neither function can be on at the same time. The Alternate Bit Polarity Mode is enabled by serially programming mode control register A4. CLKOUT OF OF D15 D15/D0 D14 D2 D14/D0 * * * D2/D0 RANDOMIZER ON D1 D1/D0 D0 D0 218543 F15 Figure 15. Functional Equivalent of Digital Output Randomizer PC BOARD CLKOUT FPGA OF D15/D0 D15 D14/D0 LTC2185 D2/D0 * * * D14 D2 D1/D0 D1 D0 D0 218543 F16 Figure 16. Unrandomizing a Randomized Digital Output Signal 218543f 25 LTC2185/LTC2184/LTC2183 Applications Information Digital Output Test Patterns To allow in-circuit testing of the digital interface to the A/D, there are several test modes that force the A/D data outputs (OF, D15-D0) to known values: All 1s: All outputs are 1 All 0s: All outputs are 0 Alternating: Outputs change from all 1s to all 0s on alternating samples. Checkerboard: Outputs change from 10101010101010101 to 01010101010101010 on alternating samples. The digital output test patterns are enabled by serially programming mode control register A4. When enabled, the Test Patterns override all other formatting modes: 2's complement, randomizer, alternate bit polarity. Output Disable The digital outputs may be disabled by serially programming mode control register A3. All digital outputs including OF and CLKOUT are disabled. The high-impedance disabled state is intended for in-circuit testing or long periods of inactivity - it is too slow to multiplex a data bus between multiple converters at full speed. When the outputs are disabled both channels should be put into either sleep or nap mode. Sleep and Nap Modes The A/D may be placed in sleep or nap modes to conserve power. In sleep mode the entire device is powered down, resulting in 1mW power consumption. The amount of time required to recover from sleep mode depends on the size of the bypass capacitors on VREF, REFH, and REFL. For the suggested values in Fig. 8, the A/D will stabilize after 2ms. In nap mode the A/D core is powered down while the internal reference circuits stay active, allowing faster wakeup than from sleep mode. Recovering from nap mode requires at least 100 clock cycles. If the application demands very accurate DC settling then an additional 50s should be allowed so the on-chip references can settle from the slight temperature shift caused by the change in supply current as the A/D leaves nap mode. Either channel 2 or both channels can be placed in nap mode; it is not possible to have channel 1 in nap mode and channel 2 operating normally. Sleep mode and nap mode are enabled by mode control register A1 (serial programming mode), or by SDI and SDO (parallel programming mode). Device Programming Modes The operating modes of the LTC2185/LTC2184/LTC2183 can be programmed by either a parallel interface or a simple serial interface. The serial interface has more flexibility and can program all available modes. The parallel interface is more limited and can only program some of the more commonly used modes. Parallel Programming Mode To use the parallel programming mode, PAR/SER should be tied to VDD. The CS, SCK, SDI and SDO pins are binary logic inputs that set certain operating modes. These pins can be tied to VDD or ground, or driven by 1.8V, 2.5V, or 3.3V CMOS logic. When used as an input, SDO should be driven through a 1k series resistor. Table 2 shows the modes set by CS, SCK, SDI and SDO. Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD) PIN DESCRIPTION CS Clock Duty Cycle Stabilizer Control Bit 0 = Clock Duty Cycle Stabilizer Off 1 = Clock Duty Cycle Stabilizer On SCK Digital Output Mode Control Bit 0 = Full-Rate CMOS Output Mode 1 = Double Data Rate LVDS Output Mode (3.5mA LVDS Current, Internal Termination Off) SDI/SDO Power Down Control Bit 00 = Normal Operation 01 = Channel 1 in Normal Operation, Channel 2 in Nap Mode 10 = Channel 1 and Channel 2 in Nap Mode 11 = Sleep Mode (Entire Device Powered Down) 218543f 26 LTC2185/LTC2184/LTC2183 Applications Information Serial Programming Mode Grounding And Bypassing To use the serial programming mode, PAR/SER should be tied to ground. The CS, SCK, SDI and SDO pins become a serial interface that program the A/D mode control registers. Data is written to a register with a 16-bit serial word. Data can also be read back from a register to verify its contents. The LTC2185/LTC2184/LTC2183 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane in the first layer beneath the ADC is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first 16 rising edges of SCK. Any SCK rising edges after the first 16 are ignored. The data transfer ends when CS is taken high again. The first bit of the 16-bit input word is the R/W bit. The next seven bits are the address of the register (A6:A0). The final eight bits are the register data (D7:D0). If the R/W bit is low, the serial data (D7:D0) will be written to the register set by the address bits (A6:A0). If the R/W bit is high, data in the register set by the address bits (A6:A0) will be read back on the SDO pin (see the timing diagrams). During a read back command the register is not updated and data on SDI is ignored. The SDO pin is an open drain output that pulls to ground with a 200 impedance. If register data is read back through SDO, an external 2k pull-up resistor is required. If serial data is only written and read back is not needed, then SDO can be left floating and no pull-up resistor is needed. Table 3 shows a map of the mode control registers. Software Reset If serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. The first serial command must be a software reset which will reset all register data bits to logic 0. To perform a software reset, bit D7 in the reset register is written with a logic 1. After the reset is complete, bit D7 is automatically set back to zero. High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, VREF, REFH and REFL pins. Bypass capacitors must be located as close to the pins as possible. Size 0402 ceramic capacitors are recommended. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. Of particular importance is the capacitor between REFH and REFL. This capacitor should be on the same side of the circuit board as the A/D, and as close to the device as possible. A low inductance interdigitated capacitor is suggested for REFH/REFL if the sampling frequency is greater than 110Msps. The analog inputs, encode signals, and digital outputs should not be routed next to each other. Ground fill and grounded vias should be used as barriers to isolate these signals from each other. Heat Transfer Most of the heat generated by the LTC2185/LTC2184/ LTC2183 is transferred from the die through the bottomside exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board. This pad should be connected to the internal ground planes by an array of vias. 218543f 27 LTC2185/LTC2184/LTC2183 Applications Information Table 3. Serial Programming Mode Register Map (PAR/SER = GND) REGISTER A0: RESET REGISTER (ADDRESS 00h) D7 D6 D5 D4 D3 D2 D1 D0 RESET X X X X X X X RESET Bit 7 Software Reset Bit 0 = Not Used 1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC Is Momentarily Placed in SLEEP Mode. This Bit Is Automatically Set Back to Zero After the Reset Is Complete Bits 6-0 Unused, Don't Care Bits. REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h) D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X PWROFF1 PWROFF0 Bits 7-2 Unused, Don't Care Bits. Bits 1-0 PWROFF1:PWROFF0 Power Down Control Bits 00 = Normal Operation 01 = Channel 1 in Normal Operation, Channel 2 in Nap Mode 10 = Channel 1 and Channel 2 in Nap Mode 11 = Sleep Mode REGISTER A2: TIMING REGISTER (ADDRESS 02h) D7 D6 D5 D4 D3 D2 D1 D0 X X X X CLKINV CLKPHASE1 CLKPHASE0 DCS Bits 7-4 Unused, Don't Care Bits. Bit 3 CLKINV Output Clock Invert Bit 0 = Normal CLKOUT Polarity (As Shown in the Timing Diagrams) 1 = Inverted CLKOUT Polarity Bits 2-1 CLKPHASE1:CLKPHASE0 Output Clock Phase Delay Bits 00 = No CLKOUT Delay (As Shown in the Timing Diagrams) 01 = CLKOUT+/CLKOUT- Delayed by 45 (Clock Period * 1/8) 10 = CLKOUT+/CLKOUT- Delayed by 90 (Clock Period * 1/4) 11 = CLKOUT+/CLKOUT- Delayed by 135 (Clock Period * 3/8) Note: If the CLKOUT Phase Delay Feature Is Used, the Clock Duty Cycle Stabilizer Must Also Be Turned On Bit 0 DCS Clock Duty Cycle Stabilizer Bit 0 = Clock Duty Cycle Stabilizer Off 1 = Clock Duty Cycle Stabilizer On 218543f 28 LTC2185/LTC2184/LTC2183 Applications Information REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h) D7 D6 D5 D4 D3 D2 D1 D0 X ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF OUTMODE1 OUTMODE0 Bit 7 Unused, Don't Care Bit. Bits 6-4 ILVDS2:ILVDS0 LVDS Output Current Bits 000 = 3.5mA LVDS Output Driver Current 001 = 4.0mA LVDS Output Driver Current 010 = 4.5mA LVDS Output Driver Current 011 = Not Used 100 = 3.0mA LVDS Output Driver Current 101 = 2.5mA LVDS Output Driver Current 110 = 2.1mA LVDS Output Driver Current 111 = 1.75mA LVDS Output Driver Current Bit 3 TERMON LVDS Internal Termination Bit 0 = Internal Termination Off 1 = Internal Termination On. LVDS Output Driver Current is 2x the Current Set by ILVDS2:ILVDS0 Bit 2 OUTOFF Output Disable Bit 0 = Digital Outputs Are Enabled 1 = Digital Outputs Are Disabled and Have High Output Impedance Note: If the Digital Outputs Are Disabled the Part Should Also Be Put in Sleep or Nap Mode (Both Channels). Bits 1-0 OUTMODE1:OUTMODE0 Digital Output Mode Control Bits 00 = Full-Rate CMOS Output Mode 01 = Double Data Rate LVDS Output Mode 10 = Double Data Rate CMOS Output Mode 11 = Not Used REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h) D7 D6 D5 D4 D3 D2 D1 D0 X X OUTTEST2 OUTTEST1 OUTTEST0 ABP RAND TWOSCOMP Bit 7-6 Unused, Don't Care Bits. Bits 5-3 OUTTEST2:OUTTEST0 Digital Output Test Pattern Bits 000 = Digital Output Test Patterns Off 001 = All Digital Outputs = 0 011 = All Digital Outputs = 1 101 = Checkerboard Output Pattern. OF, D15-D0 Alternate Between 1 0101 0101 0101 0101 and 0 1010 1010 1010 1010 111 = Alternating Output Pattern. OF, D15-D0 Alternate Between 0 0000 0000 0000 0000 and 1 1111 1111 1111 1111 Note: Other Bit Combinations Are not Used Bit 2 ABP Alternate Bit Polarity Mode Control Bit 0 = Alternate Bit Polarity Mode Off 1 = Alternate Bit Polarity Mode On. Forces the Output Format to Be Offset Binary Bit 1 Data Output Randomizer Mode Control Bit RAND 0 = Data Output Randomizer Mode Off 1 = Data Output Randomizer Mode On Bit 0 TWOSCOMP Two's Complement Mode Control Bit 0 = Offset Binary Data Format 1 = Two's Complement Data Format 218543f 29 LTC2185/LTC2184/LTC2183 Typical Applications Silkscreen Top Top Side 218543f 30 LTC2185/LTC2184/LTC2183 TYPICAL APPLICATIONS Inner Layer 2 GND Inner Layer 3 218543f 31 LTC2185/LTC2184/LTC2183 TYPICAL APPLICATIONS Inner Layer 4 Inner Layer 5 Power 218543f 32 LTC2185/LTC2184/LTC2183 TYPICAL APPLICATIONS Bottom Side 218543f 33 LTC2185/LTC2184/LTC2183 TYPICAL APPLICATIONS SDO C23 2.2F SENSE 50 51 49 D1_6_7- D1_6_7+ D1_8_9- 53 54 55 56 57 58 52 D1_8_9+ D1_10_11- D1_10_11+ D1_12_13- D1_12_13+ D1_14_15- D1_14_15+ 60 61 59 OF2_1- OF2_1 + SDO 62 PAR/SER D2_14_15+ + D2_14_15- - D2_12_13+ AIN2 AIN2 GND D2_12_13- VCM2 D2_10_11+ D2_10_11- D2_8_9+ PAD 48 DIGITAL OUTPUTS 47 46 45 44 43 42 C37 0.1F 41 40 OVDD 39 38 37 36 35 34 33 DIGITAL OUTPUTS 65 32 D2_8_9- D2_6_7+ 31 30 D2_6_7- 29 28 ENC+ VDD 17 C18 0.1F D2_4_5+ VDD AIN2- C67 0.1F VREF CLKOUT- REFL AIN2+ VDD CLKOUT+ D2_4_5- PAR/SER LTC2185 REFH 27 16 OGND D2_2_3+ 15 OVDD REFL 26 14 REFH D2_2_3- 13 GND 25 12 D1_0_1- D2_0_1+ 11 AIN1 D2_0_1- + - D1_0_1+ 24 C21 0.1F - + 10 - AIN1 23 9 CN1 D1_2_3- SDI 8 + 19 - + 6 GND SCK + - 7 5 D1_2_3+ 22 4 D1_4_5- 18 C15 0.1F AIN1+ AIN1- D1_4_5+ VCM1 CS 3 21 2 VDD 20 1 SENSE VDD 64 C19 C20 0.1F 0.1F ENC- VDD 63 C17 1F C78 0.1F C79 0.1F R51 100 ENCODE CLOCK SPI BUS LTC2185 Schematic 218543f 34 LTC2185/LTC2184/LTC2183 Package Description UP Package 64-Lead Plastic QFN (9mm x 9mm) (Reference LTC DWG # 05-08-1705 Rev C) 0.70 0.05 7.15 0.05 7.50 REF 8.10 0.05 9.50 0.05 (4 SIDES) 7.15 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 9 .00 0.10 (4 SIDES) 0.75 0.05 R = 0.10 TYP R = 0.115 TYP 63 64 0.40 0.10 PIN 1 TOP MARK (SEE NOTE 5) 1 2 PIN 1 CHAMFER C = 0.35 7.50 REF (4-SIDES) 7.15 0.10 7.15 0.10 (UP64) QFN 0406 REV C 0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE 0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD 218543f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 35 LTC2185/LTC2184/LTC2183 Typical Application 1.8V 1.8V VDD 2-Tone FFT, fIN = 70MHz and 69MHz OVDD 0 -10 CH 2 ANALOG INPUT D1_15 * * * D1_0 16-BIT ADC CORE S/H 16-BIT ADC CORE S/H 125MHz D2_15 * * * D2_0 OUTPUT DRIVERS -30 CMOS OR LVDS OUTPUTS -40 -50 -60 -70 -80 -90 -100 -110 -120 CLOCK CONTROL CLOCK -20 AMPLITUDE (dBFS) CH 1 ANALOG INPUT 0 10 20 30 40 FREQUENCY (MHz) 50 218543 TA03b 218543 TA03a GND 60 OGND Related Parts PART NUMBER DESCRIPTION COMMENTS ADCs LTC2259-14/LTC2260-14/ 14-Bit, 80Msps/105Msps/125Msps LTC2261-14 1.8V ADCs, Ultralow Power 89mW/106mW/127mW, 73.4dB SNR, 85dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs, 6mm x 6mm QFN-40 LTC2266-14/LTC2267-14/ 14-Bit, 80Msps/105Msps/125Msps LTC2268-14 1.8V Dual ADCs, Ultralow Power 216mW/250mW/293mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs, 6mm x 6mm QFN-40 LTC2266-12/LTC2267-12/ 12-Bit, 80Msps/105Msps/125Msps LTC2268-12 1.8V Dual ADCs, Ultralow Power 216mW/250mW/293mW, 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs, 6mm x 6mm QFN-40 RF Mixers/Demodulators LTC5517 40MHz to 900MHz Direct Conversion Quadrature Demodulator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator LTC5527 400MHz to 3.7GHz High Linearity Downconverting Mixer 24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB, 50 Single-Ended RF and LO Ports LTC5557 400MHz to 3.8GHz High Linearity Downconverting Mixer 23.7dBm IIP3 at 2.6GHz, 23.5dBm IIP3 at 3.5GHz, NF = 13.2dB, 3.3V Supply Operation, Integrated Transformer LTC5575 800MHz to 2.7GHz Direct Conversion Quadrature Demodulator High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator, Integrated RF and LO Transformer Amplifiers/Filters LTC6412 800MHz, 31dB Range, Analog-Controlled Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise Figure, Variable Gain Amplifier 4mm x 4mm QFN-24 LTC6420-20 1.8GHz Dual Low Noise, Low Distortion Differential ADC Drivers for 300MHz IF Fixed Gain 10V/V, 1nV/Hz Total Input Noise, 80mA Supply Current per Amplifier, 3mm x 4mm QFN-20 LTC6421-20 1.3GHz Dual Low Noise, Low Distortion Differential ADC Drivers Fixed Gain 10V/V, 1nV/Hz Total Input Noise, 40mA Supply Current per Amplifier, 3mm x 4mm QFN-20 LTC6605-7/LTC6605-10/ LTC6605-14 Dual Matched 7MHz/10MHz/14MHz Filters with ADC Drivers Dual Matched 2nd Order Lowpass Filters with Differential Drivers, Pin-Programmable Gain, 6mm x 3mm DFN-22 14-Bit Dual Channel IF/Baseband Receiver Subsystem Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers Signal Chain Receivers LTM9002 218543f 36 Linear Technology Corporation LT 0111 * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com LINEAR TECHNOLOGY CORPORATION 2011