FS6245 Dual PLL VCXO Clock Generator IC 1.0 Features 2.0 * On-chip tunable voltage-controlled crystal oscillator circuitry (VCXO) allows precise system frequency tuning (pull range typically 300ppm) * VCXO tuning range: 0-3V * Uses inexpensive fundamental-mode crystals * Two integrated phase-locked loops (PLL) multiply VCXO frequency to the higher system frequencies needed * 5V core supply voltage (contact factory for 3.3V) * 3.3V / 5V output supply voltage * Small circuit board footprint (20-pin SOIC) * Custom frequency selections available - contact your local AMI Sales Representative for more information Figure 1: Pin Configuration n/c 1 20 n/c 2 19 n/c XIN 3 18 CLKC 17 n/c 16 n/c 15 VDDO 14 VSS 4 5 n/c 6 VSS 7 OE 8 13 CLKB 9 12 n/c 10 11 n/c FS6245 VDD XTUNE n/c The FS6245 is a monolithic CMOS clock generator IC designed to minimize cost and component count in digital video/audio systems. At the core of the FS6245 is circuitry that implements a voltage-controlled crystal oscillator when an external resonator is attached. The VCXO allows device frequencies to be precisely adjusted for use in systems that have frequency matching requirements, such as digital satellite receivers. Two high-resolution phase-locked loops generate the output clock frequencies (CLKA, CLKB, and CLKC). These frequencies are phase-locked and frequencylocked to the VCXO frequency. Synthesis error of the PLLs is +/-0 ppm unless otherwise noted. Table 1: Crystal / Output Frequencies XOUT CLKA Description DEVICE fXIN (MHz) CLKA (MHz) CLKB (MHz) CLKC (MHz) FS6245-01 13.500 11.0592 18.432 27.000 NOTE: Contact AMI for custom PLL frequencies Figure 2: Block Diagram XIN VCXO CLKA PLL XOUT XTUNE Divider Array CLKB PLL CLKC FS6245 This document contains information on a preproduction product. Specifications and information herein are subject to change without notice. ISO9001 2.28.02 FS6245 Dual PLL VCXO Clock Generator IC Table 2: Pin Descriptions Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin PIN TYPE NAME 1 - N/C No Connection 2 AI XIN VCXO Crystal Feedback 3 AO XOUT / FREF 4 P VDD 5 AI XTUNE DESCRIPTION VCXO Crystal Drive / External Reference Clock Input Core Power Supply VCXO Tune Input 6 - N/C No Connection 7 P VSS Ground 8 DIU OE Output Enable 9 DO CLKA 10 - N/C No Connection 11 - N/C No Connection 12 - N/C No Connection 13 DO CLKB 14 P VSS 15 P VDDO 16 - N/C No Connection 17 - N/C No Connection 18 DO CLKC 19 - N/C No Connection 20 - N/C No Connection Clock Output "A" Clock Output "B" Ground Output Power Supply (must be less than or equal to VDD) Clock Output "C" 2 ISO9001 2.28.02 FS6245 Dual PLL VCXO Clock Generator IC 3.0 Functional Block Description 3.1 Phase-Locked Loop (PLL) A simple formula to obtain the warping capability of a crystal oscillator is: f ( ppm) = The on-chip PLL is a standard frequency- and phaselocked loop architecture. The PLL multiplies the reference oscillator to the desired frequency by a ratio of integers. The frequency multiplication is exact with a zero synthesis error (unless otherwise noted). 3.2 C1 x (C L 2 - C L1) x 10 2 x (C 0 + C L 2 ) x (C 0 + C L1) 6 where CL1 and CL2 are the two extremes of the applied load capacitance. EXAMPLE: A crystal with the following parameters is used. With C1 = 0.025pF, C0 = 6pF, CL1 = 10pF, and CL2 = 20pF, the tuning range is Voltage-Controlled Crystal Oscillator (VCXO) f = The VCXO provides a tunable, low-jitter frequency reference for the rest of the FS6245 system components. Loading capacitance for the crystal is internal to the FS6245. No external components (other than the crystal resonator itself) are required for operation of the VCXO. Continuous fine-tuning of the VCXO frequency is accomplished by varying the voltage on the XTUNE pin. The oscillator operates the crystal resonator in the parallel-resonant mode. Crystal warping, or the "pulling" of the crystal oscillation frequency, is accomplished by altering the effective load capacitance presented to the crystal by the oscillator circuit. The actual amount that changing the load capacitance alters the oscillator frequency will be dependent on the characteristics of the crystal as well as the oscillator circuit itself. Specifically, the motional capacitance of the crystal (usually referred to by crystal manufacturers as C1), the static capacitance of the crystal (C0), and the load capacitance (CL) of the oscillator determine the "warping" or "pulling" capability of the crystal in the oscillator circuit. 0.025 x (20 - 10) x 106 = 300 ppm . 2 x (6 + 20) x (6 + 10 ) FS6245 Typical VCXO Deviation vs. XTUNE Input 250 Deviation from 13.500MHz - ppm 200 150 100 50 0 0 0.5 1 1.5 2 2.5 3 -50 -100 -150 -200 V(XTUNE) - volts 3 ISO9001 2.28.02 FS6245 Dual PLL VCXO Clock Generator IC 4.0 Electrical Specifications Table 3: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability. PARAMETER SYMBOL MIN. MAX. UNITS VDD VSS-0.5 7 V Input Voltage, dc VI VSS-0.5 VDD+0.5 V Output Voltage, dc VO VSS-0.5 VDD+0.5 V Input Clamp Current, dc (VI < 0 or VI > VDD) IIK -50 50 mA Output Clamp Current, dc (VI < 0 or VI > VDD) IOK -50 50 mA Storage Temperature Range (non-condensing) TS -65 150 C Ambient Temperature Range, Under Bias TA -55 125 C Junction Temperature TJ 125 C 260 C 2 kV Supply Voltage (VSS = ground) Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 4: Operating Conditions PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. MAX. UNITS V Core Supply Voltage (VDD) VDD 4.75 5 5.25 CLK Pin Supply Voltage (VDDO) VDDO 3.0 - VDD+0.3 V TA 0 70 C 18 MHz Ambient Operating Temperature Range Crystal Resonator Frequency fXTAL 5V 10% MIN. Fundamental Mode 5 13.5 Crystal Resonator Motional Capacitance C1(xtal) AT cut 25 fF Crystal Load Capacitance CL(xtal) AT cut 14 pF 4 ISO9001 2.28.02 FS6245 Dual PLL VCXO Clock Generator IC Table 5: DC Electrical Specifications Unless otherwise stated, VDD = 5V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are 3 from typical. Negative currents indicate current flows out of the device. PARAMETER SYMBOL Supply Current, Dynamic, with Loaded Outputs IDD CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Overall fXTAL = 13.5MHz; CL = 10pF 20 mA 14 pF Voltage Controlled Crystal Oscillator - VDD=5.0V Crystal Loading Capacitance CL(xtal) As seen by a crystal connected to XIN and XOUT (@ VXTUNE = 1.65V) Crystal Resonator Motional Capacitance C1(xtal) AT cut 25 fF VCXO Tuning Range fXTAL = 13.5MHz; CL(xtal) = 14pF; C1(xtal) = 25fF 300 ppm VCXO Tuning Characteristic Note: positive F for positive V 100 ppm/V Crystal Drive Level RXTAL=20; CL(xtal) = 14pF 200 uW IOH VO = 2.0V -40 mA mA Clock Outputs (CLKx) - VDDO=3.3V High-Level Output Source Current * Low-Level Output Sink Current * IOL VO = 0.4V 17 zOH VO = 0.5VDD; output driving high 30 zOL VO = 0.5VDD; output driving low 30 Short Circuit Source Current * IOSH VO = 0V; shorted for 30s, max. -55 mA Short Circuit Sink Current * IOSL VO = 3.3V; shorted for 30s, max. 55 mA IOH VO = 4.5V -30 mA mA Output Impedance * Clock Outputs (CLKx) - VDDO=5.0V High-Level Output Source Current * Low-Level Output Sink Current * IOL VO = 0.4V 26 zOH VO = 0.5VDD; output driving high 25 zOL VO = 0.5VDD; output driving low 25 Short Circuit Source Current * IOSH VO = 0V; shorted for 30s, max. -100 mA Short Circuit Sink Current * IOSL VO = 5V; shorted for 30s, max. 100 mA Output Impedance * 5 ISO9001 2.28.02 FS6245 Dual PLL VCXO Clock Generator IC Table 6: AC Timing Specifications Unless otherwise stated, VDD = 5V 10%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are 3 from typical. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Overall VCXO Stabilization Time * PLL Stabilization Time * tVCXOSTB tPLLSTB Output Frequency Synthesis Error From power valid 10 From VCXO stable 500 (unless otherwise noted in Frequency Table) ms us 0 ppm 55 % Clock Output (CLK) Ratio of high pulse width (as measured from rising edge to next falling edge at VDD/2) to one clock period Duty Cycle * 45 Jitter, Period (peak-peak) * tj(P) From rising edge to next rising edge at VDD/2, CL = 10pF 300 ps Jitter, Long Term (y()) * tj(LT) From 0-500s at VDD/2, CL = 10pF compared to ideal clock source 150 ps Rise Time * tr VDD = 5V; VDDO = 3.3V; VO = 0.3V to 3.0V; CL = 10pF 1.8 ns Fall Time * tf VDD = 5V; VDDO = 3.3V; VO = 0.3V to 3.0V; CL = 10pF 1.4 ns Rise Time * tr VDD = 5V; VDDO = 5.0V; VO = 0.5V to 4.5V; CL = 10pF 1.4 ns Fall Time * tf VDD = 5V; VDDO = 5.0V; VO = 4.5V to 0.5V; CL = 10pF 1.25 ns 6 ISO9001 2.28.02 FS6245 Dual PLL VCXO Clock Generator IC 5.0 Package Information Table 7: 20-pin SOIC (0.300") Package Dimensions DIMENSIONS INCHES MILLIMETERS MIN. MAX. MIN. MAX. A 0.0926 0.1043 2.35 2.65 A1 0.004 0.0118 0.10 0.30 B 0.013 0.020 0.33 0.51 C 0.0091 0.0125 0.23 0.32 D 0.4961 0.5118 12.60 13.00 E 0.2914 0.2992 7.40 7.60 e 0.05 BSC AMERICAN MICROSYSTEMS, INC. 1.27 BSC H 0.394 0.419 10.00 10.65 h 0.010 0.029 0.25 0.75 L 0.016 0.050 0.40 1.27 E H B A1 8 0 A c L D SEATING PLANE BASE PLANE 0 h x 45 e 8 Table 8: 20-pin SOIC (0.300") Package Characteristics PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS Thermal Impedance, Junction to Free-Air JA Air flow = 0 m/s 80 C/W Lead Inductance, Self L11 Center lead 2.5 nH Lead Inductance, Mutual L12 Center lead to any adjacent lead 0.85 nH Lead Capacitance, Bulk C11 Center lead to VSS 0.42 pF Lead Capacitance, Mutual C12 Center lead to any adjacent lead 0.08 pF 7 ISO9001 2.28.02 FS6245 Dual PLL VCXO Clock Generator IC 6.0 Ordering Information ORDERING CODE DEVICE NUMBER PACKAGE TYPE OPERATING TEMPERATURE RANGE SHIPPING CONFIGURATION 11640-223 FS6245-01 20-pin (0.300") SOIC (Small Outline Package) 0C to 70C (Commercial) Tape and Reel Copyright (c) 1998-2000 American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: tgp@amis.com 8 ISO9001 2.28.02