SY87700VZH - MICROCHIP TECHNOLOGY

SY87700V

Micrel, Inc.

M9999-073008

hbwhelp@micrel.com or (408) 955-1690 Rev.: L Amendment: /0

Issue Date: July 2008

FEATURES

SY87700V

■3.3V and 5V power supply options

■SONET/SDH/ATM compatible

■Clock and data recovery from 32Mbps up to

175Mbps NRZ data stream, clock generation from

32Mbps to 175Mbps

■Two on-chip PLLs: one for clock generation and

another for clock recovery

■Selectable reference frequencies

■Differential PECL high-speed serial I/O

■Line receiver input: no external buffering needed

■Link Fault indication

■100K ECL compatible I/O

■Complies with Bellcore, ITU/CCITT and ANSI

specifications such as OC-1, OC-3, FDDI, Fast

Ethernet, as well as proprietary applications

■Available in 32-pin EPAD-TQFP and 28-pin SOIC

packages (28-pin SOIC is available, but not

recommended for new designs, see page 2 for

details)

The SY87700V is a complete Clock Recovery and Data

Retiming integrated circuit for data rates from 32Mbps

up to 175Mbps NRZ. The device is ideally suited for

SONET/SDH/ATM applications and other high-speed data

transmission systems.

Clock recovery and data retiming is performed by

synchronizing the on-chip VCO directly to the incoming

data stream. The VCO center frequency is controlled by

the reference clock frequency and the selected divide

ratio. On-chip clock generation is performed through the

use of a frequency multiplier PLL with a byte rate source

as reference.

The SY87700V also includes a link fault detection

circuit.

Datasheets and support documentation can be found on

Micrel’s web site at: www.micrel.com.

5V/3.3V 32-175Mbps AnyRate®

CLOCK AND DATA RECOVERY

Use lower-power SY87700AL for 3.3V systems

APPLICATIONS

■SONET/SDH/ATM OC-1/OC-3

■Fast Ethernet

■Proprietary architectures up to 175Mbps

BLOCK DIAGRAM

PHASE

DETECTOR

PHASE/

FREQUENCY

DETECTOR CHARGE

PUMP VCO

CHARGE

PUMP VCO

LINK

FAULT

DETECTOR

DIVIDER

BY 8, 10, 16, 20

REFCLK

RDINN

RDINP

PLLR P/N

CLKSEL

RDOUTP

RCLKP

RCLKN

RDOUTN

LFIN

FREQSEL 1/2/3

PLLS P/N

DIVSEL 1/2

SY87700V

TCLKP

TCLKN

VCC

VCCA

VCCO

GND

(PECL)

(TTL)

(PECL)

(TTL)

(PECL)

(TTL) (TTL)

PHASE/

FREQUENCY

DETECTOR

AnyRate is a registered trademark of Micrel, Inc.

DESCRIPTION

AnyRate®

SY87700V

Micrel, Inc.

M9999-073008

hbwhelp@micrel.com or (408) 955-1690

PACKAGE/ORDERING INFORMATION

28-Pin SOIC (Z28-1)

RDINP

RDINN

FREQSEL1

REFCLK

FREQSEL2

FREQSEL3

RDOUTP

RDOUTN

VCCO

RCLKP

RCLKN

VCCO

TCLKP

TCLKN

910 11 12 13 14 15 16

CLKSEL

PLLRP

PLLRN

GND

GNDA

PLLSN

PLLSP

32 31 30 29 28 27 26 25

DIVSEL2

VCC

VCCA

LFIN

DIVSEL1

T op View

EPAD-TQFP

H32-1

32-Pin EPAD TQFP (H32-1)

Ordering Information(1)

Package Operating Package Lead

Part Number Type Range Marking Finish

SY87700VZC(3, 4) Z28-1 Commercial SY87700VZC Sn-Pb

SY87700VZCTR(2, 3, 4) Z28-1 Commercial SY87700VZC Sn-Pb

SY87700VHC(3) H32-1 Commercial SY87700VHC Sn-Pb

SY87700VHCTR(2, 3) H32-1 Commercial SY87700VHC Sn-Pb

SY87700VZH(3, 4) Z28-1 Commercial SY87700VZH with NiPdAu

Pb-Free bar line indicator Pb-Free

SY87700VZHTR(2, 3, 4) Z28-1 Commercial SY87700VZH with NiPdAu

Pb-Free bar line indicator Pb-Free

SY87700VHH(3) H32-1 Commercial SY87700VHH with NiPdAu

Pb-Free bar line indicator Pb-Free

SY87700VHHTR(2, 3) H32-1 Commercial SY87700VHH with NiPdAu

Pb-Free bar line indicator Pb-Free

Notes:

1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.

2. Tape and Reel.

3. Pb-Free package is recommended for new designs.

4. For optimum reliability, care should be taken when using the Z28-1 SOIC package to maintain

the package case temperature at or below 70°C.

PLLSP TCLKN1811

PLLSN CLKSEL1712

GND PLLRP1613

GND PLLRN1514

1VCCA

LFIN

DIVSEL1

RDINP

RDINN

FREQSEL1

REFCLK

FREQSEL2

FREQSEL3

N/C

28 VCC

DIVSEL2

RDOUTP

RDOUTN

VCCO

RCLKP

RCLKN

VCCO

TCLKP

T op View

SOIC

Z28-1

S28-1

SY87700V

Micrel, Inc.

M9999-073008

hbwhelp@micrel.com or (408) 955-1690

PIN DESCRIPTIONS

INPUTS

RDINP, RDINN [Serial Data Input] Differential PECL.

These built-in line receiver inputs are connected to the

differential receive serial data stream. An internal receive

PLL recovers the embedded clock (RCLK) and data

(RDOUT) information. The incoming data rate can be within

one of five frequency ranges depending on the state of the

FREQSEL pins. See

“Frequency Selection”

Table.

REFCLK [Reference Clock] TTL Inputs.

This input is used as the reference for the internal

frequency synthesizer and the “training” frequency for the

receiver PLL to keep it centered in the absence of data

coming in on the RDIN inputs.

CD [Carrier Detect] PECL Input.

This input controls the recovery function of the Receive

PLL and can be driven by the carrier detect output of optical

modules or from external transition detection circuitry. When

this input is HIGH the input data stream (RDIN) is recovered

normally by the Receive PLL. When this input is LOW the

data on the inputs RDIN will be internally forced to a constant

LOW, the data outputs RDOUT will remain LOW, the Link

Fault Indicator output LFIN forced LOW and the clock

recovery PLL forced to look onto the clock frequency

generated from REFCLK.

FREQSEL1, ..., FREQSEL3 [Frequency Select]

TTL

Inputs.

These inputs select the output clock frequency range as

shown in the “Frequency Selection” Table.

DIVSEL1, DIVSEL2 [Divider Select] TTL Inputs.

These inputs select the ratio between the output clock

frequency (RCLK/TCLK) and the REFCLK input frequency

as shown in the “Reference Frequency Selection” Table.

CLKSEL [Clock Select] TTL Inputs.

This input is used to select either the recovered clock of

the receiver PLL (CLKSEL = HIGH) or the clock of the

frequency synthesizer (CLKSEL = LOW) to the TCLK

outputs.

OUTPUTS

LFIN [Link Fault Indicator] TTL Output.

This output indicates the status of the input data stream

RDIN. Active HIGH signal is indicating when the internal

clock recovery PLL has locked onto the incoming data

stream. LFIN will go HIGH if CD is HIGH and RDIN is within

the frequency range of the Receive PLL (1000ppm). LFIN

is an asynchronous output.

RDOUTP, RDOUTN [Receive Data Output] Differential

PECL.

These ECL 100K outputs (+3.3V or +5V referenced)

represent the recovered data from the input data stream

(RDIN). This recovered data is specified against the rising

edge of RCLK.

RCLKP, RCLKN [Clock Output] Differential PECL.

These ECL 100K outputs (+3.3V or +5V referenced)

represent the recovered clock used to sample the recovered

data (RDOUT).

TCLKP, TCLKN [Clock Output] Differential PECL.

These ECL 100K outputs (+3.3V or +5V referenced)

represent either the recovered clock (CLKSEL = HIGH) used

to sample the recovered data (RDOUT) or the transmit clock

of the frequency synthesizer (CLKSEL = LOW).

PLLSP, PLLSN [Clock Synthesis PLL Loop Filter]

External loop filter pins for the clock synthesis PLL.

PLLRP, PLLRN [Clock Recovery PLL Loop Filter]

External loop filter pins for the receiver PLL.

POWER & GROUND

VCC Supply Voltage(1)

VCCA Analog Supply Voltage(1)

VCCO Output Supply Voltage(1)

GND Ground

N/C No Connect

Note 1. VCC, VCCA, VCCO must be the same value.

SY87700V

Micrel, Inc.

M9999-073008

hbwhelp@micrel.com or (408) 955-1690

FUNCTIONAL DESCRIPTION

Clock Recovery

Clock Recovery, as shown in the block diagram generates

a clock that is at the same frequency as the incoming data

bit rate at the Serial Data input. The clock is phase aligned

by a PLL so that it samples the data in the center of the

data eye pattern.

The phase relationship between the edge transitions of

the data and those of the generated clock are compared by

a phase/frequency detector. Output pulses from the detector

indicate the required direction of phase correction. These

pulses are smoothed by an integral loop filter. The output of

the loop filter controls the frequency of the Voltage Controlled

Oscillator (VCO), which generates the recovered clock.

Frequency stability without incoming data is guaranteed

by an alternate reference input (REFCLK) that the PLL locks

onto when data is lost. If the Frequency of the incoming

signal varies by greater than approximately 1000ppm with

respect to the synthesizer frequency, the PLL will be declared

out of lock, and the PLL will lock to the reference clock.

The loop filter transfer function is optimized to enable the

PLL to track the jitter, yet tolerate the minimum transition

density expected in a received SONET data signal. This

transfer function yields a 30µs data stream of continuous

1’s or 0’s for random incoming NRZ data.

The total loop dynamics of the clock recovery PLL

provides jitter tolerance which is better than the specified

tolerance in GR-253-CORE.

Lock Detect

The SY87700V contains a link fault indication circuit which

monitors the integrity of the serial data inputs. If the received

serial data fails the frequency test, the PLL will be forced to

lock to the local reference clock. This will maintain the correct

frequency of the recovered clock output under loss of signal

or loss of lock conditions. If the recovered clock frequency

deviates from the local reference clock frequency by more

than approximately 1000ppm, the PLL will be declared out

of lock. The lock detect circuit will poll the input data stream

in an attempt to reacquire lock to data. If the recovered

clock frequency is determined to be within approximately

1000ppm, the PLL will be declared in lock and the lock

detect output will go active.

SY87700V

Micrel, Inc.

M9999-073008

hbwhelp@micrel.com or (408) 955-1690

CHARACTERISTICS

Performance

The SY87700V PLL complies with the jitter specifications

proposed for SONET/SDH equipment defined by the Bellcore

Specifications: GR-253-CORE, Issue 2, December 1995 and

ITU-T Recommendations: G.958 document, when used with

differential inputs and outputs.

Input Jitter Tolerance

Input jitter tolerance is defined as the peak-to-peak

amplitude of sinusoidal jitter applied on the input signal that

causes an equivalent 1dB optical/electrical power penalty.

SONET input jitter tolerance requirement condition is the

input jitter amplitude which causes an equivalent of 1dB

power penalty.

Figure 1. Input Jitter Tolerance

OC/STS-N f0 f1 f2 f3 ft

Level (Hz) (Hz) (Hz) (kHz) (kHz)

3 10 30 300 6.5 65

1.5

0.40

f0 f1 f2 f4 ft

Sinusoidal Input

Jitter Amplitude

(UI p-p)

Frequency

-20dB/decade

Figure 2. Jitter Transfer

OC/STS-N fc P

Level (kHz) (dB)

3 130 0.1

0.1

-20

Jitter Transfer (dB)

Fre

uenc

-20dB/decade

Acceptable

Range

Jitter Transfer

Jitter transfer function is defined as the ratio of jitter on

the output OC-N/STS-N signal to the jitter applied on the

input OC-N/STS-N signal versus frequency. Jitter transfer

requirements are shown in Figure 2.

Jitter Generation

The jitter of the serial clock and serial data outputs shall

not exceed .01 U.I. rms when a serial data input with no

jitter is presented to the serial data inputs.

SY87700V

Micrel, Inc.

M9999-073008

hbwhelp@micrel.com or (408) 955-1690

FREQUENCY SELECTION TABLE(1)

FREQSEL1 FREQSEL2 FREQSEL3 fVCO/fRCLK fRCLK Data Rates (Mbps)

0 1 1 6 125 –175

1 0 0 8 94 – 157

1 0 1 12 63 – 104

1 1 0 16 47 – 78

1 1 1 24 32 – 52

01 0 —undefined

00X

(Note 2) —undefined

Note 1. SY87700V operates from 32-175MHz. For higher speed applications, the SY87701V operates from 35-1250MHz.

Note 2. X is a DON'T CARE.

REFERENCE FREQUENCY SELECTION

DIVSEL1 DIVSEL2 fRCLK/fREFCLK

00 8

01 10

10 16

11 20

LOOP FILTER COMPONENTS(1)

R5 C3

PLLSP PLLSN

Wide Range

R6 = 680Ω

C4 = 1.0µF (X7R Dielectric)

R6 C4

PLLRP PLLRN

Note 1. Suggested Values. Values may vary for different applications.

Wide Range

R5 = 350Ω

C3 = 1.0µF (X7R Dielectric)

SY87700V

Micrel, Inc.

M9999-073008

hbwhelp@micrel.com or (408) 955-1690

Symbol Rating Value Unit

VCC Power Supply Voltage –0.5 to +7.0 V

VIN Input Voltage –0.5 to VCC V

IOUT Output Current mA

– Continuous 50

– Surge 100

Tstore Storage Temperature –65 to +150 °C

TAOperating Temperature 0 to +85 °C

TCCase Temperature 0 to +70 °C

ABSOLUTE MAXIMUM RATINGS(1)

Note 1. Permanent device damage may occur if

“Absolute Maximum Ratings”

are exceeded. This is a stress rating only and functional operation is

not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to

“Absolute Maximum Ratings”

conditions for extended periods may affect device reliability.

Note 1. Case temperature not to exceed 70°C recommended for 28-pin

SOIC.

Note 2. 28-pin SOIC package is NOT recommended for new designs.

Note 3. Using JEDEC standard test boards with die attach pad soldered

to PCB. See www.amkor.com for additional package details.

PACKAGE THERMAL DATA(1)

Package(1, 2) 0 200 500

28-Pin SOIC(1, 2) 80 ——

32-Pin EP-TQFP(3) 27.6 22.6 20.7

θJA (°C/W) by Velocity (LFPM)

SY87700V

Micrel, Inc.

M9999-073008

hbwhelp@micrel.com or (408) 955-1690

Symbol Parameter Min. Typ. Max. Unit Condition

fVCO VCO Center Frequency 750 —1250 MHz fREFCLK × Byte Rate

∆fVCO VCO Center Freq. Tolerance —5—% Nominal

tACQ Acquisition Lock Time ——15 µs

tCPWH REFCLK Pulse Width HIGH 4 ——ns

tCPWL REFCLK Pulse Width LOW 4 ——ns

tir REFCLK Input Rise Time —0.5 2 ns

tODC Output Duty Cycle (RCLK/TCLK) 45 —55 % of UI

trECL Output Rise/Fall Time 100 —500 ps 50Ω to VCC –2V

tf(20% to 80%)

tSKEW Recovered Clock Skew –200 —+200 ps

tDV Data Valid 1/(2×fRCLK) – 200 ——ps

tDH Data Hold 1/(2×fRCLK) – 200 ——ps

Symbol Parameter Min. Typ. Max. Unit Condition

VCC Power Supply Voltage 3.15 3.3 3.45 V

4.75 5.0 5.25 V

ICC Power Supply Current —170 230 mA

DC ELECTRICAL CHARACTERISTICS

Symbol Parameter Min. Typ. Max. Unit Condition

VIH Input HIGH Voltage VCC –1.165 —VCC –0.880 V

VIL Input LOW Voltage VCC –1.810 —VCC –1.475 V

VOH Output HIGH Voltage VCC –1.075 —VCC –0.830 V 50Ω to VCC –2V

VOL Output LOW Voltage VCC –1.860 —VCC –1.570 V 50Ω to VCC –2V

IIL Input LOW Current 0.5 ——µAV

IN = VIL(Min.)

VCC = VCCO = VCCA = 3.3V ±5% or 5.0V ±5%, TA = 0°C to + 85°C.

PECL 100K DC ELECTRICAL CHARACTERISTICS

Symbol Parameter Min. Typ. Max. Unit Condition

VIH Input HIGH Voltage 2.0 —VCC V

VIL Input LOW Voltage ——0.8 V

VOH Output HIGH Voltage 2.0 ——VI

OH = –0.4mA

VOL Output LOW Voltage ——0.5 V IOL = 4mA

IIH Input HIGH Current –125 ——µAV

IN = 2.7V, VCC = Max.

——+100 µAV

IN = VCC, VCC = Max.

IIL Input LOW Current –300 ——µAV

IN = 0.5V, VCC = Max.

IOS Output Short Circuit Current –15 —–100 mA VOUT = 0V (maximum 1sec)

VCC = VCCO = VCCA = 3.3V ±5% or 5.0V ±5%, TA = 0°C to + 85°C for 32-TQFP, TC = 0°C to 70°C for SOIC.

TTL DC ELECTRICAL CHARACTERISTICS

VCC = VCCO = VCCA = 3.3V ±5% or 5.0V ±5%, TA = 0°C to + 85°C for 32-TQFP, TC = 0°C to 70°C for SOIC.

AC ELECTRICAL CHARACTERISTICS

VCC = VCCO = VCCA = 3.3V ±5% or 5.0V ±5%, TA = 0°C to + 85°C for 32-TQFP, TC = 0°C to 70°C for SOIC.

SY87700V

Micrel, Inc.

M9999-073008

hbwhelp@micrel.com or (408) 955-1690

TIMING WAVEFORMS

tCPWL tCPWH

RDOUT

RCLK

REFCLK

tODC tODC

tSKEW

tDV tDH

SY87700V

Micrel, Inc.

M9999-073008

hbwhelp@micrel.com or (408) 955-1690

32-PIN APPLICATION EXAMPLE

RDINP

RDINN

FREQSEL1

REFCLK

FREQSEL2

FREQSEL3

RDOUTP

RDOUTN

VCCO

RCLKP

RCLKN

VCCO

TCLKP

TCLKN

910 11 12 13 14 15 16

CLKSEL

PLLRP

PLLRN

VEE

VEEA

PLLSN

PLLSP

32 31 30 29 28 27 26 25

DIVSEL2

VCC

VCCA

LFIN

DIVSEL1

SW1

VCC

R12

2N2222A

LED

VEE

R1 C1

DIODE

1N4148

R10

R11

1kΩ

DIVSEL2

DIVSEL1

CLKSEL

VEE

R13

VCC

Ferrite Bead

BLM21A102

22 F C6

0.1 F C7

6.8 F C8

6.8 F C9

6.8 F

GND

VCCO (+2V)

C11

0.1 F C13

0.1 F C15

0.1 F

C12

0.01 F C14

0.01 F C16

0.01 F

C10

6.8 F C17

0.1 F C18

0.01 F

VEE

C19

1.0 F C20

0.1 F C21

0.01 F

VCC (+2V)

VCCA (+2V)

VEE (—3V)

VEEA (—3V)

GND

C1 = C2 = 1.0µF

R1 = 350Ω

R2 = 680Ω

R3 through R10 = 5kΩ

R12 = 12kΩ

R13 = 130Ω

Note:

C3, C4 are optional

SY87700V

Micrel, Inc.

M9999-073008

hbwhelp@micrel.com or (408) 955-1690

28-PIN APPLICATION EXAMPLE

SW1

GND

123456

DIVSEL1

VCC

RDOUTP

DIVSEL2

RDINP

LFIN

RDINN

VCCA

FREQSEL1

REFCLK

RDOUTN

VCCO

RCLKP

RCLKN

FREQSEL2

PLLSP

PLLSN

N/C

FREQSEL3 VCCO

TCLKP

TCLKN

CLKSEL

13 16

GND PLLRP

14 15

GND PLLRN

80Ω

1.5 F

GND

R6 50‰

1.0 F

VCC

GND

R2R1

R3 R4

0.1 F

22 F

0.1 F

22 F

Ferrite Bead

BLM21A102

FB1

(R17 - R22)

5kΩ x 6

Diode D1

1N4148

C14

0.1 F

C15

C16

C17

C18

C19

0.1 F

R11

R12

R13

R14

R15

R16

Capacitor Pads

(1206 format)

RDIN

0.1 F C13

120ΩR21

VCC

DPDT

Slide Switch

REFCLK

(TTL)

LOOP FILTER

NETWORK

VCC Stand Off

1kΩ

XTAL

Oscillator

If VCC = +3.3V:

R9 through R14 = 220

Ω

See Table 1

J1 VCC

130Ω

LED

GND

Pin 1 (VCCA)

Pin 28 (VCC)

Pin 23 (VCCO)

Pin 20 (VCCO)

C10

C11

C12

0.1 F

VCC

If VCC = +5V:

R9 through R14 = 33

0ΩΩ

For AC-Coupling Only

when VCC = +5V when VCC = +3.3V

C1 = C2 = 0.1µF C1 = C2 = 0.1µF

R1 = R2 = 1.2kΩR1 = R2 = 680Ω

R3 = R4 = 3.4kΩR3 = R4 = 1kΩ

Table 1.

For DC Mode Only

when VCC = +5V when VCC = +3.3V

C1 = C2 = Shorted C1 = C2 = Shorted

R1 = R2 = 82ΩR1 = R2 = 130Ω

R3 = R4 = 130ΩR3 = R4 = 82Ω

Note 1. C5 and C10–C12 are decoupling capacitors and should be kept

as close to the power pins as possible.

SY87700V

Micrel, Inc.

M9999-073008

hbwhelp@micrel.com or (408) 955-1690

BILL OF MATERIALS (32-PIN EPAD-TQFP)

Item Part Number Manufacturer Description Qty.

C1, C2 VJ0603Y105JXJAT Vishay 1.0µF Ceramic Capacitor, Size 1206 2

X7R Dielectric, Loop Filter, Critical

C3, C4 VJ0603Y105JXJAT Vishay 1.0µF Ceramic Capacitor, Size 1206 2

X7R Dielectric, Loop Filter, Optional

C5 ECS-T1ED226R Panasonic 22µF Tantalum Electrolytic Capacitor, Size D 1

C6 ECU-V1H104KBW Panasonic 0.1µF Ceramic Capacitor, Size 1206 1

X7R Dielectric, Power Supply Decoupling

C7, C8, C9, C10 ECS-T1EC685R Panasonic 6.8µF Tantalum Electrolytic Capacitor, Size C 4

C19 ECJ-3YB1E105K Panasonic 1.0µF Ceramic Capacitor, Size 1206 1

X7R Dielectric, VEEA Decoupling

C11, C13 ECU-V1H104KBW Panasonic 0.1µF Ceramic Capacitor, Size 1206 1

X7R Dielectric, VCCO/VCC Decoupling

C15, C17 ECU-V1H104KBW Panasonic 0.1µF Ceramic Capacitor, Size 1206 1

X7R Dielectric, VCCA/VEEA Decoupling

C20 ECU-V1H104KBW Panasonic 0.1µF Ceramic Capacitor, Size 1206 1

X7R Dielectric, VEEA Decoupling

C12, C14 ECU-V1H103KBW Panasonic 0.01µF Ceramic Capacitor, Size 1206 1

X7R Dielectric, VCCO/VCC Decoupling

C16, C18 ECU-V1H103KBW Panasonic 0.01µF Ceramic Capacitor, Size 1206 1

X7R Dielectric, VCCA/VEEA Decoupling

C21 ECU-V1H103KBW Panasonic 0.01µF Ceramic Capacitor, Size 1206 1

X7R Dielectric, VEEA Decoupling

D1 1N4148 Diode 1

D2 P300-ND/P301-ND Panasonic T-1 3/4 Red LED 1

J1, J2, J3, J4, J5 142-0701-851 Johnson Gold Plated, Jack, SMA, PCB Mount 12

J6, J7, J8, J9, Components

J10, J11, J12

L1, L2, L3 BLM21A102F Murata Ferrite Beads, Power Noise Suppression 3

Q1 NTE123A NTE 2N2222A Buffer/Driver Transistor, NPN 1

R1 350Ω Resistor, 2%, Size 0402 1

Loop Filter Component, Critical

R2 680Ω Resistor, 2%, Size 0402 1

Loop Filter Component, Critical

R3, R4, R5, R6 5kΩ Pullup Resistors, 2%, Size 1206 8

R7, R8, R9, R10

R11 1kΩ Pulldown Resistor, 2%, Size 1206 1

R12 12kΩ Resistor, 2%, Size 1206 1

R13 130Ω Pullup Resistor, 2%, Size 1206 1

SW1 206-7 CTS SPST, Gold Finish, Sealed Dip Switch 1

SY87700V

Micrel, Inc.

M9999-073008

hbwhelp@micrel.com or (408) 955-1690

28 LEAD SOIC .300" WIDE (Z28-1)

Rev. 02

Note:

The 28 Lead SOIC package is NOT recommended for new designs.

SY87700V

Micrel, Inc.

M9999-073008

hbwhelp@micrel.com or (408) 955-1690

32 LEAD EPAD TQFP (DIE UP) (H32-1)

Package

EP- Exposed Pad

Die

CompSide Island

Heat Dissipation

Heavy Copper Plane

Heat Dissipation

PCB Thermal Consideration for 32-Pin EPAD-TQFP Package

SY87700V

Micrel, Inc.

M9999-073008

hbwhelp@micrel.com or (408) 955-1690

APPENDIX A

Layout and General Suggestions

1. Establish controlled impedance stripline, microstrip, or co-planar construction techniques.

2. Signal paths should have, approximately, the same width as the device pads.

3. All differential paths are critical timing paths, where skew should be matched to within ±10ps.

4. Signal trace impedance should not vary more than ±5%. If in doubt, perform TDR analysis of all high-speed signal

traces.

5. Maintain compact filter networks as close to filter pins as possible. Provide ground plane relief under filter path to

reduce stray capacitance. Be careful of crosstalk coupling into the filter network.

6. Maintain low jitter on the REFCLK input. Isolate the XTAL oscillator from power supply noise by adequately

decoupling. Keep XTAL oscillator close to device, and minimize capacitive coupling from adjacent signals.

7. Higher speed operation may require use of fundamental-tone (third-overtone typically have more jitter) crystal based

oscillator for optimum performance. Evaluate and compare candidates by measuring TXCLK jitter.

8. All unused outputs must be terminated. To conserve power, unused PECL outputs can be terminated with a 1kΩ

resistor to VEE.

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