LMC6572, LMC6574 www.ti.com SNOS707D - DECEMBER 1996 - REVISED MARCH 2013 LMC6572/LMC6574 Dual and Quad Low Voltage (2.7V and 3V) Operational Amplifier Check for Samples: LMC6572, LMC6574 FEATURES DESCRIPTION * * * Low voltage operation and low power dissipation make the LMC6574/2 ideal for battery-powered systems. 1 2 * * * * * * (Typical Unless Otherwise Noted) Guaranteed 2.7V and 3V Performance Rail-to-Rail Output Swing (Within 5 mV of Supply Rail, 100 k Load) Ultra-Low Supply Current: 40 A/Amplifier Low Cost Ultra-Low Input Current: 20 fA High Voltage Gain @ VS=2.7V, RL=100 k: 120 dB Specified for 100 k and 5 k Loads Available in VSSOP Package APPLICATIONS * * * * * * Transducer Amplifier Portable or Remote Equipment Battery-Operated Instruments Data Acquisition Systems Medical Instrumentation Improved Replacement for TLV2322 and TLV2324 3V amplifier performance is backed by 2.7V guarantees to ensure operation throughout battery lifetime. These guarantees also enable analog circuits to operate from the same 3.3V supply used for digital logic. Battery life is maximized because each amplifier dissipates only micro-watts of power. The LMC6574/2 does not sacrifice functionality for low voltage operation. The LMC6574/2 generates 120 dB of open-loop gain just like a conventional amplifier, but the LMC6574/2 can do this from a 2.7V supply. These amplifiers are designed with features that optimize low voltage operation. The output voltage swings rail-to-rail to maximize signal-to-noise ratio and dynamic signal range. The common-mode input voltage range extends from 800 mV below the positive supply to 100 mV below ground. This device is built with Texas Instruments' advanced Double-Poly Silicon-Gate CMOS process. LMC6572 is also available in VSSOP package which is almost half the size of a SOIC-8 device. Connection Diagram Figure 1. 8-Pin PDIP/SOIC/VSSOP Package See Package Number P, D, or DGK 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1996-2013, Texas Instruments Incorporated LMC6572, LMC6574 SNOS707D - DECEMBER 1996 - REVISED MARCH 2013 www.ti.com Figure 2. 14-Pin PDIP/SOIC Package See Package Number NFF or D These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) ESD Tolerance (3) 2000V Differential Input Voltage Supply Voltage (V+) +0.3V, (V-) -0.3V Voltage at Input/Output Pin Supply Voltage (V+ - V-) 12V Current at Input Pin 5 mA Current at Output Pin (4) 10 mA Current at Power Supply Pin 35 mA Lead Temperature (Soldering, 10 Seconds) 260C -65C to +150C Storage Temperature Range Junction Temperature (5) (1) (2) (3) (4) (5) 150C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human body model, 1.5 k in series with 100 pF. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150C. The maximum power dissipation is a function of TJ(Max), JA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(Max) - TA)/JA. All numbers apply for packages soldered directly into a PC board. Operating Ratings (1) 2.7V V+ 11V Supply Voltage Junction Temperature Range Thermal Resistance (JA) LMC6572AI, LMC6572BI -40C TJ +85C LMC6574AI, LMC6574BI -40C TJ +85C P Package, 8-Pin PDIP 115C/W D Package, 8-Pin SOIC 193C/W DGK Package, 8-Pin VSSOP 217C/W NFF Package, 14-Pin PDIP 81C/W D Package, 14-Pin SOIC (1) 2 126C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics. Submit Documentation Feedback Copyright (c) 1996-2013, Texas Instruments Incorporated Product Folder Links: LMC6572 LMC6574 LMC6572, LMC6574 www.ti.com SNOS707D - DECEMBER 1996 - REVISED MARCH 2013 2.7V DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25C. V+ = 2.7V, V- = 0V, VCM = VO = V+/2 and RL > 1M. Boldface limits apply at the temperature extremes. Symbol VOS Parameter Input Offset Voltage Conditions V+ = 2.7V and 3V Typ (1) 0.5 TCVOS Input Offset Voltage Average Drift 1.5 IB Input Current 0.02 IOS Input Offset Current Input Resistance CIN Common-Mode Input Capacitance CMRR Common Mode Rejection Ratio 0V VCM 3.5V V+ = 5V Positive Power Supply Rejection Ratio 2.7V V+ 5V, V- = 0V Negative Power Supply Rejection Ratio -2.7V V- -5V, V+ = 0V Input Common-Mode Voltage Range V+ = 2.7V and 3V for CMRR 50 dB -PSRR VCM 3 7 mV 3.5 7.5 Max V/C pA 10 10 Max 6 6 Max pA Tera 3 pF 75 63 60 dB 60 57 Min 67 60 dB 65 58 Min 75 67 dB 73 65 Min -0.05 -0.05 V 0 0 Max V+ - 1.0 V+ - 1.0 V 75 83 -0.1 + V - 1.3 VO Large Signal Voltage Gain Output Swing RL = 100 k (3) + V = 2.7V RL = 100 k to V+/2 V+ = 2.7V RL = 5 k to V+/2 Min V/mV Sinking 500 V/mV 2.695 2.66 2.995 0.005 V+ = 3V RL = 5 k to V+/2 V - 1.3 1000 0.04 V+ = 3V RL = 100 k to V+/2 + Sourcing 0.005 2.96 0.04 (1) (2) (3) Units >1 V+ - 0.8 AV LMC6574BI LMC6572BI Limit (2) 0.01 RIN +PSRR LMC6574AI LMC6572AI Limit (2) 2.68 2.65 V 2.66 2.62 Min 0.03 0.06 V 0.05 0.09 Max 2.55 2.45 V 2.45 2.35 Min 0.15 0.25 V 0.25 0.35 Max 2.98 2.95 V 2.96 2.93 Min 0.03 0.06 V 0.05 0.09 Max 2.85 2.75 V 2.75 2.65 Min 0.15 0.25 V 0.25 0.35 Max Typical values represent the most likely parametric norm. All limits are guaranteed by testing or statistical analysis. V+ = 3V, VCM = 1.5V and RL connected to 1.5V. For Sourcing tests, 1.5V VO 2.5V. For Sinking tests, 0.5V VO 1.5V. Copyright (c) 1996-2013, Texas Instruments Incorporated Product Folder Links: LMC6572 LMC6574 Submit Documentation Feedback 3 LMC6572, LMC6574 SNOS707D - DECEMBER 1996 - REVISED MARCH 2013 www.ti.com 2.7V DC Electrical Characteristics (continued) Unless otherwise specified, all limits guaranteed for TJ = 25C. V+ = 2.7V, V- = 0V, VCM = VO = V+/2 and RL > 1M. Boldface limits apply at the temperature extremes. Symbol ISC Parameter Output Short Circuit Current IS Supply Current Conditions Sourcing, VO = 0V Typ (1) LMC6574AI LMC6572AI Limit (2) LMC6574BI LMC6572BI Limit (2) 6.0 4.0 3.0 mA 3.0 2.0 Min 2.5 mA Min Units Sinking, VO = 2.7V 4.0 3.0 2.0 1.5 Quad Package V+ = +2.7V, VO = V+/2 160 240 240 A 280 280 Max Quad Package V+ = +3V, VO = V+/2 160 240 240 A 280 280 Max Dual Package V+ = +2.7V, VO = V+/2 80 120 120 A 140 140 Max Dual Package V+ = +3V, VO = V+/2 80 120 120 A 140 140 Max 2.7V AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25C, V+ = 2.7V, V- = 0V, VCM = VO = V+/2 and RL > 1 M. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions SR Slew Rate V+ = 2.7V and 3V (3) GBW Gain-Bandwidth Product V+ = 3V m Gm Typ (1) LMC6574AI LMC6572AI Limit (2) LMC6574BI LMC6572BI Limit (2) Units 90 30 30 V/ms 10 10 MHz Phase Margin 60 Deg Gain Margin 12 dB (4) 120 dB Amp-to-Amp Isolation See en Input-Referred Voltage Noise F = 1 kHz VCM = 1V 45 in Input-Referred Current Noise F = 1 kHz 0.002 T.H.D. Total Harmonic Distortion F = 10 kHz, AV = -2 RL = 10 k, VO = 1.0 VPP 0.05 (1) (2) (3) (4) 4 Min 0.22 nV/Hz pA/Hz % Typical values represent the most likely parametric norm. All limits are guaranteed by testing or statistical analysis. Connected as Voltage Follower with 1.0V step input. Number specified is the slower of the positive and negative slew rates. Input referred, V+ = 3V and RL = 100 k connected to 1.5V. Each amp excited in turn with 1 KHz to produce VO = 2 VPP. Submit Documentation Feedback Copyright (c) 1996-2013, Texas Instruments Incorporated Product Folder Links: LMC6572 LMC6574 LMC6572, LMC6574 www.ti.com SNOS707D - DECEMBER 1996 - REVISED MARCH 2013 Typical Performance Characteristics VS = +3V, TA = 25C, Unless otherwise specified Supply Current vs Supply Voltage (Dual Package) Input Current vs Temperature Figure 3. Figure 4. Sourcing Current vs Output Voltage Sinking Current vs Output Voltage Figure 5. Figure 6. Output Voltage Swing vs Supply Voltage Input Voltage Noise vs Frequency Figure 7. Figure 8. Copyright (c) 1996-2013, Texas Instruments Incorporated Product Folder Links: LMC6572 LMC6574 Submit Documentation Feedback 5 LMC6572, LMC6574 SNOS707D - DECEMBER 1996 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = +3V, TA = 25C, Unless otherwise specified 6 Crosstalk Rejection vs Frequency Positive PSRR vs Frequency Figure 9. Figure 10. Negative PSRR vs Frequency CMRR vs Frequency Figure 11. Figure 12. Input Voltage vs Output Voltage (VS = 1.5) Open Loop Frequency Response Figure 13. Figure 14. Submit Documentation Feedback Copyright (c) 1996-2013, Texas Instruments Incorporated Product Folder Links: LMC6572 LMC6574 LMC6572, LMC6574 www.ti.com SNOS707D - DECEMBER 1996 - REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = +3V, TA = 25C, Unless otherwise specified Open Loop Frequency Response vs Temperature Maximum Output Swing vs Frequency Figure 15. Figure 16. ZOUT vs Frequency Slew Rate vs Supply Voltage Figure 17. Figure 18. Non-Inverting Large Signal Pulse Response Non-Inverting Small Signal Pulse Response Figure 19. Figure 20. Copyright (c) 1996-2013, Texas Instruments Incorporated Product Folder Links: LMC6572 LMC6574 Submit Documentation Feedback 7 LMC6572, LMC6574 SNOS707D - DECEMBER 1996 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = +3V, TA = 25C, Unless otherwise specified 8 Inverting Large Signal Pulse Response Inverting Small Signal Pulse Response Figure 21. Figure 22. Stability vs Capacitive Load Stability vs Capacitive Load Figure 23. Figure 24. Stability vs Capacitive Load Stability vs Capacitive Load Figure 25. Figure 26. Submit Documentation Feedback Copyright (c) 1996-2013, Texas Instruments Incorporated Product Folder Links: LMC6572 LMC6574 LMC6572, LMC6574 www.ti.com SNOS707D - DECEMBER 1996 - REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = +3V, TA = 25C, Unless otherwise specified Bandwidth vs Capacitive Load Capacitive Load vs Phase Margin Figure 27. Figure 28. Capacitive Load vs Gain Margin Figure 29. Copyright (c) 1996-2013, Texas Instruments Incorporated Product Folder Links: LMC6572 LMC6574 Submit Documentation Feedback 9 LMC6572, LMC6574 SNOS707D - DECEMBER 1996 - REVISED MARCH 2013 www.ti.com APPLICATIONS HINTS LOW VOLTAGE AMPLIFIER TOPOLOGY The LMC6574/2 incorporates a novel op-amp design topology that enables it to maintain rail-to-rail output swing even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage is taken directly from the internal integrator, which provides both low output impedance and large gain. Special feed-forward compensation design techniques are incorporated to maintain stability over a wider range of operating conditions than traditional micropower op-amps. These features make the LMC6574/2 both easier to design with, and provide higher speed than products typically found in this ultra-low power class. COMPENSATING FOR INPUT CAPACITANCE It is quite common to use large values of feedback resistance for amplifiers with ultra-low input current, like the LMC6574/2. Although the LMC6574/2 is highly stable over a wide range of operating conditions, a large feedback resistor will react even with small values of capacitance at the input of the op-amp to reduce phase margin. The capacitance at the input of the op-amp comes from transducers, photodiodes and circuit board parasitics. The effect of input capacitance can be compensated for by adding a capacitor, Cf, around the feedback resistors (as in Figure 30) such that: (1) or R1 CIN R2 Cf (2) Since it is often difficult to know the exact value of CIN, Cf can be experimentally adjusted so that the desired pulse response is achieved. Refer to the LMC660 and LMC662 for a more detailed discussion on compensating for input capacitance. When high input impedances are demanded, guarding of the LMC6574/2 is suggested. Guarding input lines will not only reduce leakage, but lowers stray input capacitance as well. (See PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK Figure 30. Cancelling the Effect of Input Capacitance CAPACITIVE LOAD TOLERANCE Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created by the combination of the op-amp's output impedance and the capacitive load. This pole induces phase lag at the unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response. With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 31. 10 Submit Documentation Feedback Copyright (c) 1996-2013, Texas Instruments Incorporated Product Folder Links: LMC6572 LMC6574 LMC6572, LMC6574 www.ti.com SNOS707D - DECEMBER 1996 - REVISED MARCH 2013 Figure 31. LMC6574/2 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads In the circuit of Figure 31, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the overall feedback loop. PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LMC6574/2, typically less than 20 fA, it is essential to have an excellent layout. Fortunately, the techniques of obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination, the surface leakage will be appreciable. To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6574/2's inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the opamp's inputs, as in Figure 32. To have a significant effect, guard rings should be placed on both the top and bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier inputs, since no leakage current can flow between two points at the same potential. For example, a PC board trace-to-pad resistance of 1012, which is normally considered a very large resistance, could leak 5 pA if the trace were a 5V bus adjacent to the pad of the input. This would cause a 250 times degradation from the LMC6574/2's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance of 1011 would cause only 0.05 pA of leakage current. See Figure 35 for typical connections of guard rings for standard op-amp configurations. Figure 32. Example of Guard Ring in P.C. Board Layout Copyright (c) 1996-2013, Texas Instruments Incorporated Product Folder Links: LMC6572 LMC6574 Submit Documentation Feedback 11 LMC6572, LMC6574 SNOS707D - DECEMBER 1996 - REVISED MARCH 2013 www.ti.com Figure 33. Inverting Amplifier Figure 34. Non-Inverting Amplifier Follower Figure 35. Typical Connections of Guard Rings The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 36. (Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board). Figure 36. Air Wiring 12 Submit Documentation Feedback Copyright (c) 1996-2013, Texas Instruments Incorporated Product Folder Links: LMC6572 LMC6574 LMC6572, LMC6574 www.ti.com SNOS707D - DECEMBER 1996 - REVISED MARCH 2013 SPICE MACROMODEL A * * * * * spice macromodel is available for the LMC6574/2. This model includes accurate simulation of: input common-mode voltage range frequency and transient response GBW dependence on loading conditions quiescent and dynamic supply current output swing dependence on loading conditions and many more characteristics as listed on the macromodel disk. Contact your local Texas Instruments sales office to obtain an operational amplifier spice model library disk. Typical Single-Supply Applications Figure 37. Low-Power Two-Op-Amp Instrumentation Amplifier Figure 38. Sample and Hold Figure 39. 1 Hz Square Wave Oscillator Copyright (c) 1996-2013, Texas Instruments Incorporated Product Folder Links: LMC6572 LMC6574 Submit Documentation Feedback 13 LMC6572, LMC6574 SNOS707D - DECEMBER 1996 - REVISED MARCH 2013 www.ti.com Figure 40. Adder/Subtractor Circuit Figure 41. Low Pass Filter 14 Submit Documentation Feedback Copyright (c) 1996-2013, Texas Instruments Incorporated Product Folder Links: LMC6572 LMC6574 LMC6572, LMC6574 www.ti.com SNOS707D - DECEMBER 1996 - REVISED MARCH 2013 REVISION HISTORY Changes from Revision C (March 2013) to Revision D * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 14 Copyright (c) 1996-2013, Texas Instruments Incorporated Product Folder Links: LMC6572 LMC6574 Submit Documentation Feedback 15 PACKAGE OPTION ADDENDUM www.ti.com 15-Aug-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMC6572AIM/NOPB LIFEBUY SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC65 72AIM LMC6572AIMX/NOPB LIFEBUY SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC65 72AIM LMC6572BIM/NOPB LIFEBUY SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC65 72BIM LMC6572BIMX/NOPB LIFEBUY SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC65 72BIM LMC6574AIM/NOPB LIFEBUY SOIC D 14 55 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC6574 AIM LMC6574AIMX LIFEBUY SOIC D 14 2500 TBD Call TI Call TI -40 to 85 LMC6574 AIM LMC6574AIMX/NOPB LIFEBUY SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC6574 AIM LMC6574BIM/NOPB LIFEBUY SOIC D 14 55 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC6574 BIM LMC6574BIMX/NOPB LIFEBUY SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC6574 BIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 15-Aug-2017 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMC6572AIMX/NOPB SOIC D LMC6572BIMX/NOPB SOIC LMC6574AIMX SOIC LMC6574AIMX/NOPB LMC6574BIMX/NOPB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 5.4 2.0 8.0 12.0 Q1 8 2500 330.0 12.4 6.5 D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC6572AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC6572BIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC6574AIMX SOIC D 14 2500 367.0 367.0 35.0 LMC6574AIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0 LMC6574BIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI's published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyers and others who are developing systems that incorporate TI products (collectively, "Designers") understand and agree that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products used in or for Designers' applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will thoroughly test such applications and the functionality of such TI products as used in such applications. TI's provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, "TI Resources") are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer's company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice. TI's provision of TI Resources does not expand or otherwise alter TI's applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED "AS IS" AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers' own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer's noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2017, Texas Instruments Incorporated Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: LMC6572AIM LMC6572AIM/NOPB LMC6572AIMX LMC6572AIMX/NOPB LMC6572BIM LMC6572BIM/NOPB LMC6572BIMX LMC6572BIMX/NOPB LMC6574AIM LMC6574BIM LMC6574BIMX