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SNOS707D –DECEMBER 1996–REVISED MARCH 2013
LMC6572/LMC6574 Dual and Quad Low Voltage (2.7V and 3V) Operational Amplifier
Check for Samples: LMC6572,LMC6574
1FEATURES DESCRIPTION
Low voltage operation and low power dissipation
2• (Typical Unless Otherwise Noted) make the LMC6574/2 ideal for battery-powered
• Guaranteed 2.7V and 3V Performance systems.
• Rail-to-Rail Output Swing (Within 5 mV of 3V amplifier performance is backed by 2.7V
Supply Rail, 100 kΩLoad) guarantees to ensure operation throughout battery
• Ultra-Low Supply Current: 40 μA/Amplifier lifetime. These guarantees also enable analog circuits
to operate from the same 3.3V supply used for digital
• Low Cost logic.
• Ultra-Low Input Current: 20 fA Battery life is maximized because each amplifier
• High Voltage Gain @ VS=2.7V, dissipates only micro-watts of power.
RL=100 kΩ: 120 dB
• Specified for 100 kΩand 5 kΩLoads The LMC6574/2 does not sacrifice functionality for
low voltage operation. The LMC6574/2 generates
• Available in VSSOP Package 120 dB of open-loop gain just like a conventional
amplifier, but the LMC6574/2 can do this from a 2.7V
APPLICATIONS supply.
• Transducer Amplifier These amplifiers are designed with features that
• Portable or Remote Equipment optimize low voltage operation. The output voltage
• Battery-Operated Instruments swings rail-to-rail to maximize signal-to-noise ratio
and dynamic signal range. The common-mode input
• Data Acquisition Systems voltage range extends from 800 mV below the
• Medical Instrumentation positive supply to 100 mV below ground.
• Improved Replacement for TLV2322 and This device is built with Texas Instruments' advanced
TLV2324 Double-Poly Silicon-Gate CMOS process.
LMC6572 is also available in VSSOP package which
is almost half the size of a SOIC-8 device.
Connection Diagram
Figure 1. 8-Pin PDIP/SOIC/VSSOP Package
See Package Number P, D, or DGK
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1996–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMC6572, LMC6574
SNOS707D –DECEMBER 1996–REVISED MARCH 2013
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Figure 2. 14-Pin PDIP/SOIC Package
See Package Number NFF or D
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
ESD Tolerance(3) 2000V
Differential Input Voltage ±Supply Voltage
Voltage at Input/Output Pin (V+) +0.3V, (V−)−0.3V
Supply Voltage (V+−V−) 12V
Current at Input Pin ±5 mA
Current at Output Pin(4) ±10 mA
Current at Power Supply Pin 35 mA
Lead Temperature (Soldering, 10 Seconds) 260°C
Storage Temperature Range −65°C to +150°C
Junction Temperature(5) 150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human body model, 1.5 kΩin series with 100 pF.
(4) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
(5) The maximum power dissipation is a function of TJ(Max),θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(Max) −TA)/θJA. All numbers apply for packages soldered directly into a PC board.
Operating Ratings(1)
Supply Voltage 2.7V ≤V+≤11V
Junction Temperature Range LMC6572AI, LMC6572BI −40°C ≤TJ≤+85°C
LMC6574AI, LMC6574BI −40°C ≤TJ≤+85°C
Thermal Resistance (θJA) P Package, 8-Pin PDIP 115°C/W
D Package, 8-Pin SOIC 193°C/W
DGK Package, 8-Pin VSSOP 217°C/W
NFF Package, 14-Pin PDIP 81°C/W
D Package, 14-Pin SOIC 126°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test
conditions, see the Electrical Characteristics.
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SNOS707D –DECEMBER 1996–REVISED MARCH 2013
2.7V DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25°C. V+= 2.7V, V−= 0V, VCM = VO= V+/2 and RL> 1MΩ.Boldface
limits apply at the temperature extremes.
Symbol Parameter Conditions Typ(1) LMC6574AI LMC6574BI Units
LMC6572AI LMC6572BI
Limit(2) Limit(2)
VOS Input Offset Voltage V+= 2.7V and 3V 0.5 3 7 mV
3.5 7.5 Max
TCVOS Input Offset Voltage Average 1.5 μV/°C
Drift
IBInput Current 0.02 pA
10 10 Max
IOS Input Offset Current 0.01 pA
6 6 Max
RIN Input Resistance >1 Tera Ω
CIN Common-Mode Input 3 pF
Capacitance
CMRR Common Mode Rejection 0V ≤VCM ≤3.5V V+= 5V 75 63 60 dB
Ratio 60 57 Min
+PSRR Positive Power Supply 2.7V ≤V+≤5V, V−= 0V 75 67 60 dB
Rejection Ratio 65 58 Min
−PSRR Negative Power Supply −2.7V ≤V−≤ −5V, V+= 0V 83 75 67 dB
Rejection Ratio 73 65 Min
VCM Input Common-Mode V+= 2.7V and 3V for CMRR ≥50 dB −0.1 −0.05 −0.05 V
Voltage Range 0 0 Max
V+−0.8 V+−1.0 V+−1.0 V
V+−1.3 V+−1.3 Min
AVLarge Signal Voltage Gain RL= 100 kΩ(3) Sourcing 1000 V/mV
Sinking 500 V/mV
VOOutput Swing V+= 2.7V 2.695 2.68 2.65 V
RL= 100 kΩto V+/2 2.66 2.62 Min
0.005 0.03 0.06 V
0.05 0.09 Max
V+= 2.7V 2.66 2.55 2.45 V
RL= 5 kΩto V+/2 2.45 2.35 Min
0.04 0.15 0.25 V
0.25 0.35 Max
V+= 3V 2.995 2.98 2.95 V
RL= 100 kΩto V+/2 2.96 2.93 Min
0.005 0.03 0.06 V
0.05 0.09 Max
V+= 3V 2.96 2.85 2.75 V
RL= 5 kΩto V+/2 2.75 2.65 Min
0.04 0.15 0.25 V
0.25 0.35 Max
(1) Typical values represent the most likely parametric norm.
(2) All limits are guaranteed by testing or statistical analysis.
(3) V+= 3V, VCM = 1.5V and RLconnected to 1.5V. For Sourcing tests, 1.5V ≤VO≤2.5V. For Sinking tests, 0.5V ≤VO≤1.5V.
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2.7V DC Electrical Characteristics (continued)
Unless otherwise specified, all limits guaranteed for TJ= 25°C. V+= 2.7V, V−= 0V, VCM = VO= V+/2 and RL> 1MΩ.Boldface
limits apply at the temperature extremes.
Symbol Parameter Conditions Typ(1) LMC6574AI LMC6574BI Units
LMC6572AI LMC6572BI
Limit(2) Limit(2)
ISC Output Short Circuit Current Sourcing, VO= 0V 6.0 4.0 3.0 mA
3.0 2.0 Min
Sinking, VO= 2.7V 4.0 3.0 2.5 mA
2.0 1.5 Min
ISSupply Current Quad Package 160 240 240 μA
V+= +2.7V, VO= V+/2 280 280 Max
Quad Package 160 240 240 μA
V+= +3V, VO= V+/2 280 280 Max
Dual Package 80 120 120 μA
V+= +2.7V, VO= V+/2 140 140 Max
Dual Package 80 120 120 μA
V+= +3V, VO= V+/2 140 140 Max
2.7V AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ= 25°C, V+= 2.7V, V−= 0V, VCM = VO= V+/2 and RL> 1 MΩ.Boldface
limits apply at the temperature extremes.
Symbol Parameter Conditions Typ(1) LMC6574AI LMC6574BI Units
LMC6572AI LMC6572BI
Limit(2) Limit(2)
SR Slew Rate V+= 2.7V and 3V(3) 90 30 30 V/ms
10 10 Min
GBW Gain-Bandwidth Product V+= 3V 0.22 MHz
φmPhase Margin 60 Deg
GmGain Margin 12 dB
Amp-to-Amp Isolation See(4) 120 dB
enInput-Referred Voltage Noise F = 1 kHz 45 nV/√Hz
VCM = 1V
inInput-Referred Current Noise F = 1 kHz 0.002 pA/√Hz
T.H.D. Total Harmonic Distortion F = 10 kHz, AV=−2 0.05 %
RL= 10 kΩ, VO= 1.0 VPP
(1) Typical values represent the most likely parametric norm.
(2) All limits are guaranteed by testing or statistical analysis.
(3) Connected as Voltage Follower with 1.0V step input. Number specified is the slower of the positive and negative slew rates.
(4) Input referred, V+= 3V and RL= 100 kΩconnected to 1.5V. Each amp excited in turn with 1 KHz to produce VO= 2 VPP.
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SNOS707D –DECEMBER 1996–REVISED MARCH 2013
Typical Performance Characteristics
VS= +3V, TA= 25°C, Unless otherwise specified
Supply Current vs Input Current vs
Supply Voltage (Dual Package) Temperature
Figure 3. Figure 4.
Sourcing Current vs Sinking Current vs
Output Voltage Output Voltage
Figure 5. Figure 6.
Output Voltage Swing vs Input Voltage Noise vs
Supply Voltage Frequency
Figure 7. Figure 8.
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Typical Performance Characteristics (continued)
VS= +3V, TA= 25°C, Unless otherwise specified
Crosstalk Rejection vs Positive PSRR vs
Frequency Frequency
Figure 9. Figure 10.
CMRR
Negative PSRR vs vs
Frequency Frequency
Figure 11. Figure 12.
Input Voltage vs Open Loop Frequency
Output Voltage (VS= ±1.5) Response
Figure 13. Figure 14.
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SNOS707D –DECEMBER 1996–REVISED MARCH 2013
Typical Performance Characteristics (continued)
VS= +3V, TA= 25°C, Unless otherwise specified
Open Loop Frequency
Response
vs Maximum Output Swing
Temperature vs Frequency
Figure 15. Figure 16.
ZOUT
vs Slew Rate
Frequency vs Supply Voltage
Figure 17. Figure 18.
Non-Inverting Large Signal Non-Inverting Small Signal
Pulse Response Pulse Response
Figure 19. Figure 20.
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Typical Performance Characteristics (continued)
VS= +3V, TA= 25°C, Unless otherwise specified
Inverting Large Signal Inverting Small Signal
Pulse Response Pulse Response
Figure 21. Figure 22.
Stability Stability
vs Capacitive Load vs Capacitive Load
Figure 23. Figure 24.
Stability Stability
vs Capacitive Load vs Capacitive Load
Figure 25. Figure 26.
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SNOS707D –DECEMBER 1996–REVISED MARCH 2013
Typical Performance Characteristics (continued)
VS= +3V, TA= 25°C, Unless otherwise specified
Bandwidth
vs Capacitive Load
Capacitive Load vs Phase Margin
Figure 27. Figure 28.
Capacitive Load
vs Gain Margin
Figure 29.
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SNOS707D –DECEMBER 1996–REVISED MARCH 2013
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APPLICATIONS HINTS
LOW VOLTAGE AMPLIFIER TOPOLOGY
The LMC6574/2 incorporates a novel op-amp design topology that enables it to maintain rail-to-rail output swing
even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage
is taken directly from the internal integrator, which provides both low output impedance and large gain. Special
feed-forward compensation design techniques are incorporated to maintain stability over a wider range of
operating conditions than traditional micropower op-amps. These features make the LMC6574/2 both easier to
design with, and provide higher speed than products typically found in this ultra-low power class.
COMPENSATING FOR INPUT CAPACITANCE
It is quite common to use large values of feedback resistance for amplifiers with ultra-low input current, like the
LMC6574/2.
Although the LMC6574/2 is highly stable over a wide range of operating conditions, a large feedback resistor will
react even with small values of capacitance at the input of the op-amp to reduce phase margin. The capacitance
at the input of the op-amp comes from transducers, photodiodes and circuit board parasitics.
The effect of input capacitance can be compensated for by adding a capacitor, Cf, around the feedback resistors
(as in Figure 30) such that:
(1)
or R1CIN ≤R2Cf(2)
Since it is often difficult to know the exact value of CIN, Cfcan be experimentally adjusted so that the desired
pulse response is achieved. Refer to the LMC660 and LMC662 for a more detailed discussion on compensating
for input capacitance.
When high input impedances are demanded, guarding of the LMC6574/2 is suggested. Guarding input lines will
not only reduce leakage, but lowers stray input capacitance as well. (See PRINTED-CIRCUIT-BOARD LAYOUT
FOR HIGH-IMPEDANCE WORK
Figure 30. Cancelling the Effect of Input Capacitance
CAPACITIVE LOAD TOLERANCE
Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created
by the combination of the op-amp's output impedance and the capacitive load. This pole induces phase lag at the
unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response.
With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 31.
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SNOS707D –DECEMBER 1996–REVISED MARCH 2013
Figure 31. LMC6574/2 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads
In the circuit of Figure 31, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency
component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the
overall feedback loop.
PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires
special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the
LMC6574/2, typically less than 20 fA, it is essential to have an excellent layout. Fortunately, the techniques of
obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board,
even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or
contamination, the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6574/2's
inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-
amp's inputs, as in Figure 32. To have a significant effect, guard rings should be placed on both the top and
bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the
amplifier inputs, since no leakage current can flow between two points at the same potential. For example, a PC
board trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if
the trace were a 5V bus adjacent to the pad of the input. This would cause a 250 times degradation from the
LMC6574/2's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a
resistance of 1011Ωwould cause only 0.05 pA of leakage current. See Figure 35 for typical connections of guard
rings for standard op-amp configurations.
Figure 32. Example of Guard Ring in P.C. Board Layout
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Figure 33. Inverting Amplifier
Figure 34. Non-Inverting Amplifier
Follower
Figure 35. Typical Connections of Guard Rings
The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few
circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the
amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an
excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but
the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 36.
(Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board).
Figure 36. Air Wiring
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SNOS707D –DECEMBER 1996–REVISED MARCH 2013
SPICE MACROMODEL
A spice macromodel is available for the LMC6574/2. This model includes accurate simulation of:
• input common-mode voltage range
• frequency and transient response
• GBW dependence on loading conditions
• quiescent and dynamic supply current
• output swing dependence on loading conditions
and many more characteristics as listed on the macromodel disk.
Contact your local Texas Instruments sales office to obtain an operational amplifier spice model library disk.
Typical Single-Supply Applications
Figure 37. Low-Power Two-Op-Amp
Instrumentation Amplifier
Figure 38. Sample and Hold
Figure 39. 1 Hz Square Wave Oscillator
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SNOS707D –DECEMBER 1996–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 14
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMC6572AIM/NOPB LIFEBUY SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC65
72AIM
LMC6572AIMX/NOPB LIFEBUY SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC65
72AIM
LMC6572BIM/NOPB LIFEBUY SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC65
72BIM
LMC6572BIMX/NOPB LIFEBUY SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC65
72BIM
LMC6574AIM/NOPB LIFEBUY SOIC D 14 55 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC6574
AIM
LMC6574AIMX LIFEBUY SOIC D 14 2500 TBD Call TI Call TI -40 to 85 LMC6574
AIM
LMC6574AIMX/NOPB LIFEBUY SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC6574
AIM
LMC6574BIM/NOPB LIFEBUY SOIC D 14 55 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC6574
BIM
LMC6574BIMX/NOPB LIFEBUY SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC6574
BIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Aug-2017
Addendum-Page 2
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMC6572AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMC6572BIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMC6574AIMX SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
LMC6574AIMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
LMC6574BIMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMC6572AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMC6572BIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMC6574AIMX SOIC D 14 2500 367.0 367.0 35.0
LMC6574AIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0
LMC6574BIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 2
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