AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 1 -
Description
The AS4C4M16S are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as
1,048,576 x 16 x 4 (word x bit x bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture and clock frequency up
to 166MHz. All input and outputs are synchronized with the positive edge of the clock. The synchronous DRAMs are
compatible with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOPII.
Features
• Single 3.3V (±0.3V) power supply
• High speed clock cycle time -6ns:166MHz<3-3-3>
• Fully synchronous operation referenced to clock rising edge
• Possible to assert random column access in every cycle
• Quad internal banks controlled by BA0 & BA1 (Bank Select)
• Byte control by LDQM and UDQM
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• X16 organization
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64ms
• Burst termination by Burst stop and Precharge command
Options
• Operating temperature range Marking
- Extended (-25°C to 85°C) E
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 2 -
Pin Configurations
AS4C4M16S
1
2
3
4
5
6
7
9
10
11
12
13
8
14
15
16 39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
VSS
DQ15
17
18
19
20
21
22
23
24
A10
A0
25
26
27
A3
A2
28
29
30
31
32
33
34
35
36
37
38
A11
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A1
VDD
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
VSS
Pin Descriptions
Pin Name
Function
Pin Name
Function
CLK
Master Clock
DQM
DQ Mask Enable
CKE
Clock Enable
A0-11
Address Input
Chip Select
BA0,1
Bank Address
RAS
Row Address Strobe
VDD
Power Supply
CAS
Column Address Strobe
VDDQ
Power Supply for DQ
WE
Write Enable
VSS
Ground
DQ0 ~ DQ15
Data I/O
VSSQ
Ground for DQ
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 3 -
Block Diagram
CLK
CKE
Clock
Generator
Command Decoder
Control Logic
Mode
Register
Column
Address
Buffer
&
Burst
counter
Row
Address
Buffer
&
Burst
counter
Row Decoder
Column Decoder &
Latch Circuoit
Sense amplifier
Bank B
Bank C
Bank D
Bank A
Data Control Circuit
Latch Circuit
Input & Output
Buffer
DQ
DQM
Address
CS
RAS
CAS
WE
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 4 -
Pin Function
Symbol
Input
Function
CLK
Input
Master Clock: Other inputs signals are referenced to the CLK rising edge
CKE
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, device
input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN
and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any
bank).
Input
Chip Select:
enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when
is registered HIGH.
provides for external
bank selection on systems with multiple banks.
is considered part of the command code.
RAS
,
CAS
,
WE
Input
Command Inputs:
RAS
,
CAS
and
WE
(along with
) define the command being entered.
A0 - A13
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column address and
AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory
array in the respective bank. The row address is specified by A0-A11. The column address is
specified by A0-A7
BA0,BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
DQM, UDQM ,
LDQM
Input
Din Mask / Output Disable : When DQM is high in burst write, Din for the current cycle is
masked. When DQM is high in burst read, Dout is disable (two - clock latency).
DQ0 - DQ15
I/O
Data Input / Output: Data bus
VDD, VSS
Supply
Power Supply for the memory array and peripheral circuitry
VDDQ, VSSQ
Supply
Power Supply are supplied to the output buffers only
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 5 -
Absolute Maximum Ratings
Parameter
Symbol
Conditions
Value
Unit
Supply Voltage
VDD
with respect to VSS
-0.5 to 4.6
V
Supply Voltage for Output
VDDQ
with respect to VSSQ
-0.5 to 4.6
V
Input Voltage
VI
with respect to VSS
-0.5 to VDD+0.5
V
Output Voltage
VO
with respect to VSSQ
-0.5 to VDDQ+0.5
V
Short circuit output current
IO
50
mA
Power dissipation
PD
Ta = 25 °C
1
W
Operating temperature
TOPT
by temperature options
Ta
°C
Storage temperature
TSTG
-65 to 150
°C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be
operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability.
Recommended Operating Conditions (Ta: noted by temperature options)
Parameter
Symbol
Limits
Unit
Min.
Typ.
Max.
Supply Voltage
VDD
3.0
3.3
3.6
V
Supply Voltage for DQ
VDDQ
3.0
3.3
3.6
V
Ground
VSS
0
0
0
V
Ground for DQ
VSSQ
0
0
0
V
High Level Input Voltage (all inputs)
VIH
2.0
VDD + 0.3
V
Low Level Input Voltage (all inputs)
VIL
-0.3
0.8
V
Note :
1.All voltages are referenced to Vss = 0V.
2.VIH (max) is acceptable 5.6V AC pulse width with ≤ 3ns of duration.
3.VIL (min) is acceptable -2.0V AC pulse width with ≤ 3ns of duration.
Pin Capacitance(VDD = VDDQ = 3.3±0.3V , VSS = VSSQ = 0V, unless otherwise noted)
Parameter
Symbol
Min
Max
Unit
Input Capacitance, address & control pin
CIN
2.5
3.8
pF
Input Capacitance, CLK pin
CCLK
2.5
3.5
pF
Data input / output capacitance
CI/O
4.0
6.5
pF
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 6 -
DC Characteristics 1
(VDD = VDDQ = 3.3±0.3V, VSS = VSSQ = 0V, Output Open noted, unless otherwise noted)
Limits (max.)
Unit
Notes
Parameter
Symbol
Test Conditions
-6
Operating current
ICC1
One bank active
tRC = tRC(MIN), tCLK = tCLK(MIN),
BL = 1, CL=3
95
mA
1
ICC2P
CKE≤VIL(MAX), tCK = 15ns
2
Precharge standby current
in power down mode
ICC2PS
CKE≤VIL(MAX), CLK≤VIL(MAX)
1
mA
ICC2N
≥VDD - 0.2V
tCK = 15ns, CKE≥VIH(MIN)
20
mA
2
Precharge standby current
in non power down mode
ICC2NS
≥VDD - 0.2V
CLK≤VIL(MAX), CKE≥VIH(MIN)
All input signals are stable.
20
mA
ICC3P
CKE≤VIL(MAX), tCK = 10ns
7
Active standby current in
power down mode
ICC3PS
CKE≤VIL(MAX), CLK≤VIL(MAX)
5
mA
ICC3N
≥VDD - 0.2V
tCK = 15ns, CKE≥VIH(MIN)
35
mA
2
Active standby current in
Nonpower down mode
ICC3NS
≥VDD - 0.2V
CLK≤VIL(MAX), CKE≥VIH(MIN)
All input signals are stable.
35
mA
Operating current
(Burst mode)
ICC4
All banks active
tCK = tCK(MIN), BL=4, CL=3
All banks active
130
mA
Refresh current
ICC5
tRC = tRC(MIN), tCLK = tCLK(MIN)
150
mA
CKE≤0.2V AS4C4M16S
1
mA
Self refresh current
ICC6
NOTES
1. ICC(max) is specified at the output open condition.
2. Input signals are changed one time during 30ns.
DC Characteristics 2
(VDD = VDDQ = 3.3±0.3V , VSS = VSSQ = 0V, unless otherwise noted)
Parameter
Symbol
Test Condition
Min
Max
Unit
Input leakage current (Inputs)
II (L)
0≤VIN≤VDD(MAX)
Pins not under test = 0V
5
5
uA
Output leakage current (I/O pins)
IO (L)
0≤VOUT≤VDD(MAX)
DQ# in H - Z., DOUT is disabled
5
5
uA
High level output voltage
VOH
IOH = -2mA
2.4
V
Low level output voltage
VOL
IOL = 2mA
0.4
V
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 7 -
AC Characteristics (VDD = VDDQ = 3.3±0.3V , VSS = VSSQ = 0V, unless otherw ise noted)
Test Conditions
AC input Levels (VIH/VIL)
2.0 / 0.8V
Input timing reference level /
Output timing reference level
1.4V
Input rise and fall time
1ns
Output load condition
50pF
Note): 1.if clock rising time is longer than 1ns, (tr/2-0.5ns) should be added to the parameter.
Output Load Conditions
Ω
VDDQ VDDQ
VOUT
Device
Under
Test
50PF
Z = 50
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 8 -
Switching Characteristics (VDD
= VDDQ
= 3.3±0.3V , VSS = VSSQ
= 0V, unless otherwise noted)
Limits
-6
Parameter
Symbol
Min
Max
Unit
Note
CLK cycle time
CL=3
tCK3
6
ns
CL=2
tCK2
8
ns
CLK high pulse width
tCH
2.5
ns
CLK low pulse width
tCL
2.5
ns
Transition time of CLK
tT
1
10
ns
Input Setup time
tIS
1.5
ns
1
Input Hold time
tIH
1
ns
2
Row Cycle Time
tRC
60
ns
Refresh Cycle Time
tRFC
60
ns
Row to Column Delay
tRCD
18
ns
Row active time
tRAS
42
100
k
ns
Row Precharge time
tRP
15
ns
Write Recovery time
tWR
12
ns
3
Act to Delay time
tRRD
12
ns
Mode Register Set Cycle time
tRSC
2
tCK
Data-in to ACTIVE command
tDAL
4
tCK
Refresh Interval time
tREF
64
ms
Note :
1. tIS = tCKS (CKE setup time) , tCMS (Command setup time) , tAS (Address setup time) , tDS (Input data setup time).
2. tIH = tCKH (CKE hold time) , tCMH (Command hold time) , tAH (Address hold time) , tDH
(Input data hold time).
3. tWR
is so called tDPL.
Switching Characteristics (VDD
= VDDQ
= 3.3±0.3V , VSS = VSSQ
= 0V, unless otherwise noted)
Limits
-6
Unit
Note
Parameter
Symbol
Min
Ma
x
CL = 3
tAC3
5
ns
*1
Access time from CLK
CL = 2
tAC2
6
ns
*1
CL = 3
tCH3
2.5
ns
*1
Output Hold time from CLK
CL = 2
tCH2
2.5
ns
*1
Delay time , output low-impedance
from CLK
tOLZ
0
ns
Delay time , output high-impedance
from LCK
tOHZ
2.5
5
ns
Note :
1. If clock rising time is longer than 1ns, (tr/2-0.5ns) should be added to the parameter.
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 9 -
Basic Features and Function Description
1. Simplified State Diagram
Self
Refresh
MRSMode
Register
Set IDLE
AUTO
Refresh
REF
A
C
T
CKE
CKE
B
S
T
Power
Down
Active
Power
Down
ROW
ACTIVE
Read
CKE
CKE
READ READ
SUSPEND
CKE
CKE
READ A
READA
SUSPEND
Read with
Auto Precharge
CKE
CKE
Write (Write recovery)
WRITE
WRITE
SUSPEND
WRITE A
WRITE A
SUSPEND
CKE
CKE
Write with
Auto Precharge
POWER
ON
Precharge Precharge
P
R
E
(
P
re
c
h
a
rg
e
t
e
r
m
in
a
t
io
n
)
P
R
E
(
P
re
c
h
a
rg
e
t
e
r
m
in
a
t
i
o
n
)
R
e
a
d
w
it
h
W
r
it
e
w
it
h
A
u
t
o
p
r
e
d
h
a
r
g
eA
u
t
o
P
re
c
h
a
r
g
e
Re
ad
B
S
T
W
r
it
e
Read with
Auto
Precharg
e
(write
recovery)
Write with
Auto Precharge
Write
Read (write recovery)
P
R
E
C
K
E
C
KE
Automatic sequence
Manual input
Note: After the AUTO refresh operation, precharge operation is
performed automatically and enter the IDLE state
SELF
e
n
try
S
ELF
e
xit
Write rec
ov
ery
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 10 -
2.Truth Table
2.1 Command Truth Table
CKE
FUNCTION
Symbol
n - 1
n
RAS
CAS
WE
BA
A10
A11
A9 – A0
Device deselect
DESL
H
X
H
X
X
X
X
X
X
No operation
NOP
H
X
L
H
H
H
X
X
X
Mode register set
MRS
H
X
L
L
L
L
L
L
V
Bank activate
ACT
H
X
L
L
H
H
V
V
V
Read
READ
H
X
L
H
L
H
V
L
V
Read with auto precharge
READA
H
X
L
H
L
H
V
H
V
Write
WRIT
H
X
L
H
L
L
V
L
V
Write with auto precharge
WRITA
H
X
L
H
L
L
V
H
V
Precharge select bank
PRE
H
X
L
L
H
L
V
L
X
Precharge all banks
PALL
H
X
L
L
H
L
X
H
X
Burst stop
BST
H
X
L
H
H
L
X
X
X
CBR (Auto) refresh
REF
H
H
L
L
L
H
X
X
X
Self refresh
SELF
H
L
L
L
L
H
X
X
X
2.2 DQM Truth Table
CKE
FUNCTION
Symbol
n - 1
n
DQM
Data write/output enable
ENB
H
X
L
Data mask/output disable
MASK
H
X
H
2.3 CKE Truth Table
CKE
Current State
Function
Symbol
n - 1
n
RAS
CAS
WE
Address
Activating
Clock suspend mode entry
H
L
X
X
X
X
X
Any
Clock suspend
L
L
X
X
X
X
X
Clock suspend
Clock suspend mode exit
L
H
X
X
X
X
X
Idle
CBR refresh command
REF
H
H
L
L
L
H
X
Idle
Self refresh entry
SELF
H
L
L
L
L
H
X
Self refresh
Self refresh exit
L
H
L
H
H
H
X
L
H
H
X
X
X
X
Idle
Power down entry
H
L
X
X
X
X
X
Power down
Power down exit
L
H
X
X
X
X
X
H : High level, L : Low level
X : High or Low level (Don’t care), V : Valid Data input
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 11 -
2.4 Operative Command Table (note 1)
Current state
RAS
CAS
WE
Address
Command
Action
Notes
H
X
X
X
X
DESL
Nop or Power down
2
L
H
H
X
X
NOP or BST
Nop or Power down
2
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BR, RA
ACT
Row active
L
L
H
L
BA, A10
PRE/PALL
Nop
L
L
L
H
X
REF/SELF
Refresh or Self refresh
4
Idle
L
L
L
L
Op-Code
MPS
Mode register access
H
X
X
X
X
DESL
Nop
L
H
H
X
X
NOP or BST
Nop
L
H
L
H
BA, CA, A10
READ/READA
Begin read : Determine AP
5
L
H
L
L
BA, CA, A10
WRIT/WRITA
Begin write : Determine AP
5
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
Precharge
6
L
L
L
H
X
REF/SELF
ILLEGAL
Row active
L
L
L
L
Op-Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Continue burst to end→Row active
L
H
H
H
X
NOP
Continue burst to end→Row active
L
H
H
L
X
BST
Burst stop→Row active
L
H
L
H
BA, CA, A10
READ/READA
Term burst, new read : Determine
AP
7
L
H
L
L
BA, CA, A10
WRIT/WRITA
Term burst, start write : Determine
AP
7,8
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
Term burst, precharging
L
L
L
H
X
REF/SELF
ILLEGAL
Read
L
L
L
L
Op-Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Continue burst to end→write
recovering
L
H
H
H
X
NOP
Continue burst to end→write
recovering
L
H
H
L
X
BST
Burst stop→Row active
L
H
L
H
BA, CA, A10
READ/READA
Term burst, start read : Determine
AP
7,8
L
H
L
L
BA, CA, A10
WRIT/WRITA
Term burst, new write : Determine
AP
7
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
Term burst, precharging
9
L
L
L
H
X
REF/SELF
ILLEGAL
write
L
L
L
L
Op-Code
MRS
ILLEGAL
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 12 -
Current state
RAS
CAS
WE
Address
Command
Action
Notes
H
X
X
X
X
DESL
Continue burst to
end→Precharging
L
H
H
H
X
NOP
Continue burst to
end→Precharging
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
11
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
11
L
L
H
H
BA, RA
ACT
ILLEGAL
3,11
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3,11
L
L
L
H
X
PEF/SELF
ILLEGAL
Read with auto
precharge
L
L
L
L
Op - Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Continue burst to end→write
recovering with auto precharge
L
H
H
H
X
NOP
Continue burst to end→write
recovering with auto precharge
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
11
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
11
L
L
H
H
BA, RA
ACT
ILLEGAL
3,11
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3,11
L
L
L
H
X
REF/SELF
ILLEGAL
Write with auto
precharge
L
L
L
L
Op - code
MRS
ILLEGAL
H
X
X
X
X
DESL
Nop→Enter idle after tRP
L
H
H
H
X
NOP
Nop→Enter idle after tRP
L
H
H
L
X
BST
Nop→Enter idle after tRP
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
Nop Enter idle after tRP
L
L
L
H
X
REF/SELF
ILLEGAL
Precharging
L
L
L
L
Op - Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Nop→Enter row active after tRCD
L
H
H
H
X
NOP
Nop→Enter row active after tRCD
L
H
H
L
X
BST
Nop→Enter row active after tRCD
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3, 9
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
L
L
H
X
REF/SELF
ILLEGAL
Row activating
L
L
L
L
Op - Code
MRS
ILLEGAL
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
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Current state
RAS
CAS
WE
Address
Command
Action
Notes
H
X
X
X
X
DESL
Nop→Enter row active after tDPL
L
H
H
H
X
NOP
Nop→Enter row active after tDPL
L
H
H
L
X
BST
Nop→Enter row active after tDPL
L
H
L
H
BA, CA, A10
READ/READA
Start read, Determine AP
8
L
H
L
L
BA, CA, A10
WRIT/WRITA
New write, Determine AP
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
L
L
H
X
PEF/SELF
ILLEGAL
Write recovering
L
L
L
L
Op - Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Nop→Enter precharge after tDPL
L
H
H
H
X
NOP
Nop→Enter precharge after tDPL
L
H
H
L
X
BST
Nop→Enter precharge after tDPL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3,8,11
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3,11
L
L
H
H
BA, RA
ACT
ILLEGAL
3,11
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
L
L
H
X
REF/SELF
ILLEGAL
Write recovering
with auto
precharge
L
L
L
L
Op - Code
MRS
ILLEGAL
H
X
X
X
X
DESL
Nop→Enter idle after tRC
L
H
H
X
X
NOP/BST
Nop→Enter idle after tRC
L
H
L
X
X
READ/WRIT
ILLEGAL
L
L
H
X
X
ACT/PRE/PALL
ILLEGAL
Auto Refreshing
L
L
L
X
X
REF/SELF/MRS
ILLEGAL
H
X
X
X
X
DESL
Nop→Enter idle after 2 Clocks
L
H
H
H
X
NOP
Nop→Enter idle after 2 Clocks
L
H
H
L
X
BST
ILLEGAL
L
H
L
X
X
READ/WRITE
ILLEGAL
Mode register
setting
L
L
X
X
X
ACT/PRE/PALL/
REF/SELF/MRS
ILLEGAL
Note
1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If both banks are idle, and CKE is inactive (Low level), the device will enter Power downmode. All input buffers except CKE will be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address(BA), depending on the state of that bank.
4. If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode. All input buffers except CKE will be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy tDPL.
10. Illegal if tRRD is not satisfied.
11. Illegal for single bank, bur legal for other banks in multi-bank devices.
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4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
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2.5 Command Truth Table for CKE (Note 1)
Current state
CKE
n - 1
CKE
n
RAS
CAS
WE
Address
Action
Notes
H
X
X
X
X
X
X
INVALID, CLK (n - 1)would exit S.R.
L
H
H
X
X
X
X
S.R. Recovery
2
L
H
L
H
H
X
X
S.R. Recovery
2
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
Self refresh
(S.R.)
L
L
X
X
X
X
X
Maintain S.R.
H
H
H
X
X
X
X
Idle after tRC
H
H
L
H
H
X
X
Idle after tRC
H
H
L
H
L
X
X
ILLEGAL
H
H
L
L
X
X
X
ILLEGAL
H
L
H
X
X
X
X
Begin clock suspend next cycle
5
H
L
L
H
H
X
X
Begin clock suspend next cycle
5
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
H
X
X
X
X
X
Exit clock suspend next cycle
2
Self refresh
recovery
L
L
X
X
X
X
X
Maintain clock suspend
H
X
X
X
X
X
INVALID, CLK (n - 1) would exit P.D.
L
H
X
X
X
X
X
EXIT P.D. Idle
2
Power down
(P.D.)
L
L
X
X
X
X
X
Maintain power down mode
H
H
H
X
X
X
Refer to operations in Operative
Command Table
H
H
L
H
X
X
Refer to operations in Operative
Command Table
H
H
L
L
H
X
Refer to operation in Operative
Command Table
H
H
L
L
L
H
X
Auto Refresh
H
H
L
L
L
L
Op - Code
Refer to operations in Operative
Command Table
H
L
H
X
X
X
Refer to operations in Operative
Command Table
H
L
L
H
X
X
Refer to operations in Operative
Command Table
H
L
L
L
H
X
Refer to operations in Operative
Command Table
H
L
L
L
L
H
X
Self refresh
3
H
L
L
L
L
L
Op - Code
Refer to operations in Operative
Command Table
Both banks
idle
L
X
X
X
X
X
X
Power down
3
H
H
X
X
X
X
X
Refer to operations in Operative
Command Table
H
L
X
X
X
X
X
Begin clock suspend next cycle
4
L
H
X
X
X
X
X
Exit clock suspend next cycle
Any state
other than
listed above
L
L
X
X
X
X
X
Maintain clock suspend
1. H : High level, L : low level, X : High or low level (Don't care).
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any
command other than EXIT.
3. Power down and Self refresh can be entered only from the both banks idle state.
4. Must be legal command as defined in Operative Command Table.
5. Illegal if tSREX is not satisfied.
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
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3.Initiallization
Before starting normal operation, the following power on sequence is necessary to prevent SDRAM from damaged or
malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high , DQN high and NOP condition at the inputs.
2. Maintain stable power, table clock , and NOP input conditions for a minimum of 200us.
3. Issue precharge commands for all bank. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is in idle state and ready for normal operation.
4.Programming the Mode Register
The mode register is programmed by the mode register set command using address bits BA0,BA1,A11 through A0 as
data inputs. The register retains data until it is reprogrammed or the device loses power.
The mode register has four fields;
Options : BA0,BA1,A11 through A7
CAS latency : A6 through A4
Wrap type : A3
Burst length : A2 through A0
Following mode register programming, no command can be asserted before at least two clock cycles have elapsed.
CAS Latency
CAS latency is the most critical parameter being set. It tells the device how many clocks must elapse before the data
will be available.
The value is determined by the frequency of the clock and the speed grade of the device. The value can be pro-
grammed as 2 or 3.
Burst Length
Burst Length is the number of words that will be output or input in read or write cycle. After a read burst is completed,
the output bus will become high impedance.
The burst length is programmable as 1, 2, 4, 8 or full page.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. The order is programmable as either
“Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
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5.Mode Register
BA
0
BA
1
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
JEDEC Standard Test Set
BA
0
BA
1
11
10
9
8
7
6
5
4
3
2
1
0
x
x
x
x
0
LTMODE
WT
BL
Burst Read and Single Write (for Write Through Cache)
BA
0
BA
1
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
LTMODE
WT
BL
Burst Read and Burst Write x = Don’t care
Bits2 - 0
WT = 0
WT = 1
000
1
1
001
2
2
010
4
4
011
8
8
100
R
R
101
R
R
110
R
R
Burst length
111
Fullpage
R
0
Sequential
Wrap type
1
Interleave
Bits 6-4
CAS
latency
000
R
001
R
010
2
011
3
100
R
101
R
110
R
Latency mode
111
R
Remark R : Reserved
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
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5.1 Burst Length and Sequence
(Burst of Two)
Starting Address
(column address A0, binary)
Sequential Addressing Sequence
(decimal)
Interleave Addressing Sequence
(decimal)
0
0, 1
0, 1
1
1, 0
1, 0
(Burst of Four)
Starting Address
(column address A1 - A0, binary)
Sequential Addressing Sequence
(decimal)
Interleave Addressing Sequence
(decimal)
00
0, 1, 2, 3
0, 1, 2, 3
01
1, 2, 3, 0
1, 0, 3, 2
10
2, 3, 0, 1
2, 3, 0, 1
11
3, 0, 1, 2
3, 2, 1, 0
(Burst of Eight)
Starting Address
(column address A2 - A0, binary)
Sequential Addressing Sequence
(decimal)
Interleave Addressing Sequence
(decimal)
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1 ,2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6 ,7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7 ,0 ,1 ,2 ,3 ,4 ,5
6, 7, 4, 5, 2, 3, 0, 1
111
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
Full page burst is an extension of the above tables of sequential addressing, with the length being 256 for 4Mx16.
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
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6.Address Bits of Bank-Select and Precharge
Row
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA1
BA0
(Activate command)
Row
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA1
BA0
(Precharge command)
Row
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA1
BA0
BA1
BA0
Result
0
0
Select Bank A
“Activate “ command
0
1
Select Bank B
“Activate” command
1
0
Select Bank C
“Activate” command
1
1
Select Bank D
“Activate” command
A10
BA1
BA0
Result
0
0
0
Precharge Bank A
0
0
1
Precharge Bank B
0
1
0
Precharge Bank C
0
1
1
Precharge Bank D
1
X
X
Precharge All Banks
X : Don’t care
BA1
BA0
Result
0
0
Enables Read/Write
commands for Bank A
0
1
Enables Read/Write
commands for Bank B
1
0
Enables Read/Write
commands for Bank C
1
1
Enables Read/Write
commands for Bank D
0
Disables Auto-Precharge (End of Burst)
1
Enables Auto - Precharge (End of Burst)
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4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
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7.Precharge
The precharge command can be asserted anytime after tRAS(min.) is satisfied.
Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM enters
the idle state after tRP(min.) is satisfied. The parameter tRP is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as
follows.
In order to write all data to the memory cell correctly, the asynchronous parameter ”tDPL” must be satisfied. The tDPL(min.)
specification defines the earliest time that a precharge command can be asserted. The minimum number of clocks can be
calculated by dividing tDPL(min.) with the clock cycle time.
In summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is
valid. In the following table, minus means clocks before the reference; plus means time after the reference.
CAS
latency
Read
Write
2
-1
+ tDPL(min.)
3
-2
+ tDPL(min.)
Burst lengh=4
CLK
Command
CAS latency = 2
DQ
Command
CAS latency = 3
DQ
(tRAS
is satisfied)
Hi - Z
Q0 Q3Q2Q1
PRE
Q0 Q3Q2
Q1
Read
Read
T0 T1 T2 T3 T4 T5 T6 T7
PRE
Hi - Z
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4M X 16 CMOS Synchronous Dynamic RAM
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8.Auto Precharge
During a read or write command cycle, A10 controls whether auto precharge is selected. If A10 is high in the read or write
command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected and begins
automatically.
In the write cycle, tDAL(min.) must be satisfied before asserting the next activate command to the bank being precharged.
When using auto precharge in the read cycle, knowing when the precharge starts is important because the next activate
command to the bank being precharged cannot be executed until the precharge cycle ends. Once auto precharge has started,
an activate command to the bank can be asserted after tRP has been satisfied.
A Read or Write command without auto - precharge can be terminated in the midst of a burst operation. However, a Read or
Write command with auto - precharge can not be interrupted by the same bank commands before the entire burst operation is
completed. Therefore use of the same bank Read, Write, Precharge or Burst Stop command is prohibited during a read or write
cycle with auto - precharge. It should be noted that the device will not respond to the Auto - Precharge command if the device
is programmed for full page burst read or write cycles.
The timing when the auto precharge cycle begins depends both on both the
CAS
Iatency programmed into the mode register
and whether the cycle is read or write.
8.1 Read with Auto Precharge
During a READA cycle, the auto precharge begins one clock earlier (CL = 2) or two clocks earlier (CL = 3) than the last word
output.
READ with AUTO PRECHARGE
Burst lengh = 4
CLK
Command
CAS latency = 2
DQ
Command
CAS latency = 3
DQ
Remark READA means READ with AUTO PRECHARGE
Hi - Z
Auto precharge starts
QB0 QB3QB2
QB1
READA B
READA B
T0 T1 T2 T3 T4 T5 T6 T7
Auto precharge starts
Hi - Z
T8
QB0 QB3
QB2QB1
No New Command to Bank B
No New Command to Bank B
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
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8.2 Write with Auto Precharge
During a write cycle, the auto precharge starts at the timing that is equal to the value of tDPL(min.) after the last data word
input to the device.
WRITE with AUTO PRECHRGE
In summary, the auto precharge cycle begins relative to a reference clock that indicates
the last data word is valid.
In the table below, minus means clocks before the reference; plus means clocks after the
reference.
CAS
latency
Read
Write
2
-1
+ tDPL(min.)
3
-2
+ tDPL(min.)
Burst lengh = 4
CLK
Command
CAS latency = 2
DQ
Command
CAS latency = 3
DQ
Remark WRITA means WRITE with AUTO Precharge
Hi - Z
DB0 DB3DB2DB1
WRITA B
WRITA B
T0 T1 T2T3 T4 T5 T6 T7
Hi - Z_
T8
tDPL
tDPL
DB0 DB3
DB2
DB1
AUTO PRECHARGE starts
AUTO PRECHARGE starts
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
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9. Read / Write Command Interval
9.1 Read to Read Command Interval
During a read cycle when a new read command is asserted, it will be effective after the
CAS
latency, even if the previous
read operation has not completed. READ will be interrupted by another READ.
Each read command can be asserted in every clock without any restriction.
READ to READ Command Interval
9.2 Write to Write Command Interval
During a write cycle, when a new Write command is asserted,the previous burst will terminated and the new burst will begin
with a new write command. WRITE will be interrupted by another WRITE.
Each write command can be asserted in every clock without any restriction.
WRITE to WRITE Command Interval
Burst lengh=4, CAS latency=2
CLK
Command
DQ QA0 QB2QB1
QB0
Read A
T0 T1 T2 T3 T4 T5 T6 T7
Hi-Z_
T8
1 cycle
QB3
Read B
Burst lengh=4, CAS latency=2
CLK
Command
DQ QA0 QB2QB1QB0
Write A
T0 T1 T2 T3 T4 T5 T6 T7
Hi-Z_
T8
1 cycle
QB3
Write B
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4M X 16 CMOS Synchronous Dynamic RAM
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9.3 Write to Read Command Interval
The write command to read command interval is also a minimum of 1 cycle. Only the write data before the read command will
be written. The data bus must be Hi-Z at least one cycle prior to the first DOUT.
WRITE to READ Command Interval
9.4 Read to Write Command Interval
During a read cycle, READ can be interrupted by WRITE.
DQM must be in High at least 3 clocks prior to the write command. There is a restriction to avoid a data conflict. The data
bus must be Hi-Z using DQM before Write.
Burst lengh=4
CLK
Command
CAS latency=2
DQ
Command
CAS latency=3
DQ
QB0 QB3QB2QB1
WRITE A
Write A
T0 T1 T2 T3 T4 T5 T6 T7 T8
QB0 QB3
QB2
QB1
1 cycle
Read B
DA0
Read B
DA0 Hi-Z
Hi-Z
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
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READ to WRITE Command Interval
CAS latency=2
CLK
Command
DQM
DQ Hi-Z D0 D3D2
D1
Read
T0 T1 T2 T3 T4 T5 T6 T7 T8
1 cycle
Write
Burst length=8, CAS latency=2
CLK
Command
DQM
DQ Q0
Read
T0 T1 T2 T3 T4 T5 T6 T7 T8
Write
T9
necessary
Q2Q1 D0 D2D1
Hi-Z is
example: Burst length=4, CAS latency=3
CLK
Command
DQM
DQ
Read
T0 T1 T2 T3 T4 T5 T6 T7 T8
Write
necessary
D0 D2D1
Hi-Z is
Q2
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
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- 25 -
10.BURST Termination
There are two methods to terminate a burst operation other than using a read or a write command. One is the burst stop
command and the other is the precharge command.
10.1 BURST Stop Command
During a read burst, when the burst stop command is issued, the burst read data are terminated and the data bus goes to
high-impedance after the
CAS
latency from the burst stop command.
During a write burst, when the burst stop command is issued, the burst write data are terminated and data bus goes to Hi-Z
at the same clock with the burst stop command.
Burst Termination
Remark BST: Burst stop command
Burst lengh=X, CAS Intency=2,3
CLK
Command
CAS latency=2
DQ
CAS latency=3
DQ
Q0 Q2
Q1
Read
T0 T1 T2 T3 T4 T5 T6 T7
BST
Hi-Z
Q0 Q2Q1 Hi-Z
Burst lengh=X, CAS latency=2,3
CLK
Command
CAS latency=2,3
DQ
Q0 Q2Q1
Write
T0 T1 T2 T3 T4 T5 T6 T7
BST
Hi-Z_
Q0
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 26 -
10.2 PRECHARGE TERMINATION
10.2.1 PRECHARGE TERMINATION in READ Cycle
During READ cycle, the burst read operation is terminated by a precharge command.
When the precharge command is issued, the burst read operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command.
When
CAS
latency is 2, the read data will remain valid until one clock after the precharge command.
When
CAS
latency is 3, the read data will remain valid until two clocks after the precharge command.
Precharge Termination in READ Cycle
Burst lengh= X
CLK
Command
CAS latency=2
DQ Hi-Z
Read
T0 T1 T2 T3 T4 T5 T6 T7 T8
PRE ACT
DQ
Read PRE ACT
tRPCAS latency=3
Q0 Q3Q2Q1 Hi-Z
Q0 Q3Q2Q1
command
tRP
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 27 -
10.2.2 Precharge Termination in WRITE Cycle
During WRITE cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command. The DQM must be high to mask invalid data
in.
During WRITE cycle, the write data written prior to the precharge command will be correctly stored. However, invalid data
may be written at the same clock as the precharge command. To prevent this from happening, DQM must be high at the same
clock as the precharge command. This will mask the invalid data.
PRECHARGE TERMINATION in WRITE Cycle
Burst lengh = X
CLK
Command
CAS latency = 2
DQM
Hi - Z
Write
T0 T1 T2 T3 T4 T5 T6 T7 T8
tRP
PRE ACT
DQ
Write PRE ACT
tRP
CAS latency = 3
Hi - Z
D0 D3D2
D1
D0 D3
D2D1
DQM
D4
D4
command
DQ
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 28 -
Timing Diagram
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 29 -
Mode Register Set
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 30 -
AC Parameters for Write Timing (1 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 31 -
AC Parameters for Write Timing (2 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 32 -
AC Parameters for Read Timing (1 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 33 -
AC Parameters for Read Timing (2 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 34 -
Power on Sequence and Auto Refresh (CBR)
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 35 -
Clock Suspension During Burst Read (Using CKE)(1 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 36 -
Clock Suspension During Burst Read (Using CKE)(2 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 37 -
Clock Suspension During Burst Write (Using CKE)(1 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 38 -
Clock Suspension During Burst Write (Using CKE)(2 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 39 -
Power Down Mode and Clock Mask
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 40 -
Auto Refresh (CBR)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 41 -
Self Refresh (Entry and Exit)
*BA1=”L” , Bank C , D = Idle
*Clock can be stopped at CKE=Low. If clock is stopped, it must be restarted/stable for 4 clock cycles
before CKE=High
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 42 -
Random Column Read (Page With Same Bank)(1 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 43 -
Random Column Read (Page With Same Bank)(2 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 44 -
Random Column Write (Page With Same Bank)(1 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 45 -
Random Column Write (Page With Same Bank)(2 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 46 -
Random Row Read (Interleaving Banks)(1 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 47 -
Random Row Read (Interleaving Banks)(2 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 48 -
Random Row Write (Interleaving Banks)(1 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 49 -
Random Row Write (Interleaving Banks)(2 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 50 -
Read and Write Cycle (1 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 51 -
Read and Write Cycle (2 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 52 -
Interleaved Column Read Cycle (1 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 53 -
Interleaved Column Read Cycle (2 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 54 -
Interleaved Column Write Cycle (1 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 55 -
Interleaved Column Write Cycle (2 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 56 -
Auto Precharge after Read Burst (1 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 57 -
Auto Precharge after Read Burst (2 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 58 -
Auto Precharge after Write Burst (1 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 59 -
Auto Precharge after Write Burst (2 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 60 -
Full Page Read Cycle (1 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 61 -
Full Page Read Cycle (2 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 62 -
Full Page Write Cycle (1 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 63 -
Full Page Write Cycle (2 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 64 -
Burst Read and Single Write Operation
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 65 -
Full Page Random Column Read
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 66 -
Full Page Random Column Write
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 67 -
Precharge Termination of a Burst (1 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 68 -
Precharge Termination of a Burst (2 of 2)
*BA1=”L” , Bank C , D = Idle
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 69 -
Ordering information
Extended Temperature Range: -25C to 85C
Frequency Speed(ns) Order Part # Package
166MHz 6 AS4C4M16S-6TE 400-mil 54Pin TSOP II, Lead-Free
AS4C4M16S
4M X 16 CMOS Synchronous Dynamic RAM
Jan 2007 (Rev.3.4)
Alliance Memory,Inc.
Web : www.alliancememory.com Email : sales@alliancememory.com
TEL : 650-610-6800 Fax : 650-620-9211
- 70 -
Packaging Information
• 400mil, 54-Pin Plastic TSOP
1. CONTROLLING DIMENSION : MILLIMETERS
2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION.
MOLD PROTRUSION SHALL NOT EXCEED 0.15mm(0.006") PER SIDE.
DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION.
INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25mm(0.01") PER SIDE.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO
DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER
THAN THE MIN b DIMENSION BY MORE THAN 0.07mm.
BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm.
NOTE:
22.09
11.56
10.03
R1
ZD
E1
L
R
E
e
c
D
c1
b1
b
A
A1
A2
DIM
---
---
---
---
0.12
0.005
0.012
0.012
0.005
0.005
0.870
0.455
0.016
0.005
0.395
0.71 REF.
0.80 BASIC
10.16
0.40
0.12
0.50
---
11.76
10.29
0.25
0.60
11.96
---
0.12
0.12
22.22
---
0.30
0.30
---
---
0.21
22.35
0.16
0.45
0.40
0.028 REF.
0.400
0.020
---
0.463
0.0315 BASIC
0.405
0.024
0.010
0.471
---
0.875
---
---
---
0.008
0.880
0.006
0.016
0.018
MIN.
0.002
0.037
MILLIMETERS
---
---
0.05
0.95
---
1.00
MIN.
NOM.
1.20
0.15
1.05
MAX.
---
---
0.039
---
INCHES
NOM.
0.047
0.006
0.041
MAX.
A
b
0.100(0.004")
e
E
SEATING PLANE
28
27
D
ZD
1
54
c
B
RAD R
A2
A1
E1
DETAIL A
DETAIL A
B
L
0¢X~8¢X
RAD R1
c1
c
BASE METAL
WITH PLATING
SECTION B-B
b1
b