LM5088
LM5088/LM5088Q Wide Input Range Non-Synchronous Buck Controller
Literature Number: SNVS600G
LM5088/LM5088Q
March 14, 2011
Wide Input Range Non-Synchronous Buck Controller
General Description
The LM5088 high voltage non-synchronous buck controller
features all the necessary functions to implement an efficient
high voltage buck converter using a minimum number of ex-
ternal components. The LM5088 can be configured to operate
over an ultra-wide input voltage range of 4.5V to 75V. This
easy to use controller includes a level shifted gate driver ca-
pable of controlling an external N-channel buck switch. The
control method is based upon peak current mode control uti-
lizing an emulated current ramp. The use of an emulated
control ramp reduces noise sensitivity of the pulse-width mod-
ulation circuit, allowing reliable control of very small duty
cycles necessary in high input voltage/low output voltage ap-
plications. The LM5088 switching frequency is programmable
from 50 kHz to 1 MHz.
The LM5088 is available in two versions: The LM5088-1 pro-
vides a +/-5% frequency dithering function to reduce the
conducted and radiated EMI, while the LM5088-2 provides a
versatile restart timer for overload protection. Additional fea-
tures include a low dropout bias regulator, tri-level enable
input to control shutdown and standby modes, soft-start and
oscillator synchronization capability. The device is available
in a thermally enhanced TSSOP-16EP pin package.
Features
■LM5088Q is an Automotive Grade product that is AEC-
Q100 grade 1 qualified (-40°C to +125°C operating
junction temperature)
■Emulated current mode control
■Drives external high-side N-channel MOSFET
■Ultra-wide input voltage range from 4.5V to 75V
■Low IQ Shutdown and Standby modes
■High duty cycle ratio feature for reduced dropout voltage
■Spread spectrum EMI reduction (LM5088-1)
■Hiccup timer for overload protection (LM5088-2)
■Adjustable output voltage from 1.205V with 1.5% feedback
reference accuracy
■Wide bandwidth error amplifier
■Single resistor oscillator frequency setting
■Oscillator synchronization capability
■Programmable soft-start
■High voltage, low dropout bias regulator
■Thermal shutdown protection
Package
■TSSOP-16EP
Simplified Application Schematic
30083901
© 2011 National Semiconductor Corporation 300839 www.national.com
LM5088/LM5088Q Wide Input Range Non-Synchronous Buck Controller
Connection Diagrams
30083902
Top View (Dither version)
LM5088-1
30083903
Top View (Restart version)
LM5088-2
Ordering Information
Order Number Description NSC Package
Drawing Supplied As Feature
LM5088MH-1 TSSOP-16EP,
Dithering
MXA16A 73 Units in a Rail
LM5088MHX-1 TSSOP-16EP,
Dithering
MXA16A 2500 Units on Tape
and Reel
LM5088QMH-1 TSSOP-16EP,
Dithering
MXA16A 73 Units in a Rail AEC-Q100 Grade 1 qualified.
Automotive Grade Production
Flow*
LM5088QMHX-1 TSSOP-16EP,
Dithering
MXA16A 2500 Units on Tape
and Reel
LM5088MH-2 TSSOP-16EP, Restart MXA16A 73 Units in a Rail
LM5088MHX-2 TSSOP-16EP, Restart MXA16A 2500 Units on Tape
and Reel
LM5088QMH-2 TSSOP-16EP, Restart MXA16A 73 Units in a Rail AEC-Q100 Grade 1 qualified.
Automotive Grade Production
Flow*
LM5088QMHX-2 TSSOP-16EP, Restart MXA16A 2500 Units on Tape
and Reel
*Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market, including defect detection methodologies.
Reliability qualification is compliant with the requirements and temperature grades defined in the AEC-Q100 standard. Automotive grade products are identified
with the letter Q. For more information go to http://www.national.com/automotive.
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LM5088/LM5088Q
Pin Descriptions
Pin(S) Name Description Application Information
1 VIN Input supply voltage IC supply voltage. The operating range is 4.5V to 75V
2 EN Enable input If the EN pin voltage is below 0.4V the regulator will be in a low power state. If
the EN pin voltage is between 0.4V and 1.2V the controller will be in standby
mode. If the EN pin voltage is above 1.2V the controller will be operational. An
external voltage divider can be used to set a line under voltage shutdown
threshold. If the EN pin is left open, a 5µA pull-up current forces the pin to the
high state and enables the controller.
3 SS Soft-start When SS is below the internal 1.2V reference, the SS voltage will control the
error amplifier. An internal 11 µA current source charges an external capacitor
to set the start-up rate of the controller. The SS pin is held low in the standby,
VCC UV and thermal shutdown states. The SS pin can be used for voltage
tracking by connecting this pin to a master voltage supply less than 1.2V. The
applied voltage will act as the reference for the error amplifier.
4 RAMP Ramp control signal An external capacitor connected between this pin and the GND pin sets the
ramp slope used for emulated current mode control. Recommended capacitor
range 100 pF to 2000 pF. See the Applications section for selection of capacitor
value.
5 RT/SYNC Internal oscillator frequency
set input and
synchronization input
The internal oscillator is programmed with a single resistor between this pin
and the GND pin. The recommended frequency range is 50 kHz to 1 MHz. An
external synchronization signal, which is higher in frequency than the
programmed frequency, can be applied to this pin through a small coupling
capacitor. The RT resistor to ground is required even when using external
synchronization.
6 GND Ground Ground return.
7 COMP Output of the internal error
amplifier
The loop compensation network should be connected between this pin and the
FB pin.
8 FB Feedback signal from the
regulated output
This pin is connected to the inverting input of the internal error amplifier. The
regulation threshold is 1.205V.
9 OUT Output voltage connection Connect directly to the regulated output voltage.
10 DITH Frequency Dithering
( LM5088-1 Only)
A capacitor connected between DITH pin and GND is charged and discharged
by 27 µA current sources. As the voltage on the DITH pin ramps up and down,
the oscillator frequency is modulated between -5% to +5% of the nominal
frequency set by the RT resistor. Grounding the DITH pin will disable the
frequency dithering mode.
10 RES Hiccup Mode Restart
( LM5088-2 Only)
The RES pin is normally connected to an external capacitor that sets the timing
for hiccup mode current limiting. In normal operation, a 25µA current source
discharges the RES pin capacitor to ground. If cycle-by-cycle current limit
threshold is exceeded during any PWM cycle, the current sink is disabled and
RES capacitor is charged by an internal 50 µA current. If the RES voltage
reaches 1.2V, the HG pin gate drive signal will be disabled and the RES pin
capacitor will be discharged by a 1 µA current sink. Normal operation will
resume when the RES pin falls below 0.2V.
11 CSG Current Sense Ground Low side reference for the current sense resistor.
12 CS Current sense Current measurement connection for the re-circulating diode. An external
sense resistor and an internal sample/hold circuit sense the diode current at
the conclusion of the buck switch off-time. This current measurement provides
the DC offset level for the emulated current ramp.
13 SW Switching node Connect to the source terminal of the external MOSFET switch.
14 HG High Gate Connect to the gate terminal of the external MOSFET switch.
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LM5088/LM5088Q
Pin(S) Name Description Application Information
15 BOOT Input for bootstrap capacitor An external capacitor is required between the BOOT and the SW pins to provide
bias to the MOSFET gate driver. The capacitor is charged from VCC via an
internal diode during the off-time of the buck switch.
16 VCC Output of the bias regulator VCC tracks VIN up to the regulation level (7.8V Typ). A 0.1 µF to 10 µF ceramic
decoupling capacitor is required. An external voltage between 8.3V and 13V
can be applied to this pin to reduce internal power dissipation.
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LM5088/LM5088Q
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VIN, VOUT to GND 76V
BOOT to GND 90V
SW to GND -2V to 76V
VCC to GND -0.3V to 16V
HG to SW -0.3V to BOOT
+0.3V
EN to GND 14V
BOOT to SW -0.3V to 16V
CS, CSG to GND -0.3V to 0.3V
All other inputs to GND -0.3V to 7V
ESD Rating
Human Body Model 2 kV
Storage Temperature Range −65°C to + 150°C
Junction Temperature + 150°C
Operating Ratings (Note 1)
VIN Voltage 4.5V to 75V
VCC Voltage (externally supplied) 8.3V to 13V
Operation Junction Temperature −40°C to + 125°C
Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the
junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical
correlation. Typical values represent at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the
following conditions apply: VVIN = 48V, VVCC= 8V, VEN = 5V RRT = 31.6 kΩ, No load on HG. See Note 4.
Symbol Parameter Conditions Min Typ Max Units
VIN SUPPLY
IBIAS VIN Operating Current VFB = 1.3V 3.8 5.5 mA
ISTANDBY VIN Standby Current VEN = 1V 2.9 3.6 mA
ISHUTDOWN VIN Shutdown Current VEN = 0V 15 26 µA
VCC REGULATOR
VVCC(Reg) VCC Regulation VVCC = open 7.4 7.8 8.2 V
VVCC(Reg) VCC Regulation VVIN = 4.5V,VVCC=open 4.3 4.5 V
VCC Sourcing Current Limit VVCC = 0 30 35 mA
VVCC(UV) VCC Under-Voltage Lockout Threshold Positive going VVCC 3.7 44.2 V
VCC Under-Voltage Hysteresis 200 mV
ENABLE THRESHOLDS
EN Shutdown Threshold VEN Rising 320 400 480 mV
EN Shutdown Hysteresis VEN Falling 100 mV
EN Standby Threshold VEN Rising 1.1 1.2 1.3 V
EN Standby Hysteresis VEN Falling 120 mV
EN Pull-up Current Source VEN = 0V 5 µA
SOFT- START
SS Pull-up Current Source VSS = 0V 811 13 µA
FB to SS Offset VFB = 1.3V 150 mV
ERROR AMPLIFIER
VREF FB Reference Voltage Measured at FB Pin
FB = COMP
1.187 1.205 1.223 V
FB Input Bias Current VFB = 1.2V 18 100 nA
COMP Sink/Source Current 3 mA
AOL DC Gain 60 dB
FBW Unity gain bandwidth 3 MHz
PWM COMPARATORS
THG(OFF) Forced HG Off-time 185 280 365 ns
TON(MIN) Minimum HG On-time VVIN = 60V 55 ns
COMP to PWM comparator offset 930 mV
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LM5088/LM5088Q
Symbol Parameter Conditions Min Typ Max Units
OSCILLATOR (RT Pin)
LM5088-2 (Non-Dithering)
Fnom1 Nominal Oscillator Frequency RRT = 31.6 kΩ180 200 220 kHz
Fnom2 RRT = 11.3 kΩ430 500 565 kHz
LM5088-1 (Dithering)
Fmin Dithering Range Minimum Dither Frequency Fnom-5% kHz
Fmax Maximum Dither Frequency Fnom+5% kHz
SYNC
SYNC positive threshold 2.3 V
SYNC Pulse Width 15 150 ns
CURRENT LIMIT
VCS(TH) Cycle by cycle sense voltage threshold VRAMP = 0V 112 120 136 mV
Cycle by Cycle Current Limit Delay VRAMP = 2.5V 280 ns
Buck Switch VDS protection VIN to SW 1.5 V
CURRENT LIMIT RESTART (RES Pin)
Vresup RES Threshold Upper (rising) VCS = 0.125 1.1 1.2 1.3 V
Vresdown RES Threshold Lower (falling) 0.1 0.2 0.3 V
Icharge Charge source current VCS >= 0.125 40 50 65 µA
Idischarge Discharge sink current VCS < 0.125 20 27 34 µA
Irampdown Discharge sink current -(post fault) 0.8 1.2 1.6 µA
RAMP GENERATOR
IRAMP1 RAMP Current 1 VVIN = 60V, VOUT = 10V 235 295 345 µA
IRAMP2 RAMP Current 2 VVIN = 10V, VOUT = 10V 18 25 30 µA
VOUT Bias Current VOUT = 48V 250 µA
RAMP Output Low Voltage VVIN = 60V, VOUT = 10V 200 mV
HIGH SIDE (HG) GATE DRIVER
VOLH HG Low-state Output Voltage IHG = 100 mA 115 215 mV
VOHH HG High-state Output Voltage IHG = -100 mA, VOHH = VBOOT - VHG 240 mV
HG Rise Time Cload = 1000 pF 12 ns
HG Fall Time Cload = 1000 pF 6 ns
IOHH Peak HG Source Current VHG = 0V 1.5 A
IOLH Peak HG Sink Current VHG = VVCC 2 A
BOOT UVLO BOOT to SW 3 V
Pre RDS(ON) Pre-Charge Switch ON- resistance IVCC = 1 mA 72 Ω
Pre-Charge switch ON time 300 ns
THERMAL
TSD Thermal Shutdown Temperature Junction Temperature Rising 165 °C
Thermal Shutdown Hysterisis Junction Temperature Falling 25 °C
θJC Thermal Resistance Junction to Case 6 °C /W
θJA Thermal Resistance Junction to Ambient 40 °C /W
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Note 3: RAMP and COMP are output pins. As such they are not specified to have an external voltage applied.
Note 4: Typical specifications represent the most likely parametric norm at 25°C operation.
Note 5: For detailed information on soldering plastic MSOP packages refer to the Packaging Data Book available from National Semiconductor Corporation.
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LM5088/LM5088Q
Typical Performance Characteristics
Typical Application Circuit Efficiency
30083940
VCC vs VIN
30083941
VVCC vs IVCC
30083942
Shutdown Current
30083943
Frequency vs RRT
30083944
Frequency vs VVCC
30083945
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LM5088/LM5088Q
VFB vs Temperature
30083946
Forced-Off Time vs Temperature
30083947
Soft-Start vs Temperature
30083948
Current-Limit vs Temperature
30083949
Frequency vs Temperature
30083950
Error Amplifier Gain/Phase
30083951
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LM5088/LM5088Q
Block Diagram
30083904
FIGURE 1. Block Diagram
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LM5088/LM5088Q
Detailed Operation
The LM5088 Wide Input Range Buck Controller features all
the functions necessary to implement an efficient high voltage
step-down converter using a minimum number of external
components. The control method is based on peak current
mode control utilizing an emulated current ramp. Peak current
mode control provides inherent line voltage feed-forward, cy-
cle-by-cycle current limiting and ease of loop compensation.
The use of an emulated control ramp reduces noise sensitivity
of the pulse-width modulation circuit, allowing reliable pro-
cessing of very small duty cycles necessary in high input
voltage applications. The operating frequency is user pro-
grammable from 50 kHz to 1 MHz. The LM5088-1 provides a
±5% frequency dithering function to reduce the conducted
and radiated EMI, while the LM5088-2 provides a versatile
restart timer for overload protection. Additional features in-
clude the low dropout bias regulator, tri-level enable input to
control shutdown and standby modes, soft-start, and voltage
tracking and oscillator synchronization capability. The device
is available in a thermally enhanced TSSOP-16EP pin pack-
age.
The functional block diagram and typical application schemat-
ic of the LM5088 are shown in figure 1. The LM5088 is well
suited for a wide range of applications where efficient step-
down of high, unregulated input voltage is required. The
LM5088’s typical applications include Telecom, Industrial and
Automotive.
High Voltage Low-Dropout
Regulator
The LM5088 contains a high voltage, low-dropout regulator
that provides the VCC bias supply for the controller and the
bootstrap MOSFET gate driver. The input pin (VIN) can be
connected directly to an input voltage as high as 75V. The
output of the VCC regulator (7.8V) is internally current limited
to 30 mA. Upon power up, the regulator sources current into
the capacitor connected to the VCC pin. When the voltage at
the VCC pin exceeds the upper VCC UV threshold of 4.0V
and the EN pin is greater than 1.2 Volts, the output (HG) is
enabled and a soft-start sequence begins. The output is ter-
minated if VCC falls below its lower UV threshold (3.8V) or
the EN pin falls below 1.1V. When VIN is less than VCC reg-
ulation point of 7.8V, then the internal pass device acts as a
switch. Thereby, VCC tracks VIN with a voltage drop deter-
mined by the RDS(ON) of the internal switch and operating
current of the controller. The required VCC capacitor value is
dependant on system startup characteristics with a minimum
value no less than 0.1 µF.
An auxiliary supply voltage can be applied to the VCC pin to
reduce the IC power dissipation. If the auxiliary voltage is
greater than 8.2V, the internal regulator will be disabled. The
VCC regulator series pass transistor includes a diode be-
tween VCC and VIN that should not be forward biased in
normal operation.
In high voltage applications, additional care should be taken
to ensure that the VIN pin does not exceed the absolute max-
imum voltage rating of 76V. During line or load transients,
voltage ringing on the VIN pin that exceeds the absolute max-
imum ratings may damage the IC. Both careful PC board
layout and the use of high quality bypass capacitors located
close to the VIN and GND pins are essential.
Line Under-Voltage Detector
The LM5088 contains a dual level under-voltage lockout (UV-
LO) circuit. When the EN pin is below 0.4V, the controller is
in a low current shutdown mode. When the EN pin is greater
than 0.4V but less than 1.2V, the controller is in a standby
mode. In standby mode the VCC regulator is active but the
output switch is disabled and the SS pin is held low. When the
EN pin exceeds 1.2V and VCC exceeds the VCC UV thresh-
old, the SS pin and the output switch is enabled and normal
operation begins. An internal 5 µA pull-up current source at
the EN pin configures the controller to be fully operational if
the EN pin is left open.
An external VIN UVLO set-point voltage divider from VIN to
GND can be used to set the minimum startup input voltage of
the controller. The divider must be designed such that the
voltage at the EN pin exceeds 1.2V (typ) when VIN is in the
desired operating range. The internal 5 µA pull-up current
source must be included in calculations of the external set-
point divider. 100 mV of hysteresis is included for both the
shutdown and standby thresholds. The EN pin is internally
connected to a 1 kΩ resistor and an 8V zener clamp. If the
voltage at the EN pin exceeds 8V, the bias current for the EN
pin will increase at the rate of 1mA/V. The voltage at the EN
pin should never exceed 14V.
Oscillator and Sync Capability
The LM5088 oscillator frequency is set by a single external
resistor connected between the RT pin and the GND pin. The
RT resistor should be located very close to the device. To set
a desired oscillator frequency (fSW), the necessary value of
RT resistor can be calculated from the following equation:
The RT pin can also be used to synchronize the internal os-
cillator to an external clock. The internal oscillator is synchro-
nized to an external clock by AC coupling a positive edge into
the RT/SYNC pin. The RT/SYNC pin voltage must exceed 3V
to trip the internal clock synchronization pulse detector. The
free-running frequency should be set nominally 15% below
the external clock frequency and the pulse width applied to
the RT/SYNC pin must be less than 150ns. Synchronization
to an external clock more than twice the free-running fre-
quency can produce abnormal behavior of the pulse-width
modulator.
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LM5088/LM5088Q
30083905
FIGURE 2. Basic Enable Configuration
Error Amplifier and PWM
Comparator
The internal high gain error amplifier generates an error signal
proportional to the difference between the regulated output
voltage and an internal precision voltage reference (1.205V).
The output of the error amplifier is connected to the COMP
pin allowing the user to connect loop compensation compo-
nents. Generally a type II network, as illustrated in Figure 1,
is sufficient. This network creates a pole at DC, a mid-band
zero for phase boost and a high frequency pole for noise re-
duction. The PWM comparator compares the emulated cur-
rent signal from the RAMP generator to the error amplifier
output voltage at the COMP pin. A typical control loop gain/
phase plot is shown in performance curves section of this
document.
Ramp Generator
The ramp signal used for the pulse width modulator in current
mode control is typically derived directly from the buck switch
current. This signal corresponds to the positive slope portion
of the buck inductor current. Using this signal for the PWM
ramp simplifies the control loop transfer function to a single
pole response and provides inherent input voltage feed-for-
ward compensation. The disadvantage of using the buck
switch current signal for PWM control is the large leading
edge spike due to circuit parasitics which must be filtered or
blanked. Also, the current measurement may introduce sig-
nificant propagation delays. The filtering time, blanking time
and propagation delay limit the minimum achievable pulse
width. In applications where the input voltage may be rela-
tively large in comparison to the output voltage, controlling
small pulse widths and duty cycles is necessary for regulation.
The LM5088 utilizes a unique ramp generator which does not
actually measure the buck switch current but rather recon-
structs or emulates the signal. Emulating the inductor current
provides a ramp signal that is free of leading edge spikes and
measurement or filtering delays. The current reconstruction
is comprised of two elements; a sample & hold DC level and
an emulated current ramp.
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LM5088/LM5088Q
30083907
FIGURE 3. Composition of Current Sense Signal
The sample & hold DC level illustrated in Figure 3 is derived
from a measurement of the re-circulating (or free-wheeling)
diode current. The diode current flows through the current
sense resistor connected between the CS and CSG pins. The
voltage across the sense resistor is sampled and held just
prior to the onset of the next conduction interval of the buck
switch. The diode current sensing and sample & hold provide
the DC level for the reconstructed current signal. The positive
slope inductor current ramp is emulated by an external ca-
pacitor connected from the RAMP pin to GND and an internal
voltage controlled current source. The ramp current source
that emulates the inductor current is a function of the VIN and
VOUT voltages per the following equation:
IRAMP = 5 µA/V x (VIN x VOUT) + 25 µA
Proper selection of the RAMP capacitor depends upon the
selected value of the output inductor and the current sense
resistor (RS). For proper current emulation, the DC sample &
hold value and the ramp amplitude must have the same de-
pendence on the load current. That is:
Where, gm is the ramp current generator transconductance (5
µA/V) and A is the gain of the current sense amplifier (10V/
V). The RAMP capacitor should connected directly to the
RAMP and GND pins of the IC.
For duty cycles greater than 50%, peak current mode control
circuits are subject to sub-harmonic oscillation. Sub-harmonic
oscillation is normally characterized by alternating wide and
narrow pulses at the SW pin. Adding a fixed slope voltage
ramp (slope compensation) to the current sense signal pre-
vents this oscillation. The 25 µA offset current supplied by the
emulated current source provides a fixed slope to the ramp
signal. In some high output voltage, high duty cycles applica-
tions; additional slope compensation may be required. In
these applications, a pull-up resistor may be added between
the RAMP and VCC pins to increase the ramp slope com-
pensation. A formula to configure pull-up resistor is shown in
Applications Information section.
Dropout Voltage Reduction
The LM5088 features unique circuitry to reduce the dropout
voltage. Dropout voltage is defined as the difference between
the minimum input voltage to maintain regulation and the out-
put voltage (VINmin - Vout). Dropout voltage thus determines
the lowest input voltage at which the converter maintains reg-
ulation. In a buck converter, dropout voltage primarily de-
pends upon the maximum duty cycle. The maximum duty
cycle is dependant on the oscillator frequency and minimum
off-time.
An approximation for the dropout voltage is:
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LM5088/LM5088Q
Where, TOSC = 1/fSW and TOFF (max) is the forced off-time (280
ns typical, 365 ns maximum); fSW and TOSC are the oscillator
frequency and oscillator period, respectively.
From the above equation, it can be seen that for a given out-
put voltage, reducing the dropout voltage requires either re-
ducing the forced off-time or oscillator frequency (1/TOSC).
The forced off-time is limited by the time required to replenish
the bootstrap capacitor and time required to sample the re-
circulating diode current. The 365 ns forced off-time of the
LM5088 controller is a good trade-off between these two re-
quirements. Thus the LM5088 reduces dropout voltage by
dynamically decreasing the operating frequency during
dropout. The Dynamic Frequency Control (DFC) is achieved
using a dropout monitor, which detects a dropout condition
and reduces the operating frequency. The operating frequen-
cy will continue to decrease with decreasing input voltage until
the frequency falls to the minimum value set by the DFC cir-
cuitry.
fSW(minDFC) ≊ 1/3 x fSW(nominal)
If the VIN voltage continues to fall below this point, output
regulation can no longer be maintained. The oscillator fre-
quency will revert back to the nominal operating frequency set
by the RT resistor when the input voltage increases above the
dropout range. DFC circuitry does not affect the PWM during
normal operating conditions.
30083910
FIGURE 4. Dropout Voltage Reduction using Dynamic Frequency Control
Frequency Dithering
(LM5088-1 Only)
Electro-Magnetic Interference (EMI) emissions are funda-
mentally associated with switch-mode power supplies due to
sharp voltage transitions, diode reverse recovery currents
and the ringing of parasitic L-C circuits. These emissions will
conduct back to the power source or radiate into the environ-
ment and potentially interfering with nearby electronic sys-
tems. System designers typically use a combination of
shielding, filtering and layout techniques to reduce the EMI
emissions sufficiently to satisfy EMI emission standards es-
tablished by regulatory bodies. In a typical fixed frequency
switching converter, narrowband emissions typically peak at
the switching frequency with the successive harmonics hav-
ing less energy. Dithering the oscillator frequency spreads the
EMI energy over a range of frequencies, thus reducing the
peak levels. Dithering can also reduce the system cost by re-
ducing the size and quantity of EMI filtering components.
The LM5088-1 provides an optional frequency dithering func-
tion which is enabled by connecting a capacitor from the dither
pin (DITH) to GND. Connecting the DITH pin directly to GND
disables frequency dithering causing the oscillator to operate
at the frequency established by the RT resistor. As shown in
Figure 5, the Cdither capacitor is used to generate a triangular
wave centered at 1.2V. This triangular waveform is used to
manipulate the oscillator circuit such that the oscillator fre-
quency modulates from -5% to +5% of the nominal operating
frequency set by the RT resistor. The Cdither capacitor value
sets the rate of the low frequency modulation i.e., a lower val-
ue Cdither capacitor will modulate the oscillator frequency from
-5% to +5% at a faster rate than a higher value capacitor. For
the dither circuit to work effectively the modulation rate must
be much less than the oscillator frequency (fSW) , Cdither should
be selected such that;
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LM5088/LM5088Q
30083912
FIGURE 5. Frequency Dithering Scheme
30083913
FIGURE 6. Conducted Emissions Measured at the Input
of a LM5088 Based Buck Converter
Figure 6 shows the conducted emissions on the LM5088
evaluation board input power line. It can be seen from the
above picture that, the peak emissions with non-dithering op-
eration are centered narrowly at the operating frequency of
the converter. With dithering operation, the conducted emis-
sions are spread around the operating frequency and the
maximum amplitude is reduced by approximately 10dB. (Fig-
ure 6 was captured using a Chroma DC power supply model
number 62006P and an Agilent network analyzer model num-
ber 4395A).
Cycle-by-Cycle Current Limit
The LM5088 contains a current limit feature that protects the
circuit from extended over current conditions. The emulated
current signal is directly proportional to the buck switch cur-
rent and is applied to the current limit comparator. If the
emulated current exceeds 1.2V, the PWM cycle is terminated.
The peak inductor current required to trigger the current limit
comparator is given by:
Where, A = 10V/V is the current sense amplifier gain, CRAMP
is the Ramp capacitor, RS is the sense resistor,
is the voltage ramp added for slope compensation and 1.2V
is the reference of the current limit comparator.
Since the current that charges the RAMP capacitor is propor-
tional to VIN-VOUT, if the output is suddenly shorted, the
VOUT term is zero and the RAMP charging current increases.
The increased RAMP charging current will immediately re-
duce the PWM duty cycle.The LM5088 also includes a buck
switch protection scheme. A dedicated comparator monitors
www.national.com 14
LM5088/LM5088Q
the drain to source voltage of the buck FET when it is turned
ON, if the VDS exceeds 1.5V, the comparator turns off the buck
FET immediately. This feature will help protect the buck FET
in catastrophic conditions such as a sudden saturation of the
inductor.
Overload Protection Timer
(LM5088-2 Only)
To further protect the external circuitry during a prolonged
over current condition, the LM5088-2 provides a current limit
timer to disable the switching regulator and provide a delay
before restarting (hiccup mode). The number of current limit
events required to trigger the restart mode is programmed by
an external capacitor at the RES pin. During each PWM cycle,
as shown in Figure 8, the LM5088 either sinks current from
or sources current into the RES capacitor. If the emulated
current ramp exceeds the 1.2V current limit threshold, the
present PWM cycle is terminated and the LM5088 sources 50
µA into the RES pin capacitor during the next PWM clock cy-
cle. If a current limit event is not detected in a given PWM
cycle, the LM5088 disables the 50 µA source current and
sinks 27 µA from the RES pin capacitor during the next cycle.
In an overload condition, the LM5088 protects the converter
with cycle-by-cycle current limiting until the voltage at RES
pin reaches 1.2V. When RES reaches 1.2V, a hiccup mode
sequence is initiated as follows:
•The SS capacitor is fully discharged.
•The RES capacitor is discharged with 1.2 µA
•Once the RES capacitor reaches 0.2V, a normal soft-start
sequence begins. This provides a time delay before
restart.
•If the overload condition persists after restart, the cycle
repeats.
•If the overload condition no longer exists after restart, the
RES pin is held at ground by the 27 µA discharge current
source and normal operation resumes.
The overload protection timer is very versatile and can be
configured for the following modes of protection:
1. 1. Cycle-by-Cycle only: The hiccup mode can be
completely disabled by connecting the RES pin to GND.
In this configuration, the cycle-by-cycle protection will
limit the output current indefinitely and no hiccup
sequence will occur.
2. 2. Delayed Hiccup: Connecting a capacitor to the RES
pin provides a programmed number of cycle-by-cycle
current limit events before initiating a hiccup mode
restart, as previously described. The advantage of this
configuration is that a short term overload will not cause
a hiccup mode restart but during extended overload
conditions, the average dissipation of the power
converter will be very low.
3. 3. Externally Controlled Hiccup: The RES pin can also
be used as an input. By externally driving the pin to a level
greater than the 1.2V hiccup threshold, the controller will
be forced into the delayed restart sequence. For
example, the external trigger for a delayed restart
sequence could come from an over-temperature
protection or an output over-voltage sensor.
30083916
FIGURE 7. Current Limit Restart Circuit
15 www.national.com
LM5088/LM5088Q
30083917
FIGURE 8. Current Limit Restart Timing Diagram
Soft-Start
The soft-start (SS) feature forces the output to rise linearly
until it reaches the steady-state operating voltage set by the
feedback resistors. The LM5088 will regulate the FB pin to the
SS pin voltage or the internal 1.205V reference, which ever is
lower. At the beginning of the soft-start sequence VSS = 0V
and, an internal 11 µA current source gradually increases the
voltage of the external soft-start capacitor (CSS). An internal
amplifier clamps the SS pin voltage at 120 mV above the FB
voltage. This feature provides soft-start controlled recovery
with reduced output overshoot in the event that the output
voltage momentarily dips out of regulation.
HG Output
The LM5088 provides a high current, high-side driver and as-
sociated level shift circuit to drive an external N-Channel
MOSFET. The gate driver works in conjunction with an inter-
nal diode and external bootstrap capacitor. A ceramic boot-
strap capacitor is recommended, and should be connected
directly between the BOOT and SW pins. During the off-time
of the buck switch, the bootstrap capacitor charges from VCC
through an internal diode. When operating with a high PWM
duty cycle, the HG output will be forced-off each cycle for 365
ns (max) to ensure that BOOT capacitor is recharged. A “pre-
charge” circuit, comprised of a MOSFET between SW and
GND, is turned ON during the forced off-time to help replenish
the BOOT capacitor. The pre-charge circuit provides charge
to the BOOT capacitor under light load or pre-biased load
conditions when the SW voltage does not remain low during
the entire off-time.
Thermal Protection
Internal thermal shutdown circuitry is provided to protect the
integrated circuit in the event the maximum operating tem-
perature is exceeded. When activated, typically at 165°C, the
controller is forced into a low power reset state, disabling the
output driver and the bias supply of the controller. The feature
prevents catastrophic failures from accidental device over-
heating.
Applications Information
EXTERNAL COMPONENTS
The procedure for calculating the external components is il-
lustrated with the following design example. The Bill of Mate-
rials for this design is listed in Table 1.The circuit shown in
Figure 14 and 15 is configured for the following specifications:
•Output Voltage = 5V
•Input Voltage = 5.5V to 55V
•Maximum Load Current = 7A
•Switching Frequency = 250 kHz
TIMING RESISTOR
The RT resistor sets the oscillator switching frequency. High-
er frequencies result in smaller size components such as the
inductor and filter capacitors. However, operating at higher
frequencies also results in higher MOSFET and diode switch-
ing losses. Operation at 250 kHz was selected for this exam-
ple as a reasonable compromise between size and efficiency.
The value of RT resistor can be calculated as follows:
The nearest standard value of 24.9Ω was chosen for RT.
OUTPUT INDUCTOR
The inductor value is determined based on the operating fre-
quency, load current, ripple current and the input and output
voltages.
Knowing the switching frequency (fSW), maximum ripple cur-
rent (IPP), maximum input voltage (VIN(max)) and the nominal
output voltage (VOUT), the inductor value can be calculated as
follows:
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LM5088/LM5088Q
30083918
FIGURE 9. Inductor Current
The maximum ripple current occurs at the maximum input
voltage. Typically, IPP is selected between 20% and 40% of
the full load current. Higher ripple current will result in a small-
er inductor. However, it places more burden on the output
capacitor to smooth out the ripple current to achieve low out-
put ripple voltage. For this example 40% ripple was chosen
for a smaller sized inductor.
The nearest standard value of 6.8 µH will be used. To prevent
saturation, the inductor must be rated for the peak current.
During normal operation, the peak current occurs at maxi-
mum load current (plus maximum ripple). With properly
scaled component values, the peak current is limited to VCS
(TH)/RS During overload conditions. At the maximum input
voltage with a shorted output, the chosen inductor must be
evaluated at elevated temperature. It should be noted that the
saturation current rating of inductors drops significantly at el-
evated temperatures.
CURRENT SENSE RESISTOR
The current limit value (ILIM) is set by the current sense resis-
tor (RS).
RS can be calculated by
Some ‘margin’ beyond the maximum load current is recom-
mended for the current limit threshold. In this design example,
the current limit is set at 10% above the maximum load cur-
rent, resulting in a RS value of 10 mΩ. The CS and CSG pins
should be Kelvin connected to the current sense resistor.
RAMP CAPACITOR
With the inductor and sense resistor value selected, the value
of the ramp capacitor (CRAMP) necessary for the emulation
ramp circuit is given by:
Where, L is the value of the output inductor, gm is the ramp
generator transconductance (5 µA/V) and A is the current
sense amplifier gain (10V/V). For the current design example,
the ramp capacitor is calculated as:
The next lowest standard value 270 pF was selected for
CRAMP. An NPO capacitor with 5% or better tolerance is rec-
ommended. It should be noted that selecting a capacitor value
lower than the calculated value will increase the slope com-
pensation. Furthermore, selecting a ramp capacitor substan-
tially lower or higher than the calculated value will also result
in incorrect PWM operation.
For VOUT > 5V, internal slope compensation provided by the
LM5088 may not be adequate for certain operating conditions
especially at low input voltages. A pull-up resistor may be
added from VCC to RAMP the pin to increase the slope com-
pensation. Optimal slope compensation current may be cal-
culated from
IOS = VOUT x 5 µA/V
and RRAMP is given by
17 www.national.com
LM5088/LM5088Q
30083926
FIGURE 10. Additional Slope Compensation for
VOUT > 5V
OUTPUT CAPACITORS
The output capacitors smooth the inductor current ripple and
provide a source of charge for load transient conditions. The
output capacitor selection is primarily dictated by the following
specifications:
1. Steady-state output peak-peak ripple (ΔVPK-PK)
2. Output voltage deviation during transient condition (ΔVTran-
sient)
For the 5V output design example, ΔVPK-PK = 50 mV (1% of
VOUT) and ΔTTransient = 100 mV (2% of VOUT) was chosen.
The magnitude of output ripple primarily depends on ESR of
the capacitors while load transient voltage deviation depends
both on the output capacitance and ESR.
When a full load is suddenly removed from the output, the
output capacitor must be large enough to prevent the inductor
energy to raise the output voltage above the specified maxi-
mum voltage. In other words, the output capacitor must be
large enough to absorb the inductor’s maximum stored ener-
gy. Equating, the stored energy equations of both the inductor
and the output capacitor it can be shown that:
Evaluating, the above equation with a ΔVout of 100 mV re-
sults in an output capacitance of 475 µF. As stated earlier, the
maximum peak to peak ripple primarily depends on the ESR
of the output capacitor and the inductor ripple current. To sat-
isfy the ΔVPK-PK of 50 mV with 40% inductor current ripple, the
ESR should be less than 15 mΩ. In this design example a 470
µF aluminum capacitor with an ESR of 10 mΩ is paralleled
with two 47 µF ceramic capacitors to further reduce the ESR.
INPUT CAPACITORS
The input power supply typically has large source impedance
at the switching frequency. Good quality input capacitors are
necessary to limit the ripple voltage at the VIN pin while sup-
plying most of the switch current during the on-time. When the
buck switch turns ON, the current into the external FET steps
to the valley of the inductor current waveform at turn-on,
ramps up to the peak value, and then drops to zero at turn-
off. The input capacitors should be selected for RMS current
rating and minimum ripple voltage. A good approximation for
the ripple current is IRMS > IOUT/2.
Quality ceramic capacitors with a low ESR should be selected
for the input filter. To allow for capacitor tolerances and volt-
age rating, five 2.2 µF, 100V ceramic capacitors were select-
ed. With ceramic capacitors, the input ripple voltage will be
triangular and will peak at 50% duty cycle. Taking into account
the capacitance change with DC bias a worst case input peak-
to-peak ripple voltage can be approximated as:
When the converter is connected to an input power source, a
resonant circuit is formed by the line impedance and the input
capacitors. This can result in an overshoot at the VIN pin and
could result in VIN exceeding its absolute maximum rating.
Because of those conditions, it is recommended that either
an aluminum type capacitor with an ESR or increasing
CIN>10 x LIN While using aluminum type capacitor care
should be taken to not exceed its maximum ripple current rat-
ing. Tantalum capacitors must be avoided at the input as they
are prone to shorting.
VCC CAPACITOR
The capacitor at the VCC pin provides noise filtering and sta-
bility for the VCC regulator. The recommended value should
be no smaller than 0.1 µF, and should be a good quality, low
ESR, ceramic capacitor. A value of 1 µF was selected for this
design.
BOOTSTRAP CAPACITOR
The bootstrap capacitor between HB and SW pins supplies
the gate current to charge the high-side MOSFET gate at
each cycle’s turn-on as well as supplying the recovery charge
for the bootstrap diode (D1).The peak current can be several
amperes. The recommended value of the bootstrap capacitor
is at least 0.022 µF and should be a good quality, low ESR,
ceramic capacitor located close to the pins of the IC. The ab-
solute minimum value for the bootstrap capacitor is calculated
as:
Where, Qg is the high-side MOSFET gate charge and ΔVHB
is the tolerable voltage droop on CHB, which is typically less
than 5% of the VCC. A value of 0.1 µF was selected for this
design.
SOFT-START CAPACITOR
The capacitor at the SS capacitor determines the soft-start
time, the output voltage to reach the final regulated value. The
value of CSS for a given time is determined from:
For this design example, a value of 0.022 µF was chosen for
a soft start time of approximately 2 ms.
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LM5088/LM5088Q
OUTPUT VOLTAGE DIVIDER
RFB1 and RFB2 set the output voltage level, the ratio of these
resistors can be calculated from:
1.62 kΩ was chosen for RFB1 in this design which results in a
RFB2 value of 5.11 kΩ. A reasonable guide is to select the
value of RFB1 value such that the current through the resistor
(1.2V/ RFB1) is in between 1 mA and 100 µA.
UVLO DIVIDER
A voltage divider can be connected to the EN pin to the set
the minimum startup voltage (VIN(min)) of the regulator. If this
feature is required, set the value of RUV2 between 10 kΩ and
100 kΩ and then calculate RUV1 from:
In this design, for a VIN(min) of 5V, RUV2 was selected to be
54.9 kΩ resulting in a RUV1value of 16.2 kΩ. it is recommend-
ed to install a capacitor parallel to RUV1 for filtering. If the EN
pin is left open, the LM5088 will begin operation once the up-
per VCC UV threshold of 4.0V (typ) is reached.
RESTART CAPACITOR (LM5008-2 only)
The basic operation of the hiccup mode current limit is de-
scribed in the functional description. In the LM5088-2 appli-
cation example the RES pin is configured for delayed hiccup
mode. Please refer to the functional description to configure
this pin in alternate configurations and also refer figure 8 for
the timing diagram. The delay time to initiate a hiccup cycle
(t1) is programmed by the selection of RES pin capacitor. In
the case of continuous cycle-by-cycle current limit detection
at the CS pin, the time required for CRES to reach the 1.2V is
given by
The cool down time (t2) is set by the time taken to discharge
the RES cap with 1.2 µA current source. This feature will re-
duce the input power drawn by the converter during a pro-
longed over current condition. In this application 500 µs of
delay time was selected. The minimum value of CRES capac-
itor should be no less than 0.022 µF.
MOSFET SELECTION
Selection of the Buck MOSFET is governed by the same
tradeoffs as the switching frequency. Losses in power MOS-
FETs can be broken down into conduction losses and switch-
ing losses. The conduction loss is given by:
PDC = D x (IO2 x RDS(ON) x 1.3)
Where, D is the duty cycle and IO is the maximum load cur-
rent. The factor 1.3 accounts for the increase in MOSFET on-
resistance due to heating. Alternatively, for a more precise
calculation, the factor of 1.3 can be ignored and the on-resis-
tance of the MOSFET can be estimated using the RDS(ON) vs.
Temperature curves in the MOSFET datasheet.
The switching loss occurs during the brief transition period as
the MOSFET turns on and off. During the transition period
both current and voltage are present in the MOSFET. The
switching loss can be approximated as:
PSW = 0.5 x VIN x IO x (tR + tF) x fSW
Where, tR and tF are the rise and fall times of the MOSFET.
The rise and fall times are usually mentioned in the MOSFET
datasheet or can be empirically observed on the scope. An-
other loss, which is associated with the buck MOSFET is the
“gate-charging loss”. This loss differs from the above two
losses in the sense that it is dissipated in the LM5088 and not
in the MOSFET itself. Gate charging loss, PGC, results from
the current driving charging the gate capacitance of the power
MOSFETs and is approximated as:
PGC = VCC x Qg x fSW
For this example with the maximum input voltage of 55V, the
Vds breakdown rating of the selected MOSFET must be
greater than 55V plus any ringing across drain to source due
to parasitics. In order to minimize switching time and gate
drive losses, the selected MOSFET must also have low gate
charge (Qg). A good choice of MOSFET for this design ex-
ample is the SI7148DP which has a total gate charge of 30nC
and rise and fall times of 10 ns and 12 ns respectively.
DIODE SELECTION
A Schottky type re-circulating diode is required for all LM5088
applications. The near ideal reverse recovery current tran-
sients and low forward voltage drop are particularly important
diode characteristics for high input voltage and low output
voltage applications common to LM5088. The diode switching
loss is minimized in a Schottky diode because of near ideal
reverse recovery. The conduction loss can be approximated
by:
Pdc_diode = (1 - D) x IO x VF
Where, VF is the forward drop of the diode. The worst case is
to assume a short circuit load condition. In this case, the diode
will carry the output current almost continuously. The reverse
breakdown rating should be selected for the maximum input
voltage level plus some additional safety margin to withstand
ringing at the SW node. For this application a 60V On Semi-
conductor Schottky diode (MBRB2060) with a specified for-
ward drop of 0.6V at 7A at a junction temperature of 50°C was
selected. For output loads of 5A and greater and high input
voltage applications, a diode in a D2PAK package is recom-
mended to support the worst case power dissipation
SNUBBER COMPONENTS SELECTION
Excessive ringing and spikes can cause erratic operation and
couple spikes and noise to the output. Voltage spikes beyond
the rating of the LM5088 or the re-circulating diode can dam-
age these devices. A snubber network across the power
diode reduces ringing and spikes at the switching node. Se-
lecting the values for the snubber is best accomplished
through empirical methods. First, make sure that the lead
lengths for the snubber connections are very short. For the
current levels typical for the LM5088, a resistor value between
3 and 10Ω should be adequate. As a rule of thumb, a snubber
capacitor which is 4~5 times the Schottky diode’s junction ca-
pacitance will reduce spikes adequately. Increasing the value
of the snubber capacitor will result in more damping but also
results in higher losses. The resistor’s power dissipation is
independent of the resistance value as the resistor dissipates
the energy stored by the snubber capacitor. The resistor’s
power dissipation can be approximated as:
PR_SNUB = CSNUB x VINmax2 x fSW
19 www.national.com
LM5088/LM5088Q
ERROR AMPLIFIER COMPENSATION
RCOMP, CCOMP and CHF configure the error amplifier gain
characteristics to accomplish a stable voltage loop gain. One
advantage of current mode control is the ability of to close the
loop with only two feedback components RCOMP and CCOMP.
The voltage loop gain is the product of the modulator gain and
the error amplifier gain. For this example, the modulator can
be treated as an ideal voltage-to-current (transconductance)
converter, The DC modulator gain of the LM5088 can be
modeled as:
DC Gain (MOD) = RLOAD/ (A x RS)
The dominant low frequency pole of the modulator is deter-
mined by the load resistance (RLOAD) and the output capaci-
tance (COUT). The corner frequency of this pole is:
For, RLOAD = 5V/7A = 0.714Ω and COUT = 500 µF (effective),
then FP(MOD) = 550 Hz.
DC Gain(MOD) = 0.714/ (10 x 10 mΩ) = 7.14 = 17dB
For the 5V design example the modulator gain vs. frequency
characteristic was measured as shown in Figure 11.
30083934
FIGURE 11. Modular Gain Phase
Components RCOMP and CCOMP configure the error amplifier
as a type II compensation configuration. The DC gain of the
amplifier is 80dB which has a pole at low frequency and a zero
at FZero = 1/(2π x RCOMP x CCOMP). The error amplifier zero is
set such that it cancels the modulator pole leaving a single
pole response at the crossover frequency of the voltage loop.
A single pole response at the crossover frequency yields a
very stable loop with 90° of phase margin. For the design ex-
ample, a target loop bandwidth (crossover frequency) of 15
kHz was selected. The compensation network zero (FZero)
should be at least an order of magnitude lower than the target
crossover frequency. This constrains the product of RCOMP
and CCOMP for a desired compensation network zero 1/ (2π
x RCOMP x CCOMP) to be less than 1.5 kHz. Increasing
RCOMP, while proportionally decreasing CCOMP, decreases the
error amp gain. For the design example CCOMP was selected
to be 0.015 µF and RCOMP was selected to be 18 kΩ. These
values configure the compensation network zero at 0.6 kHz.
The error amp gain at frequencies greater than FZero is
RCOMP /RFB2, which is approximately 3.56 (11dB).
30083935
FIGURE 12. Error Amplifier Gain and Phase
The overall voltage loop gain can be predicted as the sum (in
dB) of the modulator gain and the error amp gain. If a network
analyzer is available, the modulator gain can be measured
and the error amplifier gain can be configured for the desired
loop transfer function. If a network analyzer is not available,
the error amplifier compensation components can be de-
signed with the suggested guidelines. Step load transient
tests can be performed to verify performance. The step load
goal is minimum overshoot with a damped response. CHF can
be added to the compensation network to decrease noise
susceptibility of the error amplifier. The value of CHF must be
sufficiently small since the addition of this capacitor adds a
pole in the error amplifier transfer function. A good approxi-
mation of the location of the pole added by CHF is FP2 =
FZero x CCOMP/ CHF .Using CHF is recommended to minimize
coupling of any switching noise into the modulator. The value
of CHF was selected as 100 pF for this design example.
30083936
FIGURE 13. Overall Loop Gain and Phase
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LM5088/LM5088Q
PCB BOARD LAYOUT AND THERMAL
CONSIDERATIONS
In a buck regulator there are two loops where currents are
switched very fast. The first loop starts from the input capac-
itors, through the buck MOSFET, to the inductor then out to
the load. The second loop starts from the output capacitor
ground, to the regulator PGND pins, to the current sense re-
sistor, through the Schottky diode, to the inductor and then
out to the load. Minimizing the area of these two loops reduces
the stray inductance and minimizes noise which can cause
erratic operation. A ground plane is recommended as a
means to connect the input filter capacitors of the output filter
capacitors and the PGND pin of the regulator. Connect all of
the low power ground connections (CSS, RT, CRAMP) directly
to the regulator GND pin. Connect the GND pin and PGND
pins together through to topside copper area covering the en-
tire underside of the device. Place several vias in this under-
side copper area to the ground plane. The input capacitor
ground connection should be as close as possible to the cur-
rent sense ground connection.
In a buck converter, most of the losses can be attributed to
MOSFET conduction and switching loss, re-circulating diode
conduction loss, inductor DCR loss and LM5088 VIN and
VCC loss. The other dissipative components in a buck con-
verter produce losses but these other losses collectively ac-
count for about 2% of the total loss. Formulae to calculate all
the major losses are described in their respective sections of
this datasheet. The easiest method to determine the power
dissipated within the LM5088 is to measure the total conver-
sion losses (Pin-Pout), then subtract the power losses in the
Schottky diode, MOSFET, output inductor and snubber re-
sistor. When operating at 7A of output current and at 55V, the
power dissipation of the LM5088 is approximately 850 mW.
The junction to ambient thermal resistance of the LM5088
mounted in the evaluation board is approximately 40°C with
no airflow. At 25°C ambient temperature and no airflow, the
predicted junction temperature will be 25+40*0.9 = 61°C. The
LM5088 has an exposed thermal pad to aid in power dissi-
pation. Adding several vias under the device will greatly re-
duce the controller junction temperature. The junction to
ambient thermal resistance will vary with application. The
most significant variables are the area of copper in the PC
board; the number of vias under the IC exposed pad and the
amount of forced air cooling. The integrity of solder connec-
tion from the IC exposed pad to the PC board is critical.
Excessive voids will greatly diminish the thermal dissipation
capacity.
21 www.national.com
LM5088/LM5088Q
30083937
FIGURE 14. LM5088-1 Application Schematic
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LM5088/LM5088Q
30083938
FIGURE 15. LM5088-2 Application Schematic
23 www.national.com
LM5088/LM5088Q
Bill of Materials for LM5088-1 and LM5088-2 Evaluation Boards
Part Value Package Manufacturer Manufacturer Part Number Description
C1,C2,C3,C4,
C5
2.2µF C1210 Murata GRM32ER72A225KA35L CAP CER 2.2µF 100V X7R
1210
C6,C19 0.1µF C0805 TDK Corporation C2012X7R2A104K CAP CER .10µF 100V X7R
10% 0805
C7 1µF C0603 Murata GRM188R71C105KA12D CAP CER 1µF 16V X7R 0603
C8,C11 100pF C0603 AVX Corporation 06031A101FAT2A CAP CERM 100pF 1% 100V
NP0 0603
C9 270pF C0603 Murata GRM1885C2A271JA01D CAP CER 270pF 100V 5%
C0G 0603
C13 0.1µF C0603 Murata GRM188R72A104KA35D CAP CER .1µF 100V X7R
0603
C10 0.022µF C0603 Murata GRM188R71C223KA01D CAP CER 22000pF 16V 10%
X7R 0603
C12 0.015µF C0603 Murata GRM188R71H153KA01D CAP CER 15000pF 50V 10%
X7R 0603
C15 470µF 0.327x0.327x0.
303
Nippon-Chemicon APXF6R3ARA471MH80G CAP 470UF 6.3V ELECT
POLY SMD
C17,C18 47µF C1210 Murata GRM32ER61A476KE20L CAP CER 47µF 10V X5R
1210
C20 1000pF C0805 Murata GRM2195C2A102JA01D CAP CER 1000pF 100V 5%
C0G 0805
C16 NU 0.327x0.327x0.
303
NU NU NU
C21 NU C0603 NU NU NU
C14
(LM5088-1)
0.1µF C0603 Murata GRM188R72A104KA35D CAP CER .1µF 100V X7R
0603
C14
(LM5088-2)
0.022µF C0603 Murata GRM188R71C223KA01D CAP CER 22000pF 16V 10%
X7R 0603
D1 Schottky Diode D2PAK On Semi MBRB2060CT Schottky Rectifiers 20 Amp
60 Volt
D2 NU SOD123 NU NU NU
L1 6.8µH HC9 series Coiltronics HC9-6R8-R INDUCTOR HIGH
CURRENT 6.8µH
Q1 MOSFET SO-8 Vishay IR SI7148DP-T1-E3 MOSFET N-CH 75V 28A
PWR PAK SO8
R1 54.9k Ohm R0805 Rohm MCR10EZHF5492 RES 54.9 kΩ 1/8W 1% 0805
SMD
R2 16.2k Ohm R0603 Rohm MCR03EZPFX1622 RES 16.2 kΩ 1/10W 1% 0603
SMD
R3 24.9k Ohm R0603 Rohm MCR03EZPFX2492 RES 24.9 kΩ 1/10W 1% 0603
SMD
R4 18.2k Ohm R0603 Rohm MCR03EZPFX1822 RES 18.2 kΩ 1/10W 1% 0603
SMD
R5 10m Ohm R0815 Susumu Co Ltd RL3720WT-R010-F RES .01Ω 1W 1% 0815 SMD
R6 5.1 Ohm R2512 Panasonic - ECG ERJ-1TRQF5R1U RES 5.1Ω 1W 1% 2512 SMD
R7 10 Ohm R0805 Rohm MCR10EZHF10R0 RES 10.0Ω 1/8W 1% 0805
SMD
R8 5.11k Ohm R0603 Rohm MCR03EZPFX5111 RES 5.11 kΩ 1/10W 1% 0603
SMD
R9 1.62k Ohm R0603 Rohm MCR03EZPFX1621 RES 1.62 kΩ 1/10W 1% 0603
SMD
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LM5088/LM5088Q
Part Value Package Manufacturer Manufacturer Part Number Description
R10 NU R0603 NU NU NU
J1,J2,J3,J4 Terminal_Turret Keystone 1509 Terminal, Turret
TP1,TP2 Slotted test point Keystone 1040 Terminal test point slotted
U1 PWM IC TSSOP16_EP National LM5088-1/LM5088-2 ECM Buck Controller
25 www.national.com
LM5088/LM5088Q
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead TSSOP-EP Package
NS Package Number MXA16A
www.national.com 26
LM5088/LM5088Q
Notes
27 www.national.com
LM5088/LM5088Q
Notes
LM5088/LM5088Q Wide Input Range Non-Synchronous Buck Controller
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