Features
•Single 2.5V or 2.7V to 3.6V Supply
•RapidS Serial Interface: 66 MHz Maximum Clock Frequency
– SPI Compatible Modes 0 and 3
•User Configurable Page Size
– 256 Bytes per Page
– 264 Bytes per Page
– Page Size Can Be Factory Pre-configured for 256 Bytes
•Page Program Operation
– Intelligent Programming Operation
– 2,048 Pages (256/264 Bytes/Page) Main Memory
•Flexible Erase Options
– Page Erase (256 Bytes)
– Block Erase (2 Kbytes)
– Sector Erase (64 Kbytes)
– Chip Erase (4 Mbits)
•Two SRAM Data Buffers (256/264 Bytes)
– Allows Receiving of Data while Reprogramming the Flash Array
•Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
•Low-power Dissipation
– 7 mA Active Read Current Typical
– 25 µA Standby Current Typical
– 15 µA Deep Power-down Typical
•Hardware and Software Data Protection Features
– Individual Sector
•Sector Lockdown for Secure Code and Data Storage
– Individual Sector
•Security: 128-byte Security Register
– 64-byte User Programmable Space
– Unique 64-byte Device Identifier
•JEDEC Standard Manufacturer and Device ID Read
•100,000 Program/Erase Cycles Per Page Minimum
•Data Retention – 20 Years
•Industrial Temperature Range
•Green (Pb/Halide-free/RoHS Compliant) Packaging Options
1. Description
The AT45DB041D is a 2.5V or 2.7V, serial-interface Flash memory ideally suited for a
wide variety of digital voice-, image-, program code- and data-storage applications.
The AT45DB041D supports RapidS serial interface for applications requiring very
high speed operations. RapidS serial interface is SPI compatible for frequencies up to
66 MHz. Its 4,325,376 bits of memory are organized as 2,048 pages of 256 bytes or
264 bytes each. In addition to the main memory, the AT45DB041D also contains two
SRAM buffers of 256/264 bytes each. The buffers allow the receiving of data while a
page in the main Memory is being reprogrammed, as well as writing a continuous data
stream. EEPROM emulation (bit or byte alterability) is easily handled with a self-con-
tained three step read-modify-write operation. Unlike conventional Flash memories
that are accessed randomly with multiple address lines and a parallel interface, the
DataFlash uses a RapidS serial interface to sequentially access its data. The simple
sequential access dramatically reduces active pin count, facilitates hardware layout,
4-megabit
2.5-volt or
2.7-volt
DataFlash®
AT45DB041D
3595O–DFLASH–04/09
2
3595O–DFLASH–04/09
AT45DB041D
increases system reliability, minimizes switching noise, and reduces package size. The device is
optimized for use in many commercial and industrial applications where high-density, low-pin
count, low-voltage and low-power are essential.
To allow for simple in-system reprogrammability, the AT45DB041D does not require high input
voltages for programming. The device operates from a single power supply, 2.5V to 3.6V or 2.7V
to 3.6V, for both the program and read operations. The AT45DB041D is enabled through the
chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI),
Serial Output (SO), and the Serial Clock (SCK).
All programming and erase cycles are self-timed.
2. Pin Configurations and Pinouts
Table 2-1. Pin Configurations
Symbol Name and Function
Asserted
State Type
CS
Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected
and normally be placed in the standby mode (not Deep Power-Down mode), and the output pin (SO) will be in a
high-impedance state. When the device is deselected, data will not be accepted on the input pin (SI).
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to
end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device
will not enter the standby mode until the completion of the operation.
Low Input
SCK
Serial Clock: This pin is used to provide a clock to the device and is used to control the flow of data to and from
the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK,
while output data on the SO pin is always clocked out on the falling edge of SCK.
– Input
SI Serial Input: The SI pin is used to shift data into the device. The SI pin is used for all data input including
command and address sequences. Data on the SI pin is always latched on the rising edge of SCK. – Input
SO Serial Output: The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on
the falling edge of SCK. – Output
WP
Write Protect: When the WP pin is asserted, all sectors specified for protection by the Sector Protection Register
will be protected against program and erase operations regardless of whether the Enable Sector Protection
command has been issued or not. The WP pin functions independently of the software controlled protection method.
After the WP pin goes low, the content of the Sector Protection Register cannot be modified.
If a program or erase command is issued to the device while the WP pin is asserted, the device will simply ignore
the command and perform no operation. The device will return to the idle state once the CS pin has been
deasserted. The Enable Sector Protection command and Sector Lockdown command, however, will be
recognized by the device when the WP pin is asserted.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used.
However, it is recommended that the WP pin also be externally connected to VCC whenever possible.
Low Input
RESET
Reset: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state
machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET
pin. Normal operation can resume once the RESET pin is brought back to a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during
power-on sequences. If this pin and feature are not utilized it is recommended that the RESET pin be driven high
externally.
Low Input
VCC
Device Power Supply: The VCC pin is used to supply the source voltage to the device.
Operations at invalid VCC voltages may produce spurious results and should not be attempted. – Power
GND Ground: The ground reference for the power supply. GND should be connected to the system ground. – Ground
3
3595O–DFLASH–04/09
AT45DB041D
Note: 1. The metal pad on the bottom of the MLF package is floating. This pad can be a “No Connect” or connected to GND.
3. Block Diagram
Figure 2-1. MLF (VDFN)Top View Figure 2-2. SOIC Top View
SI
SCK
RESET
CS
SO
GND
VCC
WP
8
7
6
5
1
2
3
4
1
2
3
4
8
7
6
5
SI
SCK
RESET
CS
SO
GND
VCC
WP
FLASH MEMORY ARRAY
PAGE (256/264 BYTES)
BUFFER 2 (256/264 BYTES)BUFFER 1 (256/264 BYTES)
I/O INTERFACE
SCK
CS
RESET
VCC
GND
WP
SOSI
4
3595O–DFLASH–04/09
AT45DB041D
4. Memory Array
To provide optimal flexibility, the memory array of the AT45DB041D is divided into three levels of
granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illus-
trates the breakdown of each level and details the number of pages per sector and block. All
program operations to the DataFlash occur on a page-by-page basis. The erase operations can
be performed at the chip, sector, block or page level.
Figure 4-1. Memory Architecture Diagram
5. Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions
and their associated opcodes are contained in Tables 15-1 through 15-7. A valid instruction
starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer
or main memory address location. While the CS pin is low, toggling the SCK pin controls the
loading of the opcode and the desired buffer or main memory address location through the SI
(serial input) pin. All instructions, addresses, and data are transferred with the most significant
bit (MSB) first.
Buffer addressing for the DataFlash standard page size (264 bytes) is referenced in the
datasheet using the terminology BEA8 - BFA0 to denote the 9 address bits required to designate
a byte address within a buffer. Main memory addressing is referenced using the terminology
PA10 - PA0 and BA8 - BA0, where PA10 - PA0 denotes the 11 address bits required to desig-
nate a page address and BA8 - BA0 denotes the 9 address bits required to designate a byte
address within the page.
For the “Power of 2” binary page size (256 bytes), the Buffer addressing is referenced in the
datasheet using the conventional terminology BFA7 - BFA0 to denote the 8 address bits
required to designate a byte address within a buffer. Main memory addressing is referenced
using the terminology A18 - A0, where A18 - A8 denotes the 11 address bits required to desig-
nate a page address and A7 - A0 denotes the 8 address bits required to designate a byte
address within a page.
SECTOR 0a = 8 Pages
2,048/2,112 bytes
SECTOR 0b = 248 Pages
63,488/65,472 bytes
Block = 2,048/2,112 bytes
8 Pages
SECTOR 0a
SECTOR 0b
Page = 256/264 bytes
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 2,046
PAGE 2,047
BLOCK 0
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
BLOCK 1
SECTOR ARCHITECTURE BLOCK ARCHITECTURE PAGE ARCHITECTURE
BLOCK 0
BLOCK 1
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 254
BLOCK 255
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
SECTOR 1
SECTOR 7 = 256 Pages
65,536/67,584 bytes
BLOCK 2
SECTOR 1 = 256 Pages
65,536/67,584 bytes
SECTOR 6 = 256 Pages
65,536/67,584 bytes
SECTOR 2 = 256 Pages
65,536/67,584 bytes
5
3595O–DFLASH–04/09
AT45DB041D
6. Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from either
one of the two SRAM data buffers. The DataFlash supports RapidS protocols for Mode 0 and
Mode 3. Please refer to the “Detailed Bit-level Read Timing” diagrams in this datasheet for
details on the clock cycle sequences for each mode.
6.1 Continuous Array Read (Legacy Command – E8H): Up to 66 MHz
By supplying an initial starting address for the main memory array, the Continuous Array Read
command can be utilized to sequentially read a continuous stream of data from the device by
simply providing a clock signal; no additional addressing information or control signals need to
be provided. The DataFlash incorporates an internal address counter that will automatically
increment on every clock cycle, allowing one continuous read operation without the need of
additional address sequences. To perform a continuous read from the DataFlash standard page
size (264 bytes), an opcode of E8H must be clocked into the device followed by three address
bytes (which comprise the 24-bit page and byte address sequence) and 4 don’t care bytes. The
first 11 bits (PA10 - PA0) of the 20-bit address sequence specify which page of the main mem-
ory array to read, and the last 9 bits (BA8 - BA0) of the 20-bit address sequence specify the
starting byte address within the page. To perform a continuous read from the binary page size
(256 bytes), the opcode (E8H) must be clocked into the device followed by three address bytes
and 4 don’t care bytes. The first 11 bits (A18 - A8) of the 19-bits sequence specify which page of
the main memory array to read, and the last 8 bits (A7 - A0) of the 19-bits address sequence
specify the starting byte address within the page. The don’t care bytes that follow the address
bytes are needed to initialize the read operation. Following the don’t care bytes, additional clock
pulses on the SCK pin will result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care
bytes, and the reading of data. When the end of a page in main memory is reached during a
Continuous Array Read, the device will continue reading at the beginning of the next page with
no delays incurred during the page boundary crossover (the crossover from the end of one page
to the beginning of the next page). When the last bit in the main memory array has been read,
the device will continue reading back at the beginning of the first page of memory. As with cross-
ing over page boundaries, no delays will be incurred when wrapping around from the end of the
array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output
pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by
the fCAR1 specification. The Continuous Array Read bypasses both data buffers and leaves the
contents of the buffers unchanged.
6.2 Continuous Array Read (High Frequency Mode – 0BH): Up to 66 MHz
This command can be used with the serial interface to read the main memory array sequentially
in high speed mode for any clock frequency up to the maximum specified by fCAR1. To perform a
continuous read array with the page size set to 264 bytes, the CS must first be asserted then an
opcode 0BH must be clocked into the device followed by three address bytes and a dummy
byte. The first 11 bits (PA10 - PA0) of the 20-bit address sequence specify which page of the
main memory array to read, and the last 9 bits (BA8 - BA0) of the 20-bit address sequence spec-
ify the starting byte address within the page. To perform a continuous read with the page size
set to 256 bytes, the opcode, 0BH, must be clocked into the device followed by three address
bytes (A18 - A0) and a dummy byte. Following the dummy byte, additional clock pulses on the
SCK pin will result in data being output on the SO (serial output) pin.
6
3595O–DFLASH–04/09
AT45DB041D
The CS pin must remain low during the loading of the opcode, the address bytes, and the read-
ing of data. When the end of a page in the main memory is reached during a Continuous Array
Read, the device will continue reading at the beginning of the next page with no delays incurred
during the page boundary crossover (the crossover from the end of one page to the beginning of
the next page). When the last bit in the main memory array has been read, the device will con-
tinue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the
beginning of the array. A low-to-high transition on the CS pin will terminate the read operation
and tri-state the output pin (SO). The maximum SCK frequency allowable for the Continuous
Array Read is defined by the fCAR1 specification. The Continuous Array Read bypasses both
data buffers and leaves the contents of the buffers unchanged.
6.3 Continuous Array Read (Low Frequency Mode: 03H): Up to 33 MHz
This command can be used with the serial interface to read the main memory array sequentially
without a dummy byte up to maximum frequencies specified by fCAR2. To perform a continuous
read array with the page size set to 264 bytes, the CS must first be asserted then an opcode,
03H, must be clocked into the device followed by three address bytes (which comprise the 24-bit
page and byte address sequence). The first 11 bits (PA10 - PA0) of the 20-bit address sequence
specify which page of the main memory array to read, and the last 9 bits (BA8 - BA0) of the
20-bit address sequence specify the starting byte address within the page. To perform a contin-
uous read with the page size set to 256 bytes, the opcode, 03H, must be clocked into the device
followed by three address bytes (A18 - A0). Following the address bytes, additional clock pulses
on the SCK pin will result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, and the read-
ing of data. When the end of a page in the main memory is reached during a Continuous Array
Read, the device will continue reading at the beginning of the next page with no delays incurred
during the page boundary crossover (the crossover from the end of one page to the beginning of
the next page). When the last bit in the main memory array has been read, the device will con-
tinue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the
beginning of the array. A low-to-high transition on the CS pin will terminate the read operation
and tri-state the output pin (SO). The Continuous Array Read bypasses both data buffers and
leaves the contents of the buffers unchanged.
6.4 Main Memory Page Read
A main memory page read allows the user to read data directly from any one of the 2,048 pages
in the main memory, bypassing both of the data buffers and leaving the contents of the buffers
unchanged. To start a page read from the DataFlash standard page size (264 bytes), an opcode
of D2H must be clocked into the device followed by three address bytes (which comprise the
24-bit page and byte address sequence) and 4 don’t care bytes. The first 11 bits (PA10 - PA0) of
the 20-bit address sequence specify the page in main memory to be read, and the last 9 bits
(BA8 - BA0) of the 20-bit address sequence specify the starting byte address within that page.
To start a page read from the binary page size (256 bytes), the opcode D2H must be
clocked into the device followed by three address bytes and 4 don’t care bytes. The first 11 bits
(A18 - A8) of the 19-bits sequence specify which page of the main memory array to read, and
the last 8 bits (A7 - A0) of the 19-bits address sequence specify the starting byte address within
the page. The don’t care bytes that follow the address bytes are sent to initialize the read opera-
tion. Following the don’t care bytes, additional pulses on SCK result in data being output on the
SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the
address bytes, the don’t care bytes, and the reading of data. When the end of a page in main
7
3595O–DFLASH–04/09
AT45DB041D
memory is reached, the device will continue reading back at the beginning of the same page. A
low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin
(SO). The maximum SCK frequency allowable for the Main Memory Page Read is defined by the
fSCK specification. The Main Memory Page Read bypasses both data buffers and leaves the
contents of the buffers unchanged.
6.5 Buffer Read
The SRAM data buffers can be accessed independently from the main memory array, and utiliz-
ing the Buffer Read Command allows data to be sequentially read directly from the buffers. Four
opcodes, D4H or D1H for buffer 1 and D6H or D3H for buffer 2 can be used for the Buffer Read
Command. The use of each opcode depends on the maximum SCK frequency that will be used
to read data from the buffer. The D4H and D6H opcode can be used at any SCK frequency up to
the maximum specified by fCAR1. The D1H and D3H opcode can be used for lower frequency
read operations up to the maximum specified by fCAR2.
To perform a buffer read from the DataFlash standard buffer (264 bytes), the opcode must be
clocked into the device followed by three address bytes comprised of 15 don’t care bits and
9 buffer address bits (BFA8 - BFA0). To perform a buffer read from the binary buffer (256 bytes),
the opcode must be clocked into the device followed by three address bytes comprised of
16 don’t care bits and 8 buffer address bits (BFA7 - BFA0). Following the address bytes, one
don’t care byte must be clocked in to initialize the read operation. The CS pin must remain low
during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of
data. When the end of a buffer is reached, the device will continue reading back at the beginning
of the buffer. A low-to-high transition on the CS pin will terminate the read operation and tri-state
the output pin (SO).
7. Program and Erase Commands
7.1 Buffer Write
Data can be clocked in from the input pin (SI) into either buffer 1 or buffer 2. To load data into the
DataFlash standard buffer (264 bytes), a 1-byte opcode, 84H for buffer 1 or 87H for buffer 2,
must be clocked into the device, followed by three address bytes comprised of 15 don’t care bits
and 9 buffer address bits (BFA8 - BFA0). The 9 buffer address bits specify the first byte in the
buffer to be written. To load data into the binary buffers (256 bytes each), a 1-byte opcode 84H
for buffer 1 or 87H for buffer 2, must be clocked into the device, followed by three address bytes
comprised of 16 don’t care bits and 8 buffer address bits (BFA7 - BFA0). The 8 buffer address
bits specify the first byte in the buffer to be written. After the last address byte has been clocked
into the device, data can then be clocked in on subsequent clock cycles. If the end of the data
buffer is reached, the device will wrap around back to the beginning of the buffer. Data will con-
tinue to be loaded into the buffer until a low-to-high transition is detected on the CS pin.
7.2 Buffer to Main Memory Page Program with Built-in Erase
Data written into either buffer 1 or buffer 2 can be programmed into the main memory. A 1-byte
opcode, 83H for buffer 1 or 86H for buffer 2, must be clocked into the device. For the DataFlash
standard page size (264 bytes), the opcode must be followed by three address bytes consist of
4 don’t care bits, 11 page address bits (PA10 - PA0) that specify the page in the main memory to
be written and 9 don’t care bits. To perform a buffer to main memory page program with built-in
erase for the binary page size (256 bytes), the opcode 83H for buffer 1 or 86H for buffer 2, must
be clocked into the device followed by three address bytes consisting of 5 don’t care bits
8
3595O–DFLASH–04/09
AT45DB041D
11 page address bits (A18 - A8) that specify the page in the main memory to be written and
8 don’t care bits. When a low-to-high transition occurs on the CS pin, the part will first erase the
selected page in main memory (the erased state is a logic 1) and then program the data stored
in the buffer into the specified page in main memory. Both the erase and the programming of the
page are internally self-timed and should take place in a maximum time of tEP. During this time,
the status register will indicate that the part is busy.
7.3 Buffer to Main Memory Page Program without Built-in Erase
A previously-erased page within main memory can be programmed with the contents of either
buffer 1 or buffer 2. A 1-byte opcode, 88H for buffer 1 or 89H for buffer 2, must be clocked into
the device. For the DataFlash standard page size (264 bytes), the opcode must be followed by
three address bytes consist of 4 don’t care bits, 11 page address bits (PA10 - PA0) that specify
the page in the main memory to be written and 9 don’t care bits. To perform a buffer to main
memory page program without built-in erase for the binary page size (256 bytes), the opcode
88H for buffer 1 or 89H for buffer 2, must be clocked into the device followed by three address
bytes consisting of 5 don’t care bits, 11 page address bits (A18 - A8) that specify the page in the
main memory to be written and 8 don’t care bits. When a low-to-high transition occurs on the CS
pin, the part will program the data stored in the buffer into the specified page in the main mem-
ory. It is necessary that the page in main memory that is being programmed has been previously
erased using one of the erase commands (Page Erase or Block Erase). The programming of the
page is internally self-timed and should take place in a maximum time of tP. During this time, the
status register will indicate that the part is busy.
7.4 Page Erase
The Page Erase command can be used to individually erase any page in the main memory array
allowing the Buffer to Main Memory Page Program to be utilized at a later time. To perform a
page erase in the DataFlash standard page size (264 bytes), an opcode of 81H must be loaded
into the device, followed by three address bytes comprised of 4 don’t care bits, 11 page address
bits (PA10 - PA0) that specify the page in the main memory to be erased and 9 don’t care bits.
To perform a page erase in the binary page size (256 bytes), the opcode 81H must be loaded
into the device, followed by three address bytes consist of 5 don’t care bits, 11 page address bits
(A18 - A8) that specify the page in the main memory to be erased and 8 don’t care bits. When a
low-to-high transition occurs on the CS pin, the part will erase the selected page (the erased
state is a logical 1). The erase operation is internally self-timed and should take place in a maxi-
mum time of tPE. During this time, the status register will indicate that the part is busy.
7.5 Block Erase
A block of eight pages can be erased at one time. This command is useful when large amounts
of data has to be written into the device. This will avoid using multiple Page Erase Commands.
To perform a block erase for the DataFlash standard page size (264 bytes), an opcode of 50H
must be loaded into the device, followed by three address bytes comprised of 4 don’t care bits,
8 page address bits (PA10 - PA3) and 12 don’t care bits. The 8 page address bits are used to
specify which block of eight pages is to be erased. To perform a block erase for the binary page
size (256 bytes), the opcode 50H must be loaded into the device, followed by three address
bytes consisting of 5 don’t care bits, 8 page address bits (A18 - A11) and 11 don’t care bits. The
9 page address bits are used to specify which block of eight pages is to be erased. When a low-
to-high transition occurs on the CS pin, the part will erase the selected block of eight pages. The
erase operation is internally self-timed and should take place in a maximum time of tBE. During
this time, the status register will indicate that the part is busy.
9
3595O–DFLASH–04/09
AT45DB041D
7.6 Sector Erase
The Sector Erase command can be used to individually erase any sector in the main memory.
There are 8 sectors and only one sector can be erased at one time. To perform sector 0a or sec-
tor 0b erase for the DataFlash standard page size (264 bytes), an opcode of 7CH must be
loaded into the device, followed by three address bytes comprised of 4 don’t care bits, 8 page
address bits (PA10 - PA3) and 12 don’t care bits. To perform a sector 1-7 erase, the opcode
7CH must be loaded into the device, followed by three address bytes comprised of 4 don’t care
bits, 3 page address bits (PA10 - PA8) and 17 don’t care bits. To perform sector 0a or sector 0b
erase for the binary page size (256 bytes), an opcode of 7CH must be loaded into the device,
followed by three address bytes comprised of 5 don’t care bit and 8 page address bits (A18 -
A11) and 11 don’t care bits. To perform a sector 1-15 erase, the opcode 7CH must be loaded
into the device, followed by three address bytes comprised of 5 don’t care bit and 3 page
address bits (A18 - A16) and 16 don’t care bits. The page address bits are used to specify any
valid address location within the sector which is to be erased. When a low-to-high transition
occurs on the CS pin, the part will erase the selected sector. The erase operation is internally
self-timed and should take place in a maximum time of tSE. During this time, the status register
will indicate that the part is busy.
Table 7-1. Block Erase Addressing
PA10/
A18
PA9/
A17
PA8/
A16
PA7/
A15
PA6/
A14
PA5/
A13
PA4/
A12
PA3/
A11
PA2/
A10
PA1/
A9
PA0/
A8 Block
00000000XXX 0
00000001XXX 1
00000010XXX 2
00000011XXX 3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
11111100XXX 252
11111101XXX 253
11111110XXX 254
11111111XXX 255
10
3595O–DFLASH–04/09
AT45DB041D
7.7 Chip Erase(1)
The entire main memory can be erased at one time by using the Chip Erase command.
To execute the Chip Erase command, a 4-byte command sequence C7H, 94H, 80H and 9AH
must be clocked into the device. Since the entire memory array is to be erased, no address
bytes need to be clocked into the device, and any data clocked in after the opcode will be
ignored. After the last bit of the opcode sequence has been clocked in, the CS pin can be deas-
serted to start the erase process. The erase operation is internally self-timed and should take
place in a time of tCE. During this time, the Status Register will indicate that the device is busy.
The Chip Erase command will not affect sectors that are protected or locked down; the contents
of those sectors will remain unchanged. Only those sectors that are not protected or locked
down will be erased.
The WP pin can be asserted while the device is erasing, but protection will not be activated until
the internal erase cycle completes.
Figure 7-1. Chip Erase
Note: 1. Refer to the errata regarding Chip Erase on page 54.
Table 7-2. Sector Erase Addressing
PA10/
A18
PA9/
A17
PA8/
A16
PA7/
A15
PA6/
A14
PA5/
A13
PA4/
A12
PA3/
A11
PA2/
A10
PA1/
A9
PA0/
A8 Sector
00000000XXX 0a
00000001XXX 0b
0 0 1XXXXXXXX 1
0 1 0XXXXXXXX 2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1 0 0XXXXXXXX 4
1 0 1XXXXXXXX 5
1 1 0XXXXXXXX 6
1 1 1XXXXXXXX 7
Command Byte 1 Byte 2 Byte 3 Byte 4
Chip Erase C7H 94H 80H 9AH
Opcode
Byte 1
Opcode
Byte 2
Opcode
Byte 3
Opcode
Byte 4
CS
Each transition
represents 8 bits
SI
11
3595O–DFLASH–04/09
AT45DB041D
7.8 Main Memory Page Program Through Buffer
This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program
with Built-in Erase operations. Data is first clocked into buffer 1 or buffer 2 from the input pin (SI)
and then programmed into a specified page in the main memory. To perform a main memory
page program through buffer for the DataFlash standard page size (264 bytes), a 1-byte opcode,
82H for buffer 1 or 85H for buffer 2, must first be clocked into the device, followed by three
address bytes. The address bytes are comprised of 4 don’t care bits, 11 page address bits,
(PA10 - PA0) that select the page in the main memory where data is to be written, and 9 buffer
address bits (BFA8 - BFA0) that select the first byte in the buffer to be written. To perform a
main memory page program through buffer for the binary page size (256 bytes), the opcode 82H
for buffer 1 or 85H for buffer 2, must be clocked into the device followed by three address bytes
consisting of 5 don’t care bits, 11 page address bits (A18 - A8) that specify the page in the main
memory to be written, and 8 buffer address bits (BFA7 - BFA0) that selects the first byte in the
buffer to be written. After all address bytes are clocked in, the part will take data from the input
pins and store it in the specified data buffer. If the end of the buffer is reached, the device will
wrap around back to the beginning of the buffer. When there is a low-to-high transition on the CS
pin, the part will first erase the selected page in main memory to all 1s and then program the
data stored in the buffer into that memory page. Both the erase and the programming of the
page are internally self-timed and should take place in a maximum time of tEP. During this time,
the status register will indicate that the part is busy.
8. Sector Protection
Two protection methods, hardware and software controlled, are provided for protection against
inadvertent or erroneous program and erase cycles. The software controlled method relies on
the use of software commands to enable and disable sector protection while the hardware con-
trolled method employs the use of the Write Protect (WP) pin. The selection of which sectors
that are to be protected or unprotected against program and erase operations is specified in the
nonvolatile Sector Protection Register. The status of whether or not sector protection has been
enabled or disabled by either the software or the hardware controlled methods can be deter-
mined by checking the Status Register.
12
3595O–DFLASH–04/09
AT45DB041D
8.1 Software Sector Protection
8.1.1 Enable Sector Protection Command
Sectors specified for protection in the Sector Protection Register can be protected from program
and erase operations by issuing the Enable Sector Protection command. To enable the sector
protection using the software controlled method, the CS pin must first be asserted as it would be
with any other command. Once the CS pin has been asserted, the appropriate 4-byte command
sequence must be clocked in via the input pin (SI). After the last bit of the command sequence
has been clocked in, the CS pin must be deasserted after which the sector protection will be
enabled.
Figure 8-1. Enable Sector Protection
8.1.2 Disable Sector Protection Command
To disable the sector protection using the software controlled method, the CS pin must first be
asserted as it would be with any other command. Once the CS pin has been asserted, the
appropriate 4-byte sequence for the Disable Sector Protection command must be clocked in via
the input pin (SI). After the last bit of the command sequence has been clocked in, the CS pin
must be deasserted after which the sector protection will be disabled. The WP pin must be in the
deasserted state; otherwise, the Disable Sector Protection command will be ignored.
Figure 8-2. Disable Sector Protection
8.1.3 Various Aspects About Software Controlled Protection
Software controlled protection is useful in applications in which the WP pin is not or cannot be
controlled by a host processor. In such instances, the WP pin may be left floating (the WP pin is
internally pulled high) and sector protection can be controlled using the Enable Sector Protection
and Disable Sector Protection commands.
If the device is power cycled, then the software controlled protection will be disabled. Once the
device is powered up, the Enable Sector Protection command should be reissued if sector pro-
tection is desired and if the WP pin is not used.
Command Byte 1 Byte 2 Byte 3 Byte 4
Enable Sector Protection 3DH 2AH 7FH A9H
Opcode
Byte 1
Opcode
Byte 2
Opcode
Byte 3
Opcode
Byte 4
CS
Each transition
represents 8 bits
SI
Command Byte 1 Byte 2 Byte 3 Byte 4
Disable Sector Protection 3DH 2AH 7FH 9AH
Opcode
Byte 1
Opcode
Byte 2
Opcode
Byte 3
Opcode
Byte 4
CS
Each transition
represents 8 bits
SI
13
3595O–DFLASH–04/09
AT45DB041D
9. Hardware Controlled Protection
Sectors specified for protection in the Sector Protection Register and the Sector Protection Reg-
ister itself can be protected from program and erase operations by asserting the WP pin and
keeping the pin in its asserted state. The Sector Protection Register and any sector specified for
protection cannot be erased or reprogrammed as long as the WP pin is asserted. In order to
modify the Sector Protection Register, the WP pin must be deasserted. If the WP pin is perma-
nently connected to GND, then the content of the Sector Protection Register cannot be changed.
If the WP pin is deasserted, or permanently connected to VCC, then the content of the Sector
Protection Register can be modified.
The WP pin will override the software controlled protection method but only for protecting the
sectors. For example, if the sectors were not previously protected by the Enable Sector Protec-
tion command, then simply asserting the WP pin would enable the sector protection within the
maximum specified tWPE time. When the WP pin is deasserted; however, the sector protection
would no longer be enabled (after the maximum specified tWPD time) as long as the Enable Sec-
tor Protection command was not issued while the WP pin was asserted. If the Enable Sector
Protection command was issued before or while the WP pin was asserted, then simply deassert-
ing the WP pin would not disable the sector protection. In this case, the Disable Sector
Protection command would need to be issued while the WP pin is deasserted to disable the sec-
tor protection. The Disable Sector Protection command is also ignored whenever the WP pin is
asserted.
A noise filter is incorporated to help protect against spurious noise that may inadvertently assert
or deassert the WP pin.
The table below details the sector protection status for various scenarios of the WP pin, the
Enable Sector Protection command, and the Disable Sector Protection command.
Figure 9-1. WP Pin and Protection Status
WP
12
3
Table 9-1. WP Pin and Protection Status
Time
Period WP Pin
Enable Sector Protection
Command
Disable Sector
Protection Command
Sector Protection
Status
Sector
Protection
Register
1High
Command Not Issued Previously
–
Issue Command
X
Issue Command
–
Disabled
Disabled
Enabled
Read/Write
Read/Write
Read/Write
2 Low X X Enabled Read Only
3High
Command Issued During Period 1
or 2
–
Issue Command
Not Issued Yet
Issue Command
–
Enabled
Disabled
Enabled
Read/Write
Read/Write
Read/Write
14
3595O–DFLASH–04/09
AT45DB041D
9.1 Sector Protection Register
The nonvolatile Sector Protection Register specifies which sectors are to be protected or unpro-
tected with either the software or hardware controlled protection methods. The Sector Protection
Register contains 8 bytes of data, of which byte locations 0 through 7 contain values that specify
whether sectors 0 through 7 will be protected or unprotected. The Sector Protection Register is
user modifiable and must first be erased before it can be reprogrammed. Table 9-3 illustrates the
format of the Sector Protection Register.:
Note: 1. The default value for bytes 0 through 7 when shipped from Atmel® is 00H.
x = don’t care.
Table 9-2. Sector Protection Register
Sector Number 0 (0a, 0b) 1 to 7
Protected
See Table 9-3
FFH
Unprotected 00H
Table 9-3. Sector 0 (0a, 0b)
0a 0b
Bit 3, 2
Data
Value
(Page 0-7) (Page 8-255)
Bit 7, 6 Bit 5, 4 Bit 1, 0
Sectors 0a, 0b Unprotected 00 00 xx xx 0xH
Protect Sector 0a 11 00 xx xx CxH
Protect Sector 0b (Page 8-255) 00 11 xx xx 3xH
Protect Sectors 0a (Page 0-7), 0b
(Page 8-255)(1) 11 11 xx xx FxH
15
3595O–DFLASH–04/09
AT45DB041D
9.1.1 Erase Sector Protection Register Command
In order to modify and change the values of the Sector Protection Register, it must first be
erased using the Erase Sector Protection Register command.
To erase the Sector Protection Register, the CS pin must first be asserted as it would be with
any other command. Once the CS pin has been asserted, the appropriate 4-byte opcode
sequence must be clocked into the device via the SI pin. The 4-byte opcode sequence must
start with 3DH and be followed by 2AH, 7FH, and CFH. After the last bit of the opcode sequence
has been clocked in, the CS pin must be deasserted to initiate the internally self-timed erase
cycle. The erasing of the Sector Protection Register should take place in a time of tPE, during
which time the Status Register will indicate that the device is busy. If the device is powered-
down before the completion of the erase cycle, then the contents of the Sector Protection Regis-
ter cannot be guaranteed.
The Sector Protection Register can be erased with the sector protection enabled or disabled.
Since the erased state (FFH) of each byte in the Sector Protection Register is used to indicate
that a sector is specified for protection, leaving the sector protection enabled during the erasing
of the register allows the protection scheme to be more effective in the prevention of accidental
programming or erasing of the device. If for some reason an erroneous program or erase com-
mand is sent to the device immediately after erasing the Sector Protection Register and before
the register can be reprogrammed, then the erroneous program or erase command will not be
processed because all sectors would be protected.
Figure 9-2. Erase Sector Protection Register
Command Byte 1 Byte 2 Byte 3 Byte 4
Erase Sector Protection Register 3DH 2AH 7FH CFH
Opcode
Byte 1
Opcode
Byte 2
Opcode
Byte 3
Opcode
Byte 4
CS
Each transition
represents 8 bits
SI
16
3595O–DFLASH–04/09
AT45DB041D
9.1.2 Program Sector Protection Register Command
Once the Sector Protection Register has been erased, it can be reprogrammed using the
Program Sector Protection Register command.
To program the Sector Protection Register, the CS pin must first be asserted and the appropri-
ate 4-byte opcode sequence must be clocked into the device via the SI pin. The 4-byte opcode
sequence must start with 3DH and be followed by 2AH, 7FH, and FCH. After the last bit of the
opcode sequence has been clocked into the device, the data for the contents of the Sector Pro-
tection Register must be clocked in. As described in Section 9.1, the Sector Protection Register
contains 8 bytes of data, so 8 bytes must be clocked into the device. The first byte of data corre-
sponds to sector 0, the second byte corresponds to sector 1, and so on with the last byte of data
corresponding to sector 7.
After the last data byte has been clocked in, the CS pin must be deasserted to initiate the inter-
nally self-timed program cycle. The programming of the Sector Protection Register should take
place in a time of tP, during which time the Status Register will indicate that the device is busy. If
the device is powered-down during the program cycle, then the contents of the Sector Protection
Register cannot be guaranteed.
If the proper number of data bytes is not clocked in before the CS pin is deasserted, then the
protection status of the sectors corresponding to the bytes not clocked in can not be guaranteed.
For example, if only the first two bytes are clocked in instead of the complete 8 bytes, then the
protection status of the last 6 sectors cannot be guaranteed. Furthermore, if more than 8 bytes
of data is clocked into the device, then the data will wrap back around to the beginning of the
register. For instance, if 9 bytes of data are clocked in, then the 9th byte will be stored at byte
location 0 of the Sector Protection Register.
If a value other than 00H or FFH is clocked into a byte location of the Sector Protection Register,
then the protection status of the sector corresponding to that byte location cannot be guaran-
teed. For example, if a value of 17H is clocked into byte location 2 of the Sector Protection
Register, then the protection status of sector 2 cannot be guaranteed.
The Sector Protection Register can be reprogrammed while the sector protection enabled or dis-
abled. Being able to reprogram the Sector Protection Register with the sector protection enabled
allows the user to temporarily disable the sector protection to an individual sector rather than
disabling sector protection completely.
The Program Sector Protection Register command utilizes the internal SRAM buffer 1 for
processing. Therefore, the contents of the buffer 1 will be altered from its previous state when
this command is issued.
Figure 9-3. Program Sector Protection Register
Command Byte 1 Byte 2 Byte 3 Byte 4
Program Sector Protection Register 3DH 2AH 7FH FCH
Data Byte
n
Opcode
Byte 1
Opcode
Byte 2
Opcode
Byte 3
Opcode
Byte 4
Data Byte
n + 1
Data Byte
n + 7
CS
Each transition
represents 8 bits
SI
17
3595O–DFLASH–04/09
AT45DB041D
9.1.3 Read Sector Protection Register Command
To read the Sector Protection Register, the CS pin must first be asserted. Once the CS pin has
been asserted, an opcode of 32H and 3 dummy bytes must be clocked in via the SI pin. After the
last bit of the opcode and dummy bytes have been clocked in, any additional clock pulses on the
SCK pins will result in data for the content of the Sector Protection Register being output on the
SO pin. The first byte corresponds to sector 0 (0a, 0b), the second byte corresponds to sector 1
and the last byte (byte 8) corresponds to sector 7. Once the last byte of the Sector Protection
Register has been clocked out, any additional clock pulses will result in undefined data being
output on the SO pin. The CS must be deasserted to terminate the Read Sector Protection Reg-
ister operation and put the output into a high-impedance state.
Note: xx = Dummy Byte
Figure 9-4. Read Sector Protection Register
9.1.4 Various Aspects About the Sector Protection Register
The Sector Protection Register is subject to a limit of 10,000 erase/program cycles. Users are
encouraged to carefully evaluate the number of times the Sector Protection Register will be
modified during the course of the applications’ life cycle. If the application requires that the Sec-
tor Protection Register be modified more than the specified limit of 10,000 cycles because the
application needs to temporarily unprotect individual sectors (sector protection remains enabled
while the Sector Protection Register is reprogrammed), then the application will need to limit this
practice. Instead, a combination of temporarily unprotecting individual sectors along with dis-
abling sector protection completely will need to be implemented by the application to ensure that
the limit of 10,000 cycles is not exceeded.
Command Byte 1 Byte 2 Byte 3 Byte 4
Read Sector Protection Register 32H xxH xxH xxH
Opcode X X X
Data Byte
n
Data Byte
n + 1
CS
Data Byte
n + 7
SI
SO
Each transition
represents 8 bits
18
3595O–DFLASH–04/09
AT45DB041D
10. Security Features
10.1 Sector Lockdown
The device incorporates a Sector Lockdown mechanism that allows each individual sector to be
permanently locked so that it becomes read only. This is useful for applications that require the
ability to permanently protect a number of sectors against malicious attempts at altering program
code or security information. Once a sector is locked down, it can never be erased or pro-
grammed, and it can never be unlocked.
To issue the Sector Lockdown command, the CS pin must first be asserted as it would be for
any other command. Once the CS pin has been asserted, the appropriate 4-byte opcode
sequence must be clocked into the device in the correct order. The 4-byte opcode sequence
must start with 3DH and be followed by 2AH, 7FH, and 30H. After the last byte of the command
sequence has been clocked in, then three address bytes specifying any address within the sec-
tor to be locked down must be clocked into the device. After the last address bit has been
clocked in, the CS pin must then be deasserted to initiate the internally self-timed lockdown
sequence.
The lockdown sequence should take place in a maximum time of tP, during which time the Status
Register will indicate that the device is busy. If the device is powered-down before the comple-
tion of the lockdown sequence, then the lockdown status of the sector cannot be guaranteed. In
this case, it is recommended that the user read the Sector Lockdown Register to determine the
status of the appropriate sector lockdown bits or bytes and reissue the Sector Lockdown com-
mand if necessary.
Figure 10-1. Sector Lockdown
Command Byte 1 Byte 2 Byte 3 Byte 4
Sector Lockdown 3DH 2AH 7FH 30H
Opcode
Byte 1
Opcode
Byte 2
Opcode
Byte 3
Opcode
Byte 4
CS
Address
Bytes
Address
Bytes
Address
Bytes
Each transition
represents 8 bits
SI
19
3595O–DFLASH–04/09
AT45DB041D
10.1.1 Sector Lockdown Register
Sector Lockdown Register is a nonvolatile register that contains 16 bytes of data, as shown
below:
10.1.2 Reading the Sector Lockdown Register
The Sector Lockdown Register can be read to determine which sectors in the memory array are
permanently locked down. To read the Sector Lockdown Register, the CS pin must first be
asserted. Once the CS pin has been asserted, an opcode of 35H and 3 dummy bytes must be
clocked into the device via the SI pin. After the last bit of the opcode and dummy bytes have
been clocked in, the data for the contents of the Sector Lockdown Register will be clocked out
on the SO pin. The first byte corresponds to sector 0 (0a, 0b) the second byte corresponds to
sector 1 and the las byte (byte 8) corresponds to sector 7. After the last byte of the Sector Lock-
down Register has been read, additional pulses on the SCK pin will simply result in undefined
data being output on the SO pin.
Deasserting the CS pin will terminate the Read Sector Lockdown Register operation and put the
SO pin into a high-impedance state.
Table 10-2 details the values read from the Sector Lockdown Register.
Figure 10-2. Read Sector Lockdown Register
Sector Number 0 (0a, 0b) 1 to 7
Locked
See Below
FFH
Unlocked 00H
Table 10-1. Sector 0 (0a, 0b)
0a 0b
Bit 3, 2
Data
Value
(Page 0-7) (Page 8-255)
Bit 7, 6 Bit 5, 4 Bit 1, 0
Sectors 0a, 0b Unlocked 00 00 00 00 00H
Sector 0a Locked (Page 0-7) 11 00 00 00 C0H
Sector 0b Locked (Page 8-255) 00 11 00 00 30H
Sectors 0a, 0b Locked (Page 0-255) 11 11 00 00 F0H
Table 10-2. Sector Lockdown Register
Command Byte 1 Byte 2 Byte 3 Byte 4
Read Sector Lockdown Register 35H xxH xxH xxH
Note: xx = Dummy Byte
Opcode X X X
Data Byte
n
Data Byte
n + 1
CS
Data Byte
n + 7
SI
SO
Each transition
represents 8 bits
20
3595O–DFLASH–04/09
AT45DB041D
10.2 Security Register
The device contains a specialized Security Register that can be used for purposes such as
unique device serialization or locked key storage. The register is comprised of a total of
128 bytes that is divided into two portions. The first 64 bytes (byte locations 0 through 63) of the
Security Register are allocated as a one-time user programmable space. Once these 64 bytes
have been programmed, they cannot be reprogrammed. The remaining 64 bytes of the register
(byte locations 64 through 127) are factory programmed by Atmel and will contain a unique
value for each device. The factory programmed data is fixed and cannot be changed.
10.2.1 Programming the Security Register
The user programmable portion of the Security Register does not need to be erased before it is
programmed.
To program the Security Register, the CS pin must first be asserted and the appropriate 4-byte
opcode sequence must be clocked into the device in the correct order. The 4-byte opcode
sequence must start with 9BH and be followed by 00H, 00H, and 00H. After the last bit of the
opcode sequence has been clocked into the device, the data for the contents of the 64-byte user
programmable portion of the Security Register must be clocked in.
After the last data byte has been clocked in, the CS pin must be deasserted to initiate the inter-
nally self-timed program cycle. The programming of the Security Register should take place in a
time of tP, during which time the Status Register will indicate that the device is busy. If the device
is powered-down during the program cycle, then the contents of the 64-byte user programmable
portion of the Security Register cannot be guaranteed.
If the full 64 bytes of data is not clocked in before the CS pin is deasserted, then the values of
the byte locations not clocked in cannot be guaranteed. For example, if only the first two bytes
are clocked in instead of the complete 64 bytes, then the remaining 62 bytes of the user pro-
grammable portion of the Security Register cannot be guaranteed. Furthermore, if more than
64 bytes of data is clocked into the device, then the data will wrap back around to the beginning
of the register. For instance, if 65 bytes of data are clocked in, then the 65th byte will be stored at
byte location 0 of the Security Register.
The user programmable portion of the Security Register can only be programmed one
time. Therefore, it is not possible to only program the first two bytes of the register and then pro-
gram the remaining 62 bytes at a later time.
The Program Security Register command utilizes the internal SRAM buffer 1 for processing.
Therefore, the contents of the buffer 1 will be altered from its previous state when this command
is issued.
Figure 10-3. Program Security Register
Table 10-3. Security Register
Security Register Byte Number
01• • • 62 63 64 65 • • • 126 127
Data Type One-time User Programmable Factory Programmed By Atmel
Data Byte
n
Opcode
Byte 1
Opcode
Byte 2
Opcode
Byte 3
Opcode
Byte 4
Data Byte
n + 1
Data Byte
n + x
CS
Each transition
represents 8 bits
SI
21
3595O–DFLASH–04/09
AT45DB041D
10.2.2 Reading the Security Register
The Security Register can be read by first asserting the CS pin and then clocking in an opcode
of 77H followed by three dummy bytes. After the last don't care bit has been clocked in, the con-
tent of the Security Register can be clocked out on the SO pins. After the last byte of the
Security Register has been read, additional pulses on the SCK pin will simply result in undefined
data being output on the SO pins.
Deasserting the CS pin will terminate the Read Security Register operation and put the SO pins
into a high-impedance state.
Figure 10-4. Read Security Register
11. Additional Commands
11.1 Main Memory Page to Buffer Transfer
A page of data can be transferred from the main memory to either buffer 1 or buffer 2. To start
the operation for the DataFlash standard page size (264 bytes), a 1-byte opcode, 53H for buffer
1 and 55H for buffer 2, must be clocked into the device, followed by three address bytes com-
prised of 4 don’t care bits, 11 page address bits (PA10 - PA0), which specify the page in main
memory that is to be transferred, and 9 don’t care bits. To perform a main memory page to buffer
transfer for the binary page size (256 bytes), the opcode 53H for buffer 1 or 55H for buffer 2,
must be clocked into the device followed by three address bytes consisting of 5 don’t care bits,
11 page address bits (A18 - A8) which specify the page in the main memory that is to be trans-
ferred, and 8 don’t care bits. The CS pin must be low while toggling the SCK pin to load the
opcode and the address bytes from the input pin (SI). The transfer of the page of data from the
main memory to the buffer will begin when the CS pin transitions from a low to a high state. Dur-
ing the transfer of a page of data (tXFR), the status register can be read to determine whether the
transfer has been completed.
11.2 Main Memory Page to Buffer Compare
A page of data in main memory can be compared to the data in buffer 1 or buffer 2. To initiate
the operation for the DataFlash standard page size, a 1-byte opcode, 60H for buffer 1 and 61H
for buffer 2, must be clocked into the device, followed by three address bytes consisting of
4 don’t care bits, 11 page address bits (PA10 - PA0) that specify the page in the main memory
that is to be compared to the buffer, and 9 don’t care bits. To start a main memory page to buffer
compare for a binary page size, the opcode 60H for buffer 1 or 61H for buffer 2, must be clocked
into the device followed by three address bytes consisting of 5 don’t care bits, 11 page address
bits (A18 - A8) that specify the page in the main memory that is to be compared to the buffer,
and 8 don’t care bits. The CS pin must be low while toggling the SCK pin to load the opcode and
Opcode X X X
Data Byte
n
Data Byte
n + 1
CS
Data Byte
n + x
Each transition
represents 8 bits
SI
SO
22
3595O–DFLASH–04/09
AT45DB041D
the address bytes from the input pin (SI). On the low-to-high transition of the CS pin, the data
bytes in the selected main memory page will be compared with the data bytes in buffer 1 or buf-
fer 2. During this time (tCOMP), the status register will indicate that the part is busy. On completion
of the compare operation, bit 6 of the status register is updated with the result of the compare.
11.3 Auto Page Rewrite
This mode is only needed if multiple bytes within a page or multiple pages of data are modified in
a random fashion within a sector. This mode is a combination of two operations: Main Memory
Page to Buffer Transfer and Buffer to Main Memory Page Program with Built-in Erase. A page of
data is first transferred from the main memory to buffer 1 or buffer 2, and then the same data
(from buffer 1 or buffer 2) is programmed back into its original page of main memory. To start the
rewrite operation for the DataFlash standard page size (264 bytes), a 1-byte opcode, 58H for
buffer 1 or 59H for buffer 2, must be clocked into the device, followed by three address bytes
comprised of 4 don’t care bits, 11 page address bits (PA10-PA0) that specify the page in main
memory to be rewritten and 9 don’t care bits. To initiate an auto page rewrite for a binary page
size (256 bytes), the opcode 58H for buffer 1 or 59H for buffer 2, must be clocked into the device
followed by three address bytes consisting of 5 don’t care bits, 11 page address bits (A18 - A8)
that specify the page in the main memory that is to be written and 8 don’t care bits. When a low-
to-high transition occurs on the CS pin, the part will first transfer data from the page in main
memory to a buffer and then program the data from the buffer back into same page of main
memory. The operation is internally self-timed and should take place in a maximum time of tEP.
During this time, the status register will indicate that the part is busy.
If a sector is programmed or reprogrammed sequentially page by page, then the programming
algorithm shown in Figure 25-1 (page 46) is recommended. Otherwise, if multiple bytes in a
page or several pages are programmed randomly in a sector, then the programming algorithm
shown in Figure 25-2 (page 47) is recommended. Each page within a sector must be
updated/rewritten at least once within every 10,000 cumulative page erase/program operations
in that sector.
11.4 Status Register Read
The status register can be used to determine the device’s ready/busy status, page size, a Main
Memory Page to Buffer Compare operation result, the Sector Protection status or the device
density. The Status Register can be read at any time, including during an internally self-timed
program or erase operation. To read the status register, the CS pin must be asserted and the
opcode of D7H must be loaded into the device. After the opcode is clocked in, the 1-byte status
register will be clocked out on the output pin (SO), starting with the next clock cycle. The data in
the status register, starting with the MSB (bit 7), will be clocked out on the SO pin during the next
eight clock cycles. After the one byte of the status register has been clocked out, the sequence
will repeat itself (as long as CS remains low and SCK is being toggled). The data in the status
register is constantly updated, so each repeating sequence will output new data.
Ready/busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device is
not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy
state. Since the data in the status register is constantly updated, the user must toggle SCK pin to
check the ready/busy status. There are several operations that can cause the device to be in a
busy state: Main Memory Page to Buffer Transfer, Main Memory Page to Buffer Compare, Buf-
fer to Main Memory Page Program, Main Memory Page Program through Buffer, Page Erase,
Block Erase, Sector Erase, Chip Erase and Auto Page Rewrite.
23
3595O–DFLASH–04/09
AT45DB041D
The result of the most recent Main Memory Page to Buffer Compare operation is indicated using
bit 6 of the status register. If bit 6 is a 0, then the data in the main memory page matches the
data in the buffer. If bit 6 is a 1, then at least one bit of the data in the main memory page does
not match the data in the buffer.
Bit 1 in the Status Register is used to provide information to the user whether or not the sector
protection has been enabled or disabled, either by software-controlled method or hardware-con-
trolled method. A logic 1 indicates that sector protection has been enabled and logic 0 indicates
that sector protection has been disabled.
Bit 0 in the Status Register indicates whether the page size of the main memory array is config-
ured for “power of 2” binary page size (256 bytes) or the DataFlash standard page size
(264 bytes). If bit 0 is a 1, then the page size is set to 256 bytes. If bit 0 is a 0, then the page size
is set to 264 bytes.
The device density is indicated using bits 5, 4, 3, and 2 of the status register. For the
AT45DB041D, the four bits are 0111 The decimal value of these four binary bits does not equate
to the device density; the four bits represent a combinational code relating to differing densities
of DataFlash devices. The device density is not the same as the density code indicated in the
JEDEC device ID information. The device density is provided only for backward compatibility.
Table 11-1. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RDY/BUSY COMP 0 1 1 1 PROTECT PAGE SIZE
24
3595O–DFLASH–04/09
AT45DB041D
12. Deep Power-down
After initial power-up, the device will default in standby mode. The Deep Power-down command
allows the device to enter into the lowest power consumption mode. To enter the Deep Power-
down mode, the CS pin must first be asserted. Once the CS pin has been asserted, an opcode
of B9H command must be clocked in via input pin (SI). After the last bit of the command has
been clocked in, the CS pin must be de-asserted to initiate the Deep Power-down operation.
After the CS pin is de-asserted, the will device enter the Deep Power-down mode within the
maximum tEDPD time. Once the device has entered the Deep Power-down mode, all instructions
are ignored except for the Resume from Deep Power-down command.
Figure 12-1. Deep Power-down
12.1 Resume from Deep Power-down
The Resume from Deep Power-down command takes the device out of the Deep Power-down
mode and returns it to the normal standby mode. To Resume from Deep Power-down mode, the
CS pin must first be asserted and an opcode of ABH command must be clocked in via input pin
(SI). After the last bit of the command has been clocked in, the CS pin must be de-asserted to
terminate the Deep Power-down mode. After the CS pin is de-asserted, the device will return to
the normal standby mode within the maximum tRDPD time. The CS pin must remain high during
the tRDPD time before the device can receive any commands. After resuming form Deep Power-
down, the device will return to the normal standby mode.
Figure 12-2. Resume from Deep Power-Down
Command Opcode
Deep Power-down B9H
Opcode
CS
Each transition
represents 8 bits
SI
Command Opcode
Resume from Deep Power-down ABH
Opcode
CS
Each transition
represents 8 bits
SI
25
3595O–DFLASH–04/09
AT45DB041D
13. “Power of 2” Binary Page Size Option
“Power of 2” binary page size Configuration Register is a user-programmable nonvolatile regis-
ter that allows the page size of the main memory to be configured for binary page size
(256 bytes) or the DataFlash standard page size (264 bytes). The “power of 2” page size is a
one-time programmable configuration register and once the device is configured for
“power of 2” page size, it cannot be reconfigured again. The devices are initially shipped
with the page size set to 264 bytes. The user has the option of ordering binary page size (256
bytes) devices from the factory. For details, please refer to Section 26. ”Ordering Information” on
page 48.
For the binary “power of 2” page size to become effective, the following steps must be followed:
1. Program the one-time programmable configuration resister using opcode sequence
3DH, 2AH, 80H and A6H (please see Section 13.1).
2. Power cycle the device (i.e. power down and power up again).
3. The page for the binary page size can now be programmed.
If the above steps are not followed to set the page size prior to page programming, incorrect
data during a read operation may be encountered.
13.1 Programming the Configuration Register
To program the Configuration Register for “power of 2” binary page size, the CS pin must first be
asserted as it would be with any other command. Once the CS pin has been asserted, the
appropriate 4-byte opcode sequence must be clocked into the device in the correct order. The
4-byte opcode sequence must start with 3DH and be followed by 2AH, 80H, and A6H. After the
last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate
the internally self-timed program cycle. The programming of the Configuration Register should
take place in a time of tP, during which time the Status Register will indicate that the device is
busy. The device must be power-cycled after the completion of the program cycle to set the
“power of 2” page size. If the device is powered-down before the completion of the program
cycle, then setting the Configuration Register cannot be guaranteed. However, the user should
check bit 0 of the status register to see whether the page size was configured for binary page
size. If not, the command can be re-issued again.
Figure 13-1. Erase Sector Protection Register
14. Manufacturer and Device ID Read
Identification information can be read from the device to enable systems to electronically query
and identify the device while it is in system. The identification method and the command opcode
comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI
Compatible Serial Interface Memory Devices”. The type of information that can be read from the
device includes the JEDEC defined Manufacturer ID, the vendor specific Device ID, and the ven-
dor specific Extended Device Information.
Command Byte 1 Byte 2 Byte 3 Byte 4
Power of Two Page Size 3DH 2AH 80H A6H
Opcode
Byte 1
Opcode
Byte 2
Opcode
Byte 3
Opcode
Byte 4
CS
Each transition
represents 8 bits
SI
26
3595O–DFLASH–04/09
AT45DB041D
To read the identification information, the CS pin must first be asserted and the opcode of 9FH
must be clocked into the device. After the opcode has been clocked in, the device will begin out-
putting the identification data on the SO pin during the subsequent clock cycles. The first byte
that will be output will be the Manufacturer ID followed by two bytes of Device ID information.
The fourth byte output will be the Extended Device Information String Length, which will be 00H
indicating that no Extended Device Information follows. As indicated in the JEDEC standard,
reading the Extended Device Information String Length and any subsequent data is optional.
Deasserting the CS pin will terminate the Manufacturer and Device ID Read operation and put
the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not
require that a full byte of data be read.
14.1 Manufacturer and Device ID Information
Note: Based on JEDEC publication 106 (JEP106), Manufacturer ID data can be comprised of any number of bytes. Some manufacturers may have
Manufacturer ID codes that are two, three or even four bytes long with the first byte(s) in the sequence being 7FH. A system should detect code
7FH as a “Continuation Code” and continue to read Manufacturer ID bytes. The first non-7FH byte would signify the last byte of Manufacturer ID
data. For Atmel (and some other manufacturers), the Manufacturer ID data is comprised of only one byte.
14.1.1 Byte 1 – Manufacturer ID
Hex
Value
JEDEC Assigned Code
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1FH 0 0 0 1 1 1 1 1 Manufacturer ID 1FH = Atmel
14.1.2 Byte 2 – Device ID (Part 1)
Hex
Value
Family Code Density Code
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Family Code 001 = DataFlash
24H 0 0 1 0 0 1 0 0 Density Code 00100 = 4-Mbit
14.1.3 Byte 3 – Device ID (Part 2)
Hex
Value
MLC Code Product Version Code
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MLC Code 000 = 1-bit/Cell Technology
00H 0 0 0 0 0 0 0 0 Product Version 00000 = Initial Version
14.1.4 Byte 4 – Extended Device Information String Length
Hex
Value
Byte Count
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00H 0 0 0 0 0 0 0 0 Byte Count 00H = 0 Bytes of Information
9FH
Manufacturer ID
Byte n
Device ID
Byte 1
Device ID
Byte 2
This information would only be output
if the Extended Device Information String Length
value was something other than 00H.
Extended
Device
Information
String Length
Extended
Device
Information
Byte x
Extended
Device
Information
Byte x + 1
CS
1FH 24H 00H 00H Data Data
SI
SO
Opcode
Each transition
represents 8 bits
27
3595O–DFLASH–04/09
AT45DB041D
14.2 Operation Mode Summary
The commands described previously can be grouped into four different categories to better
describe which commands can be executed at what times.
Group A commands consist of:
1. Main Memory Page Read
2. Continuous Array Read
3. Read Sector Protection Register
4. Read Sector Lockdown Register
5. Read Security Register
Group B commands consist of:
1. Page Erase
2. Block Erase
3. Sector Erase
4. Chip Erase
5. Main Memory Page to Buffer 1 (or 2) Transfer
6. Main Memory Page to Buffer 1 (or 2) Compare
7. Buffer 1 (or 2) to Main Memory Page Program with Built-in Erase
8. Buffer 1 (or 2) to Main Memory Page Program without Built-in Erase
9. Main Memory Page Program through Buffer 1 (or 2)
10. Auto Page Rewrite
Group C commands consist of:
1. Buffer 1 (or 2) Read
2. Buffer 1 (or 2) Write
3. Status Register Read
4. Manufacturer and Device ID Read
Group D commands consist of:
1. Erase Sector Protection Register
2. Program Sector Protection Register
3. Sector Lockdown
4. Program Security Register
If a Group A command is in progress (not fully completed), then another command in Group A,
B, C, or D should not be started. However, during the internally self-timed portion of Group B
commands, any command in Group C can be executed. The Group B commands using buffer 1
should use Group C commands using buffer 2 and vice versa. Finally, during the internally self-
timed portion of a Group D command, only the Status Register Read command should be
executed.
28
3595O–DFLASH–04/09
AT45DB041D
15. Command Tables
Table 15-1. Read Commands
Command Opcode
Main Memory Page Read D2H
Continuous Array Read (Legacy Command) E8H
Continuous Array Read (Low Frequency) 03H
Continuous Array Read (High Frequency) 0BH
Buffer 1 Read (Low Frequency) D1H
Buffer 2 Read (Low Frequency) D3H
Buffer 1 Read D4H
Buffer 2 Read D6H
Table 15-2. Program and Erase Commands
Command Opcode
Buffer 1 Write 84H
Buffer 2 Write 87H
Buffer 1 to Main Memory Page Program with Built-in Erase 83H
Buffer 2 to Main Memory Page Program with Built-in Erase 86H
Buffer 1 to Main Memory Page Program without Built-in Erase 88H
Buffer 2 to Main Memory Page Program without Built-in Erase 89H
Page Erase 81H
Block Erase 50H
Sector Erase 7CH
Chip Erase C7H, 94H, 80H, 9AH
Main Memory Page Program Through Buffer 1 82H
Main Memory Page Program Through Buffer 2 85H
29
3595O–DFLASH–04/09
AT45DB041D
Note: 1. These legacy commands are not recommended for new designs.
Table 15-3. Protection and Security Commands
Command Opcode
Enable Sector Protection 3DH + 2AH + 7FH + A9H
Disable Sector Protection 3DH + 2AH + 7FH + 9AH
Erase Sector Protection Register 3DH + 2AH + 7FH + CFH
Program Sector Protection Register 3DH + 2AH + 7FH + FCH
Read Sector Protection Register 32H
Sector Lockdown 3DH + 2AH + 7FH + 30H
Read Sector Lockdown Register 35H
Program Security Register 9BH + 00H + 00H + 00H
Read Security Register 77H
Table 15-4. Additional Commands
Command Opcode
Main Memory Page to Buffer 1 Transfer 53H
Main Memory Page to Buffer 2 Transfer 55H
Main Memory Page to Buffer 1 Compare 60H
Main Memory Page to Buffer 2 Compare 61H
Auto Page Rewrite through Buffer 1 58H
Auto Page Rewrite through Buffer 2 59H
Deep Power-down B9H
Resume from Deep Power-down ABH
Status Register Read D7H
Manufacturer and Device ID Read 9FH
Table 15-5. Legacy Commands(1)
Command Opcode
Buffer 1 Read 54H
Buffer 2 Read 56H
Main Memory Page Read 52H
Continuous Array Read 68H
Status Register Read 57H
30
3595O–DFLASH–04/09
AT45DB041D
Notes: x = Don’t Care
Table 15-6. Detailed Bit-level Addressing Sequence for Binary Page Size (256 Bytes)
Page Size = 256 bytes Address Byte Address Byte Address Byte
Additional
Don’t Care
BytesOpcode Opcode
Reserved
Reserved
Reserved
Reserved
Reserved
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
03h 0000001 1 xxxxxAAAAAAAAAA A AAAAAAA A N/A
0Bh 0000101 1 xxxxxAAAAAAAAAA A AAAAAAA A 1
50h 0101000 0 xxxxxAAAAAAAAxx x xxxxxxx x N/A
53h 0101001 1 xxxxxAAAAAAAAAA A x x xxxxx x N/A
55h 0101010 1 xxxxxAAAAAAAAAA A x x xxxxx x N/A
58h 0101100 0 xxxxxAAAAAAAAAA A x x xxxxx x N/A
59h 0101100 1 xxxxxAAAAAAAAAA A x x xxxxx x N/A
60h 0110000 0 xxxxxAAAAAAAAAA A x x xxxxx x N/A
61h 0110000 1 xxxxxAAAAAAAAAA A x x xxxxx x N/A
77h 0111011 1 xxxxxxx x xxxxxxx x xxxxxxx x N/A
7Ch 0111110 0 xxxxxAAAxxxxxxx x xxxxxxx x N/A
81h 1000000 1 xxxxxAAAAAAAAAA A x x xxxxx x N/A
82h 1000001 0 xxxxxAAAAAAAAAA A AAAAAAA A N/A
83h 1000001 1 xxxxxAAAAAAAAAA A x x xxxxx x N/A
84h 1000010 0 xxxxxxx x xxxxxxx xAAAAAAA A N/A
85h 1000010 1 xxxxxAAAAAAAAAA A AAAAAAA A N/A
86h 1000011 0 xxxxxAAAAAAAAAA A x x xxxxx x N/A
87h 1000011 1 xxxxxxx x xxxxxxx xAAAAAAA A N/A
88h 1000100 0 xxxxxAAAAAAAAAA A x x xxxxx x N/A
89h 1000100 1 xxxxxAAAAAAAAAA A x x xxxxx x N/A
9Fh 1001111 1 N/A N/A N/A N/A
B9h 1011100 1 N/A N/A N/A N/A
ABh 1010101 1 N/A N/A N/A N/A
D1h 1101000 1 xxxxxxx x xxxxxxx xAAAAAAA A N/A
D2h 1101001 0 xxxxxAAAAAAAAAA A AAAAAAA A 4
D3h 1101001 1 xxxxxxx x xxxxxxx xAAAAAAA A N/A
D4h 1101010 0 xxxxxxx x xxxxxxx xAAAAAAA A 1
D6h 1101011 0 xxxxxxx x xxxxxxx xAAAAAAA A 1
D7h 1101011 1 N/A N/A N/A N/A
E8h 1110100 0 xxxxxAAAAAAAAAA A AAAAAAA A 4
31
3595O–DFLASH–04/09
AT45DB041D
Notes: P = Page Address Bit B = Byte/Buffer Address Bit x = Don’t Care
Table 15-7. Detailed Bit-level Addressing Sequence for Standard DataFlash Page Size (264 Bytes)
Page Size = 264 bytes Address Byte Address Byte Address Byte
Additional
Don’t Care
BytesOpcode Opcode
Reserved
Reserved
Reserved
Reserved
PA10
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
BA0
BA8
BA7
BA6
BA5
BA4
BA3
BA2
BA1
BA0
03h 0000001 1 xxxxPPPPPPPPPPPBBBBBBBB B N/A
0Bh 0 0 0 0 1 0 1 1 x x x x PPP PPPPPPPP B BBBBBBB B 1
50h 0101000 0 xxxxPPPPPPPPxxx x xxxxxxx x N/A
53h 0101001 1 xxxxPPPPPPPPPPPx xxxxxxx x N/A
55h 0101010 1 xxxxPPPPPPPPPPPx xxxxxxx x N/A
58h 0101100 0 xxxxPPPPPPPPPPPx xxxxxxx x N/A
59h 0101100 1 xxxxPPPPPPPPPPPx xxxxxxx x N/A
60h 0110000 0 xxxxPPPPPPPPPPPx xxxxxxx x N/A
61h 0110000 1 xxxxPPPPPPPPPPPx xxxxxxx x N/A
77h 01110111 xxxxxxx x xxxxxxx x xxxxxxx x N/A
7Ch 01111100 xxxxPPPx xxxxxxx x xxxxxxx x N/A
81h 1000000 1 xxxxPPPPPPPPPPPx xxxxxxx x N/A
82h 1000001 0 xxxxPPPPPPPPPPPBBBBBBBB B N/A
83h 1000001 1 xxxxPPPPPPPPPPPx xxxxxxx x N/A
84h 10000100 xxxxxxx x xxxxxxxBBBBBBBBB N/A
85h 1000010 1 xxxxPPPPPPPPPPPBBBBBBBB B N/A
86h 1000011 0 xxxxPPPPPPPPPPPx xxxxxxx x N/A
87h 10000111 xxxxxxx x xxxxxxxBBBBBBBBB N/A
88h 1000100 0 xxxxPPPPPPPPPPPx xxxxxxx x N/A
89h 1000100 1 xxxxPPPPPPPPPPPx xxxxxxx x N/A
9Fh 1001111 1 N/A N/A N/A N/A
B9h 1011100 1 N/A N/A N/A N/A
ABh 1010101 1 N/A N/A N/A N/A
D1h 11010001 xxxxxxx x xxxxxxxBBBBBBBBB N/A
D2h 1 1 0 1 0 0 1 0 x x x xPPP P PPPPPPP B BBBBBBB B 4
D3h 11010001 xxxxxxx x xxxxxxxBBBBBBBBB N/A
D4h 11010100 xxxxxxx x xxxxxxxBBBBBBBBB 1
D6h 11010110 xxxxxxx x xxxxxxxBBBBBBBBB 1
D7h 1101011 1 N/A N/A N/A N/A
E8h 1 1 1 0 1 0 0 0 x x x x PPP PPPPPPPP B BBBBBBB B 4
32
3595O–DFLASH–04/09
AT45DB041D
16. Power-on/Reset State
When power is first applied to the device, or when recovering from a reset condition, the device
will default to Mode 3. In addition, the output pin (SO) will be in a high impedance state, and a
high-to-low transition on the CS pin will be required to start a valid instruction. The mode (Mode
3 or Mode 0) will be automatically selected on every falling edge of CS by sampling the inactive
clock state.
16.1 Initial Power-up/Reset Timing Restrictions
At power up, the device must not be selected until the supply voltage reaches the VCC (min.) and
further delay of tVCSL. During power-up, the internal Power-on Reset circuitry keeps the device in
reset mode until the VCC rises above the Power-on Reset threshold value (VPOR). At this time, all
operations are disabled and the device does not respond to any commands. After power up is
applied and the VCC is at the minimum operating voltage VCC (min.), the tVCSL delay is required
before the device can be selected in order to perform a read operation.
Similarly, the tPUW delay is required after the VCC rises above the Power-on Reset threshold
value (VPOR) before the device can perform a write (Program or Erase) operation. After initial
power-up, the device will default in Standby mode.
17. System Considerations
The RapidS serial interface is controlled by the clock SCK, serial input SI and chip select CS
pins. These signals must rise and fall monotonically and be free from noise. Excessive noise or
ringing on these pins can be misinterpreted as multiple edges and cause improper operation of
the device. The PC board traces must be kept to a minimum distance or appropriately termi-
nated to ensure proper operation. If necessary, decoupling capacitors can be added on these
pins to provide filtering against noise glitches.
As system complexity continues to increase, voltage regulation is becoming more important. A
key element of any voltage regulation scheme is its current sourcing capability. Like all Flash
memories, the peak current for DataFlash occur during the programming and erase operation.
The regulator needs to supply this peak current requirement. An under specified regulator can
cause current starvation. Besides increasing system noise, current starvation during program-
ming or erase can lead to improper operation and possible data corruption.
Symbol Parameter Min Typ Max Units
tVCSL VCC (min.) to Chip Select low 70 µs
tPUW Power-Up Device Delay before Write Allowed 20 ms
VPOR Power-ON Reset Voltage 1.5 2.5 V
33
3595O–DFLASH–04/09
AT45DB041D
18. Electrical Specifications
Table 18-1. Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. The "Absolute Maximum Rat-
ings" are stress ratings only and functional
operation of the device at these or any other con-
ditions beyond those indicated in the operational
sections of this specification is not implied. Expo-
sure to absolute maximum rating conditions for
extended periods may affect device reliability.
Voltage Extremes referenced in the "Absolute
Maximum Ratings" are intended to accommo-
date short duration undershoot/overshoot condi-
tions and does not imply or guarantee functional
device operation at these levels for any extended
period of time.
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages (except VCC but including NC pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Table 18-2. DC and AC Operating Range
AT45DB041D (2.5V Version) AT45DB041D
Operating Temperature (Case) Ind. -40°C to 85°C-40°C to 85°C
VCC Power Supply 2.5V to 3.6V 2.7V to 3.6V
34
3595O–DFLASH–04/09
AT45DB041D
Notes: 1. ICC1 during a buffer read is 20 mA maximum @ 20 MHz.
2. All inputs (SI, SCK, CS#, WP#, and RESET#) are guaranteed by design to be 5-Volt tolerant.
Table 18-3. DC Characteristics
Symbol Parameter Condition Min Typ Max Units
IDP Deep Power-down Current CS, RESET, WP = VIH, all
inputs at CMOS levels 15 25 µA
ISB Standby Current CS, RESET, WP = VIH, all
inputs at CMOS levels 25 50 µA
ICC1(1) Active Current, Read
Operation
f = 20 MHz; IOUT = 0 mA;
VCC = 3.6V 710mA
f = 33 MHz; IOUT = 0 mA;
VCC = 3.6V 812mA
f = 50 MHz; IOUT = 0 mA;
VCC = 3.6V 10 14 mA
f = 66 MHz; IOUT = 0 mA;
VCC = 3.6V 11 15 mA
ICC2
Active Current, Program/Erase
Operation VCC = 3.6V 12 17 mA
ILI Input Load Current VIN = CMOS levels 1 µA
ILO Output Leakage Current VI/O = CMOS levels 1 µA
VIL Input Low Voltage VCC x 0.3 V
VIH Input High Voltage VCC x 0.7 V
VOL Output Low Voltage IOL = 1.6 mA; VCC = 2.7V 0.4 V
VOH Output High Voltage IOH = -100 µA VCC - 0.2V V
35
3595O–DFLASH–04/09
AT45DB041D
Table 18-4. AC Characteristics – RapidS/Serial Interface
Symbol Parameter
AT45DB041D
(2.5V Version) AT45DB041D
Min Typ Max Min Typ Max Units
fSCK SCK Frequency 50 66 MHz
fCAR1 SCK Frequency for Continuous Array Read 50 66 MHz
fCAR2
SCK Frequency for Continuous Array Read
(Low Frequency) 33 33 MHz
tWH SCK High Time 6.8 6.8 ns
tWL SCK Low Time 6.8 6.8 ns
tSCKR(1) SCK Rise Time, Peak-to-Peak (Slew Rate) 0.1 0.1 V/ns
tSCKF(1) SCK Fall Time, Peak-to-Peak (Slew Rate) 0.1 0.1 V/ns
tCS Minimum CS High Time 50 50 ns
tCSS CS Setup Time 5 5 ns
tCSH CS Hold Time 5 5 ns
tSU Data In Setup Time 2 2 ns
tHData In Hold Time 3 3 ns
tHO Output Hold Time 0 0 ns
tDIS Output Disable Time 27 35 27 35 ns
tVOutput Valid 8 6 ns
tWPE WP Low to Protection Enabled 1 1 µs
tWPD WP High to Protection Disabled 1 1 µs
tEDPD CS High to Deep Power-down Mode 3 3 µs
tRDPD CS High to Standby Mode 35 35 µs
tXFR Page to Buffer Transfer Time 200 200 µs
tcomp Page to Buffer Compare Time 200 200 µs
tEP
Page Erase and Programming Time
(256/264 bytes) 14 35 14 35 ms
tPPage Programming Time (256/264 bytes) 2 4 2 4 ms
tPE Page Erase Time (256/264 bytes) 13 32 13 32 ms
tBE Block Erase Time (2,048/2,112 bytes) 30 75 30 75 ms
tSE Sector Erase Time (65,536/67,584 bytes) 1.6 5 1.6 5 s
tCE Chip Erase Time 6 12 6 12 s
tRST RESET Pulse Width 10 10 µs
tREC RESET Recovery Time 1 1 µs
36
3595O–DFLASH–04/09
AT45DB041D
19. Input Test Waveforms and Measurement Levels
tR, tF < 2 ns (10% to 90%)
20. Output Test Load
21. AC Waveforms
Six different timing waveforms are shown on page 37. Waveform 1 shows the SCK signal being
low when CS makes a high-to-low transition, and waveform 2 shows the SCK signal being high
when CS makes a high-to-low transition. In both cases, output SO becomes valid while the
SCK signal is still low (SCK low time is specified as tWL). Timing waveforms 1 and 2 conform to
RapidS serial interface but for frequencies up to 66 MHz. Waveforms 1 and 2 are compatible
with SPI Mode 0 and SPI Mode 3, respectively.
Waveform 3 and waveform 4 illustrate general timing diagram for RapidS serial interface. These
are similar to waveform 1 and waveform 2, except that output SO is not restricted to become
valid during the tWL period. These timing waveforms are valid over the full frequency range (max-
imum frequency = 66 MHz) of the RapidS serial case.
AC
DRIVING
LEVELS
AC
MEASUREMENT
LEVEL
0.45V
1.5V
2.4V
DEVICE
UNDER
TEST
30 pF
37
3595O–DFLASH–04/09
AT45DB041D
21.1 Waveform 1 – SPI Mode 0 Compatible (for Frequencies up to 66 MHz)
21.2 Waveform 2 – SPI Mode 3 Compatible (for Frequencies up to 66 MHz)
21.3 Waveform 3 – RapidS Mode 0 (FMAX = 66 MHz)
21.4 Waveform 4 – RapidS Mode 3 (FMAX = 66 MHz)
CS
SCK
SI
SO
t
CSS
VALID IN
t
H
t
SU
t
WH
t
WL
t
CSH
t
CS
t
V
HIGH IMPEDANCE VALID OUT
t
HO
t
DIS
HIGH IMPEDANCE
CS
SCK
SO
t
CSS
VALID IN
t
H
t
SU
t
WL
t
WH
t
CSH
t
CS
t
V
HIGH Z VALID OUT
t
HO
t
DIS
HIGH IMPEDANCE
SI
CS
SCK
SI
SO
tCSS
VALID IN
tH
tSU
tWH tWL tCSH
tCS
tV
HIGH IMPEDANCE VALID OUT
tHO tDIS
HIGH IMPEDANCE
CS
SCK
SO
t
CSS
VALID IN
t
H
t
SU
t
WL
t
WH
t
CSH
t
CS
t
V
HIGH Z VALID OUT
t
HO
t
DIS
HIGH IMPEDANCE
SI
38
3595O–DFLASH–04/09
AT45DB041D
21.5 Utilizing the RapidS Function
To take advantage of the RapidS function's ability to operate at higher clock frequencies, a full
clock cycle must be used to transmit data back and forth across the serial bus. The DataFlash is
designed to always clock its data out on the falling edge of the SCK signal and clock data in on
the rising edge of SCK.
For full clock cycle operation to be achieved, when the DataFlash is clocking data out on the
falling edge of SCK, the host controller should wait until the next falling edge of SCK to latch the
data in. Similarly, the host controller should clock its data out on the rising edge of SCK in
order to give the DataFlash a full clock cycle to latch the incoming data in on the next rising edge
of SCK.
Figure 21-1. RapidS Mode
SCK
MOSI
MISO
1234567812345678
MOSI = Master Out, Slave In
MISO = Master In, Slave Out
The Master is the host controller and the Slave is the DataFlash
The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK.
The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK.
A. Master clocks out first bit of BYTE-MOSI on the rising edge of SCK.
B. Slave clocks in first bit of BYTE-MOSI on the next rising edge of SCK.
C. Master clocks out second bit of BYTE-MOSI on the same rising edge of SCK.
D. Last bit of BYTE-MOSI is clocked out from the Master.
E. Last bit of BYTE-MOSI is clocked into the slave.
F. Slave clocks out first bit of BYTE-SO.
G. Master clocks in first bit of BYTE-SO.
H. Slave clocks out second bit of BYTE-SO.
I. Master clocks in last bit of BYTE-SO.
ABCD
E
FG
1
H
BYTE-MOSI
MSB LSB
BYTE-SO
MSB LSB
Slave CS
I
39
3595O–DFLASH–04/09
AT45DB041D
21.6 Reset Timing
Note: The CS signal should be in the high state before the RESET signal is deasserted.
21.7 Command Sequence for Read/Write Operations for Page Size 256 Bytes (Except Status
Register Read, Manufacturer and Device ID Read)
21.8 Command Sequence for Read/Write Operations for Page Size 264 Bytes (Except Status
Register Read, Manufacturer and Device ID Read)
CS
SCK
RESET
SO (OUTPUT) HIGH IMPEDANCE HIGH IMPEDANCE
SI (INPUT)
tRST
tREC tCSS
SI (INPUT) CMD 8 bits 8 bits 8 bits
Page Address
(A18 - A8)
X X X X X X X X X X X X X X X X LSB
X X X X X X X X
Byte/Buffer Address
(A7 - A0/BFA7 - BFA0)
MSB
5 Don’t Care
Bits
Page Address
(PA10 - PA0)
Byte/Buffer Address
(BA8 - BA0/BFA8 - BFA0)
SI (INPUT) CMD 8 bits 8 bits 8 bits
X X X X X X X X X X X X LSB
X X X X X X X X
MSB
4 Don’t Care
Bits
X X X X
40
3595O–DFLASH–04/09
AT45DB041D
22. Write Operations
The following block diagram and waveforms illustrate the various write sequences available.
22.1 Buffer Write
22.2 Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page)
FLASH MEMORY ARRAY
PAGE (256/264 BYTES)
BUFFER (256/264 BYTES)
I/O INTERFACE
SI
BUFFER TO
MAIN MEMORY
PAGE PROGRAM
BUFFER
WRITE
SI (INPUT) CMD
Completes writing into selected buffer
CS
X
X···X, BFA8
BFA7-0
nn+1 Last Byte
BINARY PAGE SIZE
16 DON'T CARE + BFA7-BFA0
SI (INPUT) CMD
PA10-7 PA6-0, X
CS
Starts self-timed erase/program operation
XXXX XX
Each transition
represents 8 bits
n = 1st byte read
n+1 = 2nd byte read
BINARY PAGE SIZE
A18-A8 + 8 DON'T CARE BITS
41
3595O–DFLASH–04/09
AT45DB041D
23. Read Operations
The following block diagram and waveforms illustrate the various read sequences available.
23.1 Main Memory Page Read
23.2 Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)
FLASH MEMORY ARRAY
PAGE (256/264 BYTES)
BUFFER 2 (256/264 BYTES)BUFFER 1 (256/264 BYTES)
I/O INTERFACE
MAIN MEMORY
PAGE TO
BUFFER 1
MAIN MEMORY
PAGE TO
BUFFER 2
MAIN MEMORY
PAGE READ
BUFFER 1
READ
BUFFER 2
READ
SO
SI (INPUT)
CMD PA10-7 PA6-0, BA8
X
CS
n n+1
SO (OUTPUT)
BA7-0
4 Dummy Bytes
X
ADDRESS FOR BINARY PAGE SIZE
A18-A16 A15-A8 A7-A0
Starts reading page data into buffer
SI (INPUT)
CMD PA10-7 PA6-0, X
CS
SO (OUTPUT)
XXXX XXXX
BINARY PAGE SIZE
A18-A8 + 8 DON'T CARE BITS
42
3595O–DFLASH–04/09
AT45DB041D
23.3 Buffer Read
24. Detailed Bit-level Read Waveform – RapidS Serial Interface Mode 0/Mode 3
24.1 Continuous Array Read (Legacy Opcode E8H)
24.2 Continuous Array Read (Opcode 0BH)
CMD
CS
n n+1
X
X
X..X, BFA8
BFA7- 0
BINARY PAGE SIZE
16 DON'T CARE + BFA7-BFA0
Each transition
represents 8 bits
SI (INPUT)
SO (OUTPUT)
No Dummy Byte (opcodes D1H and D3H)
1 Dummy Byte (opcodes D4H and D6H)
SCK
CS
SI
SO
MSB MSB
2310
11101000
675410119812 63666765646233 3431 3229 30 68 71 727069
OPCODE
AAAA AAAAA
MSB
XXXX XX
MSB MSB
DDDDDDDDDD
ADDRESS BITS 32 DON'T CARE BITS
DATA BYTE 1
HIGH-IMPEDANCE
BIT 2047/2111
OF PAGE n
BIT 0 OF
PAGE n+1
SCK
CS
SI
SO
MSB MSB
2310
00001011
675410119812 39424341403833 3431 3229 30 44 47 484645
OPCODE
AAAA AAAAA
MSB
XXXX XX
MSB MSB
DDDDDDDDDD
ADDRESS BITS A18 - A0 DON'T CARE
DATA BYTE 1
HIGH-IMPEDANCE
36 3735
XX
43
3595O–DFLASH–04/09
AT45DB041D
24.3 Continuous Array Read (Low Frequency: Opcode 03H)
24.4 Main Memory Page Read (Opcode: D2H)
24.5 Buffer Read (Opcode D4H or D6H)
SCK
CS
SI
SO
MSB MSB
2310
00000011
675410119812 373833 36353431 3229 30 39 40
OPCODE
AAAA AAAAA
MSB MSB
DDDDDDDDDD
ADDRESS BITS A18-A0
DATA BYTE 1
HIGH-IMPEDANCE
SCK
CS
SI
SO
MSB MSB
2310
11010010
675410119812 63666765646233 3431 3229 30 68 71 727069
OPCODE
AAAA AAAAA
MSB
XXXX XX
MSB MSB
DDDDDDDDDD
ADDRESS BITS 32 DON'T CARE BITS
DATA BYTE 1
HIGH-IMPEDANCE
SCK
CS
SI
SO
MSB MSB
2310
11010100
675410119812 394243414037 3833 36353431 3229 30 44 47 484645
OPCODE
XXXX AAAXX
MSB
XXXXXXXX
MSB MSB
DDDDDDDDDD
ADDRESS BITS
BINARY PAGE SIZE = 16 DON'T CARE + BFA7-BFA0
STANDARD DATAFLASH PAGE SIZE =
15 DON'T CARE + BFA8-BFA0 DON'T CARE
DATA BYTE 1
HIGH-IMPEDANCE
44
3595O–DFLASH–04/09
AT45DB041D
24.6 Buffer Read (Low Frequency: Opcode D1H or D3H)
24.7 Read Sector Protection Register (Opcode 32H)
24.8 Read Sector Lockdown Register (Opcode 35H)
SCK
CS
SI
SO
MSB MSB
2310
11010001
675410119812 373833 36353431 3229 30 39 40
OPCODE
XXXX AAAXX
MSB MSB
DDDDDDDDDD
DATA BYTE 1
HIGH-IMPEDANCE
ADDRESS BITS
BINARY PAGE SIZE = 16 DON'T CARE + BFA7-BFA0
STANDARD DATAFLASH PAGE SIZE =
15 DON'T CARE + BFA8-BFA0
SCK
CS
SI
SO
MSB MSB
2310
00110010
675410119812 373833 36353431 3229 30 39 40
OPCODE
XXXX XXXXX
MSB MSB
DDDDDDDDD
DON'T CARE
DATA BYTE 1
HIGH-IMPEDANCE
SCK
CS
SI
SO
MSB MSB
2310
00110101
675410119812 373833 36353431 3229 30 39 40
OPCODE
XXXX XXXXX
MSB MSB
DDDDDDDDD
DON'T CARE
DATA BYTE 1
HIGH-IMPEDANCE
45
3595O–DFLASH–04/09
AT45DB041D
24.9 Read Security Register (Opcode 77H)
24.10 Status Register Read (Opcode D7H)
24.11 Manufacturer and Device Read (Opcode 9FH)
SCK
CS
SI
SO
MSB MSB
2310
01110111
675410119812 373833 36353431 3229 30 39 40
OPCODE
XXXX XXXXX
MSB MSB
DDDDDDDDD
DON'T CARE
DATA BYTE 1
HIGH-IMPEDANCE
SCK
CS
SI
SO
MSB
2310
11010111
675410119812 212217 20191815 1613 14 23 24
OPCODE
MSB MSB
DDDDDD DDDD
MSB
DDDDDDDD
STATUS REGISTER DATA STATUS REGISTER DATA
HIGH-IMPEDANCE
SCK
CS
SI
SO
60
9FH
87 38
OPCODE
1FH DEVICE ID BYTE 1 DEVICE ID BYTE 2 00H
HIGH-IMPEDANCE
14 1615 22 2423 30 3231
Note: Each transition shown for SI and SO represents one byte (8 bits)
46
3595O–DFLASH–04/09
AT45DB041D
25. Auto Page Rewrite Flowchart
Figure 25-1. Algorithm for Programming or Reprogramming of the Entire Array Sequentially
Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by-
page.
2. A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer
to Main Memory Page Program operation.
3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page
within the entire array.
START
MAIN MEMORY PAGE PROGRAM
THROUGH BUFFER
(82H, 85H)
END
provide address
and data
BUFFER WRITE
(84H, 87H)
BUFFER TO MAIN
MEMORY PAGE PROGRAM
(83H, 86H)
47
3595O–DFLASH–04/09
AT45DB041D
Figure 25-2. Algorithm for Randomly Modifying Data
Notes: 1. To preserve data integrity, each page of a DataFlash sector must be updated/rewritten at least once within every 10,000
cumulative page erase and program operations.
2. A Page Address Pointer must be maintained to indicate which page is to be rewritten. The Auto Page Rewrite command
must use the address specified by the Page Address Pointer.
3. Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000
cumulative page erase and program operations have accumulated before rewriting all pages of the sector. See application
note AN-4 (“Using Atmel’s Serial DataFlash”) for more details.
START
MAIN MEMORY PAGE
TO BUFFER TRANSFER
(53H, 55H)
INCREMENT PAGE
ADDRESS POINTER(2)
AUTO PAGE REWRITE(2)
(58H, 59H)
END
provide address of
page to modify
If planning to modify multiple
bytes currently stored within
a page of the Flash array
MAIN MEMORY PAGE PROGRAM
THROUGH BUFFER
(82H, 85H)
BUFFER WRITE
(84H, 87H)
BUFFER TO MAIN
MEMORY PAGE PROGRAM
(83H, 86H)
48
3595O–DFLASH–04/09
AT45DB041D
26. Ordering Information
26.1 Ordering Code Detail
Notes: 1. The shipping carrier option is not marked on the devices.
2. Standard parts are shipped with the page size set to 264 bytes. The user is able to configure these parts to a 256-byte page
size if desired.
3. Parts ordered with suffix SL954 are shipped in bulk with the page size set to 256 bytes. Parts will have a 954 or SL954
marked on them.
4. Parts ordered with suffix SL955 are shipped in tape and reel with the page size set to 256 bytes. Parts will have a 954 or
SL954 marked on them.
AT4 5D 04 SSU1D–B
Atmel Designator
Product Family
Device Density
4 = 4-megabit
Interface
1 = Serial
Package Option
M = 8-pad, 6 x 5 x 1 mm MLF (VDFN)
SS = 8-lead, 0.150" wide SOIC
S = 8-lead, 0.209" wide SOIC
Device Grade
U = Matte Sn lead finish, industrial
temperature range (-40°C to +85°C)
Device Revision
26.2 Green Package Options (Pb/Halide-free/RoHS Compliant)
Ordering Code(1)(2) Package Lead Finish Operating Voltage fSCK (MHz) Operation Range
AT45DB041D-MU
AT45DB041D-MU-SL954(3)
AT45DB041D-MU-SL955(4)
8M1-A
Matte Sn 2.7V to 3.6V 66
Industrial
(-40°C to +85°C)
AT45DB041D-SSU
AT45DB041D-SSU-SL954(3)
AT45DB041D-SSU-SL955(4)
8S1
AT45DB041D-SU
AT45DB041D-SU-SL954(3)
AT45DB041D-SU-SL955(4)
8S2
AT45DB041D-MU-2.5 8M1-A
Matte Sn 25V to 3.6V 50AT45DB041D-SSU-2.5 8S1
AT45DB041D-SU-2.5 8S2
49
3595O–DFLASH–04/09
AT45DB041D
Package Type
8M1-A 8-pad, 6 x 5 x 1.00 mm Body, Very Thin Dual Flat Package No Lead MLF™ (VDFN)
8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8S2 8-lead, 0.209” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
50
3595O–DFLASH–04/09
AT45DB041D
27. Packaging Information
27.1 8M1-A – MLF (VDFN)
TITLE DRAWING NO.GPC REV.
Package Drawing Contact:
packagedrawings@atmel.com 8MA1YFG D
8MA1, 8-pad (5 x 6 x 0.6 mm Body), Thermally
Enhanced Plastic Ultra Thin Dual Flat No Lead
Package (UDFN)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 0.45 0.55 0.60
A1 0.00 0.02 0.05
b 0.35 0.40 0.48
C 0.152 REF
D 4.90 5.00 5.10
D2 3.80 4.00 4.20
E 5.90 6.00 6.10
E2 3.20 3.40 3.60
e 1.27
L 0.50 0.60 0.75
y 0.00 – 0.08
K 0.20 – –
4/15/08
Pin 1 ID
TOP VIEW
E
D
A1
A
SIDE VIEW
y
C
BOTTOM VIEW
E2
D2
L
b
e
1
2
3
4
8
7
6
5
Pin #1 Notch
(0.20 R)
0.45
K
Pin #1
Chamfer
(C 0.35)
Option A
(Option B)
51
3595O–DFLASH–04/09
AT45DB041D
27.2 8S1 – JEDEC SOIC
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE DRAWING NO.
R
REV.
Note:
3/17/05
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC) 8S1 C
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 – 0.25
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
Ø
Ø
E
E
1
1
N
N
TOP VIEW
C
C
E1
E1
END VIEW
A
A
b
b
L
L
A1
A1
e
e
D
D
SIDE VIEW
52
3595O–DFLASH–04/09
AT45DB041D
27.3 8S2 – EIAJ SOIC
TITLE DRAWING NO. GPC REV.
Package Drawing Contact:
packagedrawings@atmel.com 8S2STN F
8S2, 8-lead, 0.208” Body, Plastic Small
Outline Package (EIAJ)
4/15/08
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs aren't included.
3. Determines the true geometric position.
4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
A 1.70 2.16
A1 0.05 0.25
b 0.35 0.48 4
C 0.15 0.35 4
D 5.13 5.35
E1 5.18 5.40 2
E 7.70 8.26
L 0.51 0.85
θ 0° 8°
e 1.27 BSC 3
θ
θ
1
1
N
N
E
E
TOP VIEW
TOP VIEW
C
C
E1
E1
END VIEW
END VIEW
A
A
b
b
L
L
A1
A1
e
e
D
D
SIDE VIEW
SIDE VIEW
53
3595O–DFLASH–04/09
AT45DB041D
28. Revision History
Revision Level – Revision Date History
A – October 2005 Initial Release
B – March 2006
Added “Preliminary”.
Added text, in “Programming the Configuration Register”, to
indicate that power cycling is required to switch to “power of 2”
page size after the opcode enable has been executed.
Added “Legacy Commands” table.
C – June 2006 Corrected typographical errors.
D – July 2006 Corrected typographical errors.
E – August 2006 Added errata regarding Chip Erase.
F – November 2006 Removed “Preliminary”.
G – February 2007 Removed RDY/BUSY pin references.
H – March 2007
Changed page size description from 512 to 256 in Table 15-6.
Changed page size description from 528 to 264 in Table 15-7.
Added additional text for “power of 2” binary page size option.
I – April 2007
Removed SER/BYTE statement from SI and SO pin descriptions in
Table 2-1.
Changed the number of don’t care bits from 17 to 16 for sector 1-15
erase in Section 7.6.
Corrected the density code description from 16-Mbit to 4-Mbit in
Section 14.1.2.
Changed A16 address bit for opcode 7Ch from “x” to “A” in Table
15-6.
Chagned PA8 address bit for opcode 7Ch from “x” to “P” in Table
15-7.
J – August 2007
Changed tXFR and tCOMP values from 400 µs to 200 µs.
Changed tVCSL from 50 µs to 70 µs.
Changed tRDPD from 30 µs to 35 µs.
K – December 2007 Changed Note 1 on page 14 from “0 through 15” to “0 through 7”.
L – April 2008
The Chip Erase command is supported on devices with date code
0810 and later.
Added Chip Erase time.
Added part nuber ordering code details for suffixes SL954/955.
Added ordering code detail.
M – February 2009 Changed tDIS (Typ and Max) to 27 ns and 35 ns, respectively.
N – March 2009
Changed Deep Power-Down Current values
- Increased typical value from 5 µA to 15 µA.
- Increased maximum value from 15 µA to 25 µA.
O - April 2009 Updated Absolute Maximum Ratings
Removed Chip Erase Errata
54
3595O–DFLASH–04/09
AT45DB041D
29. Errata
29.1 No Errata Conditions
3595O–DFLASH–04/09
Headquarters International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Atmel Asia
Unit 1-5 & 16, 19/F
BEA Tower, Millennium City 5
418 Kwun Tong Road
Kwun Tong, Kowloon
Hong Kong
Tel: (852) 2245-6100
Fax: (852) 2722-1369
Atmel Europe
Le Krebs
8, Rue Jean-Pierre Timbaud
BP 309
78054 Saint-Quentin-en-
Yvelines Cedex
France
Tel: (33) 1-30-60-70-00
Fax: (33) 1-30-60-71-11
Atmel Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Product Contact
Web Site
www.atmel.com
Technical Support
dataflash@atmel.com
Sales Contact
www.atmel.com/contacts
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-
TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT
OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided
otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use
as components in applications intended to support or sustain life.
© 2009 Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, Everywhere You Are®, DataFlash®, RapidS®
logo and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trade-
marks of others.
