LMP90080/LMP90079/
LMP90078/LMP90077
May 29, 2012
Sensor AFE System: Multi-Channel, Low-Power 16-Bit
Sensor AFE with True Continuous Background Calibration
1.0 General Description
The LMP90080/LMP90079/LMP90078/LMP90077 are highly
integrated, multi-channel, low-power 16-bit Sensor AFEs.
The devices feature a precision, 16-bit Sigma Delta Analog-
to-Digital Converter (ADC) with a low-noise programmable
gain amplifier and a fully differential high impedance analog
input multiplexer. A true continuous background calibration
feature allows calibration at all gains and output data rates
without interrupting the signal path. The background calibra-
tion feature essentially eliminates gain and offset errors
across temperature and time, providing measurement accu-
racy without sacrificing speed and power consumption.
Another feature of the LMP90080/LMP90079/LMP90078/
LMP90077 is continuous background sensor diagnostics, al-
lowing the detection of open and short circuit conditions and
out-of-range signals, without requiring user intervention, re-
sulting in enhanced system reliability.
Two sets of independent external reference voltage pins allow
multiple ratiometric measurements. In addition, two matched
programmable current sources are available in the
LMP90080/LMP90078 to excite external sensors such as re-
sistive temperature detectors and bridge sensors. Further-
more, seven GPIO pins are provided for interfacing to external
LEDs and switches to simplify control across an isolation bar-
rier.
Collectively, these features make the LMP90080/LMP90079/
LMP90078/LMP90077 complete analog front-ends for low-
power, precision sensor applications such as temperature,
pressure, strain gauge, and industrial process control. The
LMP90080/LMP90079/LMP90078/LMP90077 are guaran-
teed over the extended temperature range of -40°C to +125°
C and are available in a 28-pin TSSOP package with an ex-
posed pad.
2.0 Features
16-Bit Low-Power Sigma Delta ADC
True Continuous Background Calibration at all gains
In-Place System Calibration using Expected Value
programming
Low-Noise programmable gain (1x - 128x)
Continuous background open/short and out of range
sensor diagnostics
8 output data rates (ODR) with single-cycle settling
2 matched excitation current sources from 100 µA to
1000 µA (LMP90080/LMP90078)
4-DIFF / 7-SE inputs (LMP90080/LMP90079)
2-DIFF / 4-SE inputs (LMP90078/LMP90077)
7 General Purpose Input/Output pins
Chopper-stabilized buffer for low offset
SPI 4/3-wire with CRC data link error detection
50 Hz to 60 Hz line rejection at ODR 13.42 SPS
Independent gain and ODR selection per channel
Supported by Webench Sensor AFE Designer
Automatic Channel Sequencer
3.0 Key Specifications
■ ENOB/NFR Up to 16/16 bits
■ Offset Error (typ) 8.4 nV
■ Gain Error (typ) 7 ppm
■ Total Noise < 10 µV-rms
■ Integral Non-Linearity (INL max) ±1LSB
■ Output Data Rates (ODR) 1.6775 SPS - 214.65 SPS
■ Analog Voltage, VA +2.85V to +5.5V
■ Operating Temp Range -40°C to 125°C
■ Package 28-Pin TSSOP
exposed pad
4.0 Applications
Temperature and Pressure Transmitters
Strain Gauge Interface
Industrial Process Control
5.0 Typical Application
30169774
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2012 Texas Instruments Incorporated 301697 SNAS521E www.ti.com
LMP90080/LMP90079/LMP90078/LMP90077 Sensor AFE System: Multi-Channel, Low-Power 16-
Bit Sensor AFE with True Continuous Background Calibration
6.0 Block Diagram
30169775
FIGURE 1. Block Diagram
• True Continuous Background Calibration
The LMP90080/LMP90079/LMP90078/LMP90077 feature a
16 bit ΣΔ core with continuous background calibration to com-
pensate for gain and offset errors in the ADC, virtually elimi-
nating any drift with time and temperature. The calibration is
performed in the background without user or ADC input in-
terruption, making it unique in the industry and eliminating
down time associated with field calibration required with other
solutions. Having this continuous calibration improves perfor-
mance over the entire life span of the end product.
• Continuous Background Sensor Diagnostics
Sensor diagnostics are also performed in the background,
without interfering with signal path performance, allowing the
detection of sensor shorts, opens, and out-of-range signals,
which vastly improves system reliability. In addition, the fully
flexible input multiplexer described below allows any input pin
to be connected to any ADC input channel providing addi-
tional sensor path diagnostic capability.
• Flexible Input MUX Channels
The flexible input MUX allows interfacing to a wide range of
sensors such as thermocouples, RTDs, thermistors, and
bridge sensors. The LMP90080/LMP90079’s multiplexer sup-
ports 4 differential channels while the LMP90078/LMP90077
supports 2. Each effective input voltage that is digitized is VIN
= VINx – VINy, where x and y are any input. In addition, the
input multiplexer of the LMP90080/LMP90079 also supports
7 single-ended channels (LMP90078/LMP90077 supports 4),
where the common ground is any one of the inputs.
• Programmable Gain Amplifiers (FGA & PGA)
The LMP90080/LMP90079/LMP90078/LMP90077 contain
an internal 16x fixed gain amplifier (FGA) and a 1x, 2x, 4x, or
8x programmable gain amplifier (PGA). This allows accurate
gain settings of 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x through
configuration of internal registers. Having an internal amplifier
eliminates the need for external amplifiers that are costly,
space consuming, and difficult to calibrate.
• Excitation Current Sources (IB1 & IB2) - LMP90080/
LMP90078
Two matched internal excitation currents, IB1 and IB2, can be
used for sourcing currents to a variety of sensors. The current
range is from 100 µA to 1000 µA in steps of 100 µA.
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LMP90080/LMP90079/LMP90078/LMP90077
Table of Contents
1.0 General Description ......................................................................................................................... 1
2.0 Features ........................................................................................................................................ 1
3.0 Key Specifications ........................................................................................................................... 1
4.0 Applications .................................................................................................................................... 1
5.0 Typical Application ........................................................................................................................... 1
6.0 Block Diagram ................................................................................................................................ 2
7.0 Ordering Information ........................................................................................................................ 5
8.0 Connection Diagram ........................................................................................................................ 5
9.0 Pin Descriptions .............................................................................................................................. 6
10.0 Absolute Maximum Ratings ............................................................................................................. 7
11.0 Operating Ratings .......................................................................................................................... 7
12.0 Electrical Characteristics ................................................................................................................ 7
13.0 Timing Diagrams ......................................................................................................................... 12
14.0 Specific Definitions ...................................................................................................................... 15
15.0 Typical Performance Characteristics .............................................................................................. 16
16.0 Functional Description .................................................................................................................. 21
16.1 SIGNAL PATH ..................................................................................................................... 21
16.1.1 Reference Input (VREF) .............................................................................................. 21
16.1.2 Flexible Input MUX (VIN) ............................................................................................. 21
16.1.3 Selectable Gains (FGA & PGA) .................................................................................... 22
16.1.4 Buffer (BUFF) ............................................................................................................ 22
16.1.5 Internal/External CLK Selection .................................................................................... 22
16.1.6 Programmable ODRs .................................................................................................. 22
16.1.7 Digital Filter ............................................................................................................... 24
16.1.8 GPIO (D0–D6) ........................................................................................................... 27
16.2 CALIBRATION ..................................................................................................................... 27
16.2.1 Background Calibration ............................................................................................... 27
16.2.2 System Calibration ...................................................................................................... 28
FIGURE 15. Post-calibration Scaling Data-Flow Diagram ................................................... 29
16.3 CHANNELS SCAN MODE ..................................................................................................... 29
16.4 SENSOR INTERFACE .......................................................................................................... 30
16.4.1 IB1 & IB2 - Excitation Currents (LMP90080/LMP90078) ................................................... 30
16.4.2 Burnout Currents ........................................................................................................ 30
16.4.3 Sensor Diagnostic Flags .............................................................................................. 30
16.5 SERIAL DIGITAL INTERFACE ............................................................................................... 32
16.5.1 Register Address (ADDR) ............................................................................................ 32
16.5.2 Register Read/Write Protocol ....................................................................................... 32
16.5.3 Streaming .................................................................................................................. 32
16.5.4 CSB - Chip Select Bar ................................................................................................. 33
16.5.5 SPI Reset .................................................................................................................. 33
16.5.6 DRDYB - Data Ready Bar ............................................................................................ 33
16.5.7 Data Only Read Transaction ........................................................................................ 36
16.5.8 Cyclic Redundancy Check (CRC) ................................................................................. 37
16.6 POWER MANAGEMENT ...................................................................................................... 38
16.7 RESET and RESTART .......................................................................................................... 38
17.0 Applications Information ............................................................................................................... 39
17.1 QUICK START ..................................................................................................................... 39
17.2 CONNECTING THE SUPPLIES ............................................................................................. 39
17.2.1 VA and VIO ............................................................................................................... 39
17.2.2 VREF ........................................................................................................................ 39
17.3 ADC_DOUT CALCULATION .................................................................................................. 39
17.4 REGISTER READ/WRITE EXAMPLES ................................................................................... 40
17.4.1 Writing to Register Examples ....................................................................................... 40
17.4.2 Reading from Register Example ................................................................................... 41
17.5 STREAMING EXAMPLES ..................................................................................................... 42
17.5.1 Normal Streaming Example ......................................................................................... 42
17.5.2 Controlled Streaming Example ..................................................................................... 43
17.6 EXAMPLE APPLICATIONS ................................................................................................... 45
17.6.1 3–Wire RTD ............................................................................................................... 45
17.6.2 Thermocouple and IC Analog Temperature .................................................................... 47
18.0 Registers .................................................................................................................................... 48
18.1 REGISTER MAP .................................................................................................................. 48
18.2 POWER AND RESET REGISTERS ........................................................................................ 49
18.3 ADC REGISTERS ................................................................................................................ 51
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LMP90080/LMP90079/LMP90078/LMP90077
18.4 CHANNEL CONFIGURATION REGISTERS ............................................................................ 52
18.5 CALIBRATION REGISTERS .................................................................................................. 56
18.6 SENSOR DIAGNOSTIC REGISTERS ..................................................................................... 57
18.7 SPI REGISTERS .................................................................................................................. 58
18.8 GPIO REGISTERS ............................................................................................................... 60
19.0 Physical Dimensions .................................................................................................................... 61
List of Figures
FIGURE 1. Block Diagram ......................................................................................................................... 2
FIGURE 2. Timing Diagram ...................................................................................................................... 12
FIGURE 3. Simplified VIN Circuitry .............................................................................................................. 21
FIGURE 4. CLK Register Settings ............................................................................................................... 22
FIGURE 5. Digital Filter Response, 1.6775 SPS and 3.355 SPS .......................................................................... 24
FIGURE 6. Digital Filter Response, 6.71 SPS and 13.42 SPS .............................................................................. 24
FIGURE 7. Digital Filter Response at 13.42 SPS ............................................................................................. 25
FIGURE 8. Digital Filter Response, 26.83125 SPS and 53.6625 SPS .................................................................... 25
FIGURE 9. Digital Filter Response 107.325 SPS and 214.65 SPS ........................................................................ 26
FIGURE 10. Digital Filter Response for a 3.5717MHz versus 3.6864 MHz XTAL ...................................................... 26
FIGURE 11. GPIO Register Settings ............................................................................................................ 27
FIGURE 12. Types of Calibration ................................................................................................................ 27
FIGURE 13. BgcalMode2 Register Settings ................................................................................................... 28
FIGURE 14. System Calibration Data-Flow Diagram ......................................................................................... 28
FIGURE 15. Post-calibration Scaling Data-Flow Diagram ................................................................................... 29
FIGURE 16. Burnout Currents .................................................................................................................... 30
FIGURE 17. Burnout Currents Injection for ScanMode3 ..................................................................................... 30
FIGURE 18. Sensor Diagnostic Flags Diagram ............................................................................................... 31
FIGURE 19. Register Read/Write Protocol ..................................................................................................... 32
FIGURE 20. DRDYB Behavior .................................................................................................................... 33
FIGURE 21. DRDYB Behavior for an Incomplete ADC_DOUT Reading .................................................................. 33
FIGURE 22. DrdybCase1 Connection Diagram ............................................................................................... 34
FIGURE 23. Timing Protocol for DrdybCase1 ................................................................................................. 34
FIGURE 24. Timing Protocol for DrdybCase2 ................................................................................................. 35
FIGURE 25. DrdybCase3 Connection Diagram ............................................................................................... 36
FIGURE 26. Timing Protocol for DrdybCase3 ................................................................................................. 36
FIGURE 27. Timing Protocol for Reading SPI_CRC_DAT .................................................................................. 37
FIGURE 28. Timing Protocol for Reading SPI_CRC_DAT beyond normal DRDYB deassertion at every 1/ODR seconds ...... 37
FIGURE 29. Active, Power-Down, Stand-by State Diagram ................................................................................ 38
FIGURE 30. ADC_DOUT vs. VIN of a 16-Bit Resolution (VREF = 5.5V, Gain = 1). .................................................... 39
FIGURE 31. Register-Write Example 1 ......................................................................................................... 40
FIGURE 32. Register-Write Example 2 ......................................................................................................... 40
FIGURE 33. Register-Read Example ........................................................................................................... 41
FIGURE 34. Normal Streaming Example ....................................................................................................... 42
FIGURE 35. Setting up SPI_STREAMCN ...................................................................................................... 43
FIGURE 36. Controlled Streaming Example ................................................................................................... 44
FIGURE 37. Topology #1: 3-wire RTD Using 2 Current Sources ........................................................................... 45
FIGURE 38. Topology #2: 3-wire RTD Using 1 Current Source ............................................................................ 46
FIGURE 39. Thermocouple with CJC ........................................................................................................... 47
List of Tables
TABLE 1. ENOB (Noise Free Resolution) vs. Sampling Rate and Gain at VA = VIO = VREF = 3V ................................. 11
TABLE 2. RMS Noise (µV) vs. Sampling Rate and Gain at VA = VIO = VREF = 3V .................................................... 11
TABLE 3. ENOB (Noise Free Resolution) vs. Sampling Rate and Gain at VA = VIO = VREF = 5V .................................. 11
TABLE 4. RMS Noise (µV) vs. Sampling Rate and Gain at VA = VIO = VREF = 5V .................................................... 11
TABLE 5. Data First Mode Transactions ........................................................................................................ 36
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LMP90080/LMP90079/LMP90078/LMP90077
7.0 Ordering Information
Product Channel Configuration Current Sources
LMP90080 4 Differential / 7 Single-Ended Yes
LMP90079 4 Differential / 7 Single-Ended No
LMP90078 2 Differential / 4 Single-Ended Yes
LMP90077 2 Differential / 4 Single-Ended No
Order Code Temperature Range Description
LMP90080MH/NOPB −40°C to +125°C 28-Lead TSSOP Package, Rail of 48
LMP90080MHE/NOPB −40°C to +125°C 28-Lead TSSOP Package, Reel of 250
LMP90080MHX/NOPB −40°C to +125°C 28-Lead TSSOP Package, Reel of 2500
LMP90079MH/NOPB −40°C to +125°C 28-Lead TSSOP Package, Rail of 48
LMP90079MHE/NOPB −40°C to +125°C 28-Lead TSSOP Package, Reel of 250
LMP90079MHX/NOPB −40°C to +125°C 28-Lead TSSOP Package, Reel of 2500
LMP90078MH/NOPB −40°C to +125°C 28-Lead TSSOP Package, Rail of 48
LMP90078MHE/NOPB −40°C to +125°C 28-Lead TSSOP Package, Reel of 250
LMP90078MHX/NOPB −40°C to +125°C 28-Lead TSSOP Package, Reel of 2500
LMP90077MH/NOPB −40°C to +125°C 28-Lead TSSOP Package, Rail of 48
LMP90077MHE/NOPB −40°C to +125°C 28-Lead TSSOP Package, Reel of 250
LMP90077MHX/NOPB −40°C to +125°C 28-Lead TSSOP Package, Reel of 2500
8.0 Connection Diagram
30169776
See Pin Descriptions for specific information regarding options LMP90079, LMP90078, and LMP90077.
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LMP90080/LMP90079/LMP90078/LMP90077
9.0 Pin Descriptions
Pin # Pin Name Type Function
1 VA Analog Supply Analog power supply pin
2 - 4 VIN0 - VIN2 Analog Input Analog input pins
5 - 7
(LMP90080,
LMP90079)
VIN3 - VIN5 Analog Input Analog input pins
5 - 7
(LMP90078,
LMP90077)
VIN3 - VIN5 No Connect No connect: must be left unconnected
8 VREFP1 Analog Input Positive reference input
9 VREFN1 Analog Input Negative reference input
10 VIN6 / VREFP2 Analog Input Analog input pin or VREFP2 input
11 VIN7 / VREFN2 Analog Input Analog input pin or VREFN2 input
12 - 13
(LMP90080,
LMP90078)
IB2 & IB1 Analog output Excitation current sources for external RTDs
12 - 13
(LMP90080,
LMP90078)
IB2 & IB1 No Connect No connect: must be left unconnected
14 XOUT Analog output External crystal oscillator connection
15 XIN / CLK Analog input External crystal oscillator connection or external
clock input
16 GND Ground Power supply ground
17 CSB Digital Input Chip select bar
18 SCLK Digital Input Serial clock
19 SDI Digital Input Serial data input
20 SDO / DRDYB Digital Output Serial data output and data ready bar
21 - 26 D0 - D5 Digital IO General purpose input/output (GPIO) pins
27 D6 / DRDYB Digital IO General purpose input/output pin or data ready bar
28 VIO Digital Supply Digtal input/output supply pin
Thermal Pad Leave the thermal pad floating
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LMP90080/LMP90079/LMP90078/LMP90077
10.0 Absolute Maximum Ratings (Note
1, Note 2)
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
Analog Supply Voltage, VA -0.3V to 6.0V
Digital I/O Supply Voltage, VIO -0.3V to 6.0V
Reference Voltage, VREF -0.3V to VA+0.3V
Voltage on Any Analog Input Pin to
GND (Note 3)
-0.3V to VA+0.3V
Voltage on Any Digital Input PIN to
GND (Note 3)
-0.3V to VIO+0.3V
Voltage on SDO (Note 3) -0.3V to VIO + 0.3V
Input Current at Any Pin (Note 3) 5mA
Output Current Source or Sink by SDO 3mA
Total Package Input and Output
Current 20mA
ESD Susceptibility
Human Body Model (HBM) 2500V
Machine Models (MM) 200V
Charged Device Model (CDM) 1250V
Junction Temperature (TJMAX)+150°C
Storage Temperature Range –65°C to +150°C
For soldering specifications:
see product folder at www.national.com and
www.national.com/ms/MS/MS-SOLDERING.pdf
11.0 Operating Ratings
Analog Supply Voltage, VA +2.85V to 5.5V
Digital I/O Supply Voltage, VIO +2.7V to 5.5V
Full Scale Input Range, VIN ±VREF / PGA
Reference Voltage, VREF +0.5V to VA
Temperature Range for Electrical
Characteristics
TMIN = –40°C
TMAX = +125°C
Operating Temperature Range –40°C TA +125°C
Junction to Ambient Thermal
Resistance (θJA) (Note 4)41°C/W
12.0 Electrical Characteristics
Unless otherwise noted, the key for the condition is (VA = VIO = VREF) / ODR (SPS) / buffer / calibration / gain . Boldface limits
apply for TMIN TA TMAX; the typical values apply for TA = +25°C.
Symbol Parameter Conditions Min Typ Max Units
n Resolution 16 Bits
ENOB /
NFR
Effective Number
of Bits and Noise
Free Resolution
3V / all / ON / OFF / all. Shorted input. Table 1 Bits
5V / all / ON / OFF / all. Shorted input. Table 3 Bits
ODR Output Data Rates 1.6675 Table 1 214.6 SPS
Gain FGA × PGA 1 Table 1 128
INL Integral Non-
Linearity
3V / 214.65 / ON / ON / 1 -1 ± 0.5 +1 LSB
3V & 5V / 214.65 / ON / ON / 16 ± 1 LSB
Total Noise 3V / all / ON / ON / all. Shorted input. Table 2 µV
5V / all / ON / OFF / all. Shorted input. Table 4 µV
OE Offset Error
3V & 5V / all / ON or OFF / ON / all Below Noise
Floor (rms) µV
3V / 214.65 / ON / ON / 1 1.22 9.52 µV
3V / 214.65 / ON / ON / 128 0.00838 0.70 µV
5V / 214.65 / ON / ON / 1 1.79 8.25 µV
5V / 214.65 / ON / ON / 128 0.0112 0.63 µV
Offset Drift Over
Temp (Note 5)
3V & 5V / 214.65 / ON or OFF / OFF /
1-8
100 nV/°C
3V & 5V / 214.65 / ON / ON / 1-8 3 nV/°C
3V & 5V / 214.65 / ON / OFF / 16 25 nV/°C
3V & 5V / 214.65 / ON / ON / 16 0.4 nV/°C
3V & 5V / 214.65 / ON / OFF / 128 6 nV/°C
3V & 5V / 214.65 / ON / ON / 128 0.125 nV/°C
Offset Drift over
Time (Note 5)
5V / 214.65 / ON / OFF / 1, TA = 150°C 2360 nV /
1000 hours
5V / 214.65 / ON / ON / 1, TA = 150°C 100 nV /
1000 hours
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LMP90080/LMP90079/LMP90078/LMP90077
Symbol Parameter Conditions Min Typ Max Units
GE Gain Error
3V & 5V / 214.65 / ON / ON / 1 -80 780 ppm
3V & 5V / 13.42 / ON / ON / 16 50 ppm
3V & 5V / 13.42 / ON / ON / 64 50 ppm
3V & 5V / 13.42 / ON / ON / 128 100 ppm
Gain Drift over
Temp (Note 5)3V & 5V / 214.65 / ON / ON / all 0.5 ppm/°C
Gain Drift over
Time (Note 5)
5V / 214.65 / ON / OFF / 1, TA = 150°C 5.9 ppm / 1000
hours
5V / 214.65 / ON / ON / 1, TA = 150°C 1.6 ppm / 1000
hours
CONVERTER'S CHARACTERISTIC
CMRR
Input Common
Mode Rejection
Ratio
DC, 3V / 214.65 / ON / ON / 1 70 117 dB
DC, 5V / 214.65 / OFF / OFF / 1 90 120 dB
50/60 Hz, 5V / 214.65 / OFF / OFF / 1 117 dB
Reference
Common Mode
Rejection
VREF = 2.5V
101
dB
PSRR Power Supply
Rejection Ratio
DC, 3V / 214.65 / ON / ON / 1 75 115 dB
DC, 5V / 214.65 / ON / ON / 1 112 dB
NMRR
Normal Mode
Rejection Ratio
(Note 5)
47 Hz to 63 Hz, 5V / 13.42 / OFF / OFF /
178
dB
Cross-talk 3V / 214.65 / OFF / OFF / 1 95 136 dB
5V / 214.65 / OFF / OFF / 1 95 143 dB
POWER SUPPLY CHARACTERISTICS
VA Analog Supply
Voltage
2.85 3.0 5.5 V
VIO Digital Supply
Voltage
2.7 3.3 5.5 V
IVA Analog Supply
Current
3V / 13.42 / OFF / OFF / 1, ext. CLK 400 500 µA
5V / 13.42 / OFF / OFF / 1, ext. CLK 464 555 µA
3V / 13.42 / ON / OFF / 64, ext. CLK 600 700 µA
5V / 13.42 / ON / OFF / 64, ext. CLK 690 800 µA
3V / 214.65 / ON / OFF / 64, int. CLK 1547 1700 µA
5V / 214.65 / ON / OFF / 64, int. CLK 1760 2000 µA
3V / 214.65 / OFF / OFF / 1, int. CLK 826 1000 µA
5V / 214.65 / OFF / OFF / 1, int. CLK 941 1100 µA
Standby, 3V , int. CLK 3 10 µA
Standby, 3V , ext. CLK 257 µA
Standby, 5V, int. CLK 5 15 µA
Standby, 3V, ext. CLK 300 µA
Power-down, 3V, int/ext CLK 2.6 5µA
Power-down, 5V, int/ext CLK 4.6 9µA
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LMP90080/LMP90079/LMP90078/LMP90077
Symbol Parameter Conditions Min Typ Max Units
REFERENCE INPUT
VREFP Positive Reference VREFN + 0.5 VA V
VREFN Negative
Reference
GND VREFP - 0.5 V
VREF Differential
Reference VREF = VREFP - VREFN 0.5 VA V
ZREF Reference
Impedance 3V / 13.42 / OFF / OFF / 1 10 MOhm
IREF Reference Input 3V / 13.42 / ON or OFF / ON or OFF /
all ±2 µA
CREFP Capacitance of the
Positive Reference (Note 5), gain = 1 6 pF
CREFN
Capacitance of the
Negative
Reference
(Note 5), gain = 1
6
pF
ILREF Reference
Leakage Current
Power-down 1 nA
ANALOG INPUT
VINP Positive Input
Gain = 1-8, buffer ON GND + 0.1 VA - 0.1 V
Gain = 16 - 128, buffer ON GND + 0.4 VA - 1.5 V
Gain = 1-8, buffer OFF GND VA V
VINN Negative Input
Gain = 1-8, buffer ON GND + 0.1 VA - 0.1 V
Gain = 16 - 128, buffer ON GND + 0.4 VA - 1.5 V
Gain = 1-8, buffer OFF GND VA V
VIN Differential Input VIN = VINP - VINN ±VREF / PGA
ZIN Differential Input
Impedance
ODR = 13.42 SPS 15.4 MOhm
CINP Capacitance of the
Positive Input
5V / 214.65 / OFF / OFF / 1 4 pF
CINN Capacitance of the
Negative Input
5V / 214.65 / OFF / OFF / 1 4 pF
IIN Input Leakage
Current
3V & 5V / 13.42 / ON / OFF / 1-8 500 pA
3V & 5V / 13.42 / ON / OFF / 16 - 128 100 pA
DIGITAL INPUT CHARACTERISTICS at VA = VIO = VREF = 3.0V
VIH Logical "1" Input
Voltage
0.7 x VIO V
VIL Logical "0" Input
Voltage
0.3 x VIO V
IIL Digital Input
Leakage Current
-10 +10 µA
VHYST Digital Input
Hysteresis
0.1 x VIO V
DIGITAL OUTPUT CHARACTERISTICS at VA = VIO = VREF = 3.0V
VOH Logical "1" Output
Voltage
Source 300 µA 2.6 V
VOL Logical "0" Output
Voltage
Sink 300 µA 0.4 V
IOZH,
IOZL
TRI-
STATE®Leakage
Current
-10
10 µA
COUT TRI-STATE
Capacitance (Note 5) 5 pF
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LMP90080/LMP90079/LMP90078/LMP90077
Symbol Parameter Conditions Min Typ Max Units
EXCITATION CURRENT SOURCES CHARACTERISTICS (LMP90080/LMP90078 only)
IB1, IB2 Excitation Current
Source Output
0, 100, 200,
300, 400, 500,
600, 700, 800,
900, 1000
µA
IB1/IB2 Tolerance VA = VREF = 3V -7 2.5 7%
VA = VREF = 5V -3.5 0.2 3.5 %
IB1/IB2 Output
Compliance Range
VA = 3.0V & 5.0V,
IB1/IB2 = 100 µA to 1000 µA
VA - 0.8 V
IB1/IB2 Regulation VA = 5.0V,
IB1/IB2 = 100 µA to 1000 µA
0.07 % / V
IBTC IB1/IB2 Drift VA = 3.0V 95 ppm/°C
VA = 5.0V 60 ppm/°C
IBMT IB1/IB2 Matching
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 100 µA 0.34 1.53 %
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 200 µA 0.22 1%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 300 µA 0.2 0.85 %
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 400 µA 0.15 0.8 %
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 500 µA 0.14 0.7 %
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 600 µA 0.13 0.7 %
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 700 µA 0.075 0.65 %
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 800 µA 0.085 0.6 %
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 900 µA 0.11 0.55 %
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 1000 µA 0.11 0.45 %
IBMTC IB1/IB2 Matching
Drfit
VA = 3.0V & 5.0V,
IB1/IB2 = 100 µA to 1000 µA 2 ppm/°C
INTERNAL/EXTERNAL CLK
CLKIN Internal Clock
Frequency
893 kHz
CLKEXT External Clock
Frequency (Note 5) 1.8 3.5717 7.2 MHz
External Crystal
Frequency
Input Low Voltage 0 V
Input High Voltage 1 V
Frequency 1.8 3.5717 7.2 MHz
Start-up time 7 ms
SCLK Serial Clock 10 MHz
www.ti.com 10
LMP90080/LMP90079/LMP90078/LMP90077
TABLE 1. ENOB (Noise Free Resolution) vs. Sampling Rate and Gain at VA = VIO = VREF = 3V
ODR (SPS) Gain
1 2 4 8 16 32 64 128
1.6775 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5)
3.355 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (14.5)
6.71 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (16) 16 (16) 16 (15) 16 (14.5)
13.42 16 (16) 16 (16) 16 (15.5) 16 (15) 16 (16) 16 (15.5) 16 (15) 16 (14)
26.83125 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (15)
53.6625 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15) 16 (14.5)
107.325 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (16) 16 (15.5) 16 (14.5) 16 (14)
214.65 16 (16) 16 (16) 16 (15.5) 16 (15) 16 (16) 16 (15) 16 (14.5) 16 (13.5)
TABLE 2. RMS Noise (µV) vs. Sampling Rate and Gain at VA = VIO = VREF = 3V
ODR (SPS) Gain of the ADC
1 2 4 8 16 32 64 128
1.6775 3.08 1.90 1.53 1.27 0.23 0.21 0.15 0.14
3.355 4.56 2.70 2.21 1.67 0.34 0.27 0.24 0.26
6.71 6.15 4.10 3.16 2.39 0.51 0.40 0.37 0.35
13.42 8.60 5.85 4.29 3.64 0.67 0.54 0.51 0.49
26.83125 3.35 2.24 1.65 1.33 0.33 0.27 0.26 0.25
53.6625 4.81 3.11 2.37 1.90 0.44 0.39 0.37 0.36
107.325 6.74 4.51 3.38 2.66 0.63 0.54 0.52 0.49
214.65 9.52 6.37 4.72 3.79 0.90 0.79 0.72 0.70
TABLE 3. ENOB (Noise Free Resolution) vs. Sampling Rate and Gain at VA = VIO = VREF = 5V
SPS Gain of the ADC
1 2 4 8 16 32 64 128
1.6775 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16)
3.355 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5)
6.71 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15)
13.42 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (15)
26.83125 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5)
53.6625 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15)
107.325 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (14.5)
214.65 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15) 16 (14)
TABLE 4. RMS Noise (µV) vs. Sampling Rate and Gain at VA = VIO = VREF = 5V
SPS Gain of the ADC
1 2 4 8 16 32 64 128
1.6775 2.68 1.65 1.24 1.00 0.22 0.19 0.17 0.16
3.355 3.86 2.36 1.78 1.47 0.34 0.27 0.22 0.22
6.71 5.23 3.49 2.47 2.09 0.44 0.34 0.30 0.32
13.42 7.94 5.01 3.74 2.94 0.61 0.50 0.45 0.43
26.83125 2.90 1.86 1.34 1.08 0.29 0.24 0.23 0.23
53.6625 4.11 2.60 1.90 1.50 0.39 0.35 0.32 0.31
107.325 5.74 3.72 2.72 2.11 0.56 0.48 0.46 0.44
214.65 8.25 5.31 3.82 2.97 0.79 0.68 0.64 0.63
11 www.ti.com
LMP90080/LMP90079/LMP90078/LMP90077
13.0 Timing Diagrams
Unless otherwise noted, specified limits apply for VA = VIO = 3.0V. Boldface limits apply for TMIN TA TMAX; the typical values
apply for TA = +25°C.
30169701
FIGURE 2. Timing Diagram
Symbol Parameter Conditions Min Typical Max Units
fSCLK 10 MHz
tCH SCLK High time 0.4 / fSCLK ns
tCL SCLK Low time 0.4 / fSCLK ns
30169702
30169703
Symbol Parameter Conditions Min Typical Max Units
tCSSU
CSB Setup time prior to an SCLK
rising edge 5 ns
tCSH
CSB Hold time after the last rising
edge of SCLK 6 ns
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LMP90080/LMP90079/LMP90078/LMP90077
30169704
30169705
Symbol Parameter Conditions Min Typical Max Units
tCLKR SCLK Rise time 1.15 ns
tCLKF SCLK Fall time 1.15 ns
tDISU
SDI Setup time prior to an SCLK
rising edge 5 ns
tDIH
SDI Hold time after an SCLK rising
edge 6 ns
30169706
30169707
Symbol Parameter Conditions Min Typical Max Units
tDOA
SDO Access time after an SCLK
falling edge 35 ns
tDOH
SDO Hold time after an SCLK
falling edge 5 ns
tDOD1
SDO Disable time after the rising
edge of CSB 5 ns
13 www.ti.com
LMP90080/LMP90079/LMP90078/LMP90077
30169708 30169709
Symbol Parameter Conditions Min Typical Max Units
tDOD2
SDO Disable time after either
edge of SCLK 27 ns
30169710
30169711
Symbol Parameter Conditions Min Typical Max Units
tDOE
SDO Enable time from the falling
edge of the 8th SCLK 35 ns
tDOR SDO Rise time (Note 5) 7 ns
tDOF SDO Fall time (Note 5) 7 ns
tDRDYB
Data Ready Bar pulse at every
1/ODR second
ODR 13.42 SPS 64 µs
13.42 < ODR 214.65 SPS 4 µs
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified
Note 3: When the input voltage (VIN) exceeds the power supply (VIN < GND or VIN > VA), the current at that pin must be limited to 5mA and VIN has to be within
the Absolute Maximum Rating for that pin. The 20 mA package input current rating limits the number of pins that can safely exceed the power supplies with current
flow to four pins.
Note 4: The maximum power dissipation is a function of TJ(MAX) AND θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ
(MAX) - TA) / θJA.
Note 5: This parameter is guaranteed by design and/or characterization and is not tested in production.
www.ti.com 14
LMP90080/LMP90079/LMP90078/LMP90077
14.0 Specific Definitions
COMMON MODE REJECTION RATIO is a measure of how
well in-phase signals common to both input pins are rejected.
To calculate CMRR, the change in output offset is measured
while the common mode input voltage is changed.
CMRR = 20 LOG(ΔCommon Input / ΔOutput Offset)
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) – says that the converter is equivalent to a perfect ADC
of this (ENOB) number of bits. LMP90080’s ENOB is a DC
ENOB spec, not the dynamic ENOB that is measured using
FFT and SINAD. Its equation is as follows:
GAIN ERROR is the deviation from the ideal slope of the
transfer function.
INTEGRAL NON-LINEARITY (INL) is a measure of the de-
viation of each individual code from a straight line through the
input to output transfer function. The deviation of any given
code from this straight line is measured from the center of that
code value. The end point fit method is used. INL for this
product is specified over a limited range, per the Electrical
Tables.
NEGATIVE FULL-SCALE ERROR is the difference between
the differential input voltage at which the output code transi-
tions to negative full scale and (-VREF + 1LSB).
NEGATIVE GAIN ERROR is the difference between the neg-
ative full-scale error and the offset error divided by (VREF /
Gain).
NOISE FREE RESOLUTION is a method of specifying the
number of bits for a converter with noise.
ODR Output Data Rate.
OFFSET ERROR is the difference between the differential
input voltage at which the output code transitions from code
0000h to 0001h and 1 LSB.
POSITIVE FULL-SCALE ERROR is the difference between
the differential input voltage at which the output code transi-
tions to positive full scale and (VREF – 1LSB).
POSITIVE GAIN ERROR is the difference between the pos-
itive full-scale error and the offset error divided by (VREF /
Gain).
POWER SUPPLY REJECTION RATIO (PSRR) is a measure
of how well a change in the analog supply voltage is rejected.
PSRR is calculated from the ratio of the change in offset error
for a given change in supply voltage, expressed in dB.
PSRR = 20 LOG (ΔVA / ΔOutput Offset)
15 www.ti.com
LMP90080/LMP90079/LMP90078/LMP90077
15.0 Typical Performance Characteristics Unless otherwise noted, specified limits apply for VA =
VIO = VREF = 3.0V. The maximum and minimum values apply for TA = TMIN to TMAX; the typical values apply for TA = +25°C.
Noise Measurement without Calibration at Gain = 1
0 200 400 600 800 1000
150
170
190
210
230
250
VOUT (μV)
TIME (ms)
VA = 3V
30169715
Noise Measurement with Calibration at Gain = 1
0 200 400 600 800 1000
-50
-30
-10
10
30
50
VOUT (μV)
TIME (ms)
VA = 3V
30169716
Histogram without Calibration at Gain = 1
30169721
Histogram with Calibration at Gain = 1
30169722
Noise Measurement without Calibration at Gain = 8
0 200 400 600 800 1000
0
5
10
15
20
25
30
35
40
VOUT (μV)
TIME (ms)
VA = 3V
30169717
Noise Measurement with Calibration at Gain = 8
0 200 400 600 800 1000
-20
-15
-10
-5
0
5
10
15
20
VOUT (μV)
TIME (ms)
VA = 3V
30169718
www.ti.com 16
LMP90080/LMP90079/LMP90078/LMP90077
Histogram without Calibration at Gain = 8
30169723
Histogram with Calibration at Gain = 8
30169724
Noise Measurement without Calibration at Gain = 128
0 200 400 600 800 1000
-4
-3
-2
-1
0
1
2
3
4
VOUT (μV)
TIME (ms)
VA = 3V
30169719
Noise Measurement with Calibration at Gain = 128
0 200 400 600 800 1000
-4
-3
-2
-1
0
1
2
3
4
VOUT (μV)
TIME (ms)
VA = 3V
30169720
Histogram without Calibration at Gain = 128
30169725
Histogram with Calibration at Gain = 128