TL071, TL071H, TL071A, TL071B TL071, TL074B, TL071H, TL072M, TL071A, TL074M TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A,1978 TL074B, TL072M, TL074M SLOS080P - SEPTEMBER - REVISED NOVEMBER 2020 www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 TL07xx Low-Noise FET-Input Operational Amplifiers 1 Features * * * * * * * * * * High slew rate: 20 V/s (TL07xH, typ) Low offset voltage: 1 mV (TL07xH, typ) Low offset voltage drift: 2 V/C Low power consumption: 940 A/ch (TL07xH, typ) Wide common-mode and differential voltage ranges - Common-mode input voltage range includes VCC+ Low input bias and offset currents Low noise: Vn = 18 nV/ Hz (typ) at f = 1 kHz Output short-circuit protection Low total harmonic distortion: 0.003% (typ) Wide supply voltage: 2.25 V to 20 V, 4.5 V to 40 V (1.5 kV, HBM), integrated EMI and RF filters, and operation across the full -40C to 125C enable the TL07xH devices to be used in the most rugged and demanding applications. Device Information PART NUMBER(1) TL071x TL072x 2 Applications * * * * * * Solar energy: string and central inverter Motor drives: AC and servo drive control and power stage modules Single phase online UPS Three phase UPS Pro audio mixers Battery test equipment TL072M TL074x 3 Description The TL07xH (TL071H, TL072H, and TL074H) family of devices are the next-generation versions of the industry-standard TL07x (TL071, TL072, and TL074) devices. These devices provide outstanding value for cost-sensitive applications, with features including low offset (1 mV, typical), high slew rate (20 V/s), and common-mode input to the positive supply. High ESD TL074M (1) PACKAGE BODY SIZE (NOM) PDIP (8) 9.59 mm x 6.35 mm SC70 (5) 2.00 mm x 1.25 mm SO (8) 6.20 mm x 5.30 mm SOIC (8) 4.90 mm x 3.90 mm SOT-23 (5) 1.60 mm x 1.20 mm PDIP (8) 9.59 mm x 6.35 mm SO (8) 6.20 mm x 5.30 mm SOIC (8) 4.90 mm x 3.90 mm SOT-23 (8) 2.90 mm x 1.60 mm TSSOP (8) 4.40 mm x 3.00 mm VSSOP (8) 3.00 mm x 3.00 mm CDIP (8) 9.59 mm x 6.67 mm CFP (10) 6.12 mm x 3.56 mm LCCC (20) 8.89 mm x 8.89 mm PDIP (14) 19.30 mm x 6.35 mm SO (14) 10.30 mm x 5.30 mm SOIC (14) 8.65 mm x 3.91 mm SOT-23 (14) 4.20 mm x 2.00 mm SSOP (14) 6.20 mm x 5.30 mm TSSOP (14) 5.00 mm x 4.40 mm CDIP (14) 19.56 mm x 6.92 mm CFP (14) 9.21 mm x 6.29 mm LCCC (20) 8.89 mm x 8.89 mm For all available packages, see the orderable addendum at the end of the data sheet. TL071 TL072 (each amplifier) TL074 (each amplifier) OFFSET N1 IN+ + IN+ + IN- - OUT IN- OFFSET N2 OUT - Copyright (c) 2017, Texas Instruments Incorporated Logic Symbols An(c)IMPORTANT NOTICEIncorporated at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyright 2020 Texas Instruments Submit Document Feedback intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 1 TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 www.ti.com Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................4 6 Specifications................................................................ 10 6.1 Absolute Maximum Ratings: TL07xH .......................10 6.2 Absolute Maximum Ratings: All Devices Except TL07xH........................................................................10 6.3 ESD Ratings: TL07xH ..............................................10 6.4 ESD Ratings: All Devices Except TL07xH................ 11 6.5 Recommended Operating Conditions: TL07xH ....... 11 6.6 Recommended Operating Conditions: All Devices Except TL07xH.............................................. 11 6.7 Thermal Information for Single Channel: TL071H ....11 6.8 Thermal Information: TL071x....................................12 6.9 Thermal Information for Dual Channel: TL072H ...... 12 6.10 Thermal Information: TL072x..................................12 6.11 Thermal Information: TL072x (cont.).......................13 6.12 Thermal Information for Quad Channel: TL074H ...13 6.13 Thermal Information: TL074x..................................13 6.14 Thermal Information: TL074x (cont)........................14 6.15 Thermal Information: TL074x (cont)........................14 6.16 Thermal Information................................................14 6.17 Electrical Characteristics: TL07xH ......................... 15 6.18 Electrical Characteristics: TL071C, TL072C, TL074C........................................................................17 6.19 Electrical Characteristics: TL071AC, TL072AC, TL074AC..................................................................... 18 6.20 Electrical Characteristics: TL071BC, TL072BC, TL074BC..................................................................... 19 6.21 Electrical Characteristics: TL071I, TL072I, TL074I......................................................................... 20 6.22 Electrical Characteristics, TL07xC, TL07xAC, TL07xBC, TL07xI........................................................ 21 6.23 Electrical Characteristics: TL071M, TL072M.......... 22 6.24 Electrical Characteristics: TL074M......................... 23 6.25 Switching Characteristics: TL07xM.........................24 6.26 Switching Characteristics: TL07xC, TL07xAC, TL07xBC, TL07xI........................................................ 24 6.27 Electrical Characteristics, TL07xM..........................25 6.28 Switching Characteristics........................................25 6.29 Typical Characteristics: TL07xH............................. 26 6.30 Typical Characteristics: All Devices Except TL07xH........................................................................33 7 Parameter Measurement Information.......................... 37 8 Detailed Description......................................................38 8.1 Overview................................................................... 38 8.2 Functional Block Diagram......................................... 38 8.3 Feature Description...................................................39 8.4 Device Functional Modes..........................................39 9 Application and Implementation.................................. 40 9.1 Application Information............................................. 40 9.2 Typical Application.................................................... 40 9.3 Unity Gain Buffer.......................................................41 9.4 System Examples..................................................... 42 10 Power Supply Recommendations..............................43 11 Layout........................................................................... 43 11.1 Layout Guidelines................................................... 43 11.2 Layout Example...................................................... 44 12 Device and Documentation Support..........................45 12.1 Related Links.......................................................... 45 12.2 Receiving Notification of Documentation Updates..45 12.3 Support Resources................................................. 45 12.4 Trademarks............................................................. 45 12.5 Electrostatic Discharge Caution..............................45 12.6 Glossary..................................................................45 13 Mechanical, Packaging, and Orderable Information.................................................................... 45 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision O (October 2020) to Revision P (November 2020) Page * Added SOIC and TSSOP package thermal information in Thermal Information for Quad Channel: TL074H section ........................................................................................................................................................... 13 * Added Typical Characteristics:TL07xH section in Specifications section......................................................... 26 Changes from Revision N (July 2017) to Revision O (October 2020) Page * Updated the numbering format for tables, figures, and cross-references throughout the document..................1 * Features of TL07xH added to the Features section........................................................................................... 1 * Added link to applications in the Applications section........................................................................................ 1 * Added TL07xH in the Description section...........................................................................................................1 * Added TL07xH device in the Device Information section................................................................................... 1 * Added SOT-23 (14), VSSOP (8), SOT-23 (8), SC70 (5), and SOT-23 (5) packages to the Device Information section................................................................................................................................................................ 1 * Added TSSOP, VSSOP and DDF packages to TL072x in Pin Configuration and Functions section................. 4 2 Submit Document Feedback Copyright (c) 2020 Texas Instruments Incorporated Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M www.ti.com * * * * TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 Added DYY package to TL074x in Pin Configuration and Functions section..................................................... 4 Removed Table of Graphs from the Typical Characteistics section..................................................................33 Deleted reference to obsolete documentation in Layout Guidelines section.................................................... 43 Removed Related Documentation section....................................................................................................... 45 Changes from Revision M (February 2014) to Revision N (July 2017) Page * Updated data sheet text to latest documentation and translation standards...................................................... 1 * Added TL072M and TL074M devices to data sheet .......................................................................................... 1 * Rewrote text in Description section ................................................................................................................... 1 * Changed TL07x 8-pin PDIP package to 8-pin CDIP package in Device Information table ............................... 1 * Deleted 20-pin LCCC package from Device Information table .......................................................................... 1 * Added 2017 copyright statement to front page schematic..................................................................................1 * Deleted TL071x FK (LCCC) pinout drawing and pinout table in Pin Configurations and Functions section ..... 4 * Updated pinout diagrams and pinout tables in Pin Configurations and Functions section ................................ 4 * Deleted differential input voltage parameter from Absolute Maximum Ratings table ...................................... 10 * Deleted table notes from Absolute Maximum Ratings table ............................................................................ 10 * Added new table note to Absolute Maximum Ratings table ............................................................................ 10 * Changed minimum supply voltage value from -18 V to -0.3 V in Absolute Maximum Ratings table...............10 * Changed maximum supply voltage from 18 V to 36 V in Absolute Maximum Ratings table............................ 10 * Changed minimum input voltage value from -15 V to VCC- - 0.3 V in Absolute Maximum Ratings table....... 10 * Changed maximum input voltage from 15 V to VCC- + 36 V in Absolute Maximum Ratings table................... 10 * Added input clamp current parameter to Absolute Maximum Ratings table ....................................................10 * Changed common-mode voltage maximum value from VCC+ - 4 V to VCC+ in the Recommended Operating Conditions table................................................................................................................................................ 11 * Changed devices in Recommended Operating Conditions table from TL07xA and TL07xB to TL07xAC and TL07xBC .......................................................................................................................................................... 11 * Added TL07xI operating free-air temperature minimum value of -40C to Recommended Operating Conditions table ............................................................................................................................................... 11 * Added U (CFP) package thermal values to Thermal Information: TL072x (cont.) table................................... 13 * Added W (CFP) package thermal values to Thermal Information: TL074x (cont.) table.................................. 14 * Added Figure 6-59 to Typical Characteristics section.......................................................................................33 * Added second Typical Application section application curves .........................................................................41 * Reformatted document references in Layout Guidelines section .................................................................... 43 Changes from Revision L (February 2014) to Revision M (February 2014) Page * Added Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section........................................................................................................ 1 Changes from Revision K (January 2014) to Revision L (February 2014) Page * Moved Tstg to Handling Ratings table .............................................................................................................. 11 Changes from Revision J (March 2005) to Revision K (January 2014) Page * Updated document to new TI datasheet format - no specification changes....................................................... 1 Copyright (c) 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 3 TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 www.ti.com 5 Pin Configuration and Functions OFFSET N1 1 8 NC IN 2 7 VCC+ IN+ 3 6 OUT VCC 4 5 OFFSET N2 Not to scale NC- no internal connection Figure 5-1. TL071x D, P, and PS Package 8-Pin SOIC, PDIP, and SO Top View Table 5-1. Pin Functions: TL071x PIN NAME 4 NO. I/O DESCRIPTION IN- 2 I Inverting input IN+ 3 I Noninverting input NC 8 -- Do not connect OFFSET N1 1 -- Input offset adjustment OFFSET N2 5 -- Input offset adjustment OUT 6 O Output VCC- 4 -- Power supply VCC+ 7 -- Power supply Submit Document Feedback Copyright (c) 2020 Texas Instruments Incorporated Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 1OUT 1 8 VCC+ 1IN 2 7 2OUT 1IN+ 3 6 2IN VCC 4 5 2IN+ Not to scale Figure 5-2. TL072x D, DDF, DGK, JG, P, PS, and PW Package 8-Pin SOIC, SOT-23 (8), VSSOP, CDIP, PDIP, SO, and TSSOP Top View Table 5-2. Pin Functions: TL072x PIN NAME NO. I/O DESCRIPTION 1IN- 2 I Inverting input 1IN+ 3 I Noninverting input 1OUT 1 O Output 2IN- 6 I Inverting input 2IN+ 5 I Noninverting input 2OUT 7 O Output VCC- 4 -- Power supply VCC+ 8 -- Power supply Copyright (c) 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 5 TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 NC 1 10 1OUT 2 9 VCC+ 1IN 3 8 2OUT 1IN+ 4 7 2IN VCC 5 6 2IN+ www.ti.com NC Not to scale NC- no internal connection Figure 5-3. TL072x U Package 10-Pin CFP Top View Table 5-3. Pin Functions: TL072x PIN NAME 1IN- 3 1IN+ 1OUT I/O DESCRIPTION I Inverting input 4 I Noninverting input 2 O Output 2IN- 7 I Inverting input 2IN+ 6 I Noninverting input 2OUT 8 O Output 1, 10 -- Do not connect VCC- 5 -- Power supply VCC+ 9 -- Power supply NC 6 NO. Submit Document Feedback Copyright (c) 2020 Texas Instruments Incorporated Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com NC 19 NC 1 VCC+ 1OUT 2 20 NC 3 SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 5 17 2OUT NC 6 16 NC 1IN+ 7 15 2IN NC 8 14 NC NC 2IN+ NC VCC NC 13 1IN 12 NC 11 18 10 4 9 NC Not to scale NC- no internal connection Figure 5-4. TL072 FK Package 20-Pin LCCC Top View Table 5-4. Pin Functions: TL072x PIN NAME NO. 1IN- 5 1IN+ 1OUT I/O DESCRIPTION I Inverting input 7 I Noninverting input 2 O Output 2IN- 15 I Inverting input 2IN+ 12 I Noninverting input 2OUT 17 O Output 1, 3, 4, 6, 8, 9, 11, 13, 14, 16, 18, 19 -- Do not connect VCC- 10 -- Power supply VCC+ 20 -- Power supply NC Copyright (c) 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 7 TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 1OUT 1 14 4OUT 1IN 2 13 4IN 1IN+ 3 12 4IN+ VCC+ 4 11 VCC 2IN+ 5 10 3IN+ 2IN 6 9 3IN 2OUT 7 8 3OUT www.ti.com Not to scale Figure 5-5. TL074x D, N, NS, PW, J, DYY, and W Packages 14-Pin SOIC, PDIP, SO, TSSOP, CDIP, SOT-23 (14), and CFP Top View Table 5-5. Pin Functions: TL074x PIN NAME 8 NO. 1IN- 2 1IN+ 1OUT I/O DESCRIPTION I Inverting input 3 I Noninverting input 1 O Output 2IN- 6 I Inverting input 2IN+ 5 I Noninverting input 2OUT 7 O Output 3IN- 9 I Inverting input 3IN+ 10 I Noninverting input 3OUT 8 O Output 4IN- 13 I Inverting input 4IN+ 12 I Noninverting input 4OUT 14 O Output VCC- 11 -- Power supply VCC+ 4 -- Power supply Submit Document Feedback Copyright (c) 2020 Texas Instruments Incorporated Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com 4IN 19 NC 1 4OUT 1OUT 2 20 1IN 3 SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 5 17 NC VCC+ 6 16 VCC NC 7 15 NC 2IN+ 8 14 3IN+ 3IN 3OUT NC 2OUT 2IN 13 NC 12 4IN+ 11 18 10 4 9 1IN+ Not to scale NC- no internal connection Figure 5-6. TL074 FK Package 20-Pin LCCC Top View Table 5-6. Pin Functions: TL074x PIN NAME NO. 1IN- 3 1IN+ 1OUT I/O DESCRIPTION I Inverting input 4 I Noninverting input 2 O Output 2IN- 9 I Inverting input 2IN+ 8 I Noninverting input 2OUT 10 O Output 3IN- 13 I Inverting input 3IN+ 14 I Noninverting input 3OUT 12 O Output 4IN- 19 I Inverting input 4IN+ 18 I Noninverting input 4OUT 20 O Output 1, 5, 7, 11, 15, 17 -- Do not connect VCC- 16 -- Power supply VCC+ 6 -- Power supply NC Copyright (c) 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 9 TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 6 Specifications 6.1 Absolute Maximum Ratings: TL07xH over operating ambient temperature range (unless otherwise noted) (1) MIN Supply voltage, VS = (VCC+) - (VCC-) Common-mode voltage (3) Signal input pins Differential voltage MAX 0 42 V (VCC-) - 0.5 (VCC+) + 0.5 V (3) Current (3) VS + 0.2 -10 Output short-circuit (2) -55 Junction temperature, TJ Storage temperature, Tstg (2) (3) V 10 mA 150 C 150 C 150 C Continuous Operating ambient temperature, TA (1) UNIT -65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Short-circuit to ground, one amplifier per package. Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be current limited to 10 mA or less. 6.2 Absolute Maximum Ratings: All Devices Except TL07xH over operating free-air temperature range (unless otherwise noted) (1) VCC+ - VCC- MIN MAX UNIT -0.3 36 V VCC- - 0.3 VCC- + 36 V -50 mA 150 C Supply voltage (3) VI Input voltage IIK Input clamp current Duration of output short circuit(2) TJ Tstg (1) (2) (3) Unlimited Operating virtual junction temperature Case temperature for 60 seconds - FK package 260 C Lead temperature 1.8 mm (1/16 inch) from case for 10 seconds 300 C 150 C Storage temperature -65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The output may be shorted to ground or to either supply. Temperature and supply voltages must be limited to ensure that the dissipation rating is not exceeded. Differential voltage only limited by input voltage. 6.3 ESD Ratings: TL07xH VALUE V(ESD) (1) (2) 10 Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 1500 Charged device model (CDM), per JEDEC specification JESD22-C101 (2) 1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Document Feedback Copyright (c) 2020 Texas Instruments Incorporated Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 6.4 ESD Ratings: All Devices Except TL07xH VALUE Human body model (HBM), per ANSI/ESDA/JEDEC V(ESD) (1) (2) Electrostatic discharge JS-001(1) UNIT 2000 Charged-device model (CDM), per JEDEC specification JESD22C101(2) V 1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.5 Recommended Operating Conditions: TL07xH over operating ambient temperature range (unless otherwise noted) MIN VS Supply voltage, (VCC+) - (VCC-) VI Input voltage range TA Specified temperature MAX UNIT 4.5 40 V (VCC-) + 2 (VCC+) + 0.1 V -40 125 C 6.6 Recommended Operating Conditions: All Devices Except TL07xH over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC+ Supply voltage (1) 5 15 V VCC- Supply voltage (1) -5 -15 V VCM Common-mode voltage V TA Operating free-air temperature VCC- + 4 VCC+ TL07xM -55 125 TL08xQ -40 125 TL07xI -40 85 0 70 TL07xAC, TL07xBC, TL07xC (1) C VCC+ and VCC- are not required to be of equal magnitude, provided that the total VCC (VCC+ - VCC-) is between 10 V and 30 V. 6.7 Thermal Information for Single Channel: TL071H TL071H THERMAL METRIC (1) (2) D (SOIC) DBV (2) (SOT-23) 8 PINS 5 PINS UNIT RJA Junction-to-ambient thermal resistance TBD TBD C/W RJC(top) Junction-to-case (top) thermal resistance TBD TBD C/W RJB Junction-to-board thermal resistance TBD TBD C/W JT Junction-to-top characterization parameter TBD TBD C/W JB Junction-to-board characterization parameter TBD TBD C/W RJC(bot) Junction-to-case (bottom) thermal resistance TBD TBD C/W (1) (2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. This package option is preview for TL071H. Copyright (c) 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 11 TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 6.8 Thermal Information: TL071x TL071x THERMAL METRIC(1) D (SOIC) P (PDIP) PS (SO) 8 PINS 8 PINS 8 PINS UNIT RJA Junction-to-ambient thermal resistance 97 85 95 C/W RJC(top) Junction-to-case (top) thermal resistance -- -- -- C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.9 Thermal Information for Dual Channel: TL072H TL072H THERMAL METRIC (1) D (2) (SOIC) DGK (2) (VSSOP) PW (2) (TSSOP) 8 PINS 8 PINS 8 PINS UNIT RJA Junction-to-ambient thermal resistance TBD TBD TBD C/W RJC(top) Junction-to-case (top) thermal resistance TBD TBD TBD C/W RJB Junction-to-board thermal resistance TBD TBD TBD C/W JT Junction-to-top characterization parameter TBD TBD TBD C/W JB Junction-to-board characterization parameter TBD TBD TBD C/W RJC(bot) Junction-to-case (bottom) thermal resistance TBD TBD TBD C/W (1) (2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. This package option is preview for TL072H. 6.10 Thermal Information: TL072x TL072x THERMAL METRIC(1) RJA Junction-to-ambient thermal resistance RJC(top) Junction-to-case (top) thermal resistance (1) 12 D (SOIC) JG (CDIP) P (PDIP) PS (SO) UNIT 8 PINS 8 PINS 8 PINS 8 PINS 97 -- 85 95 C/W -- 15.05 -- -- C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright (c) 2020 Texas Instruments Incorporated Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 6.11 Thermal Information: TL072x (cont.) TL072x THERMAL METRIC(1) PW (TSSOP) U (CFP) FK (LCCC) 8 PINS 10 PINS 20 PINS UNIT RJA Junction-to-ambient thermal resistance 150 169.8 -- C/W RJC(top) Junction-to-case (top) thermal resistance -- 62.1 5.61 C/W RJB Junction-to-board thermal resistance -- 176.2 -- C/W JT Junction-to-top characterization parameter -- 48.4 -- C/W JB Junction-to-board characterization parameter -- 144.1 -- C/W RJC(bot) Junction-to-case (bottom) thermal resistance -- 5.4 -- C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.12 Thermal Information for Quad Channel: TL074H TL074H THERMAL METRIC (1) D (SOIC) PW (TSSOP) 14 PINS 14 PINS UNIT RJA Junction-to-ambient thermal resistance 114.2 134.4 C/W RJC(top) Junction-to-case (top) thermal resistance 70.3 62.6 C/W RJB Junction-to-board thermal resistance 70.2 77.6 C/W JT Junction-to-top characterization parameter 28.8 13.0 C/W JB Junction-to-board characterization parameter 69.8 77.0 C/W RJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.13 Thermal Information: TL074x TL074x THERMAL METRIC(1) D (SOIC) N (PDIP) NS (SO) 14 PINS 14 PINS 14 PINS UNIT RJA Junction-to-ambient thermal resistance 86 80 76 C/W RJC(top) Junction-to-case (top) thermal resistance -- -- -- C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Copyright (c) 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 13 TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 6.14 Thermal Information: TL074x (cont). TL074x THERMAL METRIC(1) RJA Junction-to-ambient thermal resistance RJC(top) Junction-to-case (top) thermal resistance RJB JT J (CDIP) PW (TSSOP) W (CFP) 14 PINS 14 PINS 14 PINS UNIT -- 113 128.8 C/W 14.5 -- 56.1 C/W Junction-to-board thermal resistance -- -- 127.6 C/W Junction-to-top characterization parameter -- -- 29 C/W JB Junction-to-board characterization parameter -- -- 106.1 C/W RJC(bot) Junction-to-case (bottom) thermal resistance -- -- 0.5 C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.15 Thermal Information: TL074x (cont). TL074x THERMAL METRIC(1) FK (LCCC) UNIT 20 PINS RJA Junction-to-ambient thermal resistance RJC(top) Junction-to-case (top) thermal resistance (1) -- C/W 5.61 C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.16 Thermal Information TL071/TL072/TL074 D (SOIC) THERMAL METRIC(1) FK (LCCC) J (CDIP) 14 8 PINS 20 PINS 8 PINS PINS N (PDIP) 14 PINS 8 PINS 14 PINS NS (SO) PW (TSSOP) 8 8 PINS 14 PINS PINS UNIT 14 PINS RJA Junction-to-ambient thermal resistance 97 86 -- -- -- 85 80 95 76 150 113 C/W RJC(top) Junction-to-case (top) thermal resistance -- -- 5.61 15.05 14.5 -- -- -- -- -- -- C/W (1) 14 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright (c) 2020 Texas Instruments Incorporated Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 6.17 Electrical Characteristics: TL07xH For VS = (VCC+) - (VCC-) = 4.5 V to 40 V (2.25 V to 20 V) at TA = 25C, RL = 10 k connected to VS / 2, VCM = VS / 2, and VO UT = VS / 2, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX 1 4 UNIT OFFSET VOLTAGE VOS Input offset voltage TA = -40C to 125C 5 dVOS/dT Input offset voltage drift TA = -40C to 125C 2 PSRR Input offset voltage versus power supply VS = 5 V to 40 V, VCM = V TA = -40C to 125C S/2 1 Channel separation f = 0 Hz 10 mV V/ 10 V/V V/V INPUT BIAS CURRENT IB Input bias current IOS Input offset current 1 TA = -40C to 125C (1) 0.5 TA = -40C to 125C (1) 120 pA 5 nA 120 pA 5 nA NOISE EN 9.2 VPP 1.4 VRMS Input voltage noise f = 0.1 Hz to 10 Hz eN Input voltage noise density f = 1 kHz 37 f = 10 kHz 21 iN Input current noise f = 1 kHz 80 nV/Hz fA/Hz INPUT VOLTAGE RANGE VCM Common-mode voltage range CMRR Common-mode rejection ratio CMRR Common-mode rejection ratio CMRR Common-mode rejection ratio CMRR Common-mode rejection ratio (VCC-) + 1.5 VS = 40 V, (VCC-) + 2.5 V < VCM < (VCC+) - 1.5 V VS = 40 V, (VCC-) + 2.5 V < VCM < (VCC+) 100 TA = -40C to 125C 105 95 90 TA = -40C to 125C (VCC+) V dB dB 105 80 dB dB INPUT CAPACITANCE ZID Differential ZICM Common-mode 100 || 2 M || pF 6 || 1 T || pF OPEN-LOOP GAIN AOL VS = 40 V, VCM = VS / 2, Open-loop voltage gain (VCC-) + 0.3 V < VO < (V CC+) - 0.3 V TA = -40C to 125C 118 125 dB AOL VS = 40 V, VCM = VS / 2, Open-loop voltage gain RL = 2 k, (VCC-) + 1.2 V TA = -40C to 125C < VO < (VCC+) - 1.2 V 115 120 dB 5.25 MHz 20 V/s FREQUENCY RESPONSE GBW Gain-bandwidth product SR Slew rate VS = 40 V, G = +1, CL = 20 pF Copyright (c) 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 15 TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 For VS = (VCC+) - (VCC-) = 4.5 V to 40 V (2.25 V to 20 V) at TA = 25C, RL = 10 k connected to VS / 2, VCM = VS / 2, and VO UT = VS / 2, unless otherwise noted. PARAMETER tS Settling time Phase margin TEST CONDITIONS MIN TYP To 0.1%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF 0.63 To 0.1%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF 0.56 To 0.01%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20 pF 0.91 To 0.01%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20 pF 0.48 G = +1, RL = 10k, CL = 20 pF Overload recovery time VIN x gain > VS THD+N Total harmonic distortion + noise VS = 40 V, VO = 6 VRMS, G = +1, f = 1 kHz EMIRR EMI rejection ratio f = 1 GHz MAX UNIT s 56 300 ns 0.00012 % 53 dB OUTPUT Positive rail headroom Voltage output swing from rail Negative rail headroom ISC VS = 40 V, RL = 10 k 115 210 VS = 40 V, RL = 2 k 520 965 VS = 40 V, RL = 10 k 105 215 VS = 40 V, RL = 2 k 500 1030 mV Short-circuit current 26 mA CLOAD Capacitive load drive 300 pF ZO Open-loop output impedance 125 f = 1 MHz, IO = 0 A POWER SUPPLY IQ (1) 16 937.5 Quiescent current per amplifier IO = 0 A Turn-On Time At TA = 25C, VS = 40 V, VS ramp rate > 0.3 V/s TA = -40C to 125C 1125 1130 60 A s Max IB and Ios data is specified based on characterization results. Submit Document Feedback Copyright (c) 2020 Texas Instruments Incorporated Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 6.18 Electrical Characteristics: TL071C, TL072C, TL074C VCC = 15 V (unless otherwise noted) TEST CONDITIONS (1) (2) PARAMETER VIO Input offset voltage VO = 0 RS = 50 Temperature coefficient of input offset voltage VO = 0 RS = 50 IIO Input offset current VO = 0 IIB Input bias current (3) VICR Common-mode input voltage TA = 25C range VOM Maximum peak output voltage swing VO = 0 RL= 10 k RL 10 k RL 2 k Large-signal differential voltage amplification AVD VO = 10 V RL 2 k MIN TA = 25C TYP MAX 3 10 TA = Full range 13 TA = Full range 18 TA = 25C TA = Full range V/C 100 10 nA 65 200 pA 7 nA TA = Full range TA = 25C mV 5 TA = Full range TA = 25C UNIT 11 -12 to 15 12 13.5 pA V 12 V 10 TA = 25C 25 TA = Full range 15 200 V/mV B1 Utility-gain bandwidth TA = 25C 3 rI Input resistance TA = 25C 1012 MHz CMRR Common-mode rejection ratio VIC = VICR(min) VO = 0 RS = 50 kSVR TA = 25C 70 100 dB V = 9 V to 15 V Supply voltage rejection ratio CC VO = 0 (VCC/VIO) RS = 50 TA = 25C 70 100 dB ICC Supply current (each amplifier) VO = 0; no load TA = 25C 1.4 VO1 / VO2 Crosstalk attenuation AVD = 100 TA = 25C 120 (1) (2) (3) 2.5 mA dB All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is TA = 0C to 70C. Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 6-40. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as possible. Copyright (c) 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 17 TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 6.19 Electrical Characteristics: TL071AC, TL072AC, TL074AC VCC = 15 V (unless otherwise noted) TEST CONDITIONS (1) (2) PARAMETER VIO Input offset voltage VO = 0 RS = 50 Temperature coefficient of input offset voltage VO = 0 RS = 50 IIO Input offset current VO = 0 IIB Input bias current (3) VICR Common-mode input voltage TA = 25C range VOM Maximum peak output voltage swing VO = 0 RL= 10 k RL 10 k RL 2 k Large-signal differential voltage amplification AVD VO = 10 V RL 2 k MIN TA = 25C TYP MAX 3 TA = Full range TA = Full range 18 TA = 25C TA = 25C V/C 100 2 nA 65 200 pA 7 nA TA = Full range TA = Full range mV 5 TA = Full range TA = 25C 6 7.5 UNIT 11 -12 to 15 12 13.5 pA V 12 V 10 TA = 25C 50 TA = Full range 25 200 V/mV B1 Utility-gain bandwidth TA = 25C 3 rI Input resistance TA = 25C 1012 CMRR VIC = VICR(min) Common-mode rejection ratio VO = 0 RS = 50 TA = 25C 75 100 dB kSVR V = 9 V to 15 V Supply-voltage rejection ratio CC VO = 0 (VCC / VIO) RS = 50 TA = 25C 80 100 dB ICC Supply current (each amplifier) VO = 0; no load TA = 25C 1.4 AVD = 100 TA = 25C 120 VO1 / VO2 Crosstalk attenuation (1) (2) (3) 18 MHz 2.5 mA dB All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is TA = 0C to 70C. Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 6-40. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as possible. Submit Document Feedback Copyright (c) 2020 Texas Instruments Incorporated Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 6.20 Electrical Characteristics: TL071BC, TL072BC, TL074BC VCC = 15 V (unless otherwise noted) TEST CONDITIONS (1) (2) PARAMETER VIO Input offset voltage VO = 0 RS = 50 Temperature coefficient of input offset voltage VO = 0 RS = 50 IIO Input offset current VO = 0 IIB Input bias current (3) VO = 0 VICR Common-mode input voltage range TA = 25C VOM Maximum peak output voltage swing RL= 10 k RL 10 k RL 2 k Large-signal differential voltage amplification AVD VO = 10 V RL 2 k MIN TA = 25C TYP 2 TA = Full range 18 TA = 25C TA = 25C mV V/C 5 100 2 nA 65 200 pA 7 nA TA = Full range TA = Full range TA = Full range 3 5 TA = Full range TA = 25C MAX UNIT 11 -12 to 15 12 13.5 pA V 12 V 10 TA = 25C 50 TA = Full range 25 200 V/mV B1 Utility-gain bandwidth TA = 25C 3 rI Input resistance TA = 25C 1012 CMRR Common-mode rejection ratio VIC = VICR(min) VO = 0 RS = 50 TA = 25C 75 100 dB kSVR Supply-voltage rejection ratio (VCC/VIO) VCC = 9 V to 15 V VO = 0 RS = 50 TA = 25C 80 100 dB ICC Supply current (each amplifier) VO = 0; no load TA = 25C 1.4 VO1 / VO2 Crosstalk attenuation AVD = 100 TA = 25C 120 (1) (2) (3) MHz 2.5 mA dB All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is TA = 0C to 70C. Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 6-40. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as possible. Copyright (c) 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 19 TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 6.21 Electrical Characteristics: TL071I, TL072I, TL074I VCC = 15 V (unless otherwise noted) TEST CONDITIONS (1) (2) PARAMETER VIO Input offset voltage VO = 0 RS = 50 Temperature coefficient of input offset voltage VO = 0 RS = 50 IIO Input offset current VO = 0 IIB Input bias current (3) VICR Common-mode input voltage TA = 25C range VOM Maximum peak output voltage swing VO = 0 RL= 10 k RL 10 k RL 2 k Large-signal differential voltage amplification AVD VO = 10 V RL 2 k MIN TA = 25C TYP MAX 3 6 TA = Full range 8 TA = Full range 18 TA = 25C TA = Full range V/C 100 2 nA 65 200 pA 7 nA TA = Full range TA = 25C mV 5 TA = Full range TA = 25C UNIT 11 -12 to 15 12 13.5 pA V 12 V 10 TA = 25C 50 TA = Full range 25 200 V/mV B1 Utility-gain bandwidth TA = 25C 3 rI Input resistance TA = 25C 1012 CMRR Common-mode rejection ratio VIC = VICR(min) VO = 0 RS = 50 TA = 25C 75 100 dB kSVR Supply-voltage rejection ratio (VCC/VIO) VCC = 9 V to 15 V VO = 0 RS = 50 TA = 25C 80 100 dB ICC Supply current (each amplifier) VO = 0; no load TA = 25C 1.4 VO1 / VO2 Crosstalk attenuation AVD = 100 TA = 25C 120 (1) (2) (3) 20 MHz 2.5 mA dB All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. TA = -40C to 85C. Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 6-40. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as possible. Submit Document Feedback Copyright (c) 2020 Texas Instruments Incorporated Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 6.22 Electrical Characteristics, TL07xC, TL07xAC, TL07xBC, TL07xI VCC = 15 V (unless otherwise noted) PARAMETER TEST CONDITIONS (1) TA (2) TL071C, TL072C, TL074C MIN VIO Input offset voltage VO = 0, RS = 50 V Temperature coefficient of input offset voltage VO = 0, RS = 50 IIO Input offset current VO = 0 IO IIB Input bias current(3) VICR Common-mode input voltage range VOM RL= 10 k Maximum peak output voltage RL 10 k swing RL 2 k 25C TYP MAX 3 10 Full range Full range 18 25C 5 TYP 3 65 Full range 25C 11 25C 12 13.5 MAX MIN 6 100 5 MAX 2 3 65 100 5 11 12 13.5 100 200 65 200 65 7 11 -12 to 15 11 -12 to 15 12 13.5 12 13.5 12 10 10 10 10 pA 2 nA 200 pA 7 nA V V 25C 3 3 3 3 rI Input resistance 25C 1012 1012 1012 1012 CMRR Common-mode VIC = VICRmin, rejection ratio VO = 0, RS = 50 25C 70 100 75 100 75 100 75 100 dB kSVR Supply-voltage rejection ratio (VCC/VIO) 25C 70 100 80 100 80 100 80 100 dB ICC Supply current V = 0, (each amplifier) O VO1 /VO2 Crosstalk attenuation (1) (2) (3) RS = 50 No load AVD = 100 25 25C 1.4 25C 120 2.5 50 100 Utility-gain bandwidth VO = 0, 15 200 V/C B1 VCC = 9 V to 15 V, Full range 50 mV Large-signal differential voltage amplification RL 2 k 200 UNIT AVD VO = 10 V, 50 6 5 12 200 3 18 12 25 MAX 8 12 25C TYP 2 7 -12 to 15 MIN 18 2 200 TL071I, TL072I, TL074I TYP 5 18 7 -12 to 15 TL071BC, TL072BC, TL074BC 7.5 10 25C Full range MIN 13 Full range VO = 0 TL071AC, TL072AC, TL074AC 25 1.4 120 2.5 200 V/mV 25 1.4 120 2.5 1.4 120 MHz 2.5 mA dB All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is TA = 0C to 70C for TL07_C,TL07_AC, TL07_BC and is TA = -40C to 85C for TL07_I. Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 6-40. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as possible. Copyright (c) 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 21 TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 6.23 Electrical Characteristics: TL071M, TL072M VCC = 15 V (unless otherwise noted) TEST CONDITIONS (1) (2) PARAMETER VIO Input offset voltage VO = 0 RS = 50 VIO Temperature coefficient of input offset voltage VO = 0 RS = 50 IIO Input offset current VO = 0 IIB Input bias current VO = 0 VICR Common-mode input voltage range TA = 25C VOM Maximum peak output voltage swing RL = 10 k RL 10 k RL 2 k AVD Large-signal differential voltage amplification VO = 10 V RL 2 k B1 Unity-gain bandwidth ri Input resistance CMRR V = VICR(min), Common-mode rejection IC VO = 0 ratio RS = 50 kSVR Supply-voltage rejection ratio (VCC/VIO) ICC VO1 / VO2 (1) (2) 22 MIN TA = 25C TYP MAX 3 6 TA = Full range 9 TA = Full range 18 TA = 25C 5 100 20 nA 65 200 pA 50 nA TA = Full range 11 -12 to 15 TA = 25C TA = Full range 12 mV V/C TA = Full range TA = 25C UNIT pA V 13.5 12 V 10 TA = 25C 35 TA = Full range 15 200 V/mV 3 MHz 1012 TA = 25C 80 86 dB VCC = 9 V to 15 V VO = 0 RS = 50 TA = 25C 80 86 dB Supply current (each amplifier) VO = 0; no load TA = 25C 1.4 Crosstalk attenuation AVD = 100 TA = 25C 120 2.5 mA dB Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 6-40. Pulse techniques that maintain the junction temperature as close to the ambient temperature as possible must be used. All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is TA = -55C to +125C. Submit Document Feedback Copyright (c) 2020 Texas Instruments Incorporated Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 6.24 Electrical Characteristics: TL074M VCC = 15 V (unless otherwise noted) TEST CONDITIONS (1) (2) PARAMETER VO = 0 RS = 50 VIO Input offset voltage VIO Temperature coefficient of VO = 0, RS = 50 input offset voltage IIO Input offset current VO = 0 IIB Input bias current VO = 0 VICR Common-mode input voltage range TA = 25C VOM Maximum peak output voltage swing RL = 10 k RL 10 k RL 2 k AVD Large-signal differential voltage amplification VO = 10 V RL 2 k MIN TA = 25C TYP 3 TA = Full range TA = Full range 18 TA = 25C V/C 20 nA 65 200 pA 20 nA 11 -12 to 15 12 13.5 pA V 12 V 10 TA = 25C 35 TA = Full range 15 200 B1 Unity-gain bandwidth Input resistance CMRR Common-mode rejection ratio VIC = VICR(min) VO = 0 RS = 50 TA = 25C kSVR Supply-voltage rejection ratio (VCC/VIO) VCC = 9 V to 15 V VO = 0 RS = 50 TA = 25C ICC Supply current (each amplifier) VO = 0; no load TA = 25C 1.4 VO1 / VO2 Crosstalk attenuation AVD = 100 TA = 25C 120 (2) mV 100 TA = Full range TA = Full range UNIT 5 TA = Full range TA = 25C TA = 25C 9 15 ri (1) MAX V/mV 3 MHz 1012 80 86 dB 80 86 dB 2.5 mA dB Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 6-40. Pulse techniques that maintain the junction temperature as close to the ambient temperature as possible must be used . All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is TA = -55C to +125C. Copyright (c) 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 23 TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 6.25 Switching Characteristics: TL07xM VCC = 15 V, TA = 25C PARAMETER TEST CONDITIONS SR Slew rate at unity gain VI = 10 V CL = 100 pF RL = 2 k See Figure 7-1 tr Rise-time overshoot factor VI = 20 V CL = 100 pF RL = 2 k See Figure 7-1 Vn Equivalent input noise voltage RS = 20 In Equivalent input noise current RS = 20 THD Total harmonic distortion VIrms = 6 V RL 2 k f = 1 kHz MIN TYP MAX UNIT 5 13 V/s 0.1 s 20% f = 1 kHz 18 f = 10 Hz to 10 kHz nV/ Hz 4 f = 1 kHz V 0.01 AVD = 1 RS 1 k pA/ Hz 0.003% 6.26 Switching Characteristics: TL07xC, TL07xAC, TL07xBC, TL07xI VCC = 15 V, TA = 25C PARAMETER TEST CONDITIONS SR Slew rate at unity gain VI = 10 V CL = 100 pF tr Rise-time overshoot factor VI = 20 V CL = 100 pF Vn Equivalent input noise voltage RS = 20 In Equivalent input noise current RS = 20 THD Total harmonic distortion 24 Submit Document Feedback VIrms = 6 V RL 2 k f = 1 kHz RL = 2 k See Figure 7-1 RL = 2 k See Figure 7-1 f = 1 kHz f = 10 Hz to 10 kHz f = 1 kHz AVD = 1 RS 1 k MIN TYP MAX UNIT 8 13 V/s 0.1 s 20% 18 4 0.01 nV/ Hz V pA/ Hz 0.003% Copyright (c) 2020 Texas Instruments Incorporated Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 6.27 Electrical Characteristics, TL07xM VCC = 15 V (unless otherwise noted) PARAMETER TEST CONDITIONS(1) VIO Input offset voltage VO = 0, RS = 50 VIO Temperature coefficient of input offset voltage VO = 0, RS = 50 IIO Input offset current VO = 0 IIB Input bias current VICR Common-mode input voltage range VOM Maximum peak output voltage swing AVD Large-signal differential voltage amplification B1 Unity-gain bandwidth TA (2) TL071M, TL072M MIN TYP 25C 3 Full range MIN TYP 6 18 25C 5 Full range 3 9 15 18 100 65 5 200 65 50 RL = 10 k RL 10 k 25C 11 -12 to 15 25C 12 13.5 Full range RL 2 k 25C VO = 10 V, RL 2 k 12 12 10 10 35 100 pA 20 nA 200 pA 20 nA 11 -12 to 15 12 200 35 15 mV V/C 20 25C UNIT MAX 9 Full range VO = 0 TL074M MAX V 13.5 V 200 V/mV 15 3 3 MHz 1012 1012 ri Input resistance CMRR Common-mode rejection ratio VIC = VICRmin, VO = 0, RS = 50 25C 80 86 80 86 dB kSVR Supply-voltage rejection ratio (V CC/VIO) VCC = 9 V to 15 V, VO = 0, RS = 50 25C 80 86 80 86 dB ICC Supply current (each amplifier) VO = 0, No load 25C VO1/VO2 Crosstalk attenuation AVD = 100 25C (1) (2) 1.4 2.5 1.4 120 2.5 120 mA dB Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 6-40. Pulse techniques must be used that will maintain the junction temperature as close to the ambient temperature as possible. All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is TA = -55C to 125C. 6.28 Switching Characteristics VCC = 15 V, TA= 25C PARAMETER SR Slew rate at unity gain VI = 10 V, CL = 100 pF, RL = 2 k, See Figure 7-1 tr Rise-time overshoot factor VI = 20 V, CL = 100 pF, RL = 2 k, See Figure 7-1 Vn Equivalent input noise RS = 20 voltage In Equivalent input noise RS = 20 , current THD Total harmonic distortion VIrms = 6 V, RL 2 k, f = 1 kHz, Copyright (c) 2020 Texas Instruments Incorporated f = 1 kHz f = 10 Hz to 10 kHz f = 1 kHz AVD = 1, RS 1 k, TL07xC, TL07xAC, TL07xBC, TL07xI TL075 TL07xM TEST CONDITIONS MIN TYP 5 13 MAX UNIT MIN TYP MAX 8 13 V/s s 0.1 0.1 20% 20% 18 18 nV/ Hz 4 4 V 0.01 0.01 0.003% 0.003% pA/ Hz Submit Document Feedback Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 25 TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 6.29 Typical Characteristics: TL07xH at T A = 25C, V S = 40 V ( 20 V), V CM = V S / 2, R LOAD = 10 k connected to V S / 2, and C L = 20 pF (unless otherwise noted) TA = 25C Figure 6-1. Offset Voltage Production Distribution VCM = VS / 2 Figure 6-3. Offset Voltage vs Temperature TA = 125C Figure 6-5. Offset Voltage vs Common-Mode Voltage 26 Submit Document Feedback Figure 6-2. Offset Voltage Drift Distribution TA = 25C Figure 6-4. Offset Voltage vs Common-Mode Voltage TA = -40C Figure 6-6. Offset Voltage vs Common-Mode Voltage Copyright (c) 2020 Texas Instruments Incorporated Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 Figure 6-7. Offset Voltage vs Power Supply Figure 6-8. Open-Loop Gain and Phase vs Frequency Figure 6-9. Closed-Loop Gain vs Frequency Figure 6-10. Input Bias Current vs Common-Mode Voltage Figure 6-11. Input Bias Current vs Temperature Figure 6-12. Output Voltage Swing vs Output Current (Sourcing) Copyright (c) 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 27 TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 Figure 6-13. Output Voltage Swing vs Output Current (Sinking) f = 0 Hz 28 www.ti.com Figure 6-14. CMRR and PSRR vs Frequency f = 0 Hz Figure 6-15. CMRR vs Temperature (dB) Figure 6-16. PSRR vs Temperature (dB) Figure 6-17. 0.1-Hz to 10-Hz Noise Figure 6-18. Input Voltage Noise Spectral Density vs Frequency Submit Document Feedback Copyright (c) 2020 Texas Instruments Incorporated Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 BW = 80 kHz, VOUT = 1 VRMS Figure 6-19. THD+N Ratio vs Frequency BW = 80 kHz, f = 1 kHz Figure 6-20. THD+N vs Output Amplitude VCM = VS / 2 Figure 6-21. Quiescent Current vs Supply Voltage Figure 6-22. Quiescent Current vs Temperature Figure 6-23. Open-Loop Voltage Gain vs Temperature (dB) Figure 6-24. Open-Loop Output Impedance vs Frequency Copyright (c) 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 29 TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 G = -1, 25-mV output step Figure 6-25. Small-Signal Overshoot vs Capacitive Load www.ti.com G = 1, 10-mV output step Figure 6-26. Small-Signal Overshoot vs Capacitive Load VS = 10 V, VIN = VOUT Figure 6-27. Phase Margin vs Capacitive Load G = -10 Figure 6-29. Positive Overload Recovery 30 Submit Document Feedback Figure 6-28. No Phase Reversal G = -10 Figure 6-30. Negative Overload Recovery Copyright (c) 2020 Texas Instruments Incorporated Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 CL = 20 pF, G = 1, 10-mV step response Figure 6-31. Small-Signal Step Response, Rising CL = 20 pF, G = 1 Figure 6-33. Large-Signal Step Response (Rising) CL = 20 pF, G = 1, 10-mV step response Figure 6-32. Small-Signal Step Response, Falling CL = 20 pF, G = 1 Figure 6-34. Large-Signal Step Response (Falling) CL = 20 pF, G = 1 Figure 6-35. Large-Signal Step Response Copyright (c) 2020 Texas Instruments Incorporated Figure 6-36. Short-Circuit Current vs Temperature Submit Document Feedback Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 31 TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 Figure 6-37. Maximum Output Voltage vs Frequency www.ti.com Figure 6-38. Channel Separation vs Frequency Figure 6-39. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency 32 Submit Document Feedback Copyright (c) 2020 Texas Instruments Incorporated Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 6.30 Typical Characteristics: All Devices Except TL07xH 15 100 VCC = 15 V VOM VOM - Maximum Peak Output Voltage - V IIIB- IB Input Bias Current - nA VCC = 15 V 10 1 0.1 0.01 -75 -50 -25 0 25 50 75 100 12.5 10 VCC = 10 V 7.5 VCC = 5 V 5 2.5 0 100 125 1k TA - Free-Air Temperature - C Figure 6-40. Input Bias Current vs Free-Air Temperature RL = 10 k TA = 25C See Figure 2 10 k 100 k f - Frequency - Hz 1M 10 M Figure 6-41. Maximum Peak Output Voltage vs Frequency VOM VOM - Maximum Peak Output Voltage - V 15 RL = 2 k TA = 25C See Figure 2 VCC = 15 V 12.5 10 VCC = 10 V 7.5 5 VCC = 5 V 2.5 8 0 100 1k 10 k 100 k f - Frequency - Hz 1M 10 M Figure 6-42. Maximum Peak Output Voltage vs Frequency Figure 6-43. Maximum Peak Output Voltage vs Frequency 15 RL = 10 k VOM - Maximum Peak Output Voltage - V VOM V VOM OM - Maximum Peak Output Voltage - V 15 12.5 RL = 2 k 10 7.5 5 2.5 VCC = 15 V 8 See Figure 2 0 -75 -50 -25 0 25 50 75 100 125 TA - Free-Air Temperature - C Figure 6-44. Maximum Peak Output Voltage vs Free-Air Temperature Copyright (c) 2020 Texas Instruments Incorporated 12.5 VCC = 15 V TA = 25C See Figure 2 10 7.5 5 2.5 8 0 0.1 0.2 0.4 0.7 1 2 4 7 10 RL - Load Resistance - k Figure 6-45. Maximum Peak Output Voltage vs Load Resistance Submit Document Feedback Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 33 TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 1000 RL = 10 k TA = 25C 400 10 7.5 5 2.5 200 100 40 20 10 4 VCC = 15 V VO = 10 V RL = 2 k 2 1 -75 0 0 2 4 6 8 10 12 14 -50 16 |VCC| - Supply Voltage - V Figure 6-46. Maximum Peak Output Voltage vs Supply Voltage -25 0 25 50 75 Normalized Unity-Gain Bandwidth 1.03 1.01 1.1 Phase Shift 1 1 0.99 0.9 VCC = 15 V RL = 2 k f = B1 for Phase Shift 0.8 -50 0.98 -25 0 25 50 75 100 TA - Free-Air Temperature - C 0.97 125 Figure 6-49. Normalized Unity-Gain Bandwidth and Phase Shift vs Free-Air Temperature 89 2 VCC = 15 V ICC - Supply Current Per Amplifier - mA I CC CMRR - Common-Mode Rejection Ratio - dB 1.02 Unity-Gain Bandwidth 1.2 0.7 -75 RL = 10 k 88 87 86 85 84 83 -75 -50 -25 0 25 50 75 100 125 TA - Free-Air Temperature - C Figure 6-50. Common-Mode Rejection Ratio vs Free-Air Temperature 34 125 Figure 6-47. Large-Signal Differential Voltage Amplification vs Free-Air Temperature 1.3 Figure 6-48. Large-Signal Differential Voltage Amplification and Phase Shift vs Frequency 100 TA - Free-Air Temperature - C Normalized Phase Shift 12.5 AAVD VD - Large-Signal Differential Voltage Amplification - V/mV VOM VOM - Maximum Peak Output Voltage - V 15 Submit Document Feedback TA = 25C No Signal No Load 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 |VCC| - Supply Voltage - V Figure 6-51. Supply Current Per Amplifier vs Supply Voltage Copyright (c) 2020 Texas Instruments Incorporated Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 250 VCC = 15 V No Signal No Load 1.6 PD - Total Power Dissipation - mW ICC - Supply Current Per Amplifier - mA I CC 2 1.8 1.4 1.2 1 0.8 0.6 0.4 200 175 TL074 150 125 100 0.2 0 -75 VCC =15 V No Signal No Load 225 TL072 75 TL071 50 25 -50 -25 0 25 50 75 100 0 -75 125 -50 Figure 6-54. Normalized Slew Rate vs Free-Air Temperature 0.04 0.01 0.004 1k 4 k 10 k f - Frequency - Hz 40 k 100 k Figure 6-56. Total Harmonic Distortion vs Frequency Copyright (c) 2020 Texas Instruments Incorporated 75 100 125 VCC = 15 V AVD = 10 RS = 20 TA = 25C 40 30 20 10 10 40 100 400 1 k 4 k 10 k f - Frequency - Hz 40 k 100 k Figure 6-55. Equivalent Input Noise Voltage vs Frequency VI and VO - Input and Output Voltages - V THD - Total Harmonic Distortion - % 0.1 400 50 6 VCC = 15 V AVD = 1 VI(RMS) = 6 V TA = 25C 0.001 100 25 50 0 0.4 0 Figure 6-53. Total Power Dissipation vs Free-Air Temperature V n - Equivalent Input Noise Voltage - nV/Hz nV/ Hz Figure 6-52. Supply Current Per Amplifier vs FreeAir Temperature 1 -25 TA - Free-Air Temperature -C TA - Free-Air Temperature - C VCC = 15 V RL = 2 k CL = 100 pF TA = 25C 4 Output 2 0 -2 Input -4 -6 0 0.5 1 1.5 t - Time - s 2 2.5 3 3.5 Figure 6-57. Voltage-Follower Large-Signal Pulse Response Submit Document Feedback Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 35 TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 10 8 VCCr = r15 V 6 VIO (mV) 4 2 0 -2 -4 -6 -8 -10 -13 -11 -9 -7 -5 -3 -1 1 3 5 7 9 11 VCM (V) Figure 6-58. Output Voltage vs Elapsed Time 36 Submit Document Feedback 13 15 17 D003 Figure 6-59. VIO vs VCM Copyright (c) 2020 Texas Instruments Incorporated Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M www.ti.com TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 7 Parameter Measurement Information - OUT + VI CL = 100 pF RL = 2 k Figure 7-1. Unity-Gain Amplifier 10 k 1 k - VI OUT + RL CL = 100 pF Figure 7-2. Gain-of-10 Inverting Amplifier Figure 7-3. Input Offset-Voltage Null Circuit Copyright (c) 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 37 TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 8 Detailed Description 8.1 Overview The TL07xH (TL071H, TL072H, and TL074H) family of devices are the next-generation versions of the industrystandard TL07x (TL071, TL072, and TL074) devices. These devices provide outstanding value for cost-sensitive applications, with features including low offset (1 mV, typ), high slew rate (25 V/s, typ), and common-mode input to the positive supply. High ESD (1.5 kV, HBM), integrated EMI and RF filters, and operation across the full -40C to 125C enable the TL07xH devices to be used in the most rugged and demanding applications. The C-suffix devices are characterized for operation from 0C to 70C. The I-suffix devices are characterized for operation from -40C to +85C. The M-suffix devices are characterized for operation over the full military temperature range of -55C to +125C. 8.2 Functional Block Diagram VCC+ IN+ IN- 64 128 OUT 64 C1 18 pF 1080 1080 VCC- OFFSET N1 OFFSET N2 TL071 Only All component values shown are nominal. COMPONENT COUNT COMPONENT TYPE Resistors Transistors JFET Diodes Capacitors epi-FET 38 Submit Document Feedback TL071 TL072 TL074 11 14 2 1 1 1 22 28 4 2 2 2 44 56 6 4 4 4 Includes bias and trim circuitry Copyright (c) 2020 Texas Instruments Incorporated Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 8.3 Feature Description The TL07xH family of devices improve many specifications as compared to the industry-standard TL07x family. Several comparisons of key specifications between these families are included below to show the advantages of the TL07xH family. 8.3.1 Total Harmonic Distortion Harmonic distortions to an audio signal are created by electronic components in a circuit. Total harmonic distortion (THD) is a measure of harmonic distortions accumulated by a signal in an audio system. These devices have a very low THD of 0.003% meaning that the TL07x device adds little harmonic distortion when used in audio signal applications. 8.3.2 Slew Rate The slew rate is the rate at which an operational amplifier can change the output when there is a change on the input. These devices have a 13-V/s slew rate. 8.4 Device Functional Modes These devices are powered on when the supply is connected. These devices can be operated as a singlesupply operational amplifier or dual-supply amplifier depending on the application. Copyright (c) 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 39 TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 www.ti.com 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information A typical application for an operational amplifier is an inverting amplifier. This amplifier takes a positive voltage on the input, and makes the voltage a negative voltage. In the same manner, the amplifier makes negative voltages positive. 9.2 Typical Application RF RI Vsup+ VOUT + VIN Vsup- Figure 9-1. Inverting Amplifier 9.2.1 Design Requirements The supply voltage must be selected so the supply voltage is larger than the input voltage range and output range. For instance, this application scales a signal of 0.5 V to 1.8 V. Setting the supply at 12 V is sufficient to accommodate this application. 9.2.2 Detailed Design Procedure Vo = ( Vi + Vi o ) * ( 1 + 1M 1k ) (1) Determine the gain required by the inverting amplifier: AV = VOUT VIN (2) AV = 1.8 = -3.6 -0.5 (3) Once the desired gain is determined, select a value for RI or RF. Selecting a value in the kilohm range is desirable because the amplifier circuit uses currents in the milliamp range. This ensures the part does not draw too much current. This example uses 10 k for RI which means 36 k is used for RF. This is determined by Equation 4. AV = - 40 RF RI Submit Document Feedback (4) Copyright (c) 2020 Texas Instruments Incorporated Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 9.2.3 Application Curve 2 VIN 1.5 VOUT 1 Volts 0.5 0 -0.5 -1 -1.5 -2 0 0.5 1 Time (ms) 1.5 2 Figure 9-2. Input and Output Voltages of the Inverting Amplifier 9.3 Unity Gain Buffer U1 TL072 VIN + + VOUT 10 k + 12 Copyright (c) 2017, Texas Instruments Incorporated Figure 9-3. Single-Supply Unity Gain Amplifier 9.3.1 Design Requirements * * * VCC must be within valid range per Section 6.6. This example uses a value of 12 V for VCC. Input voltage must be within the recommended common-mode range, as shown in Section 6.6. The valid common-mode range is 4 V to 12 V (VCC- + 4 V to VCC+). Output is limited by output range, which is typically 1.5 V to 10.5 V, or VCC- + 1.5 V to VCC+ - 1.5 V. 9.3.2 Detailed Design Procedure * * Avoid input voltage values below 1 V to prevent phase reversal where output goes high. Avoid input values below 4 V to prevent degraded VIO that results in an apparent gain greater than 1. This may cause instability in some second-order filter designs. Copyright (c) 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 41 TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 12 1.5 10 1 8 0.5 Gain (V/V) VOUT (V) 9.3.3 Application Curves 6 0 4 -0.5 2 -1 -1.5 0 0 2 4 6 VIN (V) 8 10 0 12 2 4 6 VIN (V) 8 10 12 D002 D001 Figure 9-5. Gain vs Input Voltage Figure 9-4. Output Voltage vs Input Voltage 9.4 System Examples VCC+ - R1 R2 + Input Output VCC- C3 R1 = R2 = 2R3 = 1.5 MW C1 R3 C1 C1 = C2 = fo = Figure 9-6. 0.5-Hz Square-Wave Oscillator C3 = 110 pF 2 1 = 1kHz 2p R1 C1 Figure 9-7. High-Q Notch Filter Figure 9-8. 100-kHz Quadrature Oscillator Figure 9-9. AC Amplifier 42 Submit Document Feedback Copyright (c) 2020 Texas Instruments Incorporated Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 10 Power Supply Recommendations CAUTION Supply voltages larger than 36 V for a single-supply or outside the range of 18 V for a dual-supply can permanently damage the device (see Section 6.2). Place 0.1-F bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see Section 11. 11 Layout 11.1 Layout Guidelines For best operational performance of the device, use good PCB layout practices, including: * * * * * * Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power sources local to the analog circuitry. - Connect low-ESR, 0.1-F ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from VCC+ to ground is applicable for singlesupply applications. Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to physically separate digital and analog grounds, paying attention to the flow of the ground current. To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace. Place the external components as close to the device as possible. Keeping RF and RG close to the inverting input minimizes parasitic capacitance, as shown in Section 11.2 . Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. Copyright (c) 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 43 TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 11.2 Layout Example Place components close to device and to each other to reduce parasitic errors Run the input traces as far away from the supply lines as possible RF NC NC IN1i VCC+ IN1+ OUT VCCi NC VS+ Use low-ESR, ceramic bypass capacitor RG GND VIN RIN GND Only needed for dual-supply operation GND VS(or GND for single supply) VOUT Ground (GND) plane on another layer Figure 11-1. Operational Amplifier Board Layout for Noninverting Configuration RIN VIN + VOUT RG RF Figure 11-2. Operational Amplifier Schematic for Noninverting Configuration 44 Submit Document Feedback Copyright (c) 2020 Texas Instruments Incorporated Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M TL071, TL071H, TL071A, TL071B TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M www.ti.com SLOS080P - SEPTEMBER 1978 - REVISED NOVEMBER 2020 12 Device and Documentation Support 12.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 12-1. Related Links PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TL071 Click here Click here Click here Click here Click here TL071A Click here Click here Click here Click here Click here TL071B Click here Click here Click here Click here Click here TL072 Click here Click here Click here Click here Click here TL072A Click here Click here Click here Click here Click here TL072B Click here Click here Click here Click here Click here TL072M Click here Click here Click here Click here Click here TL074 Click here Click here Click here Click here Click here TL074A Click here Click here Click here Click here Click here TL074B Click here Click here Click here Click here Click here TL074M Click here Click here Click here Click here Click here 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Support Resources TI E2ETM support forums are an engineer's go-to source for fast, verified answers and design help -- straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks TI E2ETM is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser based versions of this data sheet, refer to the left hand navigation. Copyright (c) 2020 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A TL074B TL072M TL074M 45 PACKAGE OPTION ADDENDUM www.ti.com 9-Mar-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) 81023052A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 81023052A TL072MFKB 8102305HA ACTIVE CFP U 10 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8102305HA TL072M 8102305PA ACTIVE CDIP JG 8 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8102305PA TL072M 81023062A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 81023062A TL074MFKB 8102306CA ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8102306CA TL074MJB 8102306DA ACTIVE CFP W 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8102306DA TL074MWB JM38510/11905BPA ACTIVE CDIP JG 8 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510 /11905BPA M38510/11905BPA ACTIVE CDIP JG 8 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510 /11905BPA TL071ACD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 071AC TL071ACDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 071AC TL071ACDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 071AC TL071ACP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL071ACP TL071BCD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 071BC TL071BCDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 071BC TL071BCP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL071BCP TL071CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL071C TL071CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL071C TL071CDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL071C Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 9-Mar-2021 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) TL071CDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL071C TL071CP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL071CP TL071CPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL071CP TL071CPSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T071 TL071ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL071I TL071IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL071I TL071IDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL071I TL071IP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL071IP TL072ACD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072AC TL072ACDE4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072AC TL072ACDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072AC TL072ACDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072AC TL072ACDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072AC TL072ACP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL072ACP TL072ACPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL072ACP TL072BCD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072BC TL072BCDE4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072BC TL072BCDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072BC TL072BCDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072BC TL072BCDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072BC TL072BCP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL072BCP Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 9-Mar-2021 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) TL072BCPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL072BCP TL072CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL072C TL072CDE4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL072C TL072CDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL072C TL072CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL072C TL072CDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL072C TL072CDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL072C TL072CP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL072CP TL072CPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL072CP TL072CPS ACTIVE SO PS 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T072 TL072CPSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T072 TL072CPSRE4 ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T072 TL072CPSRG4 ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T072 TL072CPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T072 TL072CPWRE4 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T072 TL072CPWRG4 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T072 TL072ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL072I TL072IDE4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL072I TL072IDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL072I TL072IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL072I TL072IDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL072I Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com 9-Mar-2021 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) TL072IDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL072I TL072IP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL072IP TL072IPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL072IP TL072MFKB ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 81023052A TL072MFKB TL072MJG ACTIVE CDIP JG 8 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 TL072MJG TL072MJGB ACTIVE CDIP JG 8 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8102305PA TL072M TL072MUB ACTIVE CFP U 10 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8102305HA TL072M TL074ACD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC TL074ACDE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC TL074ACDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC TL074ACDRE4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC TL074ACDRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC TL074ACN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL074ACN TL074ACNE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL074ACN TL074ACNSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074A TL074BCD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC TL074BCDE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC TL074BCDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC TL074BCDRE4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC TL074BCDRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC Addendum-Page 4 Samples PACKAGE OPTION ADDENDUM www.ti.com 9-Mar-2021 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) TL074BCN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL074BCN TL074BCNE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL074BCN TL074CD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074C TL074CDBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T074 TL074CDG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074C TL074CDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM 0 to 70 TL074C TL074CDRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074C TL074CN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL074CN TL074CNE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL074CN TL074CNSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074 TL074CNSRG4 ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074 TL074CPW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T074 TL074CPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T074 TL074CPWRE4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T074 TL074CPWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T074 TL074HIDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TL074HID TL074HIPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TL074PW TL074ID ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I TL074IDE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I TL074IDG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I TL074IDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I Addendum-Page 5 Samples PACKAGE OPTION ADDENDUM www.ti.com 9-Mar-2021 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) TL074IDRE4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I TL074IDRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I TL074IN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL074IN TL074MFK ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 TL074MFK TL074MFKB ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 81023062A TL074MFKB TL074MJ ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 TL074MJ TL074MJB ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8102306CA TL074MJB TL074MWB ACTIVE CFP W 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 8102306DA TL074MWB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 6 Samples PACKAGE OPTION ADDENDUM www.ti.com 9-Mar-2021 (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TL072, TL072M, TL074, TL074M : * Catalog: TL072, TL074 * Enhanced Product: TL072-EP, TL072-EP, TL074-EP, TL074-EP * Military: TL072M, TL074M NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Enhanced Product - Supports Defense, Aerospace and Medical Applications * Military - QML certified for Military and Defense Applications Addendum-Page 7 PACKAGE MATERIALS INFORMATION www.ti.com 30-Dec-2020 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TL071ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL071BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL071CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL071CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL071IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL072ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL072BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL072CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL072CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL072CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 TL072IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL072IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL074ACDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL074ACNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 TL074BCDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL074CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL074CDRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL074CNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Dec-2020 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TL074CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TL074HIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL074HIPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TL074IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL071ACDR SOIC D 8 2500 340.5 338.1 20.6 TL071BCDR SOIC D 8 2500 340.5 338.1 20.6 TL071CDR SOIC D 8 2500 340.5 338.1 20.6 TL071CDR SOIC D 8 2500 853.0 449.0 35.0 TL071IDR SOIC D 8 2500 340.5 338.1 20.6 TL072ACDR SOIC D 8 2500 340.5 338.1 20.6 TL072BCDR SOIC D 8 2500 340.5 338.1 20.6 TL072CDR SOIC D 8 2500 853.0 449.0 35.0 TL072CDR SOIC D 8 2500 340.5 338.1 20.6 TL072CPWR TSSOP PW 8 2000 853.0 449.0 35.0 TL072IDR SOIC D 8 2500 853.0 449.0 35.0 TL072IDR SOIC D 8 2500 340.5 338.1 20.6 TL074ACDR SOIC D 14 2500 333.2 345.9 28.6 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 30-Dec-2020 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL074ACNSR SO NS 14 2000 853.0 449.0 35.0 TL074BCDR SOIC D 14 2500 333.2 345.9 28.6 TL074CDR SOIC D 14 2500 333.2 345.9 28.6 TL074CDRG4 SOIC D 14 2500 333.2 345.9 28.6 TL074CNSR SO NS 14 2000 853.0 449.0 35.0 TL074CPWR TSSOP PW 14 2000 853.0 449.0 35.0 TL074HIDR SOIC D 14 2500 853.0 449.0 35.0 TL074HIPWR TSSOP PW 14 2000 853.0 449.0 35.0 TL074IDR SOIC D 14 2500 333.2 345.9 28.6 Pack Materials-Page 3 PACKAGE OUTLINE U0010A CFP - 2.03 mm max height SCALE 1.400 CERAMIC FLATPACK .045 MAX TYP .010 .002 PIN 1 ID .27 MAX GLASS .005 MIN TYP 1 10 8X .050 .005 .27 MAX GLASS 10X .017 .002 5 6 5X .32 .01 .241 +.019 -.003 5X .32 .01 .005 .001 +.013 -.012 .067 .045 .026 4225582/A 01/2020 NOTES: 1. All linear dimensions are in inches. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID (OPTIONAL) A 4X .005 MIN [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 [0.36-0.66] 14X .045-.065 [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 8 7 B .245-.283 [6.22-7.19] .2 MAX TYP [5.08] C .13 MIN TYP [3.3] SEATING PLANE .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 TYP 14X .008-.014 [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL A SEE DETAIL B 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 8 7 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX [0.05] ALL AROUND (.063) [1.6] METAL ( .063) [1.6] SOLDER MASK OPENING METAL (R.002 ) TYP [0.05] .002 MAX [0.05] ALL AROUND SOLDER MASK OPENING DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com MECHANICAL DATA MCER001A - JANUARY 1995 - REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0-15 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OUTLINE PW0008A TSSOP - 1.2 mm max height SCALE 2.800 SMALL OUTLINE PACKAGE C 6.6 TYP 6.2 SEATING PLANE PIN 1 ID AREA A 0.1 C 6X 0.65 8 1 3.1 2.9 NOTE 3 2X 1.95 4 5 B 4.5 4.3 NOTE 4 SEE DETAIL A 8X 0.30 0.19 0.1 C A 1.2 MAX B (0.15) TYP 0.25 GAGE PLANE 0 -8 0.15 0.05 0.75 0.50 DETAIL A TYPICAL 4221848/A 02/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. www.ti.com EXAMPLE BOARD LAYOUT PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM 1 8 (R0.05) TYP SYMM 6X (0.65) 5 4 (5.8) LAND PATTERN EXAMPLE SCALE:10X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221848/A 02/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM (R0.05) TYP 1 8 SYMM 6X (0.65) 5 4 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221848/A 02/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0-8 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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