74LCX32646GX - Fairchild Semiconductor

Preliminary

August 2001

Revised August 2001

74LCX32646 Low Voltage 32-Bit Transceiver/Register with 5V Tolerant Inputs and Outputs ( Preliminary)

74LCX32646

Low Voltage 32-Bi t Transceive r/Register

with 5V Tolerant Inputs and Outputs (Preliminary)

General Description

The LCX32646 contains thirty-two non-inverting bidirec-

tional registered bus transceivers with 3-STATE outputs,

providing multiplexed transmission of data directly from the

input bu s or from the inte rnal storage re gisters. Each byte

has separat e control inputs which ca n be shorted together

for full 32-bit operation.The DIRn inputs determine the

direction of data flow through the device. The CPABn and

CPBAn inputs load data into the registers on the LOW-to-

HIGH transition (see Functional Description).

The LCX3 2646 is designed for low vo ltage (2.5V or 3 .3V)

VCC applications with capability of interfacing to a 5V signal

environment.

The LCX32646 is fabricated with an advanced CMOS tech-

nology to achieve high speed operation while maintaining

CMOS low power dissipation.

Features

■5V tolerant inputs and outputs

■2.3V–3.6V VCC specifications provided

■5.2 ns tPD max (VCC = 3.3V), 20 µA ICC max

■Power down high impedance inputs and outputs

■Supports live insertion/withdrawal (Note 1)

■±24 mA Output Drive (VCC = 3.0V)

■Implements patented noise/EMI reduction circuitry

■Latch-up per for man c e exce eds 500 mA

■ESD performa nce :

Human Body Mod el > 2000V

Machine Model > 200V

■Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)

(Preliminary)

Note 1: To ensure the high-impedance state during power up or down, OE

should be tied to VCC through a p ull-up re sistor: th e minimu m value or the

resisto r is det ermin ed by the current-so urc ing capability of th e driver.

Ordering Code:

Note 2: BGA package available in Tape and Reel only.

Order Number Package Number Package Description

74LCX32646GX

(Note 2) BGA114A

(Preliminary) 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

Preliminary

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74LCX32646

Connection Diagram

Pin Assignme nt for FB GA

(Top Thru View)

Pin Descriptions

FBGA Pin Assignments

Pin Names Descripti on

1A0 - 1A15 Side A Inputs or 3-STATE Outputs

2A0 - 2A15

1B0 - 1B15 Side B Inputs or 3-STATE Outputs

2B0 - 2B15

OEnOutput Enable Inputs

CPABn, CPBAnClock Pulse Inputs

SABn, SBAnSelect Inputs

DIRnDirection Control Inputs

NC No Connect

123456

A1A0SAB1CPAB1CPBA1SBA11B0

B1A21A1DIR1OE11B11B2

C1A41A3GND GND 1B31B4

D1A61A5VCC VCC 1B51B6

E1A81A7GND GND 1B71B8

F1A10 1A9GND GND 1B91B10

G1A12 1A11 VCC VCC 1B11 1B12

H1A13 1A14 GND GND 1B14 1B13

J1A15 SAB2CPAB2CPBA2SBA21B15

KNC CPAB3DIR2OE2CPBA3NC

L2A0SAB3DIR3OE3SBA32B0

M2A22A1GND GND 2B12B2

N2A42A3VCC VCC 2B32B4

P2A62A5GND GND 2B52B6

R2A82A7GND GND 2B72B8

T2A10 2A9VCC VCC 2B92B10

U2A12 2A11 GND GND 2B11 2B12

V2A13 2A14 CPAB4CPBA42B14 2B13

W2A15 SAB4DIR4OE4SBA42B15

Preliminary

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74LCX32646

Truth Table

(Note 3)

H = HIGH Voltage Level

L = LOW Voltage L ev el

X = Immaterial



= LOW-to-H I GH Transition

Note 3: Data I/O path s (1A and 1B: 0 - 7) is shown . Thi s als o appli es to data I/O (1A a nd 1 B: 8 - 15 ) and #2 cont rol pin s, to da ta (2A and 2B : 0 - 7) and #3

control pins, to data (2A and 2B: 8 - 15) and #4 control pins.

Note 4: The data out put f unctions m ay be enabl ed or disabled by various sig nals at the OE and DIR in puts. Data input fun c ti ons are alw ay s enabled;

i.e., data at t he bus pins will be stored on every LOW-to-HIGH t ransition of the appro priate cloc k inputs.

Inputs Data I/O (Note 4) Output Operation Mode

OE1 DIR1 CPAB1 CPBA1 SAB1 SB A 1 1A0–7 1B0–7

H X H or L H or L X X Isolation

H X



X X X Input Input Clock An Data into A Register

H X X



X X Clock Bn Data Into B Register

L H X X L X A

n to Bn — Real Time (Transparent Mode)

L H



X L X Input Output Clock An Data to A Register

L H H or L X H X A Register to Bn (Stored Mo de)

L H



X H X Clock An Data into A Register and Output to Bn

L L X X X L B

n to An — Real Time (Transparent Mode)

L L X



X L Output Input Clock Bn Data into B Register

L L X H or L X H B Register to An (Stored Mode)

L L X



X H Clock Bn into B Register and Output to An

Preliminary

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74LCX32646

Logic Diagrams

Pleas e note that these diagrams are provided only fo r th e unders t anding of logic operations a nd s hould not be use d to es t im at e propag at ion delay s .

Preliminary

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74LCX32646

Logic Diagrams (Continued)

Please not e t hat these diagram s are provided only fo r t he unders t anding of logic operations a nd should not be used to estim ate propagation delays.

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74LCX32646

Functional Description

In the tr ansceiver mo de, data prese nt at the HIGH im ped-

ance port may be stored in either the A or B register or

both. The select (SABn, SBAn) controls can multiplex

stored and real-time. The examples shown below demon-

strate the four fundamental bus-management functions

that can be performed for data I/O 1A and 1B: 0 - 7.

The direction control (DIRn) determines which bus will

receive data when OEn is LOW. In the isolation mode (OEn

HIGH), A data ma y be stored i n one reg ister and/ or B data

may be stored in the other register. When an output func-

tion is disabl ed, the input functio n is still enabled an d may

be used to store and transmit data. Only one of the two

busses, A or B, may be driven at a time.

Real- Time Transfer

Bus B to Bus A Real-Time Transfer

Bus A to Bus B

Transfer Storage

Data to A or B Storage

OE1DIR1CPAB1CPBA1SAB1SBA1

LLXXXL

OE1DIR1CPAB1CPBA1SAB1SBA1

LHXXLX

OE1DIR1CPAB1CPBA1SAB1SBA1

LLXH or LXH

LHH or LXHX

OE1DIR1CPAB1CPBA1SAB1SBA1



XLX

LXX



XXX

HXX



Preliminary

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74LCX32646

Absolute Maximum Ratings(Note 5)

Recommended Operating Conditions (Note 7)

Note 5: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated

at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-

mended Operating Conditions” table will define th e c onditions fo r ac t ual device operation.

Note 6: IO Absolu te Maximu m Rating must be observed.

Note 7: Unused input s and I/Os m us t be held HIG H or LOW. They may not float.

DC Electrical Characteristics

Symbol Parameter Value Conditions Units

VCC Supply Voltage −0.5 to +7.0 V

VI DC Input Voltag e −0.5 to +7.0 V

VO DC Output Vo ltage −0.5 to +7.0 Output in 3-STATE V

−0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 6)

IIK DC Input Diode Current −50 VI < GND mA

IOK DC Output Diode Current −50 VO < GND mA

+50 VO > VCC

IO DC Output Source/Sink Current ±50 mA

ICC DC Supply Current per Supply Pin ±100 mA

IGND DC Ground Current per Ground Pin ±100 mA

TSTG Storage Temperature −65 to +150 °C

Symbol Parameter Min Max Units

VCC Supply Voltage Operating 2.0 3.6 V

Data Retention 1.5 3.6

VI Input Voltage 0 5.5 V

VO Output Voltage HIGH or LOW State 0 VCC V

3-STATE 0 5.5

IOH/IOL Output Curr ent VCC = 3.0V − 3.6V ±24 mA VCC = 2.7V − 3.0V ±12

VCC = 2.3V − 2.7V ±8

TA Free-Air Operating Temperature −40 85 °C

∆t/∆V Input Edge Rate , VIN = 0.8V–2.0V, VCC = 3.0V 0 10 ns/V

Symbol Parameter Conditions VCC TA = −40°C to +85°C Units

(V) Min Max

VIH HIGH Level Input Voltage 2.3 − 2.7 1.7 V

2.7 − 3.6 2.0

VIL LOW Level Input Voltage 2.3 − 2.7 0.7 V

2.7 − 3.6 0.8

VOH HIGH Level Output Voltage IOH = −100 µA2.3 − 3.6 VCC − 0.2

IOH = −8 mA 2.3 1.8

IOH = −12 mA 2.7 2.2

IOH = −18 mA 3.0 2.4

IOH = −24 mA 3.0 2.2

VOL LOW Level Output Voltage IOL = 100 µA 2.3 − 3.6 0.2

IOL = 8 mA 2.3 0.6

IOL = 12 mA 2.7 0.4

IOL = 16 mA 3.0 0.4

IOL = 24 mA 3.0 0.55

II Input Leakage Current 0 ≤ VI ≤ 5.5V 2.3 − 3.6 ±5.0 µA

IOZ 3-STATE I/O Leakage 0 ≤ VO ≤ 5.5V 2.3 − 3.6 ±5.0 µA

VI = VIH or VIL

IOFF Power-Off Leakage Current VI or VO = 5.5V 0 10 µA

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74LCX32646

DC Electrical Characteristics (Continued)

Note 8: Outputs dis abled or 3-STATE only.

AC Electrical Characteristics

Dynamic Switching Characteristics

Capacitance

Symbol Parameter Conditions VCC TA = −40°C to +85°C Units

(V) Min Max

ICC Quiescent Supply Current VI = VCC or GND 2.3 − 3.6 20 µA

3.6V ≤ VI, VO ≤ 5.5V (Note 8) 2.3 − 3.6 ±20

∆ICC Increase in ICC per Input VIH = VCC −0.6V 2.3 − 3.6 500 µA

Symbol Parameter

TA = −40°C to +85°C, RL = 500Ω

Units

VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5V ± 0.2V

CL = 50 pF CL = 50 pF CL = 30 pF

Min Max Min Max Min Max

fMAX Maximum Clock Frequency 170 ns

tPHL Propagation Delay 1.5 5.2 1.5 6.0 1.5 6.2 ns

tPLH Bus to Bus 1.5 5.2 1.5 6.0 1.5 6.2

tPHL Propagation Delay 1.5 6.0 1.5 7.0 1.5 7.2 ns

tPLH Clock to Bus 1.5 6.0 1.5 7.0 1.5 7.2

tPHL Propagation Delay 1.5 6.0 1.5 7.0 1.5 7.2 ns

tPLH Select to Bus 1.5 6.0 1.5 7.0 1.5 7.2

tPZL Output Enable Time 1.5 7.5 1.5 8.5 1.5 9.8 ns

tPZH 1.5 7.5 1.5 8.5 1.5 9.8

tPLZ Output Disable Time 1.5 6.5 1.5 7.5 1.5 7.8 ns

tPHZ 1.5 6.5 1.5 7.5 1.5 7.8

tS Setup Time 2.5 2.5 3.0 ns

tH Hold Time 1.5 1.5 2.0 ns

tW Pulse Width 3.0 3.0 3.5 ns

Symbol Parameter Conditions VCC TA = 25°CUnits

(V) Typical

VOLP Quiet Output Dynamic Peak VOL CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 0.8 V

CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 0.6

VOLV Quiet Output Dynamic Valley VOL CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 −0.8 V

CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 −0.6

Symbol Parameter Conditions Typical Units

CIN Input Capacitance VCC = Open, VI = 0V or VCC 7 pF

CI/O Input/Output Capacitance VCC = 3.3V, VI = 0V or VCC 8 pF

CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, F = 10 MHz 20 pF

Preliminary

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74LCX32646

AC LOADING and WAVEFORMS Generic for LCX Family

FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)

Waveform for Inverting and Non-Inverting Functions

Propagation Delay. Pulse Width and trec Waveforms

3-STATE Output Low Enable and

Disable Times for Logic

3-STATE Output Hi gh Enable and

Disable Times for Logic

Setup Time, Hold Time and Recovery Time for Logic

trise and tfall

FIGURE 2. Waveforms

(Input Characteristics; f =1MHz, tr = tf = 3ns)

Test Switch

tPLH, tPHL Open

tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V, and 2.7V

VCC x 2 at VCC = 2.5 ± 0.2V

tPZH, tPHZ GND

Symbol VCC

3.3V ± 0.3V 2.7V 2.5V ± 0.2V

Vmi 1.5V 1.5V VCC/2

Vmo 1.5V 1.5V VCC/2

VxVOL + 0.3V VOL + 0.3V VOL + 0.15V

VyVOH − 0.3V VOH − 0.3V VOH − 0.15V

Preliminary

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74LCX32646

Schematic D ia gr a m Generic for LCX Family

Preliminary

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74LCX32646 Low Voltage 32-Bit Transceiver/Register with 5V Tolerant Inputs and Outputs ( Preliminary)

Physical Dimensions inches (millimeters) unless otherwise noted

114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

Package Number BGA114A

Preliminary

Fairchild does not assume an y responsibility for use of any circuitry described , no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the l abe ling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A crit ical componen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife s upport

device or system, or to affect its safety or effectiveness.