FDD13AN06A0-F085 N-Channel PowerTrench(R) MOSFET FDD13AN06A0-F085 N-Channel PowerTrench(R) MOSFET 60V, 50A, 13.5m Applications Features * Motor / Body Load Control * r DS(ON) = 11.5m (Typ.), VGS = 10V, ID = 50A * ABS Systems * Qg(tot) = 22nC (Typ.), VGS = 10V * Powertrain Management * Low Miller Charge * Injection Systems * Low QRR Body Diode * DC-DC converters and Off-line UPS * UIS Capability (Single Pulse and Repetitive Pulse) * Distributed Power Architectures and VRMs * Qualified to AEC Q101 * Primary Switch for 12V and 24V systems * RoHS Compliant Formerly developmental type 82555 DRAIN (FLANGE) D GATE G SOURCE S TO-252AA FDD SERIES MOSFET Maximum Ratings TC = 25C unless otherwise noted Symbol VDSS Drain to Source Voltage Parameter Ratings 60 Units V VGS Gate to Source Voltage 20 V 50 A 9.9 A Drain Current ID Continuous (TC < 80oC, VGS = 10V) o o Continuous (TA = 25 C, VGS = 10V, R JA = 52 C/W) Pulsed EAS PD TJ, TSTG Single Pulse Avalanche Energy ( Note 1) Figure 4 A 56 mJ Power dissipation 115 W Derate above 25oC 0.77 W/o -55 to 175 o Operating and Storage Temperature C C Thermal Characteristics RJC RJA RJA 1.3 o C/W Thermal Resistance Junction to Ambient TO-252 100 o C/W Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area 52 o C/W Thermal Resistance Junction to Case TO-252 This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ (c)2010 Semiconductor Components Industries, LLC. September-2017, Rev. 1 Publication Order Number: FDD13AN06A0-F085/D Device Marking FDD13AN06A0 Device FDD13AN06A0-F085 Package TO-252AA Reel Size 330mm Tape Width 16mm Quantity 2500 units Electrical Characteristics TC = 25C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units V Off Characteristics BVDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250A, VGS = 0V 60 - - - - 1 - - 250 VGS = 20V - - 100 nA - 4 V V DS = 50V VGS = 0V TC = 150oC A On Characteristics VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250A 2 ID = 50A, VGS = 10V - 0.0115 0.0135 ID = 25A, VGS = 6V - 0.022 0.034 ID = 50A, VGS = 10V, TJ = 175oC - 0.026 0.030 - 1350 - pF - 260 - pF - 90 - pF 22 29 nC Dynamic Characteristics CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V Qg(TH) Threshold Gate Charge VGS = 0V to 2V Qgs Gate to Source Gate Charge Qgs2 Gate Charge Threshold to Plateau Qgd Gate to Drain "Miller" Charge V DS = 25V, VGS = 0V, f = 1MHz VDD = 30V ID = 50A Ig = 1.0mA - 2.6 3.4 nC - 8.2 - nC - 5.6 - nC - 6.4 - nC ns Switching Characteristics (VGS = 10V) tON Turn-On Time - - 130 td(ON) Turn-On Delay Time - 9 - ns tr Rise Time - 77 - ns td(OFF) Turn-Off Delay Time - 26 - ns tf Fall Time - 25 - ns tOFF Turn-Off Time - - 77 ns V V DD = 30V, ID = 50A V GS = 10V, RGS = 12 Drain-Source Diode Characteristics ISD = 50A - - 1.25 ISD = 25A - - 1.0 V Reverse Recovery Time ISD = 50A, dISD/dt = 100A/s - - 24 ns Reverse Recovered Charge ISD = 50A, dISD/dt = 100A/s - - 15 nC VSD Source to Drain Diode Voltage trr QRR Notes: 1: Starting T J = 25C, L = 45H, I AS = 50A. www.onsemi.com 2 FDD13AN06A0-F085 N-Channel PowerTrench(R) MOSFET Package Marking and Ordering Information 1.2 80 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 CURRENT LIMITED BY PACKAGE 60 40 20 0.2 0 0 0 25 50 75 100 150 125 25 175 50 75 TC , CASE TEMPERATURE (o C) 100 125 150 175 o TC, CASE TEMPERATURE ( C) Figure 1. Normalized Power Dissipation vs Ambient Temperature Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 ZJC, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x Z JC x RJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance 800 TC = 25oC IDM, PEAK CURRENT (A) FOR TEMPERATURES ABOVE 25oC DERATE PEAK TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION CURRENT AS FOLLOWS: 175 - TC I = I25 150 VGS = 10V 100 30 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) Figure 4. Peak Current Capability www.onsemi.com 3 10-1 100 101 FDD13AN06A0-F085 N-Channel PowerTrench(R) MOSFET Typical Characteristics TC = 25C unless otherwise noted 100 1000 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 100 100s 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10 1 0.1 IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 10s SINGLE PULSE TJ = MAX RATED TC = 25oC DC 10ms 10 STARTING TJ = 150oC 1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 0.01 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 100 NOTE: Refer to ON Semiconductor Application Notes AN7514 and AN7515 Figure 5. Forward Bias Safe Operating Area Figure 6. Unclamped Inductive Switching Capability 100 100 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V 80 TC = 25oC 60 TJ = 175 oC 40 VGS = 20V 80 ID, DRAIN CURRENT (A) ID , DRAIN CURRENT (A) STARTING TJ = 25o C TJ = -55oC TJ = 25oC VGS = 10V 60 VGS = 6V 40 20 20 0 0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 5V 3 4 5 6 0 7 0.5 VGS , GATE TO SOURCE VOLTAGE (V) Figure 7. Transfer Characteristics 1.5 2.0 Figure 8. Saturation Characteristics 2.5 30 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX NORMALIZED DRAIN TO SOURCE ON RESISTANCE DRAIN TO SOURCE ON RESISTANCE(m) 1.0 VDS , DRAIN TO SOURCE VOLTAGE (V) 25 VGS = 6V 20 15 VGS = 10V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.0 1.5 1.0 VGS = 10V, ID =50A 10 0 10 20 30 40 50 0.5 -80 ID, DRAIN CURRENT (A) Figure 9. Drain to Source On Resistance vs Drain Current -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature www.onsemi.com 4 200 FDD13AN06A0-F085 N-Channel PowerTrench(R) MOSFET Typical Characteristics TC = 25C unless otherwise noted 1.4 1.2 ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, I D = 250A NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.0 0.8 0.6 0.4 -80 -40 0 40 80 120 160 1.1 1.0 0.9 200 -80 -40 TJ, JUNCTION TEMPERATURE (oC) Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature 3000 40 80 120 160 200 Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 10 VGS , GATE TO SOURCE VOLTAGE (V) C, CAPACITANCE (pF) 0 TJ , JUNCTION TEMPERATURE (o C) CISS = CGS + C GD 1000 COSS C DS + C GD CRSS = CGD 100 VDD = 30V 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 50A ID = 25A 2 VGS = 0V, f = 1MHz 40 0 0.1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 0 60 Figure 13. Capacitance vs Drain to Source Voltage 5 10 15 Qg , GATE CHARGE (nC) 20 25 Figure 14. Gate Charge Waveforms for Constant Gate Current www.onsemi.com 5 FDD13AN06A0-F085 N-Channel PowerTrench(R) MOSFET Typical Characteristics TC = 25C unless otherwise noted VDS BVDSS tP L VDS VARY tP TO OBTAIN REQUIRED PEAK IAS IAS + RG VDD VDD - VGS DUT tP IAS 0V 0 0.01 tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS VGS VGS = 10V + Qgs2 VDD DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tf tr VDS 90% 90% + VGS VDD - 10% 10% 0 DUT 90% RGS VGS 50% 50% PULSE WIDTH VGS 0 Figure 19. Switching Time Test Circuit 10% Figure 20. Switching Time Waveforms www.onsemi.com 6 FDD13AN06A0-F085 N-Channel PowerTrench(R) MOSFET Test Circuits and Waveforms (T -T ) JM A P D M = ----------------------------R JA (EQ. 1) In using surface mount devices such as the TO-252 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of P DM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 125 RJA = 33.32+ 23.84/(0.268+Area) EQ.2 RJA = 33.32+ 154/(1.73+Area) EQ.3 100 RJA (oC/W) The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. 75 50 25 0.01 (0.0645) 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. ON Semiconductor provides thermal information to assist the designer's preliminary application evaluation. Figure 21 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the ON Semiconductor device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. 23.84 ( 0.268 + Area ) = 33.32 + ------------------------------------- (EQ. 2) Area in Inches Squared R JA 154 ( 1.73 + Area ) = 33.32 + ---------------------------------- 10 (64.5) AREA, TOP COPPER AREA in 2 (cm2) 3. The use of external heat sinks. JA 1 (6.45) Figure 21. Thermal Resistance vs Mounting Pad Area 2. The number of copper layers and the thickness of the board. R 0.1 (0.645) (EQ. 3) Area in Centimeters Squared www.onsemi.com 7 FDD13AN06A0-F085 N-Channel PowerTrench(R) MOSFET Thermal Resistance vs. Mounting Pad Area .SUBCKT FDD13AN06A0 2 1 3 ; rev August 2002 Ca 12 8 5.1e-10 Cb 15 14 5.8e-10 Cin 6 8 1.3e-9 LDRAIN DPLCAP 10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD RLDRAIN RSLC1 51 5 51 EVTHRES + 19 8 + LGATE GATE 1 ESLC 11 + 17 EBREAK 18 - 50 RDRAIN 6 8 ESG DBREAK + RSLC2 Ebreak 11 7 17 18 65.40 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 DRAIN 2 5 EVTEMP RGATE + 18 22 9 20 21 16 DBODY MWEAK 6 MMED MSTRO RLGATE Lgate 1 9 5.2e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 2.14e-9 LSOURCE CIN 8 7 SOURCE 3 RSOURCE RLSOURCE RLgate 1 9 52 RLdrain 2 5 10 RLsource 3 7 21.4 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD S1A 12 S2A 13 8 15 14 13 S1B CA 17 18 RVTEMP S2B 13 CB 6 8 EGS 5 8 EDS - 19 VBAT + IT 14 + + Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 3.1e-3 Rgate 9 20 3.71 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 5.5e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD RBREAK - 8 22 RVTHRES Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*160),6))} .MODEL DbodyMOD D (IS=1.0E-11 N=1.08 RS=3.5e-3 TRS1=2.2e-3 TRS2=2.5e-9 + CJO=.9e-9 M=5.1e-1 TT=1e-9 XTI=3.9) .MODEL DbreakMOD D (RS=1.5e-1 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=4.1e-10 IS=1e-30 N=10 M=0.45) .MODEL MmedMOD NMOS (VTO=3.5 KP=6 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.71) .MODEL MstroMOD NMOS (VTO=4.3 KP=50 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=2.91 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.71e+1 RS=0.1) .MODEL RbreakMOD RES (TC1=9e-4 TC2=-5e-7) .MODEL RdrainMOD RES (TC1=1.3e-2 TC2=5.2e-5) .MODEL RSLCMOD RES (TC1=1.8e-3 TC2=1.7e-5) .MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-5.3e-3 TC2=-1.0e-5) .MODEL RvtempMOD RES (TC1=-2.5e-3 TC2=1e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5 VOFF=-2) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-5) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=.5 VOFF=-1.5) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. www.onsemi.com 8 FDD13AN06A0-F085 N-Channel PowerTrench(R) MOSFET PSPICE Electrical Model rev August 2002 template FDD13AN06A0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=1.0e-11,nl=1.08,rs=3.5e-3,trs1=2.2e-3,trs2=2.5e-9,cjo=.9e-9,m=5.1e-1,tt=1e-9,xti=3.9) dp..model dbreakmod = (rs=1.5e-1,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=4.1e-10,isl=10e-30,nl=10,m=0.45) m..model mmedmod = (type=_n,vto=3.5,kp=6,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.3,kp=50,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.91,kp=0.05,is=1e-30, tox=1,rs=0.1) LDRAIN sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-5,voff=-2) DPLCAP 5 DRAIN sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-5) 2 10 sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=.5) RLDRAIN sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=.5,voff=-1.5) RSLC1 51 c.ca n12 n8 = 5.1e-10 RSLC2 c.cb n15 n14 = 5.8e-10 ISCL c.cin n6 n8 = 1.3e-9 spe.ebreak n11 n7 n17 n18 = 65.40 GATE spe.eds n14 n8 n5 n8 = 1 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE DBREAK 50 - dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod EVTEMP RGATE + 18 22 9 20 21 11 DBODY 16 MWEAK 6 EBREAK + 17 18 - MMED MSTRO RLGATE CIN 8 LSOURCE 7 RSOURCE RLSOURCE i.it n8 n17 = 1 S2A S1A 12 l.lgate n1 n9 = 5.2e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 2.14e-9 13 8 res.rlgate n1 n9 = 52 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 21.4 15 14 13 S1B CA RBREAK 17 18 RVTEMP S2B 13 CB + 6 8 EGS 19 - VBAT 5 8 EDS - m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=9e-4,tc2=-5e-7 res.rdrain n50 n16 = 3.1e-3, tc1=1.3e-2,tc2=5.2e-5 res.rgate n9 n20 = 3.71 res.rslc1 n5 n51 = 1e-6, tc1=1.8e-3,tc2=1.7e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 5.5e-3, tc1=1e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-5.3e-3,tc2=-1.0e-5 res.rvtemp n18 n19 = 1, tc1=-2.5e-3,tc2=1e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/160))** 6)) }} www.onsemi.com 9 IT 14 + + 8 22 RVTHRES SOURCE 3 FDD13AN06A0-F085 N-Channel PowerTrench(R) MOSFET SABER Electrical Model th JUNCTION REV 22 August 2002 FDD13AN06A0T CTHERM1 TH 6 9.7e-4 CTHERM2 6 5 6.2e-3 CTHERM3 5 4 4.6e-3 CTHERM4 4 3 4.9e-3 CTHERM5 3 2 8e-3 CTHERM6 2 TL 4.2e-2 RTHERM1 CTHERM1 6 RTHERM1 TH 6 5.24e-2 RTHERM2 6 5 10.08e-2 RTHERM3 5 4 4.28e-1 RTHERM4 4 3 1.8e-1 RTHERM5 3 2 1.9e-1 RTHERM6 2 TL 2.1e-1 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model FDD13AN06A0T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =9.7e-4 ctherm.ctherm2 6 5 =6.2e-3 ctherm.ctherm3 5 4 =4.6e-3 ctherm.ctherm4 4 3 =4.9e-3 ctherm.ctherm5 3 2 =8e-3 ctherm.ctherm6 2 tl =4.2e-2 RTHERM3 CTHERM3 4 RTHERM4 rtherm.rtherm1 th 6 =5.24e-2 rtherm.rtherm2 6 5 =10.08e-2 rtherm.rtherm3 5 4 =4.28e-1 rtherm.rtherm4 4 3 =1.8e-1 rtherm.rtherm5 3 2 =1.9e-1 rtherm.rtherm6 2 tl =2.1e-1 } CTHERM4 3 RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 tl www.onsemi.com 10 CASE FDD13AN06A0-F085 N-Channel PowerTrench(R) MOSFET PSPICE Thermal Model ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. "Typical" parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com (c) Semiconductor Components Industries, LLC N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5817-1050 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative www.onsemi.com