3.0 V to 5.5 V, ±12 kV IEC ESD Protected,
500 kbps/50 Mbps RS-485 Transceivers
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. F Document Feedback
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FEATURES
TIA/EIA RS-485 compliant over full supply range
3.0 V to 5.5 V operating voltage range on VCC
1.62 V to 5.5 V VIO logic supply option available
ESD protection on the bus pins
IEC 61000-4-2 ±12 kV contact discharge
IEC 61000-4-2 ≥ ±12 kV air discharge
HBM: ≥ ±30 kV
Full hot swap support (glitch free power-up/power-down)
High speed 50 Mbps data rate (ADM3065E/ADM3066E/
ADM3067E/ADM3068E)
Low speed 500 kbps data rate for long cables (ADM3061E/
ADM3062E/ADM3063E)
Full receiver short-circuit, open circuit, and bus idle fail-safe
Extended temperature range up to 125°C
PROFIBUS compliant at VCC ≥ 4.5 V
Half duplex and full duplex models available
Allows connection of up to 128 transceivers onto the bus
Space-saving package options
10-lead, 3 mm × 3 mm LFCSP
8-lead and 10-lead, 3 mm × 3 mm MSOP
8-lead and 14-lead, narrow body SOIC
APPLICATIONS
Industrial fieldbuses
Process control
Building automation
PROFIBUS networks
Motor control servo drives and encoders
FUNCTIONAL BLOCK DIAGRAMS
RO
RE
DE
DI
V
CC
A
B
GND
D
R
ADM3061E/ADM3065E
14666-001
Figure 1. ADM3061E/ADM3065E Functional Block Diagram
RO
RE
DE
DI
V
CC
A
B
GND
D
R
ADM3063E/ADM3067E
Z
Y
14666-103
Figure 2. ADM3063E/ADM3067E Functional Block Diagram
RO
RE
DE
DI
V
CC
A
B
GND
D
R
V
IO
ADM3062E/ADM3066E
LEVEL
TRANSLATOR
14666-002
Figure 3. ADM3062E/ADM3066E Functional Block Diagram
R
O
RE
DE
DI
V
CC
A
B
GND
D
R
V
IO
ADM3068E
LEVEL
TRANSLATOR
Y
Z
14666-104
Figure 4. ADM3068E Functional Block Diagram
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. F | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 4
Specifications ..................................................................................... 5
Timing Specifications .................................................................. 7
Absolute Maximum Ratings .......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution ................................................................................ 11
Pin Configurations and Function Descriptions ......................... 12
Typical Performance Characteristics ........................................... 16
Test Circuits ..................................................................................... 20
Theory of Operation ...................................................................... 21
IEC ESD Protected RS-485 ....................................................... 21
High Driver Differential Output Voltage ................................ 21
IEC 61000-4-2 ESD Protection ................................................ 21
Truth Tables................................................................................. 22
Receiver Fail-Safe ....................................................................... 22
Hot Swap Capability................................................................... 22
128 Transceivers on the Bus ...................................................... 22
Driver Output Protection .......................................................... 22
Applications Information .............................................................. 23
Isolated High Speed RS-485 Node ........................................... 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 27
REVISION HISTORY
6/2019—Rev. E to Rev. F
Added ADM3068E ............................................................. Universal
Added Figure 2; Renumbered Sequentially .................................. 1
Changes to Features Section and Figure 4 ..................................... 1
Changes to Table 1 Title ................................................................... 4
Changes to Table 2 ............................................................................ 5
Changes to ADM3061E/ADM3062E/ADM3063E Section and
Table 3 ................................................................................................ 7
Changes to ADM3065E/ADM3066E/ADM3067E/ADM3068E
Section and Table 4 ........................................................................... 8
Changes to Figure 5 and Figure 7 ................................................... 9
Changes to Figure 8 ........................................................................ 10
Added Endnote 1 to Digital Input and Output Voltage (DE, RE,
DI, and RO) Parameter, Table 5 .................................................... 11
Changes to Digital Input and Output Voltage (DE, RE, DI, and
RO) Parameter, Table 5 .................................................................. 11
Changes to Table 8 .......................................................................... 13
Added Figure 14 and Table 10; Renumbered Sequentially ....... 15
Changes to Figure 19 Caption ....................................................... 16
Changes to Figure 43 and Figure 44 ............................................. 20
Changes to Isolated High Speed RS-485 Node Section ............. 24
Changes to Ordering Guide .......................................................... 27
4/2019—Rev. D to Rev. E
Added ADM3063E ............................................................. Universal
Change to Features Section ............................................................. 1
Changes to Figure 3 .......................................................................... 1
Changes to Table 1 ............................................................................ 4
Changes to Table 2 ............................................................................ 5
Added Endnote 1, Table 2; Renumbered Sequentially ................ 5
Change to Table 7 ........................................................................... 11
Changes to Table 8 .......................................................................... 12
Changes to Figure 12 and Table 9 ................................................. 13
Changes to Figure 14, Figure 15, Figure 16, and Figure 18
Captions ........................................................................................... 14
Changes to Figure 19, Figure 20, Figure 23, and Figure 24
Captions ........................................................................................... 15
Change to Figure 25 Caption ........................................................ 14
Changes to Figure 39 ...................................................................... 18
Changes to IEC ESD Protected RS-485 Section ......................... 19
Change s to Tr uth Tables Section , Table 11, Tabl e 12, and
Receiver Fail-Safe Section ............................................................. 20
Added Table 10; Renumbered Sequentially ................................ 20
Changes to Isolated High Speed RS-485 Node Section and
Figure 47 .......................................................................................... 22
Changes to Ordering Guide ................................................................... 25
3/2019—Rev. C to Rev. D
Added ADM3067E and 14-Lead SOIC_N, R-14 ........... Universal
Changes to Feature Section ...................................................................... 1
Added Figure 3; Renumbered Sequentially .......................................... 1
Moved Table 1 to ........................................................................................ 4
Changes to Table 2 ..................................................................................... 5
Changes to ADM3065E/ADM3066E/ADM3067E Section .............. 7
Change to Pin 3, Description Column, Table 7 ................................. 11
Changes to Figure 10, Figure 11, and Table 8 ..................................... 12
Added Figure 12 and Table 9; Renumbered Sequentially ................ 13
Changes to Figure 14 ............................................................................... 14
Moved Test Circuits to ............................................................................ 18
Changes to Table 10 and Table 11 ......................................................... 20
Updated Outline Dimensions ................................................................ 26
Changes to Ordering Guide ................................................................... 27
1/2018—Rev. B to Rev. C
Added ADM3062E ............................................................. Universal
Changes to Figure 2 and Table 1 ............................................................. 1
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. F | Page 3 of 28
Changes to ADM3061E/ADM3062E Timing Specifications
Section and Figure 3 ................................................................................... 6
Changes to Figure 5 and Figure 6.............................................................. 7
Changes to Figure 9 and Figure 10 ........................................................ 11
Changes to Figure 16 and Figure 17 ...................................................... 12
Changes to Figure 44 ................................................................................. 21
Changes to Figure 45 ................................................................................. 22
Changes to Ordering Guide .................................................................... 25
12/2017—Rev. A to Rev. B
Added ADM3061E ............................................................. Universal
Changes to Product Title, Features Section, Figure 1, and Table 1 ... 1
Changes to General Description Section ....................................... 3
Changes to Table 2 ............................................................................ 4
Added ADM3061E Timing Specification Section and Table 3;
Renumbered Sequentially ................................................................ 6
Moved Figure 3 .................................................................................. 6
Moved Figure 4, Figure 5, and Figure 6 .......................................... 7
Changes to ADM3065E/ADM3066E Timing Specification
Section Title ....................................................................................... 8
Added 10-Lead MSOP Parameter and 10-Lead LFCSP Parameter,
Table 5 .................................................................................................. 9
Changes to Operating Temperature Range Parameter, Table 5
and Table 6 ......................................................................................... 9
Changes to Figure 7, Figure 8, and Table 7 ..................................... 10
Changes to Table 8 .......................................................................... 11
Changes to Figure 11 ...................................................................... 12
Added Figure 23; Renumbered Sequentially ............................... 13
Added Figure 24, Figure 25, Figure 26, Figure 27, and Figure 28 .. 14
Changed High Speed IEC ESD Protected RS-485 Section to IEC
ESD Protected RS-485 Section ................................................................ 17
Changes to IEC ESD Protected RS-485 Section ................................. 17
Added Endnote 4, Table 9 ......................................................................... 18
Changes to Table 10 ................................................................................... 18
Changes to Figure 44 ................................................................................. 21
Changes to Figure 45 ................................................................................. 22
Changes to Ordering Guide ........................................................... 25
5/2017—Rev. 0 to Rev. A
Added ADM3066E............................................................. Universal
Changes to Features Section, Figure 1, and Table 1...................... 1
Added Figure 2; Renumbered Sequentially ................................... 1
Moved General Description Section .............................................. 3
Changes to General Description Section ....................................... 3
Changes to Specifications Section and Table 2 ............................. 4
Changes to Timing Specifications Section and Figure 3 ............. 5
Changes to Figure 4, Figure 5, and Figure 6 .................................. 6
Added VIO to GND Parameter, Table 4 .......................................... 7
Changes to Thermal Resistance Section and Table 5 ................... 7
Added Figure 8 .................................................................................. 8
Changes to Table 6 ............................................................................ 8
Added Figure 9 and Figure 10 ......................................................... 9
Added Table 7; Renumbered Sequentially ..................................... 9
Changes to Figure 14, Figure 16, and Figure 17 .......................... 10
Changes to Table 8 and Table 9 ..................................................... 15
Added Figure 42 and Figure 43 ..................................................... 20
Changes to Ordering Guide ........................................................... 21
3/2017—Revision 0: Initial Version
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. F | Page 4 of 28
GENERAL DESCRIPTION
The ADM3061E/ADM3062E/ADM3063E/ADM3065E/
ADM3066E/ADM3067E/ADM3068E are 3.0 V to 5.5 V, IEC
electrostatic discharge (ESD) protected RS-485 transceivers,
allowing the devices to withstand ±12 kV contact discharges on
the transceiver bus pins without latch-up or damage. The
ADM3062E/ADM3066E/ADM3068E feature a VIO logic supply
pin that allow a flexible digital interface capable of operating as
low as 1.62 V.
The ADM3065E/ADM3066E/ADM3067E/ADM3068E are
suitable for high speed, 50 Mbps, bidirectional data commu-
nication on multipoint bus transmission lines. The ADM3061E/
ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/
ADM3068E feature a 1/4 unit load input impedance that allows
up to 128 transceivers on a bus. The ADM3061E/ADM3062E/
ADM3063E models offer all of the same features as the
ADM3065E/ADM3066E/ADM3067E/ADM3068E models at a
low 500 kbps data rate that is suitable for operation over long
cable runs.
The ADM3061E/ADM3062E/ADM3065E/ADM3066E are half-
duplex RS-485 transceivers, fully compliant to the PROFIBUS®
standard with increased 2.1 V bus differential voltage at VCC ≥
4.5 V. The ADM3063E/ADM3067E/ADM3068E are full duplex
RS-485 transceiver options.
The RS-485 transceivers are available in a number of space-
saving packages, such as the 10-lead, 3 mm × 3 mm lead frame
chip-scale package (LFCSP), the 8-lead or 10-lead, 3 mm × 3 mm
mini small outline package (MSOP), and the 8-lead or 14-lead,
narrow body standard small outline packages (SOIC_N).
Models with operating temperature ranges of −40°C to +125°C
and −40°C to +85°C are available.
Excessive power dissipation caused by bus contention or by
output shorting is prevented by a thermal shutdown circuit. If a
significant temperature increase is detected in the internal driver
circuitry during fault conditions, this feature forces the driver
output into a high impedance state.
The ADM3061E/ADM3062E/ADM3063E/ADM3065E/
ADM3066E/ADM3067E/ADM3068E guarantee a logic high
receiver output when the receiver inputs are shorted, open, or
connected to a terminated transmission line with all drivers
disabled.
Table 1 presents an overview of the ADM3061E/ADM3062E/
ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
data rate capability across temperature, power supply, and package
options. Refer to the Ordering Guide for model numbering.
Table 1. Summary of the ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Operating
Conditions—Data Rate Capability Across Temperature, Power Supply, and Package
Maximum Data Rate1 Maximum VCC (V) Maximum Temperature Package Description
50 Mbps
5.5
10-lead LFCSP
50 Mbps 5.5 −40°C to +105°C 8-lead SOIC_N, 8-lead MSOP, 10-lead MSOP, and 14-lead SOIC_N
50 Mbps 3.6 −40°C to +125°C 8-lead SOIC_N, 8-lead MSOP, 10-lead MSOP, and 14-lead SOIC_N
500 kbps 5.5 −40°C to +125°C 8-lead SOIC_N, 8-lead MSOP, 10-lead MSOP, 10-lead LFCSP, and
14-lead SOIC_N
1 The ADM3065E/ADM3066E/ADM3067E/ADM3068E data input (DI) is transmitting 50 Mbps (or 500 kbps for the ADM3061E/ADM3062E/ADM3063E) clock data, and the
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E driver enable (DE) is enabled for 50% of the DI transmit time
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. F | Page 5 of 28
SPECIFICATIONS
VCC = 3.0 V to 5.5 V, VIO = 1.62 V to VCC (ADM3062E/ADM3066E/ADM3068E), TA = TMIN (−40°C) to TMAX (+125°C), unless otherwise
noted. All typical specifications are at TA = 25°C, VIO = VCC = 3.3 V, unless otherwise noted.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
No Load Supply Current ICC 3.5 7.5 mA DE = VIO1, RE = 0 V
3.5 7.5 mA DE = VIO, RE = VIO
3 4.5 mA DE = 0 V, RE = 0 V
ADM3065E/ADM3066E/ADM3067E/
ADM3068E Supply Current,
Data Rate = 50 Mbps
ICC 107 172 mA Load resistance (RL) = 54 Ω, DE = VIO,
RE = 0 V (VCC ≥ 4.5 V)
67 75 mA RL = 54 Ω, DE = VIO, RE = 0 V (VCC = 3.0 V)
ADM3061E/ADM3062E/ADM3063E
Supply Current, Data Rate = 500 kbps
ICC 100 165 mA RL = 54 Ω, DE = VIO, RE = 0 V (VCC ≥ 4.5 V)
56 74 mA RL = 54 Ω, DE = VIO, RE = 0 V (VCC = 3.0 V)
Supply Current in Shutdown Mode
I
SHDN
210
450
µA
DE = 0 V, RE = VIO
VIO Shutdown Current2 IIOSHDN 1 50 µA DE = 0 V, RE = VIO
DRIVER
Differential Outputs
Output Voltage, Loaded |VOD2| 2.0 2.5 VCC V VCC ≥ 3.0 V, RL = 50 Ω, see Figure 38
|VOD2| 1.5 2.1 VCC V VCC ≥ 3.0 V, RL = 27 Ω (RS-485), see Figure 38
|VOD2| 2.1 3.5 VCC V VCC ≥ 4.5 V, RL = 50 Ω, see Figure 38
|VOD2| 2.1 3 VCC V VCC ≥ 4.5 V, RL = 27 Ω (RS-485), see Figure 38
|VOD3| 1.5 2.1 VCC V VCC ≥ 3.0 V, −7 V ≤ common-mode voltage
(VCM) ≤ +12 V, see Figure 39
|VOD3| 2.1 3 VCC V VCC ≥ 4.5 V, −7 V ≤ VCM ≤ +12 V, see Figure 39
Change in Differential Input Voltage for
Complementary Output States
∆|VOD| 0.2 V RL = 27 Ω or 50 Ω, see Figure 38
Common-Mode Output Voltage VOC 1.6 3.0 V RL = 27 Ω or 50 Ω, see Figure 38
Change in Common Mode Voltage for
Complementary Output States
∆|VOC| 0.2 V RL = 27 Ω or 50 Ω, see Figure 38
Output Short-Circuit Current IOS −250 +250 mA −7 V < output voltage (VOUT) < +12 V
ADM3063E/ADM3067E Output
Leakage (Y, Z)
IO +100 µA DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V,
input voltage (VIN) = 12 V
−100 µA DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V, VIN = −7 V
Logic Inputs (DE, RE, DI)
Input Voltage
Low VIL 0.33 × VIO V DE, RE, DI, 1.62 V ≤ VIO ≤ 5.5 V
High VIH 0.67 × VIO V DE, RE, DI, 1.62 V ≤ VIO ≤ 5.5 V
Input Current II −2 +2 µA DE, RE, DI, 1.62 V ≤ VIO ≤ 5.5 V, 0 V ≤ VIN ≤ VIO
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. F | Page 6 of 28
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
RECEIVER
Differential Inputs
Differential Input Threshold Voltage VTH −200 −125 −30 mV −7 V < VCM < +12 V
Input Voltage Hysteresis VHYS 30 mV −7 V < VCM < +12 V
Input Current (A, B)
I
I
0.1
0.25
mA
DE = 0 V, V
CC
= powered/unpowered, V
IN
= 12 V
−0.20 −0.1 mA DE = 0 V, VCC = powered/unpowered, VIN = −7 V
Line Input Resistance RIN 48 96 kΩ −7 V ≤ VCM ≤ +12 V
Logic Outputs
Output Voltage
Low VOL 0.4 V VIO = 3.6 V, output current (IOUT) = 2 mA,
VID3 ≤ −0.2 V
0.4 V VIO = 2.7 V, IOUT = 1 mA, VID ≤ −0.2 V2
0.2 V VIO = 1.95 V, IOUT = +500 µA, VID ≤ −0.2 V2
High VOH 2.4 V VIO = 3.0 V, IOUT = −2 mA, VID ≥ −0.03 V
2.0 V VIO = 2.3 V, IOUT = −1 mA, VID ≥ −0.03 V2
VIO − 0.2 V VIO = 1.65 V, IOUT = −500 µA, VID ≥ −0.03 V2
Short-Circuit Current 85 mA VOUT = GND or VIO
Three-State Output Leakage IOZR ±2 µA RO pin = 0 V or VIO
1 VIO = VCC for ADM3061E/ADM3063E/ADM3065E/ADM3067E.
2 ADM3062E/ADM3066E/ADM3068E only.
3 VID is the receiver input differential voltage.
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. F | Page 7 of 28
TIMING SPECIFICATIONS
ADM3061E/ADM3062E/ADM3063E
VCC = 3.0 V to 5.5 V, VIO = 1.62 V to VCC (ADM3062E), TA = TMIN (−40°C) to TMAX (+125°C), unless otherwise noted. All typical
specifications are at TA = 25°C, VIO = VCC = 3.3 V, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate1 500 kbps
Propagation Delay
t
DPLH
, t
DPHL
220
800
ns
R
LDIFF
capacitor = 54 Ω, C
L1
capacitor = C
L2
capacitor =
100 pF, see Figure 5 and Figure 40
Skew tDSKEW 5 100 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and
Figure 40
Rise/Fall Times tDR, tDF 120 300 800 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and
Figure 40
Enable to Output High tDZH 100 1000 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
Enable to Output Low tDZL 100 1000 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
Disable Time from Low tDLZ 350 2000 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
Disable Time from High tDHZ 600 2000 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
Enable Time from Shutdown to High tDZH(SHDN)2 550 2000 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
Enable Time from Shutdown to Low tDZL(SHDN)2 550 2000 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RECEIVER
Maximum Data Rate 500 kbps
Propagation Delay
t
RPLH
, t
RPHL
200
ns
C
L
= 15 pF, |V
ID
| ≥ 1.5 V, V
CM
= 1.5 V, see Figure 7 and
Figure 42
Skew/Pulse Width Distortion tRSKEW 50 ns CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 7 and
Figure 42
Enable to Output High tRZH 10 50 ns RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high, see Figure 8
and Figure 44
Enable to Output Low tRZL 10 50 ns RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high, see Figure 8
and Figure 44
Disable Time from Low tRLZ 10 50 ns RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 44
Disable Time from High tRHZ 10 50 ns RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 44
Enable from Shutdown to High tRZH(SHDN)3 2000 ns RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 43
Enable from Shutdown to Low tRZL(SHDN)3 2000 ns RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 43
TIME TO SHUTDOWN tSHDN4 40 ns
1 Maximum data rate assumes a ratio of tDR:tBIT:tDF equal to 1:0.5:1.
2 tDZH(SHDN) and tDZL(SHDN) refer to the time for the device to enable when DE changes from 0 V to VCC. RE = VCC for this condition.
3 tRZH(SHDN) and tRZL(SHDN) refer to the time for the device to enable when RE changes from VCC to 0 V. DE = 0 V for this condition.
4 Minimum time required to put the device into shutdown: DE and RE must be disabled for more than 40 ns for the device to go into shutdown.
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. F | Page 8 of 28
ADM3065E/ADM3066E/ADM3067E/ADM3068E
VCC = 3.0 V to 5.5 V, VIO = 1.62 V to VCC (ADM3066E/ADM3068E), TA = TMIN (−40°C) to TMAX (+125°C), unless otherwise noted. All
typical specifications are at TA = 25°C, VIO = VCC = 3.3 V, unless otherwise noted.
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate1 50 Mbps
Propagation Delay tDPLH, tDPHL 9 15 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and
Figure 40
Skew tDSKEW 1 2 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and
Figure 40
Rise/Fall Times tDR, tDF 4 6.7 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and
Figure 40
Enable to Output High tDZH 10 30 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
Enable to Output Low tDZL 10 30 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
Disable Time from Low
t
DLZ
10
30
ns
R
L
= 110 Ω, C
L
= 50 pF, see Figure 6 and Figure 41
Disable Time from High
t
DHZ
10
30
ns
R
L
= 110 Ω, C
L
= 50 pF, see Figure 6 and Figure 41
Enable Time from Shutdown to High tDZH(SHDN)2 550 2000 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
Enable Time from Shutdown to Low tDZL(SHDN)2 550 2000 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41
RECEIVER
Maximum Data Rate 50 Mbps
Propagation Delay tRPLH, tRPHL 20 35 ns CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 7 and
Figure 42
Skew/Pulse Width Distortion tRSKEW 1 3 ns CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 7 and
Figure 42
Enable to Output High tRZH 10 35 ns RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high,
see Figure 8 and Figure 44
Enable to Output Low tRZL 10 35 ns RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high,
see Figure 8 and Figure 44
Disable Time from Low tRLZ 10 35 ns RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 44
Disable Time from High tRHZ 10 35 ns RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 44
Enable from Shutdown to High tRZH(SHDN)3 450 2000 ns RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 43
Enable from Shutdown to Low tRZL(SHDN)3 450 2000 ns RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and
Figure 43
TIME TO SHUTDOWN tSHDN4 40 ns
1 Maximum data rate assumes a ratio of tDR:tBIT:tDF equal to 1:1:1.
2 tDZH(SHDN) and tDZL(SHDN) refer to the time for the device to enable when DE changes from 0 V to VCC. RE = VCC for this condition.
3 tRZH(SHDN) and tRZL(SHDN) refer to the time for the device to enable when RE changes from VCC to 0 V. DE = 0 V for this condition.
4 Minimum time required to put the device into shutdown: DE and RE must be disabled for more than 40 ns for the device to go into shutdown.
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. F | Page 9 of 28
Timing Diagrams
V
CC
V
OD
0V
+V
OD
NOTES
1. V
OD
IS THE DIFFERENCE BETWEEN A AND B,
WITH +V
OD
BEING THE MAXIMUM POINT OF V
OD
,
AND –V
OD
BEING THE MINIMUM POINT OF V
OD
.
–V
OD
Y, A
B, Z
V
OD
t
DR
t
DF
t
DPLH
t
DPHL
90% POINT
10% POINT
90% POINT
10% POINT
1/2V
OD
1/2V
CC
1/2V
CC
2. V
CC
= V
IO
FOR ADM3062E/ADM3066E/ADM3068E.
V
OD
= V
(A)
– V
(B)
14666-003
t
SKEW
=
t
DPLH
–
t
DPHL
Figure 5. Driver Propagation Delay Rise and Fall Timing Diagram
A
OR B
A
OR B
DE
V
IO
V
CC
0V
0V
V
OH
V
OL
1/2V
IO
1/2V
IO
1/2 (V
CC
+ V
OL
)
1/2V
OH
tDLZ
tDZL
tDZH tDHZ
V
OL
+ 0.5V
V
OH
– 0.5V
NOTES
1.
V
IO
= V
CC
FOR ADM3061E/ADM3063E/ADM3065E/ADM3067E
2
. A = Y, B = Z FOR ADM3063E/ADM3067E/ADM3068E
14666-004
Figure 6. Driver Enable and Disable Timing Diagram
1/2V
CC
1/2V
CC
t
RPLH
t
RPHL
RO
V
OH
0VA – B 0V
V
OL
NOTES
1. V
CC
= V
IO
FOR ADM3062E/ADM3066E/ADM3068E.
t
RSKEW
=
|t
RPLH
–
t
RPHL
|
14666-005
Figure 7. Receiver Propagation Delay Timing Diagram
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. F | Page 10 of 28
RO
RO
RE
VCC
0
V
0V
1/2VCC
1/2VCC
OUTPUT LOW
OUTPUT HIGH
tRLZ
tRZL
tRHZ
tRZH
VOL + 0.5V
VOH – 0.5V VOH
VOL
1/2VCC
1/2VCC
NOTES
1. VCC = VIO F OR ADM3062E/ADM3066E /ADM3068E.
14666-006
VCC
Figure 8. Receiver Enable and Disable Timing Diagram
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. F | Page 11 of 28
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
VCC to GND 6 V
V
IO
to GND
−0.3 V to +6 V
Digital Input and Output Voltage (DE, RE, DI,
and RO)
−0.3 V to
VIO1 + 0.3 V
Driver Output and Receiver Input Voltage −9 V to +14 V
Operating Temperature Ranges −40°C to +85°C
−40°C to +125°C
Storage Temperature Range
−65°C to +150°C
Continuous Total Power Dissipation
8-Lead SOIC_N 0.225 W
8-Lead MSOP 0.151 W
10-Lead MSOP 0.151 W
10-Lead LFCSP 0.450 W
14-Lead SOIC_N 0.239 W
Maximum Junction Temperature (TJ) 150°C
Lead Temperature
Soldering (10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec)
220°C
ESD on the Bus Pins (A, B, Y, Z)
IEC 61000-4-2 Contact Discharge ±12 kV
IEC 61000-4-2 Air Discharge
10 Positive and 10 Negative
Discharges
±12 kV
Three Positive or Three Negative
Discharges
±15 kV
ESD Human Body Model (HBM)
On the Bus Pins (A, B, Y, Z) ≥±30 kV
All Other Pins ±8 kV
1 VIO = VCC on the ADM3061E/ADM3063E/ADM3065E/ADM3067E.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
θJC is the junction to case thermal resistance.
Table 6. Thermal Resistance
Package Type θJA1 θJC1 Unit
R-8 110.88 58.63 °C/W
RM-8 165.69 49.61 °C/W
RM-10 165.69 49.61 °C/W
R-14 104.5 42.90 °C/W
CP-10-9 55.65 33.22 °C/W
1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with no bias. See JEDEC JESD-51.
ESD CAUTION
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. F | Page 12 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RO
1
RE
2
DE
3
DI
4
V
CC
8
B
7
A
6
GND
5
14666-007
ADM3061E/
ADM3065E
TOP VIEW
(No t t o Scal e)
Figure 9. ADM3061E/ADM3065E 8-Lead Narrow Body SOIC_N Pin
Configuration
RO 1
RE 2
DE 3
DI 4
VCC
8
B
7
A
6
GND
5
ADM3061E/
ADM3065E
TOP VIEW
(Not to S cale)
14666-008
Figure 10. ADM3061E/ADM3065E 8-Lead MSOP Pin Configuration
Table 7. ADM3061E/ADM3065E Pin Function Descriptions
Pin No. Mnemonic Description
1 RO Receiver Output Data. This output is high when (A − B) ≥ −30 mV and low when (A − B) ≤ −200 mV. This output is
tristated when the receiver is disabled; that is, when RE is driven high.
2 RE Receiver Enable Input. This is an active low input. Driving this input low enables the receiver and driving it high
disables the receiver.
3 DE Driver Enable. A high level on this pin enables the driver differential outputs, A and B. A low level places the driver
output into a high impedance state.
4
DI
Transmit Data Input. Data to be transmitted by the driver is applied to this input.
5 GND Ground.
6 A Noninverting Driver Output and Receiver Input. When the driver is disabled, or when VCC is powered down, Pin A is
put into a high impedance state to avoid overloading the bus.
7 B Inverting Driver Output and Receiver Input. When the driver is disabled, or when VCC is powered down, Pin B is put
into a high impedance state to avoid overloading the bus.
8 VCC 3.0 V to 5.5 V Power Supply. Adding a 0.1 µF decoupling capacitor between the VCC pin and the GND pin is recommended.
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. F | Page 13 of 28
1V
IO
2RO
3DE
4RE
5DI
10 V
CC
9B
8A
7NIC
6GND
ADM3062E/
ADM3066E
TOP VIEW
(Not to Scale)
14666-009
NOTES
1. NIC = NO INTERNAL CONNECTION. THIS
PIN IS NOT INTERNALLY CONNECTED.
2. EXPOSED PAD. THE EXPOSED PAD
MUST BE CONNECTED TO GROUND.
Figure 11. ADM3062E/ADM3066E 10-Lead LFCSP Pin Configuration
V
IO 1
RO
2
DE
3
RE
4
DI
5
V
CC
10
B
9
A
8
NIC
7
GND
6
ADM3062E/
ADM3066E
TOP VIEW
(Not to Scale)
1. NIC = NO INTERNAL CONNECTION. THIS
PIN IS NOT INTERNALLY CONNECTED.
14666-010
Figure 12. ADM3062E/ADM3066E 10-Lead MSOP Pin Configuration
Table 8. ADM3066E/ADM3062E Pin Function Descriptions
Pin No. Mnemonic Description
1 VIO 1.62 V to 5.5 V Logic Supply. Adding a 0.1 μF decoupling capacitor between the VIO pin and the GND pin is
recommended.
2 RO Receiver Output Data. This output is high when (A − B) ≥ −30 mV and is low when (A − B) ≤ −200 mV. This output is
tristated when the receiver is disabled; that is, when RE is driven high.
3 DE Driver Enable. A high level on this pin enables the driver differential outputs, A and B. A low level places the driver
output into a high impedance state.
4 RE Receiver Enable Input. This is an active low input. Driving this input low enables the receiver, and driving it high
disables the receiver.
5 DI Transmit Data Input. Data to be transmitted by the driver is applied to this input.
6 GND Ground.
7 NIC No Internal Connection. This pin is not internally connected.
8 A Noninverting Driver Output and Receiver Input. When the driver is disabled, or when VCC is powered down, Pin A is
put into a high impedance state to avoid overloading the bus.
9 B Inverting Driver Output and Receiver Input. When the driver is disabled, or when VCC is powered down, Pin B is put
into a high impedance state to avoid overloading the bus.
10 VCC 3.0 V to 5.5 V Power Supply. Adding a 0.1 μF decoupling capacitor between the VCC pin and the GND pin is recommended.
EPAD Exposed Pad. The exposed pad must be connected to ground.
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. F | Page 14 of 28
NIC
1
RO
2
RE
3
DE
4
DI
5
GND
6
GND
7
V
CC
14
V
CC
13
A
12
B
11
Z
10
Y
9
NIC
8
NIC = NO I NTERNAL CONNECTION. THIS
PIN IS NOT INT E RNALLY CONNE CTED.
ADM3063E/
ADM3067E
TOP VIEW
(No t t o Scal e)
14666-111
Figure 13. ADM3063E/ADM3067E 14-Lead SOIC Pin Configuration
Table 9. ADM3063E/ADM3067E Pin Function Descriptions
Pin No. Mnemonic Description
1, 8 NIC No Internal Connection. This pin is not internally connected.
2
RO
Receiver Output Data. This output is high when (A − B) ≥ −30 mV and is low when (A − B) ≤ −200 mV. This output is
tristated when the receiver is disabled; that is, when RE is driven high.
3 RE Receiver Enable Input. This is an active low input. Driving this input low enables the receiver and driving it high
disables the receiver.
4 DE Driver Enable. A high level on this pin enables the driver differential outputs, Y and Z. A low level places the driver
output into a high impedance state.
5 DI Transmit Data Input. Data to be transmitted by the driver is applied to this input.
6, 7 GND Ground.
9 Y Driver Noninverting Output. When the driver is disabled, or when VCC is powered down, Pin Y is put into a high
impedance state to avoid overloading the bus.
10 Z Driver Inverting Output. When the driver is disabled, or when VCC is powered down, Pin Z is put into a high
impedance state to avoid overloading the bus.
11 B Inverting Receiver Input.
12 A Noninverting Receiver Input.
13, 14 VCC 3.0 V to 5.5 V Power Supply. Adding a 0.1 µF decoupling capacitor between the VCC pin and the GND pin is
recommended.
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. F | Page 15 of 28
V
IO 1
RO
2
RE
3
DE
4
DI
5
GND
6
NIC
7
V
CC
14
NIC
13
A
12
B
11
Z
10
Y
9
GND
8
NIC = NO I NTERNAL CONNECTION. THIS
PIN IS NOT INT E RNALLY CONNE CTED.
ADM3068E
TOP VIEW
(No t t o Scal e)
14666-114
Figure 14. ADM3068E 14-Lead SOIC Pin Configuration
Table 10. ADM3068E Pin Function Descriptions
Pin No.
Mnemonic
Description
1 VIO 1.62 V to 5.5 V Logic Supply. Adding a 0.1 µF decoupling capacitor between the VIO pin and the GND pin is
recommended.
2 RO Receiver Output Data. This output is high when (A − B) ≥ −30 mV and is low when (A − B) ≤ −200 mV. This output is
tristated when the receiver is disabled; that is, when RE is driven high.
3 DE Driver Enable. A high level on this pin enables the driver differential outputs, Y and Z. A low level places the driver
output into a high impedance state.
4 RE Receiver Enable Input. This is an active low input. Driving this input low enables the receiver and driving it high
disables the receiver.
5 DI Transmit Data Input. Data to be transmitted by the driver is applied to this input.
6, 8 GND Ground.
7, 13 NIC No Internal Connection. This pin is not internally connected.
9 Y Driver Noninverting Output. When the driver is disabled, or when VCC is powered down, Pin Y is put into a high
impedance state to avoid overloading the bus.
10 Z Driver Inverting Output. When the driver is disabled, or when VCC is powered down, Pin Z is put into a high
impedance state to avoid overloading the bus.
11 B Inverting Receiver Input.
12 A Noninverting Receiver Input.
14 VCC 3.0 V to 5.5 V Power Supply. Adding a 0.1 µF decoupling capacitor between the VCC pin and the GND pin is
recommended.
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. F | Page 16 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
0
50
100
150
200
250
300
350
400
–40 –25 –10 520 35 50 65 80 95 110 125
SHUT DO WN CURRENT (ISHDN) (µA)
TEMPERATURE (°C)
VCC = 3.3V
VCC = 4.5V
VCC = 5.5V
14666-018
Figure 15. Shutdown Current (ISHDN) vs. Temperature
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
–40 –25 –10 520 35 50 65 80 95 110 125
SUPPLY CURRE NT (I
CC
) (A)
TEMPERATURE (°C)
R
L
= 120Ω
NO LOAD
R
L
= 54Ω
14666-019
Figure 16. Supply Current (ICC) vs. Temperature, Data Rate = 50 Mbps,
50 Mbps Models, VCC = 3.3 V
0
0.02
0.04
0.06
0.10
0.08
–55 –35 –15 12510585654525
5
SUPPLY CURRE NT (I
CC
) (A)
TEMPERATURE (°C)
R
L
= 120Ω
NO LOAD
R
L
= 54Ω
14666-020
Figure 17. Supply Current (ICC) vs. Temperature, Data Rate = 50 Mbps,
50 Mbps Models, VCC = 5.0 V
0
0.02
0.04
0.06
0.08
0.10
0.12
0 5 10 15 20 25 30 35 40 45 50
SUPPLY CURRE NT (ICC) (A)
DATA RATE (M bp s)
VCC = 3.3V
VCC = 5.0V
VCC = 5.5V
14666-021
Figure 18. Supply Current (ICC) vs. Data Rate with 54 Ω Load Resistance,
50 Mbps Models
0
0.01
0.02
0.04
0.06
0.08
0.03
0.05
0.07
0 5 10 15 20 25 30 35 40 45 50
SUPPLY CURRE NT (I
CC
) (A)
DATA RATE (M bp s)
V
CC
= 3.3V
V
CC
= 5.0V
V
CC
= 5.5V
14666-022
Figure 19. Supply Current (ICC) vs. Data Rate with No Load Resistance,
50 Mbps Models
0
0.02
0.04
0.06
0.08
0.10
0.12
050 100 150 200 250 300 350 400 450 500
SUPPLY CURRENT ( I
CC
) (A)
DATA RATE (kbp s)
V
CC
= 3.3V, NO LOAD
V
CC
= 3.3V, 54Ω LOAD
V
CC
= 5V, NO LOAD
V
CC
= 5V, 54Ω LOAD
14666-123
Figure 20. Supply Current (ICC) vs. Data Rate with 54 Ω Load Resistance and
No Load Resistance, 500 kbps Models
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. F | Page 17 of 28
0
10
20
30
40
50
60
SUPPLY CURRENT (I
CC
) (mA)
TEMPERATURE ( °C)
–55 –35 –15 525 45 65 85 105 125
14666-124
Figure 21. Supply Current (ICC) vs. Temperature, Data Rate = 500 kbps,
500 kbps Models, VCC = 3.0 V
SUPPLY CURRENT (I
CC
) (mA)
TEMPERATURE ( °C)
0
20
40
60
80
100
120
140
–60 –40 –20 020 40 60 80 100 120 140
14666-125
Figure 22. Supply Current (ICC) vs. Temperature, Data Rate = 500 kbps,
500 kbps Models, VCC = 5.5 V
140
160
180
200
220
240
260
280
300
–60 –40 –20 020 40 60 80 100 120 140
DRIVE R DIF FERENTI AL P ROPAGATION DELAY (ns)
TEMPERATURE (⁰C)
t
DPLH AT 5.5V
t
DPHL AT 5.5V
t
DPLH AT 3.0V
t
DPHL AT 3.0V
14666-126
Figure 23. Driver Differential Propagation Delay vs. Temperature,
500 kbps Models
CH1 1.0V A CH1 0V
BWCH2 1. 0V BW
1
2
ROUT
VID
14666-127
Figure 24. Receiver Propagation Delay (Oscilloscope Plot),
Data Rate = 500 kbps, VID ≥ 1.5 V
CH1 3.0V CH2 2.0V A CH1 1.98V
BWBW
CH3 2.0V M1 2.5V
BW
1
2
M1 VOD
DI
A
B
14666-128
Figure 25. Driver Propagation Delay (Oscilloscope Plot),
Data Rate = 500 kbps, 500 kbps Models
4
5
6
7
8
9
10
11
12
–40 –25 –10 520 35 50 65 80 95 110 125
DRIVE R DIF FERENTI AL PROPAG ATI ON DEL AY ( ns)
TEMPERATURE (°C)
t
DPHL
,V
CC
= 3.0V
t
DPLH
,V
CC
= 3.0V
t
DPHL
,V
CC
= 5.5V
t
DPLH
,V
CC
= 5.5V
14666-023
Figure 26. Driver Differential Propagation Delay vs. Temperature, 50 Mbps
Models
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. F | Page 18 of 28
C1 1. 0V /DI V
C2 2. 0V /DI V
50Ω
BW
: 1. 5G
50Ω
BW
: 1. 5G 20ns/DIV
5.0GS/s
200ps/pt
A C1 1.34V
1
2
V
OD
DI
14666-024
Figure 27. Driver Propagation Delay (Oscilloscope Plot),
Data Rate = 50 Mbps, 50 Mbps models
–0.12
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
DRIVE R OUT P UT CURRENT ( A)
DRIVER DIFFERENTIAL OUTPUT VOLTAGE (V)
V
CC
= 5.5V
V
CC
= 4.5V
V
CC
= 3.0V
14666-025
Figure 28. Driver Output Current vs. Driver Differential Output Voltage
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
–40 –25 –10 520 35 50 65 80 95 110 125
DRIVER DIFFERENTIAL OUTPUT VOLTAGE (V)
TEMPERATURE (°C)
VCC = 3.0V
VCC = 4.5V
14666-026
Figure 29. Driver Differential Output Voltage vs. Temperature
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
–7 –5 –3 –1–6 –4 –2 0 1 32 4 5
DRIVER OUTPUT CURRENT (A)
DRIVER OUTPUT HIGH VOLTAGE (V)
VIO = VCC = 3.3 V
14666-027
Figure 30. Driver Output Current vs. Driver Output High Voltage
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
0 2 4 6 8 10 12
DRIVE R OUT P UT CURRENT ( A)
DRIVER OUTPUT LOW VOLTAGE (V)
V
IO
= V
CC
= 3.3 V
14666-028
Figure 31. Driver Output Current vs. Driver Output Low Voltage
C1 1.0V/ DIV
C2 1.0V/ DIV
50Ω BW: 1. 5G
50Ω BW: 1. 5G 20ns/DIV
5.0GS/s
200ps/pt
A C1 0.0V
1
2
RO
VID
14666-029
Figure 32. Receiver Propagation Delay at 50 Mbps, |VID| ≥ 1.5 V
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. F | Page 19 of 28
16
18
20
22
24
26
28
–40 –25 –10 520 35 50 65 80 95 110 125
RECEI V E R P ROPAGATIO N DE LAY ( ns)
TEMPERATURE (°C)
t
RPHL
t
RPLH
14666-030
Figure 33. Receiver Propagation Delay vs. Temperature, 50 Mbps
0
0.005
0.010
0.015
0.020
0.025
0.030
0.035
00.5 1.0 1.5 2.0 2.5 3.0 3.5
RECEI V E R OUT P UT CURRENT ( A)
RECEIVER OUTPUT LOW VOLTAGE (V)
V
CC
= 3.3V
14666-031
Figure 34. Receiver Output Current vs. Receiver Output Low Voltage
(VCC = 3.3 V)
–0.040
–0.035
–0.030
–0.025
–0.020
–0.015
–0.005
–0.010
0
00.5 1.0 1.5 2.0 2.5 3.0 3.5
RECEI V E R OUT P UT CURRENT ( A)
RECEIVER OUTPUT HIGH VOLTAGE (V)
VCC = 3.3V
14666-032
Figure 35. Receiver Output Current vs. Receiver Output High Voltage
(VCC = 3.3 V)
5.0
5.2
5.4
5.6
5.8
6.0
RECEIVER OUTPUT HIGH VOLTAGE (V)
–40 –25 –10 520 35 50 65 80 95 110 125
TEMPERATURE (°C)
14666-033
Figure 36. Receiver Output High Voltage vs. Temperature
0
0.05
0.10
0.15
0.20
0.25
RECEIVER OUTPUT LOW VOLTAGE (V)
–40 –25 –10 520 35 50 65 80 95 110 125
TEMPERATURE (°C)
14666-034
Figure 37. Receiver Output Low Voltage vs. Temperature
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. F | Page 20 of 28
TEST CIRCUITS
VOD2
RL
DI
RLVOC
14666-011
Figure 38. Driver Voltage Measurements
V
OD3
60Ω
375Ω
375Ω
VCM
DI
14666-012
Figure 39. Driver Voltage Measurements over Common-Mode Range
C
L1
C
L2
R
LDIFF
DI
14666-013
Figure 40. Driver Propagation Delay
R
L
C
L
V
CC
S2
DE IN
DE
0V OR V
IO
S1
NOTES
1. V
IO
= V
CC
FO R ADM 3061E /ADM3063E /ADM3065E/ADM3067E .
14666-014
Figure 41. Driver Enable/Disable
RE
B
RE = 0V
A
C
L
V
OUT
V
IN
INPUT
GENERATOR
14666-015
Figure 42. Receiver Propagation Delay/Skew
RE
RL
VCC
S2
S1
+1.5V
–1.5V
RE IN
C
L
V
OUT
NOTES
1. VCC = VIO F OR ADM3062E/ADM3066E / ADM3068E.
14666-016
Figure 43. Receiver Enable/Disable from Shutdown
CL
RLVOUT
VCC
RE
S2
D
RE IN
VCC
S1
VCC
R
DI
DE
A
B
NOTES
1. VCC = VIO F OR ADM3062E/ADM3066E /ADM3068E.
14666-017
Figure 44. Receiver Enable/Disable
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. F | Page 21 of 28
THEORY OF OPERATION
IEC ESD PROTECTED RS-485
The ADM3065E/ADM3066E/ADM3067E/ADM3068E are 3.0 V
to 5.5 V, 5 0 Mbps RS-485 transceivers with IEC 61000-4-2 Level 4
ESD protection on the bus pins. The ADM3061E/ADM3062E/
ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
can withstand up to ±12 kV contact discharge on transceiver
bus pins (A, B, Y, and Z) without latch-up or damage. The
ADM3061E/ADM3062E/ADM3063E has the same robust IEC
61000-4-2 ESD protection as the ADM3065E/ADM3066E/
ADM3067E/ADM3068E models and operate at a lower,
500 kbps data rate.
HIGH DRIVER DIFFERENTIAL OUTPUT VOLTAGE
The ADM3061E/ADM3062E/ADM3063E/ADM3065E/
ADM3066E/ADM3067E/ADM3068E have characteristics that
are optimized for use in PROFIBUS applications. When powered at
VCC ≥ 4.5 V, the ADM3061E/ADM3062E/ADM3063E/
ADM3065E/ADM3066E/ADM3067E/ADM3068E driver output
differential voltage meets or exceeds the PROFIBUS requirements
of 2.1 V with a 54 Ω load.
IEC 61000-4-2 ESD PROTECTION
ESD is the sudden transfer of electrostatic charge between bodies at
different potentials caused either by near contact or induced by
an electric field. It has the characteristics of high current in a
short time period. The primary purpose of the IEC 61000-4-2
test is to determine the immunity of systems to external ESD
events outside the system during operation. IEC 61000-4-2
describes testing using two coupling methods: contact discharge
and air discharge. Contact discharge implies a direct contact
between the discharge gun and the equipment under test (EUT).
During air discharge testing, the charged electrode of the
discharge gun is moved toward the EUT until a discharge
occurs as an arc across the air gap. The discharge gun does not
make direct contact with the EUT. A number of factors affect
the results and repeatability of the air discharge test, including
humidity, temperature, barometric pressure, distance, and rate
of approach to the EUT. This method is a more accurate
representation of an actual ESD event but is not as repeatable.
Therefore, contact discharge is the preferred test method.
During testing, the data port is subjected to at least 10 positive
and 10 negative single discharges. Selection of the test voltage is
dependent on the system end environment.
Figure 45 shows the 8 kV contact discharge current waveform
as described in the IEC 61000-4-2 specification. Some of the
key waveform parameters are rise times of less than 1 ns and
pulse widths of approximately 60 ns.
tR = 0.7ns TO 1ns
IPEAK
I30ns
I60ns
30A
90%
16A
8A
10%
30ns60nsTIME
14666-035
Figure 45. IEC 61000-4-2 ESD Waveform (8 kV)
Figure 46 shows the 8 kV contact discharge current waveform
from the IEC 61000-4-2 standard compared to the HBM ESD
8 kV waveform. Figure 46 shows that the two standards specify a
different waveform shape and peak current. The peak current
associated with an IEC 61000-4-2 8 kV pulse is 30 A, whereas
the corresponding peak current for HBM ESD is more than five
times less, at 5.33 A. The other difference is the rise time of the
initial voltage spike, with the IEC 61000-4-2 ESD waveform having
a much faster rise time of 1 ns, compared to the 10 ns associated
with the HBM ESD waveform. The amount of power associated
with an IEC ESD waveform is much greater than that of an
HBM ESD waveform. The HBM ESD standard requires the
EUT to be subjected to three positive and three negative
discharges, whereas the IEC ESD standard requires 10 positive
and 10 negative discharge tests.
The ADM3061E/ADM3062E/ADM3063E/ADM3065E/
ADM3066E/ADM3067E/ADM3068E with IEC 61000-4-2 ESD
ratings is better suited for operation in harsh environments
compared to other RS-485 transceivers that state varying levels
of HBM ESD protection.
t
R = 0.7ns TO 1ns
IPEAK
I30ns
I60ns
30A
90%
16A
8A
5.33A
10%
30ns10ns 60ns TIME
IEC 61000-4-2 ES D 8kV
HBM ES D 8kV
14666-036
Figure 46. IEC 61000-4-2 ESD Waveform 8 kV Compared to HBM ESD
Waveform 8 kV
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. F | Page 22 of 28
TRUTH TABLES
Table 12 and Table 13 use the abbreviations shown in Table 11.
Table 11. Truth Table Abbreviations
Letter Description
H High level
I Indeterminate
L Low level
X Any state
Z High impedance (off)
Table 12. Transmitting Truth Table
Supply Status Inputs Outputs
VIO1 VCC RE
DE DI A/Y B/Z
On On X H H H L
On On X H L L H
On On X L X Z Z
Off On X X X I I
On Off X X X Z Z
Off Off X X X Z Z
1 For the ADM3061E, ADM3063E, ADM3065E, and ADM3067E, the VIO pin is
not applicable.
Table 13. Receiving Truth Table
Supply Status Inputs Outputs
VIO1 VCC A − B
RE
DE RO
On On >−0.03 V L X H
On On <−0.2 V L X L
On On −0.2 V ≤ A – B ≤
−0.03 V
L X I
On On Inputs open/shorted L X H
On
On
X
H
X
Z
On Off X L X I
On Off X H X Z
Off On X L X I
Off Off X X X I
1 For the ADM3061E, ADM3063E, ADM3065E, and ADM3067E, the VIO pin is
not applicable.
RECEIVER FAIL-SAFE
The ADM3061E/ADM3062E/ADM3063E/ADM3065E/
ADM3066E/ADM3067E/ADM3068E guarantee a logic high
receiver output when the receiver inputs are shorted, open, or
connected to a terminated transmission line with all drivers
disabled. This receiver output is achieved by setting the receiver
input threshold between −30 mV and −200 mV. If the differential
receiver input voltage (A − B) is greater than or equal to
−30 m V, the RO pin is logic high.
If the (A − B) input is less than or equal to −200 mV, RO is logic
low. In the case of a shorted, open circuit or terminated bus with all
transmitters disabled, the receiver differential input voltage is
pulled to 0 V, resulting in a logic high with a 30 mV minimum
noise margin.
HOT SWAP CAPABILITY
When a circuit board is inserted into a powered (or hot)
backplane, differential disturbances to the data bus can lead to
data errors. During this period, processor logic output drivers
are high impedance and are unable to drive the DE and RE
inputs of the RS-485 transceivers to a defined logic level. Leakage
currents up to ±10 µA from the high impedance state of the
processor logic drivers can cause standard complementary
metal-oxide semiconductor (CMOS) enable inputs of a
transceiver to drift to an incorrect logic level. Additionally,
parasitic circuit board capacitance can cause coupling of VCC
or GND to the enable inputs. Without the hot swap capability,
these factors can improperly enable the driver or receiver of
the transceiver. When VCC or VIO rises, an internal pull-down
circuit holds DE low and RE high. After the initial power-up
sequence, the pull-down circuit becomes transparent, resetting
the hot swap tolerable input.
128 TRANSCEIVERS ON THE BUS
The standard RS-485 receiver input impedance is 12 kΩ
(one unit load), and the standard driver can drive up to 32 unit
loads. The ADM3061E/ADM3062E/ADM3063E/ADM3065E/
ADM3066E/ADM3067E/ADM3068E transceivers have a one
fourth unit load receiver input impedance (48 kΩ), allowing up to
128 transceivers to be connected in parallel on one communication
line. Any combination of these devices and other RS-485
transceivers with a total of 32 unit loads or fewer can be
connected to the line.
DRIVER OUTPUT PROTECTION
The ADM3061E/ADM3062E/ADM3063E/ADM3065E/
ADM3066E/ADM3067E/ADM3068E feature two methods to
prevent excessive output current and power dissipation caused
by faults or by bus contention. Current-limit protection on the
output stage provides immediate protection against short circuits
over the whole common-mode voltage range. In addition, a
thermal shutdown circuit forces the driver outputs into a high
impedance state if the die temperature rises excessively. This
circuitry is designed to disable the driver outputs when a die
temperature of 150°C is reached. As the device cools, the drivers
are reenabled at a temperature of 140°C.
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. F | Page 23 of 28
APPLICATIONS INFORMATION
The ADM3061E/ADM3065E transceiver is designed for
bidirectional data communications on multipoint bus
transmission lines. Figure 47 shows a typical network
applications circuit.
To minimize reflections, terminate the line at both ends with a
termination resistor (the value of the termination resistor must
be equal to the characteristic impedance of the cable used) and
keep stub lengths off the main line as short as possible.
RTRT
ADM3061E/
ADM3065E
R
GND
A
B
A
B
RO
RE
DE
DI D
ADM3061E/
ADM3065E
R
GND
A
B
RO
NOTES
1. THE MAX IMUM NUM BE R OF NODES IS 128.
2. RT I S E QUAL TO THE CHARACT E RISTIC IMP E DANCE OF THE CABLE USE D.
RE
DE
DI D
ADM3061E/
ADM3065E
R
GND
A
B
RO
RE
DE
DI D
ADM3061E/
ADM3065E
R
GND
RO
RE
DE
DI
D
VCC
VCC
VCC
VCC
14666-037
Figure 47. ADM3061E/ADM3065E Typical Half-Duplex RS-485 Communications Network
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. F | Page 24 of 28
ISOLATED HIGH SPEED RS-485 NODE
Galvanic isolation, with reinforced insulation and 5 kV rms
transient withstand voltage, can be added to the ADM3065E
using Analog Devices, Inc., iCoupler® and isoPower® technology.
The ADuM6401 provides the required quad channels of 5 kV rms
signal isolation, operating at rates up to 25 Mbps, together with
an integrated dc-to-dc converter. The ADuM6401 combines with
the ADM3065E (shown in Figure 48) with the VISO pin configured
for 3.3 V by connecting the VSEL pin to GNDISO and a 5 V supply
connected to VDD1. Operation at 3.3 V ensures the ADM3065E
remains within the load capability of ADuM6401 even at 25 Mbps.
The dc-to-dc converter in the ADuM6401 isoPower device
provides regulated, isolated power to the ADM3065E (and the
ADuM241D). These isoPower devices use high frequency
switching elements to transfer power through the transformers.
Take care during PCB layout to meet emissions standards. See the
AN-0971 Application Note for PCB layout recommendations.
Galvanic isolation of the ADM3065E at the full data rate, up to
50 Mbps, can be implemented using the ADuM241D quad-
channel digital isolator and the ADuM6028 isolated dc-to-dc
converter, as shown in Figure 49. The ADuM6028 is an 8-pin
device that contains a 300 mW dc-to-dc converter optimized to
meet emissions standards on a 2-layer PCB using two ferrite
beads. The ADuM241D operates at a data rate up to 150 Mbps,
and offers the precise timing required to fully support the
ADM3065E at 50 Mbps.
5V
0.1µF GND
1
V
ISO
V
DD1
GND
ISO
GND
1
V
OA
V
OB
V
OC
V
ID
V
IA
V
IB
V
IC
V
OD
V
DDL
V
SEL
GND
ISO
RO
RE
DE
DI
A
B
D
R
GND
V
CC
ADM3065E
FERRITE
BEAD
10nF
5V
0.1µF
0.1µF
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
4-CHANNEL iCOUPL ER CORE
ADuM6401
14666-038
Figure 48. Signal and Power Isolated 25 Mbps RS-485 Solution (Simplified Diagram—All Connections Not Shown)
DECODE ENCODE
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
GND1
VDD2
VDD1
GND2
GND1
ADuM241D
VOA
VOB
VOC
VID
VIA
VIB
VIC
VOD
DISABLE2, VE2
DISABLE1, VE1GND2
+5V
+5V
RO
RE
DE
DI
A
B
D
R
GND
VCC
ADM3065E
0.1µF 10nF 10μF
FE RRI TE BE AD
FE RRI TE BE AD
0.1µF
0.1µF
14666-039
GND1
PDIS
VDDP
GND1
GNDISO
GNDISO
VSEL
VISO
1
2
3
45
6
8
7
OSC RECT REG
PCS
ADuM6028
Figure 49. Signal and Power Isolated 50 Mbps RS-485 Solution (Simplified Diagram—All Connections Not Shown)
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. F | Page 25 of 28
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 50. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDEC STANDARDS MO-187-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 51. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. F | Page 26 of 28
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50 BSC
0.30
0.15
1.10 MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 52. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
0.50
0.40
0.30
10
1
6
5
0.30
0.25
0.20
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.74
1.64
1.49
0.20 REF
0.05 M AX
0.02 NO M
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
COPLANARITY
0.08
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.20 M IN
PKG-004362
02-07-2017-C
FOR PRO P E R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFI G URATI ON AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
PIN 1
INDIC ATOR AREA O P TIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
Figure 53. 10-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-10-9)
Dimensions shown in millimeters
Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E
Rev. F | Page 27 of 28
CONTROLLING DIMENSIONSARE I N M IL LIM E TERS ; INCH DIM E NS IO NS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFE RE NCE ON LYAND ARE NO T APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDE C S TANDARDS MS-012-AB
060606-A
14 8
7
16.20 ( 0. 2441)
5.80 ( 0. 2283)
4.00 ( 0. 1575)
3.80 ( 0. 1496)
8.75 ( 0. 3445)
8.55 ( 0. 3366)
1.27 ( 0. 0500)
BSC
SEATING
PLANE
0.25 ( 0. 0098)
0.10 ( 0. 0039)
0.51 ( 0. 0201)
0.31 ( 0. 0122)
1.75 ( 0. 0689)
1.35 ( 0. 0531)
0.50 ( 0. 0197)
0.25 ( 0. 0098)
1.27 ( 0. 0500)
0.40 ( 0. 0157)
0.25 ( 0. 0098)
0.17 ( 0. 0067)
COPLANARITY
0.10
8°
0°
45°
Figure 54. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Marking Code
ADM3061EARZ −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM3061EARZ-R7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM3061EBRZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM3061EBRZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM3061EARMZ −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 MBY
ADM3061EARMZ-R7 −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 MBY
ADM3061EBRMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 MC0
ADM3061EBRMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 MC0
ADM3062EACPZ −40°C to +85°C 10-Lead Lead Frame Chip Scale Package [LFCSP] CP-10-9 MCC
ADM3062EACPZ-R7 −40°C to +85°C 10-Lead Lead Frame Chip Scale Package [LFCSP] CP-10-9 MCC
ADM3062EBCPZ −40°C to +125°C 10-Lead Lead Frame Chip Scale Package [LFCSP] CP-10-9 MCD
ADM3062EBCPZ-R7 −40°C to +125°C 10-Lead Lead Frame Chip Scale Package [LFCSP] CP-10-9 MCD
ADM3062EARMZ −40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 MC7
ADM3062EARMZ-R7 −40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 MC7
ADM3062EBRMZ −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 MC8
ADM3062EBRMZ-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 MC8
ADM3063EARZ −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
ADM3063EARZ-R7 −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
ADM3063EBRZ −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
ADM3063EBRZ-R7 −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
ADM3065EARZ −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM3065EARZ-R7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM3065EBRZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM3065EBRZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADM3065EARMZ −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 MC1
ADM3065EARMZ-R7 −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 MC1
ADM3065EBRMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 MC2
ADM3065EBRMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 MC2
ADM3061E/ADM3062E/ADM3063E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Data Sheet
Rev. F | Page 28 of 28
Model1 Temperature Range Package Description Package Option Marking Code
ADM3066EACPZ −40°C to +85°C 10-Lead Lead Frame Chip Scale Package [LFCSP] CP-10-9 MC9
ADM3066EACPZ-R7 −40°C to +85°C 10-Lead Lead Frame Chip Scale Package [LFCSP] CP-10-9 MC9
ADM3066EBCPZ −40°C to +125°C 10-Lead Lead Frame Chip Scale Package [LFCSP] CP-10-9 MCA
ADM3066EBCPZ-R7 −40°C to +125°C 10-Lead Lead Frame Chip Scale Package [LFCSP] CP-10-9 MCA
ADM3066EARMZ −40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 MC4
ADM3066EARMZ-R7 −40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 MC4
ADM3066EBRMZ −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 MC5
ADM3066EBRMZ-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 MC5
ADM3067EARZ −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
ADM3067EARZ-R7 −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
ADM3067EBRZ −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
ADM3067EBRZ-R7 −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
ADM3068EARZ −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
ADM3068EARZ-R7 −40°C to +85°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
ADM3068EBRZ −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
ADM3068EBRZ-R7 −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
EVAL-ADM3061EEBZ 8-Lead SOIC_N Evaluation Board
EVAL-ADM3061EEB1Z 8-Lead MSOP Evaluation Board
EVAL-ADM3062EEBZ 10-Lead MSOP Evaluation Board
EVAL-ADM3062EEB1Z 10-Lead LFCSP Evaluation Board
EVAL-ADM3063EEBZ 14-Lead SOIC_N Evaluation Board
EVAL-ADM3065EEBZ 8-Lead SOIC_N Evaluation Board
EVAL-ADM3065EEB1Z 8-Lead MSOP Evaluation Board
EVAL-ADM3066EEBZ 10-Lead MSOP Evaluation Board
EVAL-ADM3066EEB1Z 10-Lead LFCSP Evaluation Board
EVAL-ADM3067EEBZ 14-Lead SOIC_N Evaluation Board
EVAL-ADM3068EEBZ 14-Lead SOIC_N Evaluation Board
1 Z = RoHS Compliant Part.
©2017–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14666-0-6/19(F)