Serial 2.5Gb/s Hitless Sonet/SDH Backplane Transceiver FEATURES * 16-Bit 155MHz/4-Bit 622MHz 2.5Gb/s Serial Backplane Transceiver with Integrated CMU/CRU * Serial Quad STS-12/STM-4 to 2.5Gb/s Capability with Integrated STS-12 Input Retiming and Deskew * Operation at 155MHz, 622MHz, 2.488GHz, 2.65GHz * Redundant 2.5Gb/s Serial Outputs and Dual 2.5Gb/s Serial Inputs with Hardware Driven Hitless Selection * 2.5Gb/s Backplane Loss of Signal, Frame and Alignment Alarms * Deskews Incoming 2.5Gb/s Signals by 75ns * 16-Bit/4-Bit LVDS Parallel Bus with Both LVPECL and CML Compatibility * Single 2.5V Power Supply * 2.2 Watts Power Dissipation (max) * Ideal for low cost 2.5Gb/s Backplane Interconnect in SONET/SDH ADM, TSI or Wavelength Cross Connect Applications * 195 BGA Package General Description The VSC9180 is a SONET/SDH backplane transceiver with support for working and protection hitless backplane 1+1 protection. It is designed to serialize four STS-12/STM-4 signals, or byte interleaved SONET/SDH/OTN data from 4-bit 622MHz or 16-bit 155MHz parallel buses onto redundant 2.5Gb/s serial backplane outputs. It receives two synchronous and serial STS-48/STM-16 signals or G.709 OTU1 signals, recovers the clock, deskews them and then hitlessly selects between the two. Hitless selection criteria can be derived from BER monitoring or signal integrity monitoring. The selected signal is deserialized to a 4-bit 622MHz bus, a 16-bit 155MHz bus or quad STS-12s operating at 622Mb/s. VSC9180 Functional Block Diagram FRALIGNRST BER[B:A] LOL[B:A] RESET_b SEF[B:A] RXINA+/RXINB+/CLK311MODE Dual 2.5GHz CDR (same ) DMX DMX B E R A1/A2 Align Deinterleave RXLOA RXDATA[15:0]+/2:1 RXCLK+/CHSEL FPOUT+/- EQUIPLOOP LINELOOP INTRLV TXDATA[15:0]+/- [3:0] TXLOA STS-12/STM-4 Phase Alignment STS-48/STM-16 Interleaver [15:0] MUX 2:1 [15:0] TXCLK+/TXCLK_SRC+/- 16 bit 155MHz 4 bit 622MHz Retiming FIFO TXOUTA+/- 2:1 MUX [15:0] CMU BUSMODE G52346, Revision 4.6 September 2, 2003 (c) VITESSE SEMICONDUCTOR CORPORATION * 741 Calle Plano * Camarillo, CA 93012 Tel: (800) VITESSE * FAX: (805) 987-5896 * E-mail: prodinfo@vitesse.com Internet: www.vitesse.com TXOUTB+/REFSEL REFCLK+/- 1 of 28 Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com VSC9180 Data Sheet VSC9180 Data Sheet Draft 8/15/03 Parallel to Serial Transmit Features * Receives 16- or 4-bit parallel LVDS inputs operating at 155MHz or 622MHz, respectively, into an internal FIFO using source synchronous timing * 16-bit 155MHz bus or 4-bit 622MHz bus is bit multiplexed to serial 2.5GHz output * Retimes four serial STS-12/STM-4 inputs and deskews up to +/- 3 bytes of skew using the A1/A2 boundaries * Byte interleaves four serial STS-12/STM-4 inputs to create an STS-48 like signal * Supports bit multiplexing at 2.488GHz, and 2.65GHz Serial to Parallel Receive Features * Dual 2.5Gb/s frequency synchronous serial CML inputs with onboard clock and data recovery * On-board frame alignment of received signals and large internal FIFO for tolerance of up to +/- 75ns of serial backplane skew * Realignment of incoming signals allows hitless selection of incoming channel for maintenance purposes, and prevents downstream devices from having to reframe in a failure condition * Supports bit de-multiplexing at 2.488GHz and 2.65GHz * Hardware based switch over within receipt of two or four errored frame boundaries * Loss of lock, loss of alignment, and loss of frame alarm indication * Receive BER monitoring with selectable error thresholds * Received frame pointer output for SYNC distribution * Returns 16 or 4 bit parallel LVDS bit demultiplexed outputs operating at 155MHz or 622MHz with recovered bus clock * Returns four serial STS-12/STM-4 outputs to same signal pins as received by multiplexer for transparent STS-12/STM-4 backplane transport Other Features * 4-bit or 16-bit parallel bus loopback with output bus clock * Parallel loopback also allows quad STS-12/STM-4 retime, realign, and loopback output * Serial loopback with hitless input selection and realignment * Onboard discrete CMU and CRU to accommodate non-synchronous TX/RX applications 2 of 28 G52346, Revision 4.6 September 2, 2003 Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com Features Summary VSC9180 Data Sheet The receive circuitry interfaces to two frequency synchronous serial STS-48 `like' signals using two redundant CDRs. The CDRs lock to their respective channels, recover the clocks, and deserialize each signal internally. Both signals are then framed and dual FIFOs are used to deskew both signals by up to +/-75ns. Once this deskew has been performed, the CHSEL signal allows the user to choose which received input is then de-multiplexed to the parallel output. Loss of Lock (LOL), Severely Errored Frame (SEF), and Bit Error Rate (BER) alarms are provided on a per channel basis. SEF and BER can be used to drive the CHSEL signal so a 'hitless' transition will take place in hardware if the selected input fails for external reasons. LOL is not recommended for this if there is a possibility of one of the input channels becoming disconnected. Per channel bit error rate (BER) alarms provide additional information for controlling CHSEL. A Loss of Alignment (LOA) alarm is provided to indicate that the received signals are either non-synchronous or are skewed beyond the capability of the VSC9180 to hitlessly switch. The INTRLV and BUSMODE signals select the mode to recreate either the 4-bit or 16-bit byte interleaved STS-48/STM-16 output, or the original received STS-12/STM-4 signals. Figure 1: Hitless Backplane Sparing in Synchronous TSI/ADM Applications Protection 2.5G Backplane Interface VSC9180 'Hitless' Xceiver Pointer Processor Performance Monitor FEC CODEC VSC8144 4-bit SONET Xceiver 2.5G SDH Interface Working System Timing Domain Line Timing Domain The CDR circuitry recovers the incoming clock using the same reference provided to the CMU on the transmit side. The received signal frequency does not need to exactly match the transmitted signal frequency allowing the device to be used in wavelength cross connect applications where the bidirectional signals will be different frequencies. The VSC9180 supports both line and equipment loopback, though not both simultaneously. 3 of 28 G52346, Revision 4.6 September 2, 2003 Draft 8/15/03 The VSC9180 Hitless Transceiver receives parallel data on a 4-bit or 16-bit bus and serializes it to redundant 2.5Gb/s STS-48/STM-16 `like' signal. The parallel data can be in the form of a 4-bit or 16-bit byte interleaved STS-48/STM16 SONET/SDH signal with an accompanying word clock, much like a traditional SONET/SDH transceiver like the VSC8141 16-bit transceiver or VSC8144 4-bit transceiver. This data can also be four, frequency and nearly frame synchronous, serial STS-12/STM-4 signals with no accompanying clock. In the quad serial STS-12/STM-4 mode, the VSC9180 retimes the incoming STS-12/STM-4 signals using a reference clock, and deskews them up to +/- 3 bytes. The four STS-12/STM-4 signals are interleaved according to the SONET/SDH sequence and STS-48 `like' signal is created. The bytes are derived directly from the four received STS-12/STM-4 signals, in groups of four per signal channel, and no overwriting is performed on the A1/A2 boundary, B2 bytes, and K1/K2 protection. This allows the four received tributaries to be transported transparently across the backplane. Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com Functional Overview VSC9180 Data Sheet Draft 8/15/03 Protection Serial 2.5G To O/E Crossconnect VSC8141/4 16/4-bit SONET Xceiver VSC9180 'Hitless' Xceiver Working 2.5G SDH Interface TX Timing RX Timing Dual Clock and Data Recovery Circuit The dual on-board CDRs use a single PLL oscillator to lock on to the incoming phase and frequency of RXIN[B:A]. The CDR is locked to the incoming serial signal chosen by CHSEL, uses its clock to provide a timing reference for the remainder of the receive circuitry, demultiplexers, A1/A2 aligners, and provide the output bus clock RXCLK. When LCK2REF[B:A] is enabled the selected input channel CDR will lock to REFCLK and will no longer adjust its phase in an attempt to capture incoming serial data. The PLL lock reference is provided by REFCLK and must be within +/-40ppm of the incoming RXIN[B:A] for the CDR units to achieve lock. Note that an adjusted clock reference will be required for G.709 frequencies. Demultiplexers and Realignment Circuit The VSC9180 demultiplexes RXINA and RXINB signals and frames each signal by aligning to a 24-bit A1/A2 boundary (F6F628'h). These byte-aligned signals are written to internal FIFOs, and the setting of CHSEL determines which signal is read out of the FIFOs and provided to the RXDATA[15:0] outputs. The positions of the frame boundaries of the signal stored in the FIFOs are used to compute an offset value. This offset value is used to control the read pointers in the realignment FIFOs, which provides realigned data to be selected by CHSEL. Whatever channel is not being selected by CHSEL is in a constant state of FIFO realignment. The unselected signal (the Protection signal) can change phase relative to the selected one (the Working signal) and it's FIFO will continue to realign to the selected signal. Once CHSEL is toggled the Protection signal is now output from RXDATA[15:0] in a hitless changeover, and what was previously the Working channel is now a Protection channel constantly realigned to the Working channel. This allows a hitless changeover from RXINA to RXINB and then back to RXINA, where the phase of the `new' RXINA signal that returned after the failure was not identical to the one before the failure. FRALIGNRST forces the in-frame signals received on the RXIN[B:A] inputs to be re-centered in the realignment FIFOs such that the maximum +/-75ns deskew can be achieved. When FRALIGNRSTSEL = 0, FRALIGNRST resets both selected and unselected channel alignment FIFOs. When FRALIGNRSTSEL = 1, FRALIGNRST resets only the unselected channel alignment FIFO. When a SEF condition is detected on an input it automatically forces the A1/A2 alignment circuitry into a reframe mode. The inputs will consistently attempt to reach an in-frame state without user intervention, similar to other Vitesse products that force reframe in the presence of SEF. Multi-Rate Operation Multi-rate operation is not supported at this time. LOL, SEF, LOA, and FPOUT Behavior Loss of lock (LOL) is declared after a lack of five observed positive or negative transitions for 102.88ns (256 bit times). LOL is also declared if the CDRs are in the process of locking on to the incoming signals. 4 of 28 G52346, Revision 4.6 September 2, 2003 Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com Figure 2: Hitless backplane sparing in asynchronous wavelength cross connects VSC9180 Data Sheet This non-standard SEF behavior provides indication of an `imminent failure' and allows the CHSEL input to be toggled before downstream devices connected to RXDATA[15:0] enter a SEF state and attempt to reframe. Ideally, the SEFA output can be driven directly into the CHSEL input to provide hitless switch over from RXINA to RXINB and prevent downstream devices from entering an alarm state. Switching in this manner will restore the A1/A2 boundary to a downstream device after three errored frame boundaries. Users can bypass this behavior by delaying the assertion of CHSEL relative to SEFA by additional frames externally. In addition the SEFCNTRL signal can be used to select the normal four errored frame boundaries to assert SEF. Loss of Alignment (LOA) is declared when the received frame boundaries of the two RXIN[B:A] signals are too distant for the internal FIFO realignment of +/-75ns. If a channel is in a SEF or LOL state, then no frame boundary is present and alignment is impossible, hence LOA is always present if any channel is in a SEF or LOL state. A device in a LOA state will not perform hitless switching, but will perform asychronous selection of two inputs. Frame Pointer Output (FPOUT) indicates the start of frame of byte aligned data output from the RXDATA[15:0] bus. If the device is in INTRLV=1 mode, the rising edge on FPOUT is aligned with the first bit of the first A1 (F6'h) output from RXDATA[3:0]. If the device is in INTRLV=0 mode (bit-multiplexing), the rising edge on FPOUT is aligned with the first frame-aligned A1A1 (F6F6'h) output from RXDATA[15:0] or first `A' byte (F'h) output from RXDATA[3:0]. The timing behavior of these signals is shown in Figure 10. Quad STS-12/STM-4 Mode (INTRLV=1, BUSMODE=X) The VSC9180 accepts four STS-12/STM-4 signals with +/- 3 bytes of skew on the TXDATA[3:0] inputs, retimes and realigns them using the A1/A2 boundaries, then four-way byte interleaves them as shown in Figure 3 to form a signal similar to an STS-48. The REFCLK input and all TXDATA[3:0] signals must be frequency locked, the REFCLK signal is multiplied and used for digital clock recovery purposes. 5 of 28 G52346, Revision 4.6 September 2, 2003 Draft 8/15/03 Severely errored frame (SEF) can be declared after receipt of two errored frame boundaries, unlike the SONET/SDH standards which calls for four received errored frame boundaries. A SEF alarm is cancelled after two consecutive unerrored frames are received, in accordance with SONET/SDH standards. Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com LOL may inadvertently be de-asserted on an inactive input when it is unterminated and large voltage swings occur on the used input. This can be prevented by terminating the inactive input (RXIN+ = 1, RXIN- = 0), by reducing the voltage swings on the active input, or by asserting LCK2REF on the inactive channel. VSC9180 Data Sheet Draft 8/15/03 Channel Skew TXDATA3+ A121 TXDATA2+ A112 TXDATA1+ A133 A131 A120 A111 A103 TXDATA0+ TXOUT[A:B]+ A132 A133 A132 A131 A122 A113 A101 A130 A233 A123 A110 A102 A130 A123 A120 A111 A103 A121 A231 A121 A112 A100 A122 A232 A120 A223 A110 A102 A113 A230 A112 A111 A222 A213 A101 A233 A103 A221 A212 A100 A110 A232 A102 A220 A211 A203 A101 A231 A223 A210 A202 A100 A230 A213 A201 A233 A222 A200 A232 A231 A230 A223 All symbols are single bit serialized data. Channel skew: 4 Byte skew illustrated. 6 Byte skew maximum. The RXIN[B:A] signals are framed, realigned, four-way byte de-interleaved and output serially with recovered clock RXCLK as shown in Figure 4. The four-way byte de-interleaving does not require the serial RXIN[B:A] input to originate in a VSC9180 device. In this manner, a VSC9180 can be used to extract four STS-12 streams from an STS48 in order to perform Time Slot Interchange functions. Note that the CLEAR input must be set to logic 0 during quad STS-12/STM-4 mode for the VSC9180 to function properly. Figure 4: Quad STS-12/STM-4 Receive Operation (INTRLV=1, BUSMODE=X) RXIN[A:B] A133 A132 A131 A130 A123 A122 A121 A120 A113 A112 A111 A110 A103 A102 A101 RXDATA 3+ A133 A132 A131 A130 A233 A232 RXDATA 2+ A123 A122 A121 A120 A223 A222 RXDATA 1+ A113 A112 A111 A110 A213 A212 RXDATA 0+ A103 A102 A101 A100 A203 A202 A100 A233 A232 A231 A230 All symbols are single bit serialized data 6 of 28 G52346, Revision 4.6 September 2, 2003 Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com Figure 3: Quad STS-12/STM-4 Transmit Operation (INTRLV=1, BUSMODE=X) VSC9180 Data Sheet The VSC9180 accepts four, STS-12/STM-4 serial channels on the TXDATA[3:0]signals when INTRLV=1. In this mode, these four independent channels are four-way byte interleaved into a single STS-48/STM-16 channel. Setting B1CALCEN=1 enables B1 calculation, checking and scrambling/descrambling to be performed. The four STS-12/ STM-4 channels are individually framed, descrambled and the B1 values checked (XORed) against values calculated on the previous frame. The resulting error masks are saved for use in the interleaved STS-48/STM-16 frame. The STS-48/STM-16 frame resulting from the interleaving process has a B1 value inserted into the unscrambled frame, and the frame is then scrambled. After scrambling, a B1 value is calculated for use by the insertion process in the following frame. Any errors detected in the four STS-12/STM-4 B1 comparisons are combined with the calculated STS-48/STM-16 B1 by a simply XORing the five values (4, STS-12/STM-4 error masks with 1, STS-48/STM16 B1 value). The scrambled STS-48/STM-16 frame, with the combined B1 value, is serialized and transmitted out the TXOUT[A:B] signals. When B1CALCEN=0, the four STS-12/STM-4 channels are still interleaved into an STS-48/STM-16 frame, but descrambling/scrambling and B1 calculation/insertion are not performed. Serial STS-48/STM-16 signals received on RXINA and RXINB can be four-way byte de-interleaved into four independent STS-12/STM-4 channels when INTRLV=1. In all modes, a B1 value is calculated on an incoming STS-48/ STM-16 frame before it is descrambled. This value is stored for use in checking errors on the following frame. After de-scrambling the B1 value of the current frame is checked against the previously stored value B1 value. The resulting error mask is saved for use in the de-interleaved STS-12/STM-4 frames when that mode is active. This error mask is also used by the bit error rate monitoring logic. When B1CALCEN=1, the descrambled STS-48/STM-16 frame is de-interleaved to create four independent STS-12/ STM-4 serial channels. Each of the four channels has a B1 value inserted into the unscrambled frames, and the frames are then scrambled. After scrambling, a B1 value is calculated for use by the insertion process in the following frame. If an error was detected in the STS-48/STM-16 B1 comparison, the saved error mask is combined with the calculated B1 value of one of the four STS-12/STM-4 channels. The channel chosen to receive the STS-48/STM-16 frame error mask is performed in a sequentially rotating fashion (round-robin) in which the next channel is chosen only if a nonzero error mask was used. When B1CALCEN=0, the STS-48/STM-16 signal is still de-interleaved into four STS-12/ STM-4 channels but no de-scrambling/scrambling or B1 calculation/insertion is performed. 16-Bit and 4-Bit Multiplexing/Demultiplexing Modes The VSC9180 functions as a typical STS-48/STM-16 transceiver, bit-serializing a 16-bit or 4-bit bus to a 2.488Gb/s signal, and bit deserializing the same signal type to a parallel output bus. The BUSMODE pin indicates the width of the data bus and whether the clocking interfaces are 622MHz or 155MHz. Operation and timing parameters for this mode are shown in Figure 7 and Figure 9. The transmit section of the VSC9180 uses source synchronous timing and provides an output clock TXCLK_SRC to an upstream device. The upstream device should use the TXCLK_SRC output as the timing source for its final output latch. The upstream device should then generate a TXCLK phase-aligned with the output data and provide both to the VSC9180 input bus. TXDATA[15:0] must meet setup and hold times with respect to TXCLK. An architectural representation of the parallel transmit interface is shown in Figure 5. 7 of 28 G52346, Revision 4.6 September 2, 2003 Draft 8/15/03 Scramble and B1 Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com Timing of the INTRLV=1 modes is shown in Figure 8 and Figure 9. VSC9180 Data Sheet Draft 8/15/03 4 x 16b FIFO TXCLK+/write TXDATA[15|3:0]+/- read TXCLK_SRC+/2.488 GHz PLL REFCLK+/- Div 4/16 BUSMODE VSC9180 The use of a FIFO permits the system designer to tolerate an arbitrary amount of delay between TXCLK_SRC and TXCLK. Once RESET is asserted and the FIFO initialized, the delay between TXCLK_SRC and TXCLK can decrease or increase up to one period of the low speed clock (1.6ns or 6.4ns depending on BUSMODE). Should this delay drift exceed one period, the write pointer and the read pointer could point to the same word in the FIFO, resulting in a loss of transmitted data (a FIFO overflow). The receive section of the VSC9180 (see Demultiplexers and Realignment Circuit section) allows hitless selection of which 2.488Gb/s signal is output to the RXDATA[15:0] bus. The data is bit-demultiplexed to either a 4-bit or 16-bit wide RXDATA bus depending on BUSMODE, and has accompanying bus clock RXCLK. The output bus is byte aligned to the A1/A2 frame, with FPOUT providing indication of the start of frame. Table 1: Overview of Bus Width and Interleaving Operation Multiplexing Sequence(2) (in order of serial transmission) Clear INTRLV BUSMODE Functional Parallel I/O(1) TXCLK+/Required? 0 0 0 T/RXDATA[3:0] Yes 0 0 1 T/RXDATA[15:0] Yes TXDATA15, TXDATA14. . .TXDATA0 No TXDATA3[k], TXDATA3[k+1]. . . TXDATA3[k+7] TXDATA2[k]. . . TXDATA2[k+7], TXDATA1[k]. . . TXDATA1[k+7], TXDATA0[k], TXDATA0[k+1]. . . TXDATA0[k+7](3) 0 1 X T/RXDATA[3:0] TXDATA3, TXDATA2, TXDATA1, TXDATA0 NOTES: (1) Unused I/Os may be left unconnected. (2) Demultiplexing operation and sequencing are inverse of multiplexing operation. (3) k+n indicates the nth received STS-12 bit following the first STS-12 bit. Assumes successful quad STS-12/STM-4 realignment. G.709 Operation The VSC9180 supports hitless switching of G.709 `Digital Wrapper' OTN frames (see Figure 6) in addition to the traditional SONET/SDH operation. Setting this mode (WRAP = 1) changes the expected frame length from 38880 bytes (STS-48/STM-16) to 16320 bytes. A 24-bit A1/A2 boundary is expected in this mode as well as SONET/SDH mode (WRAP=0). This mode is available only when STS-48/STM-16 bit interleaved mode is selected (CLEAR = 0, 8 of 28 G52346, Revision 4.6 September 2, 2003 Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com Figure 5: Parallel Bus Timing Architecture (Bit Interleaved) VSC9180 Data Sheet 1 16 17 3824 3825 4080 1 2 OTUk Payload 4 x 3808 Bytes OTUk OH 3 OTUk FEC 4 x 256 Bytes 4 FAS1 FAS2 FAS3 FAS4 FAS5 FAS6 F6'H F6'H F6'H 28'H 28'H 28'H Bit Error Rate Monitor The VSC9180 provides bit error rate monitoring (BER) for each of the STS-48/STM-16 signal channels received on RXINA and RXINB. This is accomplished by calculating a B1 value on the incoming frame before it is descrambled. This value is stored for use in checking errors on the following frame. After de-scrambling the B1 value of the current frame is checked against the previously stored value B1 value. The resulting error mask is used for BER calculation. The BER calculation is performed by counting the number of error bits of the error masks of each frame that is received over a certain interval of frames. The number of frames in the sample interval is selectable by the BERSEL[2:0] signals as shown in Table 2. If the error count within a sample interval reaches the Assert Alarm level, the BER signal is then asserted for that channel (BERA or BERB) immediately. The alarm will remain asserted until the error count for a sample interval falls below the Cancel Alarm level. The BER alarm for a given channel will also be immediately asserted if SEF for that channel is asserted. Table 2: Bit Error Rate Selection BERSEL [2:0] Sample Period Frames Cancel Alarm Error Count Assert Alarm Error Count BER 000 256 971 1077 1.0E-03 001 256 971 1076 1.0E-04 010 256 507 600 1.0E-05 011 65536 19292 19932 1.0E-06 100 65536 1926 2135 1.0E-07 101 65536 171 237 1.0E-08 110 16777216 5050 5386 1.0E-09 111 16777216 469 575 1.0E-10 NOTES: The BER alarm signals can be used in determining which incoming channel should be selected (CHSEL) for output. Lower BER values from 1.0E-06 to 1.0E-10 are recommended due to their increased level of accuracy 9 of 28 G52346, Revision 4.6 September 2, 2003 Draft 8/15/03 Figure 6: G.709 OTUk Frame Format with FAS location Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com INTRLV = 0). The REFCLK+/- frequency must be increased such that 16 or 32 times REFCLK+/- is equal to the new signal frequency being serialized. VSC9180 Data Sheet Draft 8/15/03 Figure 7: Bit Interleaved Transmitter Timing Waveforms (INTRLV=0) TD TXCLK+ Parallel Data Clock Input tTXDSU TXDATA[15|3:0] Parallel Data Inputs tTXDH Valid Data (1) Valid Data (2) TXCLK_SRC Source Synchronous Clock Output TXOUT[B:A]+ D15 D14 D13 High-Speed Differential Serial Data Outputs .......... D2 D1 D0 =Don't care NOTE: Bit 15/3 is MSB and is transmitted FIRST, Bit 0 is LSB and is transmitted LAST Table 3: Multiplexer Input (TX) - Parallel Modes Parameters Description Min Typ Max 1.6/6.4 Units Conditions ns FEC rate is 15/14 of this value tD TXCLK and TXCLK_SRC period tTXDSU Data Setup time to the rising edge of TXCLK+ 350 ps INTRLV=0, BUSMODE=0 tTXDSU Data Setup time to the rising edge of TXCLK+ 600 ps INTRLV=0, BUSMODE=1 tTXDH Data hold time after the rising edge of TXCLK+ 350 ps INTRLV=0, BUSMODE=0 tTXDH Data hold time after the rising edge of TXCLK+ 600 ps INTRLV=0, BUSMODE=1 tRFTXCLKSRC TXCLK_SRC rise and fall times 500 ps tDCTXCLKSRC TXCLK_SRC duty cycle 45 55 % tDCTXCLK TXCLK duty cycle 35 65 % 10 of 28 G52346, Revision 4.6 September 2, 2003 Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com AC Characteristics VSC9180 Data Sheet F6'h TXDATA0 F6'h F6'h TXDATA1 F6'h F6'h TXDATA2 F6'h TXDATA3 F6'h 28'h 28'h 28'h F6'h 28'h 28h F6'h 28'h 28'h 28'h 28'h F6'h 28'h 28'h 28'h TXOUT[B:A] A133 A132 A131 A130 A123 A122 A121 A120 A113 A112 A111 A110 A103 A102 A101 A100 A233 A232 A231 A130 A123 All symbols are single-bit serialized data. Channel skew: 4 byte skew shown, 6 byte skew maximimum. NOTE: A phase relationship between REFCLK and TXDATA[3:0] is not required. Table 4: Multiplexer Input (TX) - Serial Mode Parameters Description tFRMSKEW Skew tolerance of incoming serial STS-12/STM-4 channels tTXDATA Period of incoming STS-12/STM-4 bits tREFCLK Period of REFCLK clock input Min Typ Max Units Conditions +/-24 Bit Times Channels must be frequency locked to REFCLK 1.6 ns Channels must be frequency locked to REFCLK 6.43/ 12.86 ns Selected by REFSEL Table 5: Multiplexer Output (TX) Parameters tRFTXOUT tJTXOUT Description Min TXOUT rise and fall times Output data jitter Typ Max Units Conditions 150 ps 20% to 80% into 100 load ps rms, wideband with 2ps rms jitter on REFCLK, REFCLK=155MHz. PREEMPEN=0 15 NOTE: Setting Preempen=1 will improve output data jitter performance over long cables or backplane traces. 11 of 28 G52346, Revision 4.6 September 2, 2003 Draft 8/15/03 tFRMSKEW Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com Figure 8: Byte Interleaved Transmitter Timing Waveforms (INTRLV=1) VSC9180 Data Sheet Draft 8/15/03 tRXPD tRXPD RXCLK+/- Duty Cycle Distortion RXCLK+ Parallel Data Clock Output 45% RXDATA[15|3:0]+ Parallel Data Outputs 55% Valid Data NOTES: Bit 15/3 is MSB and is serially received FIRST, Bit 0 is LSB and is serially received LAST. See Figure 4 for logical operation of receive output behavior when INTRLV=1. Table 6: Bit and Byte Interleaved Receiver AC Characteristics Parameters Description Min tRXPD Data invalid from rising edge of RXCLK+ tRXPD tRXPD Typ Max Units Conditions -150 150 ps INTRLV=1, BUSMODE=X Data invalid from rising edge of RXCLK+ -150 150 ps INTRLV=0, BUSMODE=0 Data invalid from rising edge of RXCLK+ -600 600 ps INTRLV=0, BUSMODE=1 tRXDR, tRXDF RXDATA[15|3:0] rise and fall times 550 ps INTRLV=1, BUSMODE=X tRXDR, tRXDF RXDATA[15|3:0] rise and fall times 550 ps INTRLV=0, BUSMODE=0 tRXDR, tRXDF RXDATA[15|3:0] rise and fall times 700 ps INTRLV=0, BUSMODE=1 tRXCLKR, tRXCLKF RXCLK rise and fall times 500 ps 20% to 80% into 100 load RXCLKD RXCLK duty cycle distortion 55 % of clock cycle 45 Figure 10: Receiver Alarm and Frame Pointer AC Timing Waveforms RXDATA[15|3:0] SPE SPE SPE FRAME FRAME FRAME RXCLK+ tRXFP FPOUT 12 of 28 G52346, Revision 4.6 September 2, 2003 Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com Figure 9: Bit and Byte Interleaved Receiver AC Timing Waveforms VSC9180 Data Sheet Description Min tRXFP Delay of FPOUT+ rising edge with respect to RXCLK+ tRXFP Typ Max Units Conditions -500 500 ps INTRLV=1, BUSMODE=X Delay of FPOUT+ rising edge with respect to RXCLK+ -500 500 ps INTRLV=0, BUSMODE=0 tRXFP Delay of FPOUT+ rising edge with respect to RXCLK+ -600 600 ps INTRLV=0, BUSMODE=1 tFPR, tFPF FPOUT rise and fall times 500 ps 20% to 80% into 100 load Max Units Conditions Table 8: Input to Output Delay Parameters Description Min Typ tRXDLY Pipeline delay through the VSC9180 in Receive mode 174 194 ns INTRLV=0, BUSMODE=0 tRXDLY Pipeline delay through the VSC9180 in Receive mode 177 197 ns INTRLV=0, BUSMODE=1 tRXDLY Pipeline delay through the VSC9180 in Receive mode 244 264 ns INTRLV=1, BUSMODE=X, B1CALCEN=0 tRXDLY Pipeline delay through the VSC9180 in Receive mode 251 271 ns INTRLV=1, BUSMODE=X, B1CALCEN=1 tTXDLY Pipeline delay through the VSC9180 in Transmit mode 85 105 ns INTRLV=0, BUSMODE=0 tTXDLY Pipeline delay through the VSC9180 in Transmit mode 70 90 ps INTRLV=0, BUSMODE=1 tTXDLY Pipeline delay through the VSC9180 in Transmit mode 381 401 ns INTRLV=1, BUSMODE=X, BlCALCEN=0 tTXDLY Pipeline delay through the VSC9180 in Transmit mode 381 401 ns INTRLV=1, BUSMODE=X, B1CALCEN=1 NOTE: All values are only valid when FIFOSEL=0. Receive mode values are only valid for the selected channel after reset (or FRALIGNRST when the selected channel is affected by FRALIGNRST). Transmit mode values are only valid after reset and assuming that TXCLK is frequency locked to REFCLK. If TXCLK has any wander with respect to REFCLK, then the delay will be affected accordingly. For INTRLV=1, the delay values apply to the earliest of the incoming TXDATA[3:0] signals Table 9: Input to Output Delay Ambiguity Parameters Description Min Typ Max Units Conditions tRXDLYD Delay ambiguity from input to output in Receive mode -5.2 5.2 ns INTRLV=1, BUSMODE=X tTXDLYD Delay ambiguity from input to output in Transmit mode -6 6 ns INTRLV=1, BUSMODE=X 13 of 28 G52346, Revision 4.6 September 2, 2003 Draft 8/15/03 Parameters Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com Table 7: Receiver Frame Pointer AC Characteristics VSC9180 Data Sheet Draft 8/15/03 Table 10: TTL, LVDS and CML Inputs and Outputs Parameters Description Min Typ Max Units Conditions TTL Inputs and Outputs VOH Output HIGH Voltage VDD - 0.3 VDD V IOH = -1mA VOL Output LOW Voltage VSS 0.4 V IOL = 2mA VIH Input HIGH Voltage VDD - 0.5 5.0 V VIL Input LOW Voltage 0 0.8 V II Input Leakage Current 100 A 0V< VIN < 5V (1) LVDS Inputs and Outputs VOCMLVDS Output Common-Mode Range 1.13 1.27 V Terminated 100 differential VODLVDS Output Swing 150 400 mV Single-ended, p-p Figure 11 mV Single-ended, p-p Figure 11. for RXCLK and TXCLK_SRC only when INTRLV=0, BUSMODE=0. VODLVDS Output Swing ROLVDS Output Driver Impedance VICMLVDS Input Common-Mode Range 0.2 2.2 V VIDLVDS Input Sensitivity 100 1200 mV RILVDS Input Termination Resistance 80 120 1.9 2.45 V 125 400 80 Guaranteed, but not tested Single-ended, p-p Figure 11 With 910, 5% resistor connected between IRSEL and VSS. CML Inputs and Outputs VOCMCML Output Common-Mode Range VODCML Output Swing ROCML Output Driver Impedance VICMCML Input Common-Mode Range VIDCML RICML 400 650 mV 100 1.59 1.94 V Input Sensitivity 70 900 mV Input Termination Resistance 80 120 VDD-1/2 V Single-ended, p-p Figure 11 Guaranteed, but not tested Single-ended, p-p Figure 11 With 910, 5% resistor connect between IRSEL and VSS. NOTE: (1) The 155/622MHz LVDS input receivers can handle most LVPECL signals. 14 of 28 G52346, Revision 4.6 September 2, 2003 Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com DC Characteristics VSC9180 Data Sheet Draft 8/15/03 VH One side of differential signal VCM V=VH-VL L NOTE: Diagram applies to all I/O swing specifications. Table 11: Internal Regulator (VDDN Supply) Parameters CFVDDN Description External filter capacitor Min Typ 4.7 Max Units Conditions 10 F Tantalum - VDDN to VSS 5 > CSR > 0.5 Max Units Conditions Table 12: Power Dissipation Parameters Description Min Typ IDD Power Supply Current from VDD 0.83 A PD Power Supply Dissipation (VDD = 2.65V) 2.2 W 15 of 28 G52346, Revision 4.6 September 2, 2003 Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com Figure 11: Single-Ended Peak-to-Peak Specifications VSC9180 Data Sheet Draft 8/15/03 Power Supply Voltage (VDD, VDDIO, VDDA) Potential to GND.........................................................-0.5V to +3.0V DC Input Voltage (LVDS/CML inputs)................................................................................. -0.5V to VDD + 0.5V DC Input Voltage (TTL inputs) ......................................................................................................... -0.5V to 5.0V DC Output Voltage (LVDS/CML outputs) ............................................................................ -0.5V to VDD + 0.5V DC Output Voltage (TTL outputs) ........................................................................................ -0.5V to VDD + 0.5V Output Current (TTL outputs) .................................................................................................................... 50mA Output Current (LVDS/CML outputs) ........................................................................................................ 50mA Case Temperature Under Bias ...................................................................................................... -55oC to +125oC Storage Temperature..................................................................................................................... -65oC to +150oC Electrostatic Discharge (Human Body Model) .............................................................................................. 500V NOTE: (1) Caution: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability. ELECTROSTATIC DISCHARGE This device can be damaged by ESD. Vitesse recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures may adversely affect reliability of the device. Recommended Operating Conditions Core Power Supply Voltage (VDD,VDDIO,VDDA) .....................................................................................+2.5V5% Operating Temperature Range(1) (T)................................................................................................. 0oC to 105oC NOTE: (1) Lower limit of specification is ambient temperature and upper limit is case temperature. 16 of 28 G52346, Revision 4.6 September 2, 2003 Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com Absolute Maximum Ratings(1) VSC9180 Data Sheet Draft 8/15/03 High-Speed CML Input Equivalent Circuit VDD VDD PAD R1 R2 VSS VSS 100 Ohms VDD VDD PAD R1 R2 VSS VSS Output Equivalent Circuit VDD VDD VDD VDD 54 54 PAD PAD VSS VSS 18mA VSS 17 of 28 G52346, Revision 4.6 September 2, 2003 Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com I/O Equivalent Circuits VSC9180 Data Sheet Draft 8/15/03 Standard (LVDS) VSC9180 + 50 - 50 100 + - Core + 250 250 LVDS Driver 50 100 50 + - LVDS Receiver Note: LVDS inputs are internally biased. 18 of 28 G52346, Revision 4.6 September 2, 2003 Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com Parallel Input/Output Termination Schemes September 2, 2003 TXDATA[5]- VSS TXDATA[1]- TXDATA[1]+ BERA LOLB VSSIO G F E D C B A TXDATA[9]- L TXDATA[6]+ TXDATA[10]+ M H VSS N VDDIO TXDATA[14]+ P J TXDATA[14]- R VSSIO INTRLV T 19 of 28 RXDATA[15]+ SEFA SEFB BERB TXDATA[0]+ TXDATA[3]+ TXDATA[3]- TXDATA[5]+ TXDATA[6]- TXDATA[8]+ TXDATA[10]- TXDATA[12]+ TXDATA[12]- TXDATA[15]- CLEAR CLK311MODE B1CALCEN 2 RXDATA[14]- WORKERR VSS RXLOA LOLA TXDATA[0]- TXDATA[2]- TXDATA[4]- TXDATA[7]- TXDATA[8]- TXDATA[11]+ TXDDATA[13]+ TXDATA[15]+ LINELOOP VDD BERSEL[2] BIAS 3 VSSIO VDDIO MULTBITERR PROTECTERR TXLOA VSSIO TXDATA[2]+ TXDATA[4]+ TXDATA[7]+ TXDATA[9]+ TXDATA[11]- TXDATA[13]- VDD VSS BERSEL[1] EQUALEN TSTCNTRL[2] 4 RXDATA[12]- VDDIO RXDATA[14]+ RXDATA[15]- BERSEL[0] FRALIGNRST TSTCNTRL[0] VDD 5 VDDIO RXDATA[12]+ RXDATA[13]- RADATA[13]+ VSS TSTCNTRL[1] FPOUT- RXCLK+ 6 RXDATA[10]+ RXDATA[11]- RXDATA[11]+ VSSIO VSSIO FPOUT+ VDDIO VDDN 7 PLLFST VDD VDD VSS 9 TXCLK+ TXCLK- VDDIO REFCLK- 10 RXDATA[9]- RXDATA[9]+ VSSIO RXDATA[10]- VDDIO VSSIO RXDATA[8]+ RXDATA[8]- RXDATA[7]+ VDDIO RXDATA[6]+ RXDATA[6]- NOT POPULATED (Bottom View) RXCLK- VSSIO VDDA VSSA 8 RXDATA[7]- RXDATA[5]+ VDDIO RXDATA[4]+ TXCLK_SRC- TXCLK_SRC+ VSSIO REFCLK+ 11 VSSIO RXDATA[5]- RXDATA[3]+ VDDIO VDDIO VSSIO 12 RXDATA[4]- RXDATA[3]- VSSIO RXDATA[1]- VSSIO TXOUTB+ 13 VSSIO RXDATA[2]- VDDIO VDD TXSTSTB SCRAMIN_EN RXSTSTA VDD LOLPHCHGEN TSTINTB VDDIO VDDIO VDDIO TXOUTB- 14 RXDATA[1]+ RXDATA[0]- RESET_b FIFOSEL ENCODER_EN PASSTOH LFSELAB[0] REFSEL VDDNEXT IRSEL BUSMODE VSS VDDIO TXOUTA+ 16 CHSEL TXSTSTA USEDATA SCRAMOUT_EN FRALIGNRSTSEL PREEMPEN RATE[0] LCK2REFB LCK2REFA VDD RXINA- RXINA+ VSSIO RXINB- RXINB+ VSSIO TXOUTA- 17 Figure 12: 195 BGA Diagram--Bottom View Draft 8/15/03 RXDATA[2]+ RXDATA[0]+ VSSIO SEFCNTRL USEECDATA VSS LFSELAB[1] VSS WRAP TSTINTA TSTINTCS VDD PLLSLW VDDIO 15 Package Descriptions Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com G52346, Revision 4.6 K EQUIPLOOP U 1 VSC9180 Data Sheet VSC9180 Data Sheet Draft 8/15/03 Signal BGA Ball Name I/O Freq Level RESET_b C16 System Reset I TTL Low active asynchronous system reset. TTL When INTRLV = 0, BUSMODE = 0, TXDATA[3:0] and RXDATA[3:0] contain valid 4-bit parallel 622Mb/s data. When INTRLV = 0, BUSMODE = 1, TXDATA[15:0] and RXDATA[15:0] contain valid 16-bit parallel 155Mb/s data. TTL When INTRLV = 0, TXDATA and RXDATA contain parallel bit-multiplexed SONET/SDH data. When INTRLV = 1, TXDATA[3:0] and RXDATA[3:0] contain 4 serial STS-12/STM-4 signals of byte-interleaved data. BUSMODE INTRLV L16 4-Bit/16-Bit Parallel Bus Mode T1 Interleave Serial/Parallel Bus Mode I I Description CLK311MODE T2 311MHz Clock Mode I TTL When CLK311MODE = 1, RXCLK and TXCLK_SRC are set to 311MHz instead of 622MHz when INTRL = 1. TXDATA[3:0] is still 622Mb/s with a valid bit on both rising and falling edges of TXCLK. PREEMPEN F17 Pre-Emphasis Enable I TTL When Preempen=0, pre-emphasis on TXOUTA/B is disabled. When Preempen=1, pre-emphasis is enabled. RATE[0] G17 Multi-Rate Selection I TTL NOT SUPPORTED. Tie to logic 0. WRAP J15 G.709 Frame Mode I TTL When WRAP = 1, framing for G.709 signals is performed instead of SONET/SDH framing. CLEAR R2 Non-SONET/SDH Mode I TTL CLEAR = 1 is no longer supported. Set CLEAR=0. TTL Determines the number of consecutive errored frame boundaries that must occur for SEFA/B to be asserted when "in frame." When SEFCNTRL = 0, the number of frame boundaries is 2. When SEFCNTRL = 1, the number of frame boundaries is 4. D15 Severely Errored Frame Control B1CALCEN U2 B1 Calculation/ Insertion Enable I TTL A logic 1 enables calculation and insertion of the B1 byte for STS-48/STM-16 to STS-12/STM-4 and STS12/STM-4 to STS-48/STM-16 conversions (INTRLV = 1, EQUIPLOOP = 0, LINELOOP = 0). BERSEL[2] T3 BERSEL[1] R4 Bit Error Rate Selection I TTL BERSEL[0] P5 These inputs determine the characteristics of the bit error rate calculation logic. The settings are described in Table 2. TTL When EQUIPLOOP = 1, data from TXDATA is taken after deskew and phase alignment have been accomplished and looped back out on RXDATA with accompanying clock on RXCLK (B1CALCEN = X). RXIN must be frequency locked to REFCLK or LCK2REF must be used. SEFCNTRL EQUIPLOOP U1 Parallel Loopback Control I I 20 of 28 G52346, Revision 4.6 September 2, 2003 Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com Table 13: Package Ball Identification VSC9180 Data Sheet FRALIGNRST CHSEL LCK2REFA LCK2REFB LFSELAB[1] Name P3 Serial Loopback Control R5 Frame Alignment Centering Reset A17 Input A/B Channel Select J17 Lock To Reference Channel A H17 Lock To Reference Channel B I/O I I I I I Freq Level Description TTL When LINELOOP = 1, data from the selected channel of RXINA/B is taken after frame alignment has been accomplished and looped back out TXOUTA/B (B1CALCEN = X). TTL A logic 1 causes frame alignment FIFO's to be centered allowing alignment of maximum channel skew (+/- 75ns). When FRALIGNRSTSEL = 01, FRALIGNRST resets both selected and unselected channel alignment FIFOs (normal operation). When FRALIGNRSTSEL = 1, FRALIGNRST resets only the unselected channel alignment FIFO. TTL Selects which input channel, RXINA or RXINB, is used to provide output data on RXDATA. CHSEL = 0 selects channel A, CHSEL = 1 selects channel B. Internally, channel switching may occur up to 18, 155MHz clock periods later, as this signal is synchronized to the channel alignment process. Transparent, error-free switching occurs only when RXLOA = 0. TTL When LCK2REFA = 1, the channel A CDR will lock to the reference clock and no longer adjust its phase in an attempt to capture channel A data. This should be used when channel A is non-operational. TTL When LCK2REFB = 1, the channel B CDR will lock to the reference clock and no longer adjust its phase in an attempt to capture channel B data. This should be used when channel B is non-operational. Loop Filter Select Channels A/B I TTL Adjusts the digital loop filters of the CDRs for input channels A and B together. 00 - slightly underdamped 01 - critically damped 10(1) - slightly overdamped (recommended default) 11 - undefined Note: Higher frequency jitter on RXIN may be handled better by lower settings. G15 LFSELAB[0] G16 LOLPHCHGEN J14 Loss of Lock Phase Change Enable I TTL A logic 1 allows the use of phase change information to be used to determine loss of lock. Recommended default = 1.(1) LOLA E3 Loss Of Lock Channel A O TTL A logic 1 indicates an inability of the channel A CDR to reach lock, for channel A, generally due to out of spec input data signals. LOLB B1 Loss Of Lock Channel B O TTL A logic 1 indicates an inability of the CDR to reach lock for channel B, generally due to out of spec input data signals. 21 of 28 G52346, Revision 4.6 September 2, 2003 Draft 8/15/03 LINELOOP BGA Ball Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com Signal Signal SEFA SEFB BERA BERB RXLOA BGA Ball B2 C2 C1 D2 D3 Name Severely Errored Frame Channel A Severely Errored Frame Channel B Bit Error Rate Channel A Bit Error Rate Alarm Channel B Loss Of A/B Channel Alignment I/O O O O O O Freq Level Description TTL A logic 1 indicates a failure to reach or maintain "in frame" status on input data for channel A. "In frame" status is achieved, and SEFA de-asserted, after 2 consecutive valid frame boundaries have been observed. SEFA is asserted after 2 or 4 (see SEFCNTRL) consecutive errored frame boundaries have occurred. TTL A logic 1 indicates a failure to reach or maintain "in frame" status on input data for channel B. "In frame" status is achieved, and SEFB de-asserted, after 2 consecutive valid frame boundaries have been observed. SEFB is asserted after 2 or 4 consecutive (see SEFCNTRL) errored frame boundaries have occurred. TTL A logic 1 indicates that the bit error rate of channel A has reached the trigger level as determined by the setting of the BERSEL inputs. Once asserted, the bit error rate must fall below the cancel level as determined by the setting of the BERSEL inputs before this signal is deasserted. TTL A logic 1 indicates that the bit error rate of channel B has reached the trigger level as determined by the setting of the BERSEL inputs. Once asserted, the bit error rate must fall below the cancel level as determined by the setting of the BERSEL inputs before this signal is deasserted. TTL A logic 1 indicates that alignment between the frame boundaries on channels A and B cannot be achieved. This may be due to asynchronous A/B channels or channel skew larger than +/-75ns. RXLOA is automatically asserted when either LOL or SEF conditions exist on either channel. PASSTOH F16 I TTL Vitesse test mode - Tie to logic 0. ENCODER_EN E16 I TTL Vitesse test mode - Tie to logic 0. SCRAMIN_EN F14 I TTL Vitesse test mode - Tie to logic 0. SCRAMOUT_EN D17 I TTL Vitesse test mode - Tie to logic 0. USEDATA C17 I TTL Vitesse test mode - Tie to logic 1. USEECDATA E15 I TTL Vitesse test mode - Tie to logic 0. WORKERR B3 O TTL Vitesse test mode. Leave unconnected. PROTECTERR D4 O TTL Vitesse test mode. Leave unconnected. MULTBITERR C4 O TTL Vitesse test mode. Leave unconnected. TTL A logic 1 enables cable equalization for RXINA and RXINB. Cable equalization increases the amplification for single bit data to improve signal detection for long cables. EQUALEN should be set to 1 when driving serial signals over long cables (1-2 meters) or over backplane traces. EQUALEN T4 Cable Equalization Enable I 22 of 28 G52346, Revision 4.6 September 2, 2003 Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com Draft 8/15/03 VSC9180 Data Sheet VSC9180 Data Sheet RXINA+/- RXINB+/- FPOUT+/- U3 CML Input BIAS M17,L17(2) R17, P17(2) R7, T6 Name (2) RXDATA[15]+/- A2, D5(2) RXDATA[14]+/- C5, A3(2) RXDATA[13]+/- D6, C6(2) RXDATA[12]+/- B6, A5(2) RXDATA[11]+/- C7, B7(2) RXDATA[10]+/- A7, D8(2) RXDATA[9]+/- B8, A8(2) RXDATA[8]+/- C9, D9(2) RXDATA[7]+/- A10, A11(2) RXDATA[6]+/- C10, D10(2) RXDATA[5]+/- B11, B12(2) RXDATA[4]+/- D11, A13(2) RXDATA[3]+/- C12, B13(2) RXDATA[2]+/- A15, B14(2) RXDATA[1]+/- A16, D13(2) RXDATA[0]+/- B15, B16(2) Serial 2.5Gb/s Data Inputs Channel A Serial 2.5Gb/s Data Inputs Channel B Frame Pointer Output Freq Level Description Analog When BIAS is connected to VSS the input differential threshold of RXINA and RXINB is set to the 100-200mV range. Increasing the voltage level on this input from VSS to VDD will cause the threshold to first decrease to a minimum and then increase to a maximum. The relationship between the voltage on this input and the differential threshold is not available. Recommended default = VSS.(1) 2.5Gb/s CML Serial 2.5 Gb/s data input for channel A. Signals must be frequency synchronous to within +/-40ppm of REFCLK. When used with channel B as a protection or working channel for hitless switching, frames must be aligned to channel B to within +/75ns. I 2.5Gb/s CML Serial 2.5 Gb/s data input for channel B. Signals must be frequency synchronous to within +/-40ppm of REFCLK. When used with channel A as a protection or working channel for hitless switching, frames must be aligned to channel A to within +/75ns. O 155/ 622Mb/s LVDS The rising edge of FPOUT+ is coincident with the first data word/bits of frames output on RXDATA. Once asserted (high), it remains high for 4, 155MHz clock periods. I/O I I Parallel/Serial Output Bus 155Mb/s LVDS O 155/ 622Mb/s LVDS 23 of 28 G52346, Revision 4.6 September 2, 2003 When INTRLV = 0, BUSMODE = 1, incoming serial data from the selected A/B channel is bit demultiplexed directly to form a 16-bit parallel word on this bus. When INTRLV = 0, BUSMODE = 0, incoming serial data from the selected A/B channel is bit demultiplexed directly to form a 4-bit parallel word on bits [3:0] of this bus. When INTRLV = 1, incoming serial data from the selected A/B channel is byte de-multiplexed to create 4, STS-12/STM-4 serial output channels on bits [3:0]. Draft 8/15/03 BIAS BGA Ball Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com Signal Signal BGA Ball Name I/O Freq Level Description 155/311/ 622MHz LVDS Output clock for RXDATA. Falling edge of RXCLK+ is centered in output data eye. When INTRLV = 1, the clock frequency is 622MHz (CLK311MODE = 0) or 311MHz (CLK311MODE = 1). When INTRLV = 0, BUSMODE = 1, the clock frequency is 155MHz. When INTRLV = 0, BUSMODE = 0, the clock frequency is 622MHz TTL A logic 1 indicates that alignment between the frame boundaries of the 4 serial, STS-12/ STM-4 channels on TXDATA[3:0] cannot be achieved. This may be due to the serial channels being asynchronous with respect to REFCLK or channel skew larger than +/-3 byte times. U6, P8(2) Parallel Output Clock TXLOA E4 Loss Of Serial STS-12/ STM-4 Channel Alignment TXDATA[15]+/- N3, P2(2) TXDATA[14]+/- P1, R1(2) TXDATA[13]+/- M3, M4(2) TXDATA[12]+/- M2, N2(2) TXDATA[11]+/- L3, L4(2) TXDATA[10]+/- M1, L2(2) TXDATA[9]+/- K4, L1(2) TXDATA[8]+/- K2, K3(2) TXDATA[7]+/- J4, J3(2) TXDATA[6]+/- H1, J2(2) TXDATA[5]+/- H2, G1(2) TXDATA[4]+/- H4, H3(2) TXDATA[3]+/- F2, G2(2) TXDATA[2]+/- G4, G3(2) TXDATA[1]+/- D1, E1(2) TXDATA[0]+/- E2, F3(2) TXCLK+/- P10, R10(2) Parallel Input Bus Clock I 155/311/ 622Mb/s LVDS Input clock, synchronous with parallel input data bus TXDATA. The rising edge of TXCLK+ is used to sample data on TXDATA. TXCLK_SRC+/- R11, P11(2) Source Synchronous Timing Reference O 155/311/ 622Mb/s LVDS This output clock provides external devices with a clock to be used in driving TXDATA and TXCLK to insure that they are synchronous with REFCLK. TXOUTA+/- U16, U17(2) O 2.5Gb/s CML Serial 2.5Gb/s data output for channel A. Serial data is the result of the bit or byte multiplexing of the input data on TXDATA. Channels A and B are identical. TXOUTB+/- U13, U14(2) O 2.5Gb/s CML Serial 2.5Gb/s data output for channel B. Serial data is the result of the bit or byte multiplexing of the input data on TXDATA. Channels A and B are identical. RXCLK+/- O O Parallel/Serial Input Bus 155Mb/s LVDS I When INTRLV = 0, BUSMODE = 1, this bus contains 16-bit parallel data that will be bit multiplexed for output on TXOUTA/B. When INTRLV = 0, BUSMODE = 0, bits [3:0] of this bus contains 4-bit, parallel data that will be bit multiplexed for output on TXOUTA/B. When INTRLV = 1, data on bits [3:0] of this bus are 4, STS-12/ STM-4 serial data channels. These serial data channels can be skewed from each other as much as +/-3 byte times and will be aligned together before being byte multiplexed for output on TXOUTA/B. 155/ 622Mb/s LVDS Serial 2.5Gb/s Data Outputs Channel A Serial 2.5Gb/s Data Outputs Channel B 24 of 28 G52346, Revision 4.6 September 2, 2003 Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com Draft 8/15/03 VSC9180 Data Sheet VSC9180 Data Sheet REFCLK+/- Name H16 Reference Clock Select U11, U10(2) PLLFST P9 PLLSLW R15 IRSEL K16 TSTCNTRL[2] U4 TSTCNTRL[1] R6 TSTCNTRL[0] T5 RXSTSTA G14 FRALIGNRSTSEL E17 PLL Reference Clock I/O Freq Level I TTL I 78/ 155MHz LVDS PLL Capacitor LVDS/CML Input Impedance Reference Resistor Description A logic 1 indicates that a nominal 78MHz PLL reference clock is being used. A logic 0 indicates that a nominal 155MHz PLL reference clock is being used. Fixed frequency reference for PLL operation. Frequency must be synchronous to within +/-40ppm of incoming data on RXINA/B. Frequency can be either nominal 78MHz or nominal 155MHz as indicated by REFSEL. Analog Capacitor for PLL operation. 0.1F between PLLFST and PLLSLW Analog Reference resistor to set input resistance for LVDS/ CML inputs within 20% tolerance. Resistor must be 8.8 times desired input impedance, with 5% tolerance, and connected to Vss. For example, a 1K resistor results in 113 input impedance, and a 910 resistor results in 103 input impedance. Test Control I TTL Test control. Tie all bits to logic 0. Test Input I TTL Reserved for future use (selectable to a logic 1 or 0). Set to logic 0. TTL When FRALIGNRSTSEL=01, FRALIGNRST resets both selected and unselected channel alignment FIFOs (normal operation). When FRALIGNRSTSEL=1, FRALIGNRST resets only the unselected channel alignment FIFO. TTL When FIFOSEL=0, the VSC9180 will deskew incoming 2.5Gb/s signals up to +/- 75ns. When FIFOSEL=1, the deskew limit will increase to greater than +/- 75ns. In addition, the Input to Output Delays as specified in Table 8 will also increase. FRALIGNRST select FIFOSEL D16 FIFO select I I TXSTSTA B17 Test Output O TTL Test output. Must be left unconnected. TXSTSTB E14 Test Output O TTL Test output. Must be left unconnected. TSTINTA K15 Test Output O Analog Test output. Must be left unconnected. TSTINTB K14 Test Output O Analog Test output. Must be left unconnected. TSTINTCS L15 Test Output O Analog Test output. Must be left unconnected. VDDNEXT J16 External 1.8V Supply Enable I TTL Test only tie to logic 0. VDDN U7 Internal 1.8V Supply PWR Capacitor for internal voltage regulator filter. Connect from VDDN to VSS. PWR Main 2.5V supply that powers internal logic. VDD D14, H14, K17, M15, 2.5V Power Supply N4, R3, R9, T9, U5 25 of 28 G52346, Revision 4.6 September 2, 2003 Draft 8/15/03 REFSEL BGA Ball Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com Signal Signal BGA Ball Name VDDIO A6, A9, B4, B5, B10, C11, C14, D12, J1, L14, P14, R16, T7, T10, T12, T14, U15 2.5V Power Supply PWR Main 2.5V supply that powers I/Os. VSS C3, F1, F15, H15, M16, N1, P4, P6, U9 0V Ground Supply PWR Main 0.0V supply for ground reference for internal logic. VSSIO A1, A4, A12, A14, B9, C8, C13, C15, D7, F4, K1, N17, P7, R8, R13, T11, T17, U12 0V Ground Supply PWR Main 0.0V supply for ground reference for I/Os. VDDA T8 2.5V Analog Power Supply PWR 2.5V isolated supply. VSSA U8 0V Analog Ground Supply PWR 0.0V isolated supply for analog ground reference. I/O Freq Level Description NOTES:(1) Designs using the VSC9180 should allow these signals to be adjusted for optimal settings. (2) In the Signal column, polarity is reflected in the BGA Ball column respectively, (A2, D5). Example A2 = (+) signal, D5 = (-) signal. Moisture Sensitivity Level The VSC9180 is rated moisture sensitivity level 3 or better as specified in JEDEC standard IPC/JEDEC J-STD-020B. For more information, see the JEDEC standard. Thermal Specifications Thermal specifications for this device are based on the JEDEC standard EIA/JESD51-2 and have been modeled using a four-layer test board with two signal layers, a power plane, and a ground plane (2s2p PCB). For more information, see the JEDEC standard. Table 14. Thermal Resistances JA (C/W) vs. Airflow (ft/min) Part Number VSC9180UV JC 0 100 200 1.7 17.3 14.6 13.0 26 of 28 G52346, Revision 4.6 September 2, 2003 Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com Draft 8/15/03 VSC9180 Data Sheet VSC9180 Data Sheet Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com Draft 8/15/03 Package Information - 195 BGA 27 of 28 G52346, Revision 4.6 September 2, 2003 ORDERING INFORMATION VSC9180 Serial 2.5Gb/s Hitless Sonet/SDH Backplane Transceiver Part Number Description VSC9180UV 23mm,195 BGA Temperature Range: 0C ambient to 105C case CORPORATE HEADQUARTERS Vitesse Semiconductor Corporation 741 Calle Plano Camarillo, CA 93012 Tel: 1-800-VITESSE FAX:1-(805) 987-5896 * For application support, latest technical literature, and locations of sales offices, please visit our web site at www.vitesse.com Copyright (c) 2002-2003 by Vitesse Semiconductor Corporation PRINTED IN THE U.S.A Vitesse Semiconductor Corporation ("Vitesse") retains the right to make changes to its products or specifications to improve performance, reliability or manufacturability. All information in this document, including descriptions of features, functions, performance, technical specifications and availability, is subject to change without notice at any time. While the information furnished herein is held to be accurate and reliable, no responsibility will be assumed by Vitesse for its use. Furthermore, the information contained herein does not convey to the purchaser of microelectronic devices any license under the patent right of any manufacturer. Vitesse products are not intended for use in life support products where failure of a Vitesse product could reasonably be expected to result in death or personal injury. Anyone using a Vitesse product in such an application without express written consent of an officer of Vitesse does so at their own risk, and agrees to fully indemnify Vitesse for any damages that may result from such use or sale. Vitesse Semiconductor Corporation is a registered trademark. All other products or service names used in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other trademarks or registered trademarks mentioned herein are the property of their respective holders. 28 of 28 G52346, Revision 4.6 September 2, 2003 Downloaded by YASSER_MOHAMMAD@SILICONEXPERT.COM on July 9, 2008 from Vitesse.com Draft 8/15/03 VSC9180 Data Sheet