UT54ACS165E Radiation-Hardened 8-Bit Parallel Shift Registers December 2003 www.aeroflex.com/radhard FUNCTION TABLE FEATURES * * * * * * * * * * Complementary outputs Direct overriding load (data) inputs Gated clock inputs Parallel-to-serial data conversions 0.6m CRH CMOS Process - Latchup immune High speed Low power consumption Wide operating power supply from 3.0V to 5.5V Available QML Q or V processes 16-lead flatpack INPUTS INTERNAL OUTPUTS OUTPUTS SH/ CLK CLK SER PARALLEL LD INH A ... H QA QB QH QH X L X L X X a ... h X a QA b QB h QH QH H L H X H QA QG QG H L L X L QA QG QG H H X X X QA QB QH QH Note: 1. Qn = The state of the referenced output one setup time prior to the Low-toHigh clock transition. DESCRIPTION The UT54ACS165E is an 8-bit serial shift register that, when clocked, shifts the data toward serial output QH. Parallel-in access to each stage is provided by eight individual data inputs that are enabled by a low level at the SH/LD input. The devices feature a clock inhibit function and a complemented serial output QH . Clocking is accomplished by a low-to-high transition of the CLK input while SH/LD is held high and CLK INH is held low. The functions of the CLK and CLK INH (clock inhibit) inputs are interchangeable. Since a low CLK input and a low-to-high transition of CLK INH will also accomplish clocking, CLK INH should be changed to the high level only while the CLK input is high. Parallel loading is disabled when SH/LD is held high. Parallel inputs to the registers are enabled while SH/LD is low independently of the levels of CLK, CLK INH or SER inputs. LOGIC SYMBOL The device is characterized over the full military temperature range of -55C to +125C. (1) SH/LD (15) CLK INH (2) CLK PINOUT (10) SER (11) A (12) B (13) C (14) D (3) E (4) F (5) G (6) H 16-Lead Flatpack Top View SH/LD 1 16 VDD CLK 2 15 CLK INH E 3 14 D F G 4 5 13 12 C H QH 6 11 A 7 8 10 9 SER QH VSS h L H B SRG8 C1 (LOAD) 1 C2/ 2D 1D 1D 1D (9) Q (7) H QH Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 1 LOGIC DIAGRAM A B (11) SH/LD CLK INH CLK SER C (12) D (13) E (14) F (3) (1) G (4) H (5) (6) (15) (2) (10) S S S S S S S S C C C C C C C C (9) D QA D QB DQ D QD D QE D QF D QG (7) D QH R R R R R R R R C RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. 2 QH QH ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD + .3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C JC Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 3.0 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C 3 DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS165E7 ( VDD = 3.0V to 5.5V; VSS = 0V6; -55C < TC < +125C) SYMBOL VIL VIH IIN VOL VOH IOS IOL IOH Description CONDITION Low-level input voltage 1 High-level input voltage 1 VDD MAX UNIT 3.0V 0.9 V 5.5V 1.65 3.0V 2.1 5.5V 3.85 -1 A 3.0V 0.25 V 4.5V 0.25 VIN = VDD or VSS 5.5V Low-level output voltage 3 IOL = 100A Short-circuit output current 2 ,4 Low level output current9 High level output current9 IOH = -100A V 1 Input leakage current High-level output voltage 3 MIN 3.0V 2.75 4.5V 4.25 3.0V -100 100 5.5V -200 200 VIN = VDD or VSS 3.0V 6 VOL = 0.4V 5.5V 8 VIN = VDD or VSS 3.0V -6 VOH = VDD-0.4V 5.5V -8 VO = VDD and VSS V mA mA mA Ptotal Power dissipation 2, 8 CL = 50pF 5.5V 2.9 mW/ MHz IDDQ Quiescent Supply Current VIN = VDD or VSS 5.5V 10 A CIN Input capacitance 5 = 1MHz 0V 15 pF Output capacitance 5 = 1MHz 0V 15 pF COUT Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/ MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition B. 8. Power dissipation specified per switching output. 9. This value is guaranteed based on characterization data, but not tested. 4 AC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS165E2 (VDD = 3.0V to 5.5V; VSS = 0V 1, -55C < TC < +125C) SYMBOL PARAMETER CONDITION VDD tPLH1 CLK or CLKINH to QH or QH CL = 30pF 3.0V & 3.6V CL = 50pF tPHL1 CLK or CLKINH to QH or QH CL = 30pF CL = 50pF tPLH2 SH/LD to QH or QH CL = 30pF CL = 50pF tPHL2 SH/LD to QH or QH CL = 30pF CL = 50pF tPLH3 H to QH CL = 30pF CL = 50pF tPHL3 H to QH CL = 30pF CL = 50pF tPLH4 H to QH CL = 30pF CL = 50pF tPLH4 H to QH CL = 30pF CL = 50pF 5 MINIMUM MAXIMUM UNIT 2 18 ns 4.5V & 5.5V 2 14 3.0V & 3.6V 2 22 4.5V & 5.5V 2 18 3.0V & 3.6V 2 21 4.5V & 5.5V 2 17 3.0V & 3.6V 2 25 4.5V & 5.5V 2 21 3.0V & 3.6V 2 18 4.5V & 5.5V 2 14 3.0V & 3.6V 2 22 4.5V & 5.5V 2 18 3.0V & 3.6V 2 21 4.5V & 5.5V 2 17 3.0V & 3.6V 2 25 4.5V & 5.5V 2 21 3.0V & 3.6V 2 17 4.5V & 5.5V 2 13 3.0V & 3.6V 2 21 4.5V & 5.5V 2 17 3.0V & 3.6V 2 21 4.5V & 5.5V 2 17 3.0V & 3.6V 2 25 4.5V & 5.5V 2 21 3.0V & 3.6V 2 18 4.5V & 5.5V 2 14 3.0V & 3.6V 2 22 4.5V & 5.5V 2 18 3.0V & 3.6V 2 20 4.5V & 5.5V 2 16 3.0V & 3.6V 2 24 4.5V & 5.5V 2 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL PARAMETER CONDITION VDD MINIMUM MAXIMUM UNIT 71 MHz fMAX Maximum clock frequency CL = 50pF 3.0V, 4.5V, and 5.5V tSU1 SER, SH/LD, CLKINH or CLK Setup time before CLK or CLKINH CL = 50pF 3.0V, 4.5V, and 5.5V 7 ns tSU2 Data setup time before SH/LD CL = 50pF 3.0V, 4.5V, and 5.5V 7 ns tH1 SER hold time after CLK or CLKINH CL = 50pF 3.0V, 4.5V, and 5.5V 2 ns tH2 CLKINH hold time after CLK CL = 50pF 3.0V, 4.5V, and 5.5V 2 ns tH33 Hold time for any input after SH/LD CL = 50pF 3.0V, 4.5V, and 5.5V 2 ns Minimum pulse width CLK or CLKINH high CLK or CLKINH low SH/LD CL = 50pF 3.0V, 4.5V, and 5.5V 7 ns tW Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition B. 3. Based on characterization, hold time (tH3) of 0ns for data pins A-H, can be assumed if data setup time (tSU2) is >10ns. This is guaranteed, but not tested. 6 Packaging 7 Ordering Information UT54ACS165E UT54 *** **** - * * * Lead Finish: (Notes 1 & 2) A = Solder C = Gold X = Optional Screening: (Note 3) C = Military Temperature Range (-55oC to +125oC) Package Type: U = 16-lead ceramic bottom-brazed dual-in-line Flatpack Part Number: 165E = 8-Bit Parallel Shift Registers I/O Type: ACS = CMOS compatible I/O level Notes: 1. Lead finish (A, C, or X) must be specified. 2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Military Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices have 48 hours of burn-in and are test at -55oC, room temperature, and 125oC. Radiation characterisitics are neither tested nor guaranteed and may not be specified. 8 UT54ACS165E: SMD 5962 * ***** ** * * * Lead Finish: (Notes 1 & 2) A = Solder C = Gold X = Optional Package Type: X = 16-lead ceramic bottom-brazed dual-in-line Flatpack Class Designator: Q = QML Class Q V = QML Class V Device Type: 02 = TID per MIL-STD-883 TM1019 Condition B 03 = TID per MIL-STD-883 TM1019 Condition A Drawing Number: 96558 = UT54ACS165E Total Dose: (Notes 3 & 4) R = 1E5 rads(Si) F = 3E5 rads(Si) G = 5E5 rads(Si) H = 1E6 rads(Si) Notes: 1. Lead finish (A, C, or X) must be specified. 2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Total dose radiation must be specified when ordering. QML V is not available without radiation testing. 4. Total dose tolerance of 1E6 rads(Si) is only available for Device Type 02. 9 COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com Aeroflex Colorado Springs (Aeroflex) reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. 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