FEATURES FUNCTIONAL BLOCK DIAGRAM VDD GND VREF AD5696R/AD5695R/AD5694R VLOGIC INPUT REGISTER DAC REGISTER 2.5V REFERENCE STRING DAC A SCL VOUTA BUFFER INTERFACE LOGIC High relative accuracy (INL): 2 LSB maximum at 16 bits Low drift 2.5 V reference: 2 ppm/C typical Tiny package: 3 mm x 3 mm, 16-lead LFCSP Total unadjusted error (TUE): 0.1% of FSR maximum Offset error: 1.5 mV maximum Gain error: 0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic compatibility Low glitch: 0.5 nV-sec 400 kHz I2C-compatible serial interface Low power: 3.3 mW at 3 V 2.7 V to 5.5 V power supply -40C to +105C temperature range SDA A1 A0 INPUT REGISTER DAC REGISTER STRING DAC B VOUTB BUFFER INPUT REGISTER DAC REGISTER STRING DAC C VOUTC BUFFER INPUT REGISTER DAC REGISTER STRING DAC D VOUTD BUFFER APPLICATIONS LDAC RESET POWER-ON RESET GAIN = x1/x2 RSTSEL GAIN POWERDOWN LOGIC 10486-001 Data Sheet Quad 16-/14-/12-Bit nanoDAC+ with 2 ppm/C Reference, I2C Interface AD5696R/AD5695R/AD5694R Figure 1. Optical transceivers Base-station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems GENERAL DESCRIPTION The AD5696R/AD5695R/AD5694R family are low power, quad, 16-/14-/12-bit buffered voltage output DACs. The devices include a 2.5 V, 2 ppm/C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). All devices operate from a single 2.7 V to 5.5 V supply, are guaranteed monotonic by design, and exhibit less than 0.1% FSR gain error and 1.5 mV offset error performance. The devices are available in a 3 mm x 3 mm LFCSP and a TSSOP package. The AD5696R/AD5695R/AD5694R also incorporate a poweron reset circuit and a RSTSEL pin that ensures that the DAC outputs power up to zero scale or midscale and remain there until a valid write takes place. Each part contains a per-channel power-down feature that reduces the current consumption of the device to 4 A at 3 V while in power-down mode. The AD5696R/AD5695R/AD5694R use a versatile 2-wire serial interface that operates at clock rates up to 400 kHz, and includes a VLOGIC pin intended for 1.8 V/3 V/5 V logic. Rev. D Table 1. Quad nanoDAC+ Devices Interface SPI I2 C Reference Internal External Internal External 16-Bit AD5686R AD5686 AD5696R AD5696 14-Bit AD5685R AD5695R 12-Bit AD5684R AD5684 AD5694R AD5694 PRODUCT HIGHLIGHTS 1. 2. 3. High Relative Accuracy (INL). AD5696R (16-bit): 2 LSB maximum. AD5695R (14-bit): 1 LSB maximum. AD5694R (12-bit): 1 LSB maximum. Low Drift 2.5 V On-Chip Reference. 2 ppm/C typical temperature coefficient. 5 ppm/C maximum temperature coefficient. Two Package Options. 3 mm x 3 mm, 16-lead LFCSP. 16-lead TSSOP. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2012-2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5696R/AD5695R/AD5694R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Operation ......................................................................... 21 Applications ....................................................................................... 1 Write Operation.......................................................................... 21 Functional Block Diagram .............................................................. 1 Read Operation........................................................................... 22 General Description ......................................................................... 1 Multiple DAC Readback Sequence .......................................... 22 Product Highlights ........................................................................... 1 Power-Down Operation ............................................................ 23 Revision History ............................................................................... 2 Load DAC (Hardware LDAC Pin) ........................................... 24 Specifications..................................................................................... 3 LDAC Mask Register ................................................................. 24 AC Characteristics........................................................................ 5 Hardware Reset (RESET) .......................................................... 25 Timing Characteristics ................................................................ 6 Reset Select Pin (RSTSEL) ........................................................ 25 Absolute Maximum Ratings............................................................ 7 Internal Reference Setup ........................................................... 25 ESD Caution .................................................................................. 7 Solder Heat Reflow..................................................................... 25 Pin Configuration and Function Descriptions ............................. 8 Long-Term Temperature Drift ................................................. 25 Typical Performance Characteristics ............................................. 9 Thermal Hysteresis .................................................................... 26 Terminology .................................................................................... 16 Applications Information .............................................................. 27 Theory of Operation ...................................................................... 18 Microprocessor Interfacing ....................................................... 27 Digital-to-Analog Converter .................................................... 18 AD5696R/AD5695R/AD5694R to ADSP-BF531 Interface .... 27 Transfer Function ....................................................................... 18 Layout Guidelines....................................................................... 27 DAC Architecture ....................................................................... 18 Galvanically Isolated Interface ................................................. 27 Serial Interface ............................................................................ 19 Outline Dimensions ....................................................................... 28 Write and Update Commands .................................................. 20 Ordering Guide .......................................................................... 29 REVISION HISTORY 4/2017--Rev. C to Rev. D Changes to Features Section............................................................ 1 Changes to Specifications Section .................................................. 3 Changes to VLOGIC Parameter, Table 1 ............................................ 4 Changes to AC Characteristics Section and Output Noise Spectral Density Parameter, Table 3 ............................................... 5 Changes to Timing Characteristics Section .................................. 6 Changes to Table 5 ............................................................................ 7 Changes to VLOGIC Pin Description and RESET Pin Description, Table 6 ................................................................................................ 8 Changes to Figure 18 to Figure 22................................................ 11 Changes to Figure 23 to Figure 26 and Figure 28 ...................... 12 Changes to Figure 29, Figure 32, and Figure 34 ......................... 13 Changes to Figure 39 and Figure 40............................................. 14 Changes to Figure 50 ...................................................................... 21 Changes to Figure 51 ...................................................................... 22 Changes to Hardware Reset (RESET) Section ............................ 25 Added Long-Term Temperature Drift Section and Figure 55; Renumbered Sequentially ................................................................... 25 Changes to Ordering Guide................................................................ 29 5/2014--Rev. B to Rev. C Deleted Long-Term Stability Drift Parameter, Table 1 .................4 Deleted Figure 8; Renumbered Sequentially .................................9 Changes to Read Operation Section and Figure 51 ................... 22 Deleted Long-Term Temperature Drift Section ......................... 25 6/2013--Rev. A to Rev. B Changes to Pin GAIN and Pin RSTSEL Descriptions; Table 6 ...8 11/2012--Rev. 0 to Rev. A Changes to Table 1.............................................................................1 Changes to Table 4.............................................................................6 Changes to Figure 10.........................................................................9 Changes to Figure 33...................................................................... 13 Changes to Serial Interface Section.............................................. 19 Changes to Figure 52...................................................................... 22 4/2012--Revision 0: Initial Version Rev. D | Page 2 of 29 Data Sheet AD5696R/AD5695R/AD5694R SPECIFICATIONS VDD = 2.7 V to 5.5 V; 1.62 V VLOGIC 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. RL = 2 k; CL = 200 pF. Table 2. Parameter STATIC PERFORMANCE2 AD5696R Resolution Relative Accuracy Differential Nonlinearity AD5695R Resolution Relative Accuracy Differential Nonlinearity AD5694R Resolution Relative Accuracy Differential Nonlinearity Zero-Code Error Offset Error Full-Scale Error Min A Grade1 Typ Max 16 Min B Grade1 Typ Max 16 2 2 8 8 1 14 1 1 4 1 12 0.5 LSB Gain = 2 Gain = 1 Guaranteed monotonic by design 1 1 Bits LSB LSB Guaranteed monotonic by design 12 1 1 Bits LSB LSB mV mV % of FSR % of FSR % of FSR % of FSR V/C 1 1 ppm Of FSR/C 0.15 0.15 mV/V DAC code = midscale; VDD = 5 V 10% 2 2 V 3 2 3 2 V/mA V Due to single channel, full-scale output change Due to load current change Due to powering down (per channel) 0.12 0.4 +0.1 +0.01 2 1 4 4 0.2 0.4 +0.1 +0.01 1 1 1.5 1.5 0.1 Gain Error 0.02 0.2 0.02 0.1 Total Unadjusted Error 0.01 0.25 0.01 0.1 0.12 0.25 Offset Error Drift3 Gain Temperature Coefficient3 DC Power Supply Rejection Ratio3 Bits LSB Test Conditions/Comments 2 3 1 14 0.5 Unit 0.2 Guaranteed monotonic by design All zeros loaded to DAC register All ones loaded to DAC register External reference; gain = 2; TSSOP Internal reference; gain = 1; TSSOP DC Crosstalk3 OUTPUT CHARACTERISTICS3 Output Voltage Range 0 0 Capacitive Load Stability Resistive Load4 Load Regulation Short-Circuit Current5 Load Impedance at Rails6 Power-Up Time VREF 2 x VREF 0 0 80 80 V V nF nF k V/mA 80 80 V/mA 40 25 2.5 40 25 2.5 mA s 2 10 1 VREF 2 x VREF 2 10 1 Rev. D | Page 3 of 29 Gain = 1 Gain = 2, see Figure 30 RL = RL = 1 k 5 V 10%, DAC code = midscale; -30 mA IOUT 30 mA 3 V 10%, DAC code = midscale; -20 mA IOUT 20 mA See Figure 30 Coming out of power-down mode; VDD = 5 V AD5696R/AD5695R/AD5694R Parameter REFERENCE OUTPUT Output Voltage7 Reference TC8, 9 Output Impedance3 Min A Grade1 Typ Max 2.4975 5 0.04 Output Voltage Noise3 Output Voltage Noise Density3 Data Sheet 2.5025 20 Min B Grade1 Typ Max 2.4975 2 0.04 12 12 240 240 2.5025 5 Unit Test Conditions/Comments V ppm/C At ambient See the Terminology section V p-p nV/Hz 0.1 Hz to 10 Hz At ambient; f = 10 kHz, CL = 10 nF Load Regulation Sourcing3 20 20 V/mA At ambient Load Regulation Sinking3 Output Current Load Capability3 40 40 At ambient 5 5 V/mA mA VDD 3 V Line Regulation3 3 Thermal Hysteresis LOGIC INPUTS3 Input Current VINL, Input Low Voltage VINH, Input High Voltage Pin Capacitance LOGIC OUTPUTS (SDA)3 Output Low Voltage, VOL Floating State Output Capacitance POWER REQUIREMENTS VLOGIC ILOGIC VDD VDD IDD Normal Mode10 All Power-Down Modes11 100 100 V/V At ambient 125 125 ppm First cycle 25 25 ppm Additional cycles 2 0.3 x VLOGIC A V V pF Per pin 0.4 V pF ISINK = 3 mA 5.5 3 5.5 5.5 V A V V 0.7 1.3 4 6 mA mA A A 2 0.3 x VLOGIC 0.7 x VLOGIC 0.7 x VLOGIC 2 2 0.4 4 1.62 4 5.5 3 5.5 5.5 2.7 VREF + 1.5 0.59 1.1 1 0.7 1.3 4 6 1.62 2.7 VREF + 1.5 0.59 1.1 1 1 Gain = 1 Gain = 2 VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V Internal reference off Internal reference on, at full scale -40C to +85C -40C to +105C Temperature range: A and B grade: -40C to +105C. DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 = VDD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280 (AD5696R), 64 to 16,320 (AD5695R), and 12 to 4080 (AD5694R). 3 Guaranteed by design and characterization; not production tested. 4 Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to 30 mA up to a junction temperature of 110C. 5 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded during current limit. Operation above the specified maximum operation junction temperature may impair device reliability. 6 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 typical channel resistance of the output devices. For example, when sinking 1 mA, the minimum output voltage = 25 x 1 mA = 25 mV (see Figure 30). 7 Initial accuracy presolder reflow is 750 V; output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section. 8 Reference is trimmed and tested at two temperatures and is characterized from -40C to +105C. 9 Reference temperature coefficient calculated as per the box method. See the Terminology section for further information. 10 Interface inactive. All DACs active. DAC outputs unloaded. 11 All DACs powered down. 2 Rev. D | Page 4 of 29 Data Sheet AD5696R/AD5695R/AD5694R AC CHARACTERISTICS VDD = 2.7 V to 5.5 V; RL = 2 k to GND; CL = 200 pF to GND; 1.62 V VLOGIC 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. 1 Table 3. Parameter 2 Output Voltage Settling Time AD5696R AD5695R AD5694R Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Total Harmonic Distortion 4 Output Noise Spectral Density Output Noise SNR SFDR SINAD Min Typ Max Unit Test Conditions/Comments 3 5 5 5 0.8 0.5 0.13 0.1 0.2 0.3 -80 300 8 8 7 s s s V/s nV-sec nV-sec nV-sec nV-sec nV-sec dB nV/Hz 1/4 to 3/4 scale settling to 2 LSB 1/4 to 3/4 scale settling to 2 LSB 1/4 to 3/4 scale settling to 2 LSB 6 90 83 80 V p-p dB dB dB Guaranteed by design and characterization; not production tested. See the Terminology section. 3 Temperature range is -40C to +105C, typical at 25C. 4 Digitally generated sine wave at 1 kHz. 1 2 Rev. D | Page 5 of 29 1 LSB change around major carry At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz DAC code = midscale, 10 kHz; gain = 2, internal reference 0.1 Hz to 10 Hz At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz AD5696R/AD5695R/AD5694R Data Sheet TIMING CHARACTERISTICS VDD = 2.5 V to 5.5 V; 1.62 V VLOGIC 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. 1 Table 4. Parameter2 t1 t2 t3 t4 t5 t63 t7 t8 t9 t10 t11 t12 t13 tSP5 CB 4 Min 2.5 0.6 1.3 0.6 100 0 0.6 0.6 1.3 0 20 + 0.1CB4 20 400 0 Max Unit s s s s ns s s s s ns ns ns ns ns pF 0.9 300 300 50 400 Conditions/Comments SCL cycle time tHIGH, SCL high time tLOW, SCL low time tHD,STA, start/repeated start condition hold time tSU,DAT, data setup time tHD,DAT, data hold time tSU,STA, setup time for repeated start tSU,STO, stop condition setup time tBUF, bus free time between a stop and a start condition tR, rise time of SCL and SDA when receiving tF, fall time of SDA and SCL when transmitting/ receiving LDAC pulse width SCL rising edge to LDAC rising edge Pulse width of suppressed spike Capacitive load for each bus line 1 See Figure 2. Guaranteed by design and characterization; not production tested. 3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of SCL's falling edge. 4 CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD. 5 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns. 2 START CONDITION REPEATED START CONDITION STOP CONDITION SDA t9 t10 t11 t4 t3 SCL t4 t2 t6 t5 t7 t1 t8 t12 t13 LDAC1 t12 LDAC2 10486-002 NOTES 1ASYNCHRONOUS 2SYNCHRONOUS LDAC UPDATE MODE. LDAC UPDATE MODE. Figure 2. 2-Wire Serial Interface Timing Diagram Rev. D | Page 6 of 29 Data Sheet AD5696R/AD5695R/AD5694R ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 5. Parameter VDD to GND VLOGIC to GND VOUT to GND VREF to GND Digital Input Voltage to GND1 SDA and SCL to GND Operating Temperature Range Storage Temperature Range Junction Temperature 16-Lead TSSOP, JA Thermal Impedance, 0 Airflow (4-Layer Board) 16-Lead LFCSP, JA Thermal Impedance, 0 Airflow (4-Layer Board) Reflow Soldering Peak Temperature, Pb Free (J-STD-020) 1 Rating -0.3 V to +7 V -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VLOGIC + 0.3 V -0.3 V to +7 V -40C to +105C -65C to +150C 125C 112.6C/W Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 70C/W 260C Excluding SDA and SCL. Rev. D | Page 7 of 29 AD5696R/AD5695R/AD5694R Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 13 RESET 14 RSTSEL 16 VOUTB 15 VREF AD5696R/AD5695R/AD5694R VOUTA 1 12 A1 11 SCL GAIN 8 LDAC 7 SDA 6 RESET 14 A1 13 SCL 12 A0 VOUTC 6 11 VLOGIC VOUTD 7 10 GAIN SDA 8 9 LDAC GND 4 AD5696R/ AD5695R/ AD5694R VDD 5 TOP VIEW (Not to Scale) VOUTA 3 10486-006 TOP VIEW (Not to Scale) NOTES 1. THE EXPOSED PAD MUST BE TIED TO GND. 15 VOUTB 2 9 VLOGIC VOUTD 5 VOUTC 4 16 RSTSEL VREF 1 10 A0 VDD 3 Figure 3. 16-Lead LFCSP Pin Configuration 10486-007 GND 2 Figure 4. 16-Lead TSSOP Pin Configuration Table 6. Pin Function Descriptions LFCSP 1 2 3 Pin No. TSSOP 3 4 5 Mnemonic VOUTA GND VDD 4 5 6 6 7 8 VOUTC VOUTD SDA 7 9 LDAC 8 10 GAIN 9 10 11 11 12 13 VLOGIC A0 SCL 12 13 14 15 A1 RESET 14 16 RSTSEL 15 1 VREF 16 17 2 N/A VOUTB EPAD Description Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Ground Reference Point for All Circuitry on the Part. Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a 10 F capacitor in parallel with a 0.1 F capacitor to GND. Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the 24-bit input shift register. SDA is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. LDAC can be operated in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. This pin can also be tied permanently low. Span Set Pin. When this pin is tied to GND, all four DAC outputs have a span from 0 V to VREF. If this pin is tied to VLOGIC, all four DACs output a span of 0 V to 2 x VREF. Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V. Address Input. Sets the first LSB of the 7-bit slave address. Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 24-bit input register. Address Input. Sets the second LSB of the 7-bit slave address. Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending on the state of the RSTSEL pin. If the pin is forced low at power-up, the POR circuit does not initialize correctly until the pin is released. Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to VLOGIC powers up all four DACs to midscale. Reference Voltage. The AD5696R/AD5695R/AD5694R have a common reference pin. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference output. Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Exposed Pad. The exposed pad must be tied to GND. Rev. D | Page 8 of 29 Data Sheet AD5696R/AD5695R/AD5694R TYPICAL PERFORMANCE CHARACTERISTICS 2.5020 1600 VDD = 5V DEVICE 1 DEVICE 2 DEVICE 3 DEVICE 4 DEVICE 5 2.5010 1400 1200 1000 NSD (nV/ Hz) VREF (V) 2.5005 2.5000 2.4995 800 600 2.4990 400 2.4985 200 -20 0 20 40 60 80 100 120 TEMPERATURE (C) 0 10 10486-212 2.4980 -40 100 1k 10k 100k 10486-111 2.5015 VDD = 5V TA = 25C 1M FREQUENCY (MHz) Figure 5. Internal Reference Voltage vs. Temperature (Grade B) Figure 8. Internal Reference Noise Spectral Density vs. Frequency 2.5020 DEVICE 1 DEVICE 2 DEVICE 3 DEVICE 4 DEVICE 5 2.5015 2.5010 VDD = 5V TA = 25C T VREF (V) 2.5005 2.5000 1 2.4995 2.4990 2.4985 -20 0 20 40 60 80 100 120 TEMPERATURE (C) CH1 2V M1.0s A CH1 160mV 10486-112 VDD = 5V 10486-109 2.4980 -40 Figure 9. Internal Reference Noise, 0.1 Hz to 10 Hz Figure 6. Internal Reference Voltage vs. Temperature (Grade A) 2.5000 90 VDD = 5V TA = 25C VDD = 5V 80 2.4999 70 VREF (V) 50 40 30 2.4997 2.4996 2.4995 20 2.4994 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 TEMPERATURE DRIFT (ppm/C) 5.0 2.4993 -0.005 -0.003 -0.001 0.001 0.003 ILOAD (A) Figure 10. Internal Reference Voltage vs. Load Current Figure 7. Reference Output Temperature Drift Histogram Rev. D | Page 9 of 29 0.005 10486-113 10 10486-250 NUMBER OF UNITS 2.4998 60 AD5696R/AD5695R/AD5694R Data Sheet 2.5002 10 TA = 25C D1 8 2.5000 6 4 2.4998 2 INL (LSB) 0 -2 2.4994 -4 -6 D2 3.5 4.0 4.5 5.0 5.5 VDD (V) -10 0 625 0.8 6 0.6 4 0.4 2 0.2 DNL (LSB) 8 0 -2 -6 -0.6 VDD = 5V TA = 25C INTERNAL REFERENCE = 2.5V -0.8 CODE -1.0 0 10000 0.8 6 0.6 4 0.4 2 0.2 DNL (LSB) 8 0 -2 -6 -0.6 VDD = 5V TA = 25C INTERNAL REFERENCE = 2.5V 5000 7500 CODE 60000 VDD = 5V TA = 25C INTERNAL REFERENCE = 2.5V -0.8 10000 50000 0 -0.4 2500 40000 -0.2 -4 12500 15000 16348 10486-119 INL (LSB) 1.0 0 30000 Figure 15. AD5696R DNL 10 -10 20000 CODE Figure 12. AD5696R INL -8 3750 4096 -0.2 -0.4 60000 3125 0 -4 10486-118 INL (LSB) 1.0 50000 2500 Figure 14. AD5694R INL 10 40000 1875 CODE Figure 11. Internal Reference Voltage vs. Supply Voltage V = 5V -8 DD TA = 25C INTERNAL REFERENCE = 2.5V -10 0 10000 20000 30000 1250 10486-121 3.0 10486-117 2.4990 2.5 VDD = 5V TA = 25C INTERNAL REFERENCE = 2.5V -8 10486-120 2.4992 -1.0 0 2500 5000 7500 10000 CODE Figure 16. AD5695R DNL Figure 13. AD5695R INL Rev. D | Page 10 of 29 12500 15000 16383 10486-122 VREF (V) D3 2.4996 AD5696R/AD5695R/AD5694R 10 0.8 8 0.6 6 0.4 4 0.2 0 -0.2 2 -4 -0.6 -6 2500 3125 3750 4096 CODE -8 TA = 25C INTERNAL REFERENCE = 2.5V -10 2.7 3.2 3.7 4.2 8 0.08 6 0.06 4 0.04 ERROR (% of FSR) INL DNL -2 -4 0 GAIN ERROR -0.02 -0.04 -0.08 V = 5V DD INTERNAL REFERENCE = 2.5V -0.10 -40 -20 0 20 40 -10 -40 10 60 10486-124 VDD = 5V INTERNAL REFERENCE = 2.5V 110 TEMPERATURE (C) 60 80 100 120 TEMPERATURE (C) 10486-127 -0.06 -6 Figure 21. Gain Error and Full-Scale Error vs. Temperature Figure 18. INL Error and DNL Error vs. Temperature 10 VDD = 5V 1.4 INTERNAL REFERENCE = 2.5V 8 1.2 4 1.0 2 ERROR (mV) 6 INL 0 DNL -2 -4 0.8 0.6 0.4 ZERO-CODE ERROR -6 0.2 -8 V = 5V DD TA = 25C -10 0 0.5 1.0 OFFSET ERROR 1.5 2.0 2.5 3.0 3.5 4.0 VREF (V) 4.5 5.0 10486-125 ERROR (LSB) FULL-SCALE ERROR 0.02 0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) Figure 22. Zero-Code Error and Offset Error vs. Temperature Figure 19. INL Error and DNL Error vs. VREF Rev. D | Page 11 of 29 10486-128 ERROR (LSB) 0.10 -8 5.2 Figure 20. INL Error and DNL Error vs. Supply Voltage 10 0 4.7 SUPPLY VOLTAGE (V) Figure 17. AD5694R DNL 2 DNL -2 -0.4 VDD = 5V -0.8 TA = 25C INTERNAL REFERENCE = 2.5V -1.0 0 625 1250 1875 INL 0 10486-126 ERROR (LSB) 1.0 10486-123 DNL (LSB) Data Sheet AD5696R/AD5695R/AD5694R Data Sheet 0.10 0.08 0.08 0.04 0.02 GAIN ERROR 0 FULL-SCALE ERROR -0.02 -0.04 -0.06 TA = 25C INTERNAL REFERENCE = 2.5V -0.10 2.7 3.2 3.7 4.2 4.7 10486-129 5.2 SUPPLY VOLTAGE (V) 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 T = 25C A INTERNAL REFERENCE = 2.5V -0.10 2.7 3.2 3.7 4.2 Figure 23. Gain Error and Full-Scale Error vs. Supply TOTAL UNADJUSTED ERROR (% of FSR) 0 1.0 0.5 ERROR (mV) 5.2 Figure 26. TUE vs. Supply, Gain = 1 1.5 ZERO-CODE ERROR 0 OFFSET ERROR -0.5 -1.0 -1.5 2.7 3.2 3.7 4.2 4.7 10486-130 TA = 25C INTERNAL REFERENCE = 2.5V 5.2 SUPPLY VOLTAGE (V) -0.01 -0.02 -0.03 -0.04 -0.05 -0.06 -0.07 -0.08 VDD = 5V -0.09 T = 25C A INTERNAL REFERENCE = 2.5V -0.10 0 10000 20000 30000 40000 50000 60000 65535 CODE Figure 24. Zero-Code Error and Offset Error vs. Supply Figure 27. TUE vs. Code 0.10 VDD = 5V 0.09 INTERNAL REFERENCE = 2.5V 25 0.08 VDD = 5V TA = 25C EXTERNAL REFERENCE = 2.5V 20 0.07 HITS 0.06 0.05 0.04 15 10 0.03 5 0.02 0.01 0 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 10486-131 TOTAL UNADJUSTED ERROR (% of FSR) 4.7 SUPPLY VOLTAGE (V) 10486-133 -0.08 0.06 0 540 560 580 600 620 IDD (A) Figure 28. IDD Histogram with External Reference, 5 V Figure 25. TUE vs. Temperature Rev. D | Page 12 of 29 640 10486-135 ERROR (% of FSR) 0.06 10486-132 TOTAL UNADJUSTED ERROR (% of FSR) 0.10 Data Sheet AD5696R/AD5695R/AD5694R 5 VDD = 5V 30 T = 25C A INTERNAL REFERENCE = 2.5V 25 4 3 VDD = 3V TA = 25C GAIN = 1 EXTERNAL REFERENCE = 2.5V 0xFFFF VOUT (V) 15 10 0xC000 2 0x8000 1 0x4000 0x0000 0 5 -1 1000 1020 1040 1060 1080 1100 1120 1140 IDD FULLSCALE (A) -2 -60 10486-136 0 -40 -20 0 20 40 60 IOUT (mA) Figure 29. IDD Histogram with Internal Reference, VREFOUT = 2.5 V, Gain = 2 10486-139 HITS 20 Figure 32. Source and Sink Capability at 3 V 1.0 1.4 0.8 1.2 0.6 0.4 CURRENT (mA) VOUT (V) SINKING 2.7V 0.2 SINKING 5V 0 -0.2 SOURCING 5V -0.4 1.0 FULL-SCALE ZERO CODE 0.8 0.6 EXTERNAL REFERENCE, FULL-SCALE 0.4 -0.6 SOURCING 2.7V -1.0 0 5 10 15 20 25 30 LOAD CURRENT (mA) 0 -40 110 Figure 33. Supply Current vs. Temperature 4.0 7 3.5 0xFFFF DAC A DAC B DAC C DAC D 3.0 4 0xC000 2.5 VOUT (V) 3 0x8000 2 2.0 0x4000 1.5 0x0000 1.0 0 -1 -2 -0.06 -0.04 -0.02 0 0.02 0.04 LOAD CURRENT (A) 0.06 VDD = 5V 0.5 TA = 25C INTERNAL REFERENCE = 2.5V 1/4 TO 3/4 SCALE 0 0 20 40 80 TIME (s) Figure 34. Settling Time, 5.25 V Figure 31. Source and Sink Capability at 5 V Rev. D | Page 13 of 29 160 320 10486-141 1 10486-138 VOUT (V) 60 TEMPERATURE (C) Figure 30. Headroom/Footroom vs. Load Current VDD = 5V 6 TA = 25C GAIN = 2 INTERNAL 5 REFERENCE = 2.5V 10 10486-140 0.2 10486-200 -0.8 AD5696R/AD5695R/AD5694R Data Sheet 6 0.06 CH A CH B CH C CH D VDD CH B CH C CH D 5 4 0.03 3 0.02 2 0.01 1 0 0 VOUT AC-COUPLED (V) 0.002 0.04 VDD (V) VOUT (V) 0.05 0.003 0.001 0 -0.001 -1 15 10 -0.002 TIME (s) 0 5 10 15 20 10486-145 5 10486-142 TA = 25C INTERNAL REFERENCE = 2.5V -0.01 -10 -5 0 25 TIME (s) Figure 35. Power-On Reset to 0 V Figure 38. Analog Crosstalk, Channel A 3 CH A CH B CH C CH D SYNC T GAIN = 2 VOUT (V) 2 GAIN = 1 1 VDD = 5V TA = 25C INTERNAL REFERENCE = 2.5V 0 5 10 TIME (s) VDD = 5V TA = 25C EXTERNAL REFERENCE = 2.5V 10486-143 0 -5 CH1 2V Figure 36. Exiting Power-Down to Midscale M1.0s A CH1 802mV 10486-146 1 Figure 39. 0.1 Hz to 10 Hz Output Noise Plot, External Reference 2.5008 T 2.4998 CHANNEL B TA = 25C VDD = 5.25V INTERNAL REFERENCE CODE = 7FFF TO 8000 ENERGY = 0.227206nV-sec 2.4993 2.4988 0 2 4 6 8 10 TIME (s) Figure 37. Digital-to-Analog Glitch Impulse 12 VDD = 5V TA = 25C INTERNAL REFERENCE = 2.5V CH1 2V M1.0s A CH1 802mV 10486-147 1 10486-144 VOUT (V) 2.5003 Figure 40. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference Rev. D | Page 14 of 29 Data Sheet AD5696R/AD5695R/AD5694R 4.0 1600 VDD = 5V TA = 25C 1400 INTERNAL REFERENCE = 2.5V FULL-SCALE MIDSCALE ZERO-SCALE 0nF 0.1nF 10nF 0.22nF 4.7nF 3.9 3.8 VDD = 5V TA = 25C INTERNAL REFERENCE = 2.5V 1200 VOUT (V) NSD (nV/ Hz) 3.7 1000 800 600 3.6 3.5 3.4 3.3 400 3.2 200 1k 10k 100k 1M FREQUENCY (Hz) 3.0 1.590 BANDWIDTH (dB) -80 -100 -120 -140 FREQUENCY (Hz) Figure 42. Total Harmonic Distortion at 1 kHz 1.620 1.625 1.630 -20 -30 -40 -50 -160 VDD = 5V TA = 25C EXTERNAL REFERENCE = 2.5V, 0.1V p-p -60 10k 10486-149 THD (dBV) -60 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 1.615 -10 -40 0 1.610 0 -20 -180 1.605 Figure 43. Settling Time vs. Capacitive Load VDD = 5V TA = 25C INTERNAL REFERENCE = 2.5V 0 1.600 TIME (ms) Figure 41. Noise Spectral Density 20 1.595 100k FREQUENCY (Hz) 1M 10M 10486-151 100 10486-150 3.1 10486-148 0 10 Figure 44. Multiplying Bandwidth, External Reference = 2.5 V, 0.1 V p-p, 10 kHz to 10 MHz Rev. D | Page 15 of 29 AD5696R/AD5695R/AD5694R Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot is shown in Figure 12. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 15. Zero-Code Error Zero-code error is a measurement of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5696R because the output of the DAC cannot go below 0 V due to a combination of the offset errors in the DAC and the output amplifier. Zero-code error is expressed in mV. A plot of zero-code error vs. temperature can be seen in Figure 22. Full-Scale Error Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. Ideally, the output should be VDD - 1 LSB. Full-scale error is expressed in percent of full-scale range (% of FSR). A plot of full-scale error vs. temperature can be seen in Figure 21. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal expressed as % of FSR. Output Voltage Settling Time This is the amount of time it takes for the output of a DAC to settle to a specified level for a 1/4 to 3/4 full-scale input change. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec, and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000) (see Figure 37). Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-sec, and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Reference Feedthrough Reference feedthrough is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated. It is expressed in dB. Noise Spectral Density This is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (nV/Hz). It is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nV/Hz. A plot of noise spectral density is shown in Figure 41. Offset Error Drift This is a measurement of the change in offset error with a change in temperature. It is expressed in V/C. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in V. Gain Temperature Coefficient This is a measurement of the change in gain error with changes in temperature. It is expressed in ppm of FSR/C. DC crosstalk due to load current change is a measure of the impact that a change in load current on one DAC has to another DAC kept at midscale. It is expressed in V/mA. Offset Error Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured on the AD5696R with Code 512 loaded in the DAC register. It can be negative or positive. Digital Crosstalk This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-sec. DC Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in mV/V. VREF is held at 2 V, and VDD is varied by 10%. Rev. D | Page 16 of 29 Data Sheet AD5696R/AD5695R/AD5694R Analog Crosstalk This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa). Then execute a software LDAC and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-sec. DAC-to-DAC Crosstalk This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent analog output change of another DAC. It is measured by loading the attack channel with a full-scale code change (all 0s to all 1s and vice versa), using the write to and update commands while monitoring the output of the victim channel that is at midscale. The energy of the glitch is expressed in nV-sec. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Total Harmonic Distortion (THD) This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measurement of the harmonics present on the DAC output. It is measured in dB. Voltage Reference TC Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature. The reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output over a given temperature range expressed in ppm/C as follows; VREFmax - VREFmin 6 TC = x 10 VREFnom x TempRange where: VREFmax is the maximum reference output measured over the total temperature range. VREFmin is the minimum reference output measured over the total temperature range. VREFnom is the nominal reference output voltage, 2.5 V. TempRange is the specified temperature range of -40C to +105C. Rev. D | Page 17 of 29 AD5696R/AD5695R/AD5694R Data Sheet THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER The AD5696R/AD5695R/AD5694R are quad 16-/14-/12-bit, serial input, voltage output DACs with an internal reference. The parts operate from supply voltages of 2.7 V to 5.5 V. Data is written to the AD5696R/AD5695R/AD5694R in a 24-bit word format via a 2-wire serial interface. The AD5696R/AD5695R/ AD5694R incorporate a power-on reset circuit to ensure that the DAC output powers up to a known output state. The devices also have a software power-down mode that reduces the typical current consumption to typically 4 A. The resistor string structure is shown in Figure 46. It is a string of resistors, each of Value R. The code loaded to the DAC register determines the node on the string where the voltage is to be tapped off and fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. VREF R TRANSFER FUNCTION R The internal reference is on by default. To use an external reference, only a nonreference option is available. Because the input coding to the DAC is straight binary, the ideal output voltage when using an external reference is given by R TO OUTPUT AMPLIFIER D VOUT = VREF x Gain N 2 DAC ARCHITECTURE The DAC architecture consists of a string DAC followed by an output amplifier. Figure 45 shows a block diagram of the DAC architecture. VREF REF (+) RESISTOR STRING REF (-) GND VOUTX Figure 46. Resistor String Structure Internal Reference The AD5696R/AD5695R/AD5694R on-chip reference is on at power-up but can be disabled via a write to a control register. See the Internal Reference Setup section for details. The AD5696R/AD5695R/AD5694R have a 2.5 V, 2 ppm/C reference, giving a full-scale output of 2.5 V or 5 V depending on the state of the GAIN pin. The internal reference associated with the device is available at the VREF pin. This buffered reference is capable of driving external loads of up to 10 mA. Output Amplifiers * GAIN (GAIN = 1 OR 2) 10486-052 DAC REGISTER R The output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. The actual range depends on the value of VREF, the GAIN pin, offset error, and gain error. The GAIN pin selects the gain of the output. 2.5V REF INPUT REGISTER R 10486-053 where: D is the decimal equivalent of the binary code that is loaded to the DAC register as follows: 0 to 4,095 for the 12-bit device. 0 to 16,383 for the 14-bit device. 0 to 65,535 for the 16-bit device. N is the DAC resolution. Gain is the gain of the output amplifier and is set to 1 by default. This can be set to x1 or x2 using the gain select pin. When this pin is tied to GND, all four DAC outputs have a span from 0 V to VREF. If this pin is tied to VDD, all four DACs output a span of 0 V to 2 x VREF. * Figure 45. Single DAC Channel Architecture Block Diagram If this pin is tied to GND, all four outputs have a gain of 1 and the output range is 0 V to VREF. If this pin is tied to VLOGIC, all four outputs have a gain of 2 and the output range is 0 V to 2 x VREF. These amplifiers are capable of driving a load of 1 k in parallel with 2 nF to GND. The slew rate is 0.8 V/s with a 1/4 to 3/4 scale settling time of 5 s. Rev. D | Page 18 of 29 Data Sheet AD5696R/AD5695R/AD5694R Table 7. Command Definitions SERIAL INTERFACE The AD5696R/AD5695R/AD5694R have 2-wire I2C-compatible serial interfaces (refer to I2C-Bus Specification, Version 2.1, January 2000, available from Philips Semiconductor). See Figure 2 for a timing diagram of a typical write sequence. The AD5696R/ AD5695R/AD5694R can be connected to an I2C bus as a slave device, under the control of a master device. The AD5696R/ AD5695R/AD5694R support standard (100 kHz) and fast (400 kHz) data transfer modes. Support is not provided for 10bit addressing and general call addressing. Power should not be removed while the device is connected to an active I2C bus. C3 0 0 Input Shift Register The input shift register of the AD5696R/AD5695R/AD5694R is 24 bits wide. Data is loaded into the device as a 24-bit word under the control of a serial clock input, SCL. The first eight MSBs make up the command byte. The first four bits are the command bits (C3, C2, C1, C0) that control the mode of operation of the device (see Table 7). The last 4 bits of first byte are the address bits (DAC A, DAC B, DAC C, DAC D) (see Table 8). Command C2 C1 0 0 0 0 C0 0 1 0 0 1 0 0 0 0 0 1 1 1 0 0 1 0 1 0 0 1 ... 1 1 1 0 ... 1 1 1 0 ... 1 0 1 0 ... 1 Description No operation Write to Input Register n (dependent on LDAC) Update DAC Register n with contents of Input Register n Write to and update DAC Channel n Power down/power up DAC Hardware LDAC mask register Software reset (power-on reset) Internal reference setup register Reserved Reserved Reserved Table 8. Address Commands Address (n) DAC C DAC B 0 0 0 1 1 0 0 0 0 1 1 1 DAC D 0 0 0 1 0 1 The data-word comprises 16-bit, 14-bit, or 12-bit input code, followed by four, two, or zero don't care bits for the AD5696R, AD5695R, and AD5694R, respectively (see Figure 47, Figure 48, and Figure 49). These data bits are transferred to the input register on the 24 falling edges of SCL. 1 DAC A 1 0 0 0 1 1 Selected DAC Channel1 DAC A DAC B DAC C DAC D DAC A and DAC B1 All DACs Any combination of DAC channels can be selected using the address bits. Commands can be executed on individual DAC channels, combined DAC channels, or on all DACs, depending on the address bits selected. C3 C2 C1 C0 COMMAND DAC D DAC C DAC B DAC A D11 D10 D9 D8 DAC ADDRESS COMMAND BYTE D7 D6 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D5 D4 D3 D2 D1 D0 X X X X DAC DATA DAC DATA DATA HIGH BYTE DATA LOW BYTE 10486-300 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 C3 C2 C1 COMMAND C0 DAC D DAC C DAC B DAC A D13 DAC ADDRESS COMMAND BYTE D12 D11 D10 D9 D8 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D7 D6 D5 D4 D3 D2 D1 D0 X X DAC DATA DAC DATA DATA HIGH BYTE DATA LOW BYTE Figure 48. AD5695R Input Shift Register Content Rev. D | Page 19 of 29 10486-301 Figure 47. AD5696R Input Shift Register Content Data Sheet DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 C3 C2 C1 COMMAND C0 DAC D DAC C DAC B DAC A D15 D14 D13 D12 DAC ADDRESS COMMAND BYTE D11 D10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DAC DATA DAC DATA DATA HIGH BYTE DATA LOW BYTE 10486-302 AD5696R/AD5695R/AD5694R Figure 49. AD5694R Input Shift Register Content WRITE AND UPDATE COMMANDS Update DAC Register n with Contents of Input Register n Write to Input Register n (Dependent on LDAC) Command 0010 loads the DAC registers/outputs with the contents of the input registers selected and updates the DAC outputs directly. Command 0001 allows the user to write to each DAC's dedicated input register individually. When LDAC is low, the input register is transparent (if not controlled by the LDAC mask register). Write to and Update DAC Channel n (Independent of LDAC) Command 0011 allows the user to write to the DAC registers and update the DAC outputs directly. Rev. D | Page 20 of 29 Data Sheet AD5696R/AD5695R/AD5694R SERIAL OPERATION 2. The AD5696R/AD5695R/AD5694R each have a 7-bit slave address. The five MSBs are 00011 and the two LSBs (A1, A0) are set by the state of the A0 and A1 address pins. The ability to make hardwired changes to A0 and A1 allows the user to incorporate up to four of these devices on one bus, as outlined in Table 9. 3. Table 9. Device Address Selection A0 Pin Connection GND VLOGIC GND A1 Pin Connection GND GND VLOGIC A0 0 1 0 A1 0 0 1 VLOGIC VLOGIC 1 1 WRITE OPERATION The 2-wire serial bus protocol operates as follows: When writing to the AD5696R/AD5695R/AD5694R, the user must begin with a start command followed by an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The AD5696R/ AD5695R/AD5694R require two bytes of data for the DAC and a command byte that controls various DAC functions. Three bytes of data must, therefore, be written to the DAC with the command byte followed by the most significant data byte and the least significant data byte, as shown in Figure 50. All these data bytes are acknowledged by the AD5696R/AD5695R/ AD5694R. A stop condition follows. The master initiates data transfer by establishing a start condition when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address. The slave address corresponding to the transmitted address responds by pulling SDA low during the 9th clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. 1 9 1 9 SCL 0 SDA 0 0 1 1 A1 A0 DB23 R/W DB22 DB21 DB20 DB19 DB18 ACK. BY AD5696R/AD5695R/AD5694R START BY MASTER DB17 DB16 ACK. BY AD5696R/AD5695R/AD5694R FRAME 1 SLAVE ADDRESS FRAME 2 COMMAND BYTE 1 9 1 9 SCL (CONTINUED) SDA (CONTINUED) DB15 DB14 DB13 DB12 DB11 DB10 FRAME 3 MOST SIGNIFICANT DATA BYTE DB9 DB8 DB7 DB6 ACK. BY AD5696R/AD5695R/AD5694R Figure 50. I2C Write Operation Rev. D | Page 21 of 29 DB5 DB4 DB3 DB2 FRAME 4 LEAST SIGNIFICANT DATA BYTE DB1 DB0 ACK. BY AD5696R/AD5695R/AD5694R STOP BY MASTER 10486-303 1. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. When all data bits have been read or written, a stop condition is established. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the 9th clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the 10th clock pulse, and then high during the 10th clock pulse to establish a stop condition. AD5696R/AD5695R/AD5694R Data Sheet READ OPERATION MULTIPLE DAC READBACK SEQUENCE When reading data back from the AD5696R DACs, the user begins with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. This address byte must be followed by the NOP command operation that sets the internal pointer to the DAC address to read from, which is also acknowledged by the DAC. Following this, there is a repeated start condition by the master and the address is resent with R/W = 1. This is acknowledged by the DAC, indicating that it is prepared to transmit data. Two bytes of data are then read from the DAC, as shown in Figure 51. A NACK condition from the master, followed by a STOP condition, completes the read sequence. Default readback is Channel A if more than one DAC is selected. The user begins with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. This address byte must be followed by the control byte, which is also acknowledged by the DAC. The user configures which channel to start the readback using the control byte. Following this, there is a repeated start condition by the master and the address is resent with R/W = 1. This is acknowledged by the DAC, indicating that it is prepared to transmit data. The first two bytes of data are then read from the DAC Input Register n selected using the control byte, most significant byte first as shown in Figure 51. The next two bytes read back are the contents of DAC Input Register n + 1, the next bytes read back are the contents of DAC Input Register n + 2. Data continues to be read from the DAC input registers in this auto-incremental fashion, until a NACK followed by a stop condition follows. If the contents of DAC Input Register D are read out, the next two bytes of data that are read are from the contents of DAC Input Register A. 1 9 1 9 SCL 0 SDA 0 0 1 1 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 ACK. BY AD5696R/AD5695R/AD5694R START BY MASTER FRAME 1 SLAVE ADDRESS ACK. BY AD5696R/AD5695R/AD5694R FRAME 2 COMMAND BYTE 1 9 1 9 SCL 0 SDA 0 0 REPEATED START BY MASTER 1 1 A1 FRAME 3 SLAVE ADDRESS A0 R/W DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 ACK. BY AD5696R/AD5695R/AD5694R 1 9 SCL (CONTINUED) DB7 DB6 DB5 DB4 DB3 DB2 FRAME 5 SLAVE ADDRESS SIGNIFICANT DATA BYTE n DB1 DB0 STOP BY MASTER Figure 51. I2C Read Operation Rev. D | Page 22 of 29 10486-304 SDA (CONTINUED) Data Sheet AD5696R/AD5695R/AD5694R POWER-DOWN OPERATION output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while the part is in power-down mode. There are three different power-down options. The output is connected internally to GND through either a 1 k or a 100 k resistor, or it is left open-circuited (three-state). The output stage is illustrated in Figure 52. Table 10. Modes of Operation Operating Mode Normal Operation Power-Down Modes 1 k to GND 100 k to GND Three-State PDx1 0 PDx0 0 0 1 1 1 0 1 AMPLIFIER DAC VOUTX POWER-DOWN CIRCUITRY RESISTOR NETWORK 10486-058 The AD5696R/AD5695R/AD5694R contain three separate power-down modes. Command 0100 is designated for the powerdown function (see Table 7). These power-down modes are software-programmable by setting eight bits, Bit DB7 to Bit DB0, in the shift register. There are two bits associated with each DAC channel. Table 10 shows how the state of the two bits corresponds to the mode of operation of the device. Figure 52. Output Stage During Power-Down Any or all DACs (DAC A to DAC D) can be powered down to the selected mode by setting the corresponding bits. See Table 11 for the contents of the input shift register during the power-down/power-up operation. The bias generator, output amplifier, resistor string, and other associated linear circuitry are shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The DAC register can be updated while the device is in power-down mode. The time required to exit power-down is typically 4.5 s for VDD = 5 V. When both Bit PDx1 and Bit PDx0 (where x is the channel selected) in the input shift register are set to 0, the parts work normally with its normal power consumption of 4 mA at 5 V. However, for the three power-down modes, the supply current falls to 4 A at 5 V. Not only does the supply current fall, but the To reduce the current consumption further, the on-chip reference can be powered off. See the Internal Reference Setup section. Table 11. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation 1 DB23 0 DB22 1 DB21 0 DB20 0 Command bits (C3 to C0) 1 DB19 to DB16 X Address bits Don't care DB15 to DB8 X DB7 PDD1 DB6 PDD0 Power-Down Select DAC D X = don't care. Rev. D | Page 23 of 29 DB5 PDC1 DB4 PDC0 Power-Down Select DAC C DB3 PDB1 DB2 PDB0 Power-Down Select DAC B DB1 PDA1 DB0 (LSB) PDA0 Power-Down Select DAC A AD5696R/AD5695R/AD5694R Data Sheet LOAD DAC (HARDWARE LDAC PIN) LDAC MASK REGISTER The AD5696R/AD5695R/AD5694R DACs have double buffered interfaces consisting of two banks of registers: input registers and DAC registers. The user can write to any combination of the input registers. Updates to the DAC register are controlled by the LDAC pin. Command 0101 is reserved for this software LDAC function. Address bits are ignored. Writing to the DAC, using Command 0101, loads the 4-bit LDAC register (DB3 to DB0). The default for each channel is 0; that is, the LDAC pin works normally. Setting the bits to 1 forces this DAC channel to ignore transitions on the LDAC pin, regardless of the state of the hardware LDAC pin. This flexibility is useful in applications where the user wishes to select which channels respond to the LDAC pin. OUTPUT AMPLIFIER REFIN 12-/14-/16-BIT DAC LDAC DAC REGISTER VOUT Table 12. LDAC Overwrite Definition Load LDAC Register LDAC Bits (DB3 to DB0) 0 1 SCL SDO INPUT SHIFT REGISTER LDAC Pin 1 or 0 X1 10486-059 INPUT REGISTER Figure 53. Simplified Diagram of Input Loading Circuitry for a Single DAC 1 Instantaneous DAC Updating (LDAC Held Low) LDAC Operation Determined by the LDAC pin. DAC channels update and override the LDAC pin. DAC channels see LDAC as 1. X = don't care. The LDAC register gives the user extra flexibility and control over the hardware LDAC pin (see Table 12). Setting the LDAC bits (DB0 to DB3) to 0 for a DAC channel means that this channel's update is controlled by the hardware LDAC pin. LDAC is held low while data is clocked into the input register using Command 0001. Both the addressed input register and the DAC register are updated on the 24th clock and the output begins to change (see Table 13). Deferred DAC Updating (LDAC is Pulsed Low) LDAC is held high while data is clocked into the input register using Command 0001. All DAC outputs are asynchronously updated by taking LDAC low after the 24th clock. The update now occurs on the falling edge of LDAC. Table 13. Write Commands and LDAC Pin Truth Table 1 Commands 0001 Description Write to Input Register n (dependent on LDAC) 0010 Update DAC Register n with contents of Input Register n 0011 Write to and update DAC Channel n Hardware LDAC Pin State VLOGIC GND 2 VLOGIC Input Register Contents Data update Data update No change GND No change VLOGIC GND Data update Data update DAC Register Contents No change (no update) Data update Updated with input register contents Updated with input register contents Data update Data update A high to low hardware LDAC pin transition always updates the contents of the contents of the DAC register with the contents of the input register on channels that are not masked (blocked) by the LDAC mask register. 2 When LDAC is permanently tied low, the LDAC mask bits are ignored. 1 Rev. D | Page 24 of 29 Data Sheet AD5696R/AD5695R/AD5694R HARDWARE RESET (RESET) SOLDER HEAT REFLOW RESET is an active low reset that allows the outputs to be cleared to either zero scale or midscale. The clear code value is user selectable via the RESET select pin. It is necessary to keep RESET low for a minimum amount of time to complete the operation (see Figure 2). When the RESET signal is returned high, the output remains at the cleared value until a new value is programmed. The outputs cannot be updated with a new value while the RESET pin is low. There is also a software executable reset function that resets the DAC to the power-on reset code. Command 0110 is designated for this software reset function (see Table 7). Any events on LDAC during a power-on reset are ignored. If the RESET pin is pulled low at power-up, the device does not initialize correctly until the pin is released. As with all IC reference voltage circuits, the reference value experiences a shift induced by the soldering process. Analog Devices, Inc., performs a reliability test called precondition to mimic the effect of soldering a device to a board. The output voltage specification quoted previously includes the effect of this reliability test. 60 POSTSOLDER HEAT REFLOW 50 PRESOLDER HEAT REFLOW 40 HITS The AD5696R/AD5695R/AD5694R contain a power-on reset circuit that controls the output voltage during power-up. By connecting the RSTSEL pin low, the output powers up to zero scale. Note that this is outside the linear region of the DAC; by connecting the RSTSEL pin high, VOUT powers up to midscale. The output remains powered up at this level until a valid write sequence is made to the DAC. 30 20 10 0 2.498 2.502 LONG-TERM TEMPERATURE DRIFT Figure 55 shows the change in the VREF (ppm) value after 1000 hours at 25C ambient temperature. 140 120 100 80 60 40 20 0 -20 0 100 200 300 400 500 600 700 800 900 ELAPSED TIME (Hours) Figure 55. Reference Drift Through to 1000 Hours Rev. D | Page 25 of 29 1000 10486-055 INTERNAL REFERENCE DRFIT (PPM) Action Reference on (default) Reference off 2.501 Figure 54. SHR Reference Voltage Shift The on-chip reference is on at power-up by default. To reduce the supply current, this reference can be turned off by setting software programmable bit, DB0, in the control register. Table 14 shows how the state of the bit corresponds to the mode of operation. Command 0111 is reserved for setting up the internal reference (see Figure 6). Table 14 shows how the state of the bits in the input shift register corresponds to the mode of operation of the device during internal reference setup. Internal Reference Setup Register (DB0) 0 1 2.500 VREF (V) INTERNAL REFERENCE SETUP Table 14. Reference Setup Register 2.499 10486-060 RESET SELECT PIN (RSTSEL) Figure 54 shows the effect of solder heat reflow (SHR) as measured through the reliability test (precondition). AD5696R/AD5695R/AD5694R Data Sheet THERMAL HYSTERESIS 9 Thermal hysteresis is the voltage difference induced on the reference voltage by sweeping the temperature from ambient to cold, to hot and then back to ambient. 8 FIRST TEMPERATURE SWEEP SUBSEQUENT TEMPERATURE SWEEPS 7 6 HITS Thermal hysteresis data is shown in Figure 56. It is measured by sweeping temperature from ambient to -40C, then to +105C, and returning to ambient. The VREF delta is then measured between the two ambient measurements and shown in blue in Figure 56. The same temperature sweep and measurements were immediately repeated and the results are shown in red in Figure 56. 5 4 3 2 0 -200 -150 -100 -50 0 DISTORTION (ppm) Figure 56. Thermal Hysteresis Table 15. 24-Bit Input Shift Register Contents for Internal Reference Setup Command 1 DB23 (MSB) 0 DB22 1 DB21 1 DB20 1 Command bits (C3 to C0) 1 DB19 X DB18 X DB17 X DB16 X Address bits (A2 to A0) X = don't care. Rev. D | Page 26 of 29 DB15 to DB1 X DB0 (LSB) 1/0 Don't care Reference setup register 50 10486-062 1 Data Sheet AD5696R/AD5695R/AD5694R APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5696R/AD5695R/ AD5694R is via a serial bus that uses a standard protocol that is compatible with DSP processors and microcontrollers. The communications channel requires a 2-wire interface consisting of a clock signal and a data signal. special considerations to design the motherboard and to mount the package. For enhanced thermal, electrical, and board level performance, solder the exposed paddle on the bottom of the package to the corresponding thermal land paddle on the PCB. Design thermal vias into the PCB land paddle area to further improve heat dissipation. The GND plane on the device can be increased (as shown in Figure 58) to provide a natural heat sinking effect. AD5696R/ AD5695R/ AD5694R The I2C interface of the AD5696R/AD5695R/AD5694R is designed to be easily connected to industry-standard DSPs and microcontrollers. Figure 57 shows the AD5696R/AD5695R/ AD5694R connected to the Analog Devices Blackfin(R) DSP. The Blackfin has an integrated I2C port that can be connected directly to the I2C pins of the AD5696R/AD5695R/AD5694R. GND PLANE AD5696R/ AD5695R/ AD5694R 10486-166 AD5696R/AD5695R/AD5694R TO ADSP-BF531 INTERFACE BOARD ADSP-BF531 LDAC RESET GALVANICALLY ISOLATED INTERFACE Figure 57. ADSP-BF531 Interface LAYOUT GUIDELINES In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The PCB on which the AD5696R/AD5695R/AD5694R are mounted should be designed so that the AD5696R/AD5695R/AD5694R lie on the analog plane. The AD5696R/AD5695R/AD5694R should have ample supply bypassing of 10 F in parallel with 0.1 F on each supply, located as close to the package as possible, ideally right up against the device. The 10 F capacitors are the tantalum bead type. The 0.1 F capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI) such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. iCoupler(R) products from Analog Devices provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5696R/AD5695R/AD5694R makes the part ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 59 shows a 4-channel isolated interface to the AD5696R/AD5695R/AD5694R using an ADuM1400. For further information, visit http://www.analog.com/icouplers. CONTROLLER SERIAL CLOCK IN SERIAL DATA OUT RESET OUT In systems where there are many devices on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate easily. LOAD DAC OUT The AD5696R/AD5695R/AD5694R LFCSP models have an exposed paddle beneath the device. Connect this paddle to the GND supply for the part. For optimum performance, use ADuM14001 VIA VIB VIC VID ENCODE DECODE ENCODE DECODE ENCODE DECODE ENCODE DECODE 1 ADDITIONAL PINS OMITTED FOR CLARITY. Rev. D | Page 27 of 29 Figure 59. Isolated Interface VOA VOB VOC VOD TO SCL TO SDA TO RESET TO LDAC 10486-167 PF9 PF8 Figure 58. Paddle Connection to Board SCL SDA 10486-164 GPIO1 GPIO2 AD5696R/AD5695R/AD5694R Data Sheet OUTLINE DIMENSIONS 3.10 3.00 SQ 2.90 0.50 BSC 13 PIN 1 INDICATOR 16 1 12 EXPOSED PAD 1.75 1.60 SQ 1.45 9 TOP VIEW 0.80 0.75 0.70 4 5 8 0.50 0.40 0.30 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.25 MIN BOTTOM VIEW 08-16-2010-E PIN 1 INDICATOR 0.30 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. Figure 60. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm x 3 mm Body, Very Very Thin Quad (CP-16-22) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8 0 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 61. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev. D | Page 28 of 29 0.75 0.60 0.45 Data Sheet AD5696R/AD5695R/AD5694R ORDERING GUIDE Model1 AD5696RACPZ-RL7 AD5696RBCPZ-RL7 AD5696RARUZ AD5696RARUZ-RL7 AD5696RBRUZ AD5696RBRUZ-RL7 AD5695RBCPZ-RL7 AD5695RARUZ AD5695RARUZ-RL7 AD5695RBRUZ AD5695RBRUZ-RL7 AD5694RBCPZ-RL7 AD5694RARUZ AD5694RARUZ-RL7 AD5694RBRUZ AD5694RBRUZ-RL7 EVAL-AD5696RSDZ 1 Resolution 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 16 Bits 14 Bits 14 Bits 14 Bits 14 Bits 14 Bits 12 Bits 12 Bits 12 Bits 12 Bits 12 Bits Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C Accuracy 8 LSB INL 2 LSB INL 8 LSB INL 8 LSB INL 2 LSB INL 2 LSB INL 1 LSB INL 4 LSB INL 4 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 2 LSB INL 2 LSB INL 1 LSB INL 1 LSB INL Reference Tempco (ppm/C) 5 (typ) 5 (max) 5 (typ) 5 (typ) 5 (max) 5 (max) 5 (max) 5 (typ) 5 (typ) 5 (max) 5 (max) 5 (max) 5 (typ) 5 (typ) 5 (max) 5 (max) Z = RoHS Compliant Part. (c)2012-2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10486-0-4/17(D) Rev. D | Page 29 of 29 Package Description 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead LFCSP_WQ 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead LFCSP_WQ 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP AD5696R TSSOP Evaluation Board Package Option CP-16-22 CP-16-22 RU-16 RU-16 RU-16 RU-16 CP-16-22 RU-16 RU-16 RU-16 RU-16 CP-16-22 RU-16 RU-16 RU-16 RU-16 Branding DJA DJD DJR DJL