Description
CXA1124/CXA1534 is an IC designed for the MTS
decoding systems. This device contains a stereo
signal demodulator, a SAP (Second Audio Program)
signal demodulator and a dbx-TV noise reduction
decoder, The Main 100% reference input level of the
CXA1124 (CXA1534) is 245mVrms (100mVrms).
Features
•All functions of the MTS decoding system included
on a chip
•Minimized external components using integrated
active filtering technique
•Reduced adjustment points using optimized filter
characteristics, a quasi-sine wave stereo demodulator
and a SAP demodulator
•Has a sub output which allows independent setting
of a mode
•Allows automatic changeover between ON and
OFF in the SAP mode when SAP broadcasting is
OFF
•Adjustment-free pilot cancel circuit
•Wide operating voltage range (4.7 to 10V)
Structure
Bipolar silicon monolithic IC
Absolute Maximum Ratings (Ta = 25°C)
•Supply voltage VCC 12 V
•LED drive current IO25 (max.) mA
•Allowable power dissipation
PD2200 (42pin SDIP) mW
600 (48pin QFP) mW
•Operating temperature Topr –20 to +75 °C
•Storage temperature Tstg –55 to +150 °C
Operating Conditions
Supply voltage VCC 4.7 to 10.0 V
– 1 –
CXA1124BS/BQ
CXA1534S/Q
E91402C79
US Audio Multiplexing Decoder IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXA1124BS/CXA1534S
42 pin SDIP (Plastic) CXA1124BS
42 pin SDIP (Plastic)
CXA1124BQ/CXA1534Q
48 pin QFP (Plastic)
– 2 –
CXA1124BS/BQ, CXA1534S/Q
Block Diagram and Pin Configuration
CXA1124BS
LFLT VCO 1/4 1/2
LFLT LPF
LPF DE.ENLPF ST.
IND
BPF SAP
VCO LPF
BPF SAP
IND MODE
DISPLAY
VCC/2
NR.SN DE.EN VE VCA
22
23
24
25
26
2728
29
30
40 39 38 37 36 35 34 31
32
33
41
42
PL INT2
MA OUT
SUB OUT
I TIME
VRS
V
CC
GND
VE
VE OUT
VCA IN
VCA TC
VCA WGT
VE TC
ST IN
MAIN IN
VE WGT
SAP BPF
PC INT1
PC INT2
COMP IN
PL INT1
MATRIX
LPF HPF
LPF
RMS
DET
RMS
DET
2345678910 11 12 13 14 15 16 17 18 19 20 21
1
SAP TC
M1
M2
SMD
FSAP
E SAP
I LPF
I SAP
MUTE
FMONO
I VCO
SAP IN
S OUT
L OUT
R OUT
NR BPF
ST LED
SAP LED
LED G
VC SAP
SAP OUT
IREF
CXA1124BQ
BPF SAP
VCO
SAP
IND
De-Em VCA
Matrix
HPF RMS
DET
IREF
LPF
LFLT VCO 1/4 1/2
FLT LPF
LPFDe-EmLPF
ST IND
VCC/2
RMS
DET
LPF LPFSW
NOISE
BPF
LED
DRIVE
2345678910 11 12
1
SAP OUT
M1
M2
SMD
FSAP
NC
E SAP
I LPF
I SAP
MUTE
FMONO
I VCO
13
14
15
16
17
18
19
20
21
22
23
24
R OUT
NC
S OUT
NR BPF
SAP IN
VE WGT
ST IN
VE TC
L OUT
GND1
VCA WGT
MAIN IN
38
37
COMP IN
PL INT1
40
39
41
42
43
44
45
46
47
48
VC SAP
LED G
SAP LED
ST LED
PC INT1
SAP TC
NC
SAP BPF
PC INT2
GND2
25
2627
28
29
30
36 35 34 31
32
33
NC
PL INT2
MA OUT
SUB OUT
I TIME
VRS
V
CC
GND
VE
VE OUT
VCA IN
VCA TC
VE
Mode Display
– 3 –
CXA1124BS/BQ, CXA1534S/Q
Pin Description and Equivalent Circuit (Ta = 25°C, VCC = 9V)
Pin No. Symbol Voltage (Typ.) Equivalent circuit Description
SDIP
1 44 SAP TC 3.4V Sets the time constant of
the SAP carrier detection
circuit.
Drives LED when stereo
broadcasting is on.
Open collector output.
Drives LED when SAP
broadcasting is on.
GND of LED.
Control pin of SAP VCO
oscillation frequency. SAP
VCO oscillating frequency
can be varied by applying
DC voltage to this pin.
Normally a resistance or a
variable resistance is
connected.
Output pin of SAP FM
detector.
0.2V
0.2V
4.5V
4.5V
ST LED
SAP LED
LED G
VC SAP
SAP OUT
245
346
447
548
61
QFP
1
VCC
12µA
GND
25µA
10k1k
8k
15k LED G
68k
VCC
2
15k LED G
68k
VCC
3
20k
40k
VCC
50µA
5
20k
10k
GND
147 500
VCC
GND
6500
– 4 –
CXA1124BS/BQ, CXA1534S/Q
SDIP
72M1 L: GND to 0.8V
H: 2.0V to VCC
Mode control switch pin.
This pin is used in
conjunction with M2 of Pin
8.
83M2 L: GND to 0.8V
H: 2.0V to VCC
Mode control switch pin.
This pin is used in
conjunction with M1 of pin
7.
QFP
147
VCC
GND
7
100k100k
147
VCC
GND
100k100k
8
9 4 FMONO
L: GND to 0.8V
M: 2.0V to VCC – 2.0
H: VCC – 0.5 to VCC
Mode control switch pin.
Has 3 ranges of input,
sets forced monoral mode
and also controls ST.LED.
147
VCC
GND
100k
9
10 5 SMD L: GND to 0.8V
H: 2.0V to VCC
Mode control switch pin.
Controls SOUT pin
output.
147
VCC
GND
100k
10
11 6 FSAP L: GND
H: VCC
Mode control switch pin.
This pin's control voltage
is different from that of
other mode control switch
pins.
100k
VCC
GND
50k
11
Pin No. Symbol Voltage (Typ.) Equivalent circuit Description
– 5 –
CXA1124BS/BQ, CXA1534S/Q
SDIP
12 8 MUTE L: GND to 0.8V
H: 2.0V to VCC
Mode control switch pin.
By setting this pin to H
level all outputs turn to
mute.
13 9 I SAP 1.3V
Sets the reference current
of SAP filters.
By adjusting the current
that flows into this pin the
cut off frequency can be
changed.
QFP
147
VCC
GND
100k
12
147
VCC
GND
30k 30k
11µA
13
14 10 I LPF 1.3V
Sets the reference current
of stereo and dbx-TV NR
filters. By adjusting the
current that flows into this
pin the respective cut off
frequency can be
changed.
147
VCC
GND
30k 30k
11µA
14
15 11 I VCO 1.3V
Sets the reference current
of stereo VCO and SAP
VCO. By adjusting the
current that flows into this
pin the respective
oscillation frequency can
be changed.
147
VCC
GND
30k 30k
11µA
15
16 12 E SAP 4.5V Inputs SAP signal from
the external dbx-TV NR
(option).
147
VCC
GND
47k
16
Pin No. Symbol Voltage (Typ.) Equivalent circuit Description
– 6 –
CXA1124BS/BQ, CXA1534S/Q
SDIP
17 13 R OUT 4.5V Rch output pin.
18 15 L OUT 4.5V Lch output pin.
QFP
147 500
VCC
GND
500 15k
17
147 500
VCC
GND
500 15k
18
19 16 S OUT 4.5V
Optional output pin. From
this pin monaural or SAP
(only when the external
dbx-TV NR is connected)
is output.
147 500
VCC
GND
500
19
20 17 NR BPF 4.5V Pin for the filter monitor of
dbx-TV block.
147
VCC
GND
20
25p
9.7p
15k
15k
21 18 SAP IN 4.5V Inputs the signal from
SAP OUT of pin 6.
147
VCC
GND
47k
21
Pin No. Symbol Voltage (Typ.) Equivalent circuit Description
– 7 –
CXA1124BS/BQ, CXA1534S/Q
SDIP
22 20 VE WGT 4.5V
Weighting pin of the
variable de-emphasis
control RMS value
detection circuit.
23 21 MAIN IN 4.5V Inputs (L + R) signal from
MAIN OUT of pin 36.
QFP
147 500
VCC
GND
22
500
147
VCC
GND
47k
23
24 22 ST IN 4.5V Inputs (L – R) signal from
SUB OUT of pin 35.
147
500
VCC
GND
24
47k
25 23 VE TC 2V
Determines the recovery
time constant of the
variable de-emphasis
control RMS value
detection circuit.
By connecting a 3.3µF
capacitance, normal
recovery time constant
can be obtained.
20k
VCC
GND
1k
25
26 24
VCA WGT
4.5V Weighting pin of VCA
control RMS value
detection circuit.
147 500
VCC
GND
500
26
Pin No. Symbol Voltage (Typ.) Equivalent circuit Description
– 8 –
CXA1124BS/BQ, CXA1534S/Q
SDIP
27 25 VCA TC 2V
Determines the recovery
time constant of VCA
control RMS value
detection circuit.
By connecting a 10µF
capacitance, normal
recovery time constant
can be obtained.
28 26 VCA IN 4.5V
VCA input pin. Through a
coupling capacitor, input
the variable de-emphasis
output signal of pin 29.
QFP
20k
VCC
GND
1k
27
20k
VCC
GND
47k
28
29 27 VE OUT 4.5V Variable de-emphasis
output pin.
147 500
VCC
GND
500 10k
29
30 28 VE 4.5V Variable de-emphasis
integral pin.
31
—
—
32
29
19
43
30
GND
GND1
GND2
VCC
GND
GND
30 147
VCC
GND
7.5k
1.25k
33 31 VRS 4.5V
Reference potential pin of
the signal. Voltage
becomes half that of the
supply voltage.
VCC
GND
10k
26µA
33
10k
Pin No. Symbol Voltage (Typ.) Equivalent circuit Description
– 9 –
CXA1124BS/BQ, CXA1534S/Q
SDIP
34 32 I TIME 1.3V
Input pin for the timing
current of the RMS value
detection. The timing
current determines the
normal time constant of
the detection circuit and
the variable de-emphasis
characteristics.
35 33 SUB OUT 4.5V Output pin of L – R signal.
QFP
147
VCC
GND
30k 30k
11µA
34
147 500
VCC
GND
500
35
36 34 MA OUT 4.5V Output pin of L + R signal.
147
VCC
GND
15k
200µA
36
37 35 PL INT2
For stereo:
5.5V
For monaural:
3.5V
Integral pin of the pilot
cancel circuit loop filter.
2.7k
VCC
50µA
45k
GND
2k
147 147
37
38 37 PL INT1 4.5V
10µA
30k GND
38
VCC
147
Pin No. Symbol Voltage (Typ.) Equivalent circuit Description
– 10 –
CXA1124BS/BQ, CXA1534S/Q
SDIP
39 38 COMP IN 4.5V Audio multiplex signals
are input through this pin.
40 39 PC INT2 4.5V
Integral pin of the stereo
block PLL loop filter.
QFP
18µA
50k
GND
39
1 / 2VCC
VCC
147
10k
VCC
50µA
2k
GND
10k
40
147
41 40 PC INT1 4.5V
VCC
10µA
30k GND
41 147
42 41 SAP BPF 4.5V SAP BPF monitor pin.
2k
VCC
GND
147
42
Pin No. Symbol Voltage (Typ.) Equivalent circuit Description
– 11 –
CXA1124BS/BQ, CXA1534S/Q
Electrical Characteristics
(Unless otherwise specified, Ta = 25°C, VCC = 9V, 0dB = 100% modulation level, FH = 15.734kHz)
100% modulation level →Main (L + R) level = –10dBm (245mVrms) (Pre-Emphasis On)
(Reference level) Sub (L – R) level = –4dBm (490mVrms) (dbx-TV OFF)
Pilot level = –24.0dBm (49mVrms)
SAP level = –14.4dBm (147mVrms) (10kHz peak deviation, dbx-TV OFF)
The reference input levels of the CXA1534 (at Pin 39) are 1/2.45 times the equivalent values at the head of
this page. The Main level is 100mVrms.
Stereo section (Including operation supply voltage and consumption circuit)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Operating
supply voltage
Consumption
current
Main
output level
De-emphasis
frequency
response
Main LPF
frequency
response
Main distortion
ratio
Main Max.
output level
Main noise
Sub output level
Sub LPF
frequency
response
Sub distortion
ratio
Sub Max.
output level
Sub noise
level
Sub pilot cancel
Stereo On
level
VCC
ICC
Vmain
FCdeem
FCmain
THDm
Vmmax
Vnmain
Vsub
FCsub
THDsub
Vsmax
Vsubn
PCsub
THst
—
ST.
ST.
ST.
ST.
ST.
ST.
ST.
—
—
—
—
—
—
—
—
—
Pin 39
Pin 39
Pin 39
Pin 39
Pin 39
—
Pin 39
Pin 39
Pin 39
Pin 39
—
Pin 39
Pin 39
—
—
Pin 17
Pin 18
Pin 17
Pin 18
Pin 17
Pin 18
Pin 17
Pin 18
Pin 17
Pin 18
Pin 17
Pin 18
Pin 35
Pin 35
Pin 35
Pin 35
Pin 35
Pin 35
—
No signal
No signal
Main 1kHz, 0dB,
75µs, pre-emphasis
ON
Main 5kHz,
–10dB, 75µs,
pre-emphasis ON
Main 12kHz,
–20dB, 75µs,
pre-emphasis ON
Main 1kHz, 0dB,
75µs,
pre-emphasis ON
15kHz LPF used
Main 1kHz,
THD = 3%,
75µs,
pre-emphasis ON
No signal
15kHz LPF used
Sub 1kHz, 0dB
Sub 12kHz,
–10dB
Sub 1kHz, 0dB,
15kHz LPF used
Sub 1kHz,
THD = 3%
No signal
15kHz LPF used
Pilot: fH
(–24dBm)
fH BPF used
Varies Pilot input.
Tests the level
where LED lights
up. Turns Pin 9
(FMONO) to L or M.
4.7
17
–5.0
–1.0
–3.0
—
2.0
—
–10.5
–3.0
—
–2.0
—
—
–9.5
25
–4.0
0
–1.0
0.1
9.0
–73
–9.0
–0.4
0.1
6.0
–75
–53
–6.5
10.0
33.0
–3.0
1.0
1.0
0.5
—
–65
–5.5
1.0
1.0
–65
–40
–4.0
V
mA
dBm
dB
dB
%
dBm
dBm
dBm
dB
%
dBm
dBm
dBm
dB
No. Item Symbol Condition Min. Typ. Max. Unit
Mode Input Output Others
– 12 –
CXA1124BS/BQ, CXA1534S/Q
16
17
18
19
20
SAP output level
SAP frequency
characteristics
SAP distortion
ratio
SAP noise level
SAP ON level
Vsap
FCsap
THDsap
VNsap
THsap
—
—
—
—
—
Pin 39
Pin 39
Pin 39
Pin 39
Pin 39
Pin 6
Pin 6
Pin 6
Pin 6
1kHz, 0dB
10kHz, –10dB
1kHz, 0dB,
15kHz LPF used
Input 5fH
(–14.4dBm)
15kHz LPF used
Varies SAP carrier
(no demodulation)
input level. Tests
level where Pin 3
LED lights up.
–10.5
–3.0
—
—
–14.0
–9.4
–0.6
2.5
–65
–10.0
–7.5
+2.0
6.0
–40
–7.0
dBm
dB
%
dBm
dB
dbx-TV section
Note) To test the dbx-TV timing current of other than pin 34 input pilot to COMP IN (Pin 39) and turn it to ST
mode. Also, turn MAIN IN (Pin 23) open.
21
22
23
24
25
26
27
dbx-TV decode
characteristics
300Hz, –5dB
dbx-TV decode
characteristics
300Hz, –15dB
dbx-TV decode
characteristics
300Hz, –30dB
dbx-TV decode
characteristics
1kHz, 0dB
dbx-TV decode
characteristics
1kHz, –10dB
dbx-TV decode
characteristics
1kHz, –20dB
dbx-TV decode
characteristics
8kHz, 0dB
Vdc-1
Vdc-2
Vdc-3
Vdc-4
Vdc-5
Vdc-6
Vdc-7
ST.
ST.
ST.
ST.
ST.
ST.
ST.
Pin 24
Pin 24
Pin 24
Pin 24
Pin 24
Pin 24
Pin 24
Pin 17
Pin 18
Pin 17
Pin 18
Pin 17
Pin 18
Pin 17
Pin 18
Pin 17
Pin 18
Pin 17
Pin 18
Pin 17
Pin 18
300Hz, –17dBm
300Hz, –27dBm
300Hz, –42dBm
1kHz, –12dBm
1kHz, –22dBm
1kHz, –32dBm
8kHz, –12dBm
1.5
–18.5
–48.5
–2.7
–23.4
–43.6
–8.3
3.0
–17.0
–47.0
–0.7
–21.4
–41.6
–5.8
4.5
–15.5
–45.5
+1.3
–19.4
–39.6
–3.3
dBm
dBm
dBm
dBm
dBm
dBm
dBm
SAP section
No. Item Symbol Condition Min. Typ. Max. Unit
Mode Input Output Others
No. Item Symbol Condition Min. Typ. Max. Unit
Mode Input Output Others
– 13 –
CXA1124BS/BQ, CXA1534S/Q
28
29
30
31
32
33
34
dbx-TV decode
characteristics
8kHz, –10dB
dbx-TV decode
characteristics
8kHz, –15dB
dbx-TV
distortion ratio
dbx-TV Max.
output level
300Hz
dbx-TV Max.
output level
8kHz
dbx-TV
Noise level
dbx-TV
Timing current
Vdc-8
Vdc-9
THDnr
Vnrmax
L
Vnrmax
H
Vnnr
Itime
ST.
ST.
ST.
ST.
ST.
ST.
—
Pin 24
Pin 24
Pin 24
Pin 24
Pin 24
—
—
Pin 17
Pin 18
Pin 17
Pin 18
Pin 17
Pin 18
Pin 17
Pin 18
Pin 17
Pin 18
Pin 17
Pin 18
—
8kHz, –22dBm
8kHz, –27dBm
1kHz, –15dBm
THD = 3%
THD = 3%
15kHz LPF used
Applies 3V voltage to
pins 25 and 27 and
tests respective input
current
–34.9
–49.2
—
2.0
2.0
—
7.1
–32.4
–46.7
0.3
9.0
8.0
–88
7.5
–29.9
–44.2
0.8
—
—
–80
7.9
dBm
dBm
%
dBm
dBm
dBm
µA
Mode Matrix Control Voltage section
35
36
37
38
39
Control
voltage 1
H level
Control
voltage 1
L level
Control
voltage 2
H level
Control
voltage 2
M level
Control
voltage 2
L level
V-HC1
V-LC1
V-HC2
V-MC2
V-LC2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Pin 7, 8, 10, 12
Control voltage
for pin 9
(FMONO) only
2.0
GND
VCC – 0.5
2.0
GND
—
—
VCC
0.8
VCC
VCC – 2.0
0.8
V
V
V
V
V
No. Item Symbol Condition Min. Typ. Max. Unit
Mode Input Output Others
No. Item Symbol Condition Min. Typ. Max. Unit
Mode Input Output Others
– 14 –
CXA1124BS/BQ, CXA1534S/Q
Electrical Characteristics Test Circuit
R4 43k
(METAL)
C4
0.47µ
CXA1124BS/CXA1534S
22
23
24
25
2627
28
29
30
40 39 38 37 36 35 34 31
32
33
4142
2345678910 11 12 13 14 15 16 17 18 19 20 21
1
C18
0.47µ R8
820 R9
820
R18
10k
R19
10k
SW11
SW4 SW5 SW6 SW7 SW8 SW9 R10
47k
VR3
47k
R11
47k
VR4
47k
R12
47k
VR5
47k
R15
100k
R16
100k R17
100k
C21
4.7µ
C20
4.7µ
C19
4.7µ
C22
4.7µ
C23
4.7µ
R12
100k
R14
2.7k
R15
7.5k
LED2
LED1 FILTER MEASURE-
MENT
Instructions for test filter
15kHz LPF:
fH BPF :
13kHz (–3dB)
15kHz (–46dB)
2fH (15.734kHz)
Band width 1.5kHz
C16
1µ
VR2
5k
C15
4.7µ
C14
4.7µ
C8
4.7µ
3V
VCC = 9V
AUDIO SG R4
600
R7
100k
C17
4.7µ
SW3
C10
1µ
R6
3.9k
SW2
C9
10µ
C13
1000p (TANTAL)
R5
2.7k
C7
3300p
C9 10µ
(TANTAL)
C6
100µ
C5
47µ
VR1
10k SW1
SG R1
600
C2
0.012µ
R2
100k
C1
5600p
R3
1M
C3
4.7µ
SW10
MODE CONTROL SW
Adjustment Procedure
(1) Adjustment of stereo and dbx filters
Input 1.5fH (23.6kHz: –10dBm) sine wave to pin 39 (COMP IN) and monitor pin 36 (MAIN OUT). Adjust
the variable resistor of pin 14 (I LPF) to reduce the output to a minimum.
(2) Adjustment of SAP filter
Input 6.2fH (97.55kHz: –14.4dBm) sine wave to pin 39 and monitor pin 42 (SAP BPF). Adjust the variable
resistor of pin (I SAP) to reduce the output to a minimum.
(3) VCO adjustment
Adjust pin 15 (I VCO) volume so as to obtain an identical value whether Pin 40 (PC INT2) DC value has
input pilot (fH = 15.734kHz: –24dBm) or not.
Note) At this point, check to see that the ST.LED of pin 2 is ON.
If the LED is OFF, turn up the variable resistor until the ST.LED lights up.
(4) Adjustment of stereo seperation
1. Create the stereo mode (by causing the 1 pin (pin 7) to be H and the M2 pin (pin 8) to be L) and input
Lch-only signal (30% modulation depth and 300Hz frequency) to pin 39. Then adjust the variable
resistor of pin 35 (SUB OUT) to reduce the Rch output to a minimum.
2. Then change only the frequency of the input signal to 3kHz and adjust the variable resistor of pin 22
(VE WGT) to reduce the Rch output to a minimum.
3. Repeat Steps 1 and 2 described above until an optimum separation is achieved.
The adjustment frequency is a combination of either 300Hz and 3kHz or 400Hz and 2kHz.
– 15 –
CXA1124BS/BQ, CXA1534S/Q
Mode Matrix No.1
∗FSAP →GND (SAP discrimination Automatic select mode)
Broadcast
Mode
MONO
MONO
+ SAP
STEREO
STEREO
+ SAP
LED
ST.
OFF
OFF
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON
OFF
OFF
ON
OFF
ON
L
L
H
H
L
L
H
H
L
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
L
H
L
H
L
H
L
H
L
L
L
H
H
H
L
L
L
H
H
L
L
L
H
H
H
L
L
L
H
H
—
—
—
—
—
—
—
—
L
M
H∗
L
M
H∗
L
M
H∗
L, M
H∗
L
M
H∗
L
M
H∗
L
M
H∗
L, M
H∗
GND
GND
GND
GND
L + R
L + R
L + R
MUTE
L + R
SAP
L + R
MUTE
L
L + R
L + R
L
L + R
L + R
L
L + R
L + R
MUTE
MUTE
L + R
L + R
L + R
SAP
SAP
SAP
L
L + R
L + R
MUTE
MUTE
L + R
L + R
L + R
MUTE
SAP
SAP
L + R
MUTE
R
L + R
L + R
R
L + R
L + R
R
L + R
L + R
MUTE
MUTE
SAP
SAP
SAP
SAP
SAP
SAP
R
L + R
L + R
MUTE
MUTE
Pin Output
M1 M2 FMONO FSAP* LOUT ROUTSAP
∗H; VCC – 0.5 to VCC
– 16 –
CXA1124BS/BQ, CXA1534S/Q
Mode Matrix No.2
∗FSAP →VCC (SAP discrimination fixing mode)
Broadcast
Mode
MONO
MONO
+ SAP
STEREO
STEREO
+ SAP
LED
ST.
OFF
OFF
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON
ON
OFF
ON
OFF
OFF
ON
OFF
ON
L
L
H
H
L
L
H
H
L
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
L
H
L
H
L
H
L
H
L
L
L
H
H
H
L
L
L
H
H
L
L
L
H
H
H
L
L
L
H
H
—
—
—
—
—
—
—
—
L
M
H∗
L
M
H∗
L
M
H∗
L, M
H∗
L
M
H∗
L
M
H∗
L
M
H∗
L, M
H∗
VCC
VCC
VCC
VCC
L + R
MUTE
L + R
MUTE
L + R
SAP
L + R
MUTE
L + R
L + R
L + R
MUTE
MUTE
MUTE
L
L + R
L + R
MUTE
MUTE
L + R
L + R
L + R
SAP
SAP
SAP
L
L + R
L + R
MUTE
MUTE
MUTE
MUTE
L + R
MUTE
SAP
SAP
L + R
MUTE
MUTE
MUTE
MUTE
MUTE
MUTE
MUTE
R
L + R
L + R
MUTE
MUTE
SAP
SAP
SAP
SAP
SAP
SAP
R
L + R
L + R
MUTE
MUTE
Pin Output
M1 M2 FMONO FSAP∗LOUT ROUTSAP
∗H: VCC – 0.5 to VCC
– 17 –
CXA1124BS/BQ, CXA1534S/Q
Mode Matrix No.3
∗SMD, FMONO pin mode control function
SMD · FUNCTION
Broadcast
Mode
•MONO
•STEREO
•MONO
+ SAP
•STEREO
+ SAP
SAP
LED
OFF
ON
L
H
L
H
L
H
L
H
VCC
VCC
GND
GND
VCC
VCC
GND
GND
L + R
Ext∗
L + R
L + R
L + R
SAP∗
L + R
SAP∗
Pin Output
FSAP SOUTSMD
∗SAP: When external dbx-TV (Option) is connected
∗EXT: Signal input to pin16 (ESAP)
Pin Output
MUTE
L
H
LOUT ROUT SOUT
Mute OFF
Mute ON
MUTE · FUNCTION
– 18 –
CXA1124BS/BQ, CXA1534S/Q
Description of Operation
The U.S. dbx system has the base band spectrum shown in Fig. 1.
6.5fH6fH5fH4fH3fH2fHfHf
fH = 15.734kHz
3
15
TELEMETRY
FM 3kHz
SAP
dbx-TV NR
FM 10kHz
50 – 10kHz
50
L – R
dbx-TV
NR
AM-DSB-SC
L + R
50 – 15kHz
2525
50
kHz
PEAK DEV
5
PILOT
Fig. 1. Base band spectrum
MAIN LPF
23
24
39 36
35
6
16
17
18
19
21
PLL
VCO
8fH
fH ∠ 90°
2fH ∠ 0°
fH ∠ 0° PILOT
DET MODE
CONTROL
ST. LED
DRIVE
PILOT
CANCEL
STEREO LPF DE. EM
L – R
(DSB)
DET
SUB LPF
(ST IN)
4.7µ
(SAP IN)
4.7µ
SAP BPF
4.7µ
SUP LPF
INJ.
LOCK
SAP
DET MODE
CONTROL
SAP LED
DRIVE
SAP (FM)
DET
(SUB OUT)
L – R
(SAP OUT)
10k
L + R
(MAIN IN)(MAIN OUT)
NR SW
MODE
CONTROL
dbx-TV
BLOCK
(A) (B)
MATRIX (L-OUT)
(R-OUT)
(S-OUT)
(E SAP)
EXT
dbx-TV
(COMP IN)
Fig. 2. Whole block diagram (See Fig. 3 for dbx-TV block)
LPF
LPF
HPF
VARIABLE
DEEMPHASIS
FIXED
DEEMPHASIS
28
29
24
21
NR SW (A) (B) TO
MATRIX
VCA
4.7µ
RMS
DET
RMS
DET
(VE OUT) (VCA IN)
Fig. 3. dbx-TV block
– 19 –
CXA1124BS/BQ, CXA1534S/Q
(1) L + R (MAIN)
The dbx signal is input from pin 39 (COMP IN) and led to the STEREO LPF which suppresses the SAP
and telemetry signals. Then the pilot signal is cannceled. In the last stage the L – R and SAP signals are
removed by the MAIN LPF and the frequency response made flat by the de-emphasis before the L + R
signal is input to the matrix.
(2) L – R (SUB)
The L – R signal follows the same route as does the L + R signal before the pilot signal is canceled. The L
– R signal has no carrier signal, as it is a suppressed-carrier double-sideband amplitude-modulated (DSB-
AM) signal. For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave) to be
used for demodulation of the L – R signal. In the last stage the residual high frequency components are
removed by the SUB LPF before the L – R signal is input through the NRSW circuit to the dbx-TV block.
(3) SAP
The SAP, as shown in Fig. 1, is an FM signal using 5fH as carrier. The SAP signal alone is first extracted,
then FM components are detected. Finally, residual high-frequency components are removed by the SAP-
LPF, the f characteristics are flattened, and the SAP signal is input through the NRSW circuit to the dbx-
TV block. If there is no SAP signal, the output from Pin 6 is muted.
(4) Mode discrimination
Stereo mode is identified by detecting the pilot signal amplitude. SAP mode is identified by detecting the
5fH carrier and noise around 20kHz after FM detection.
(5) dbx-TV block
The SAP and L – R signals respectively input to pin 24 (ST IN) and pin 21 (SAP IN) are fed to the NRSW
circuit where either one of them is selected by the mode control and is input to the dbx-TV block.
The input signal to the block is passed through the fixed de-emphasis circuit and is applied to the variable
de-emphasis circuit. The output from the circuit is passed through an externally mounted capacitance and
applied to the VCA (Voltage Controlled Amplifier). The output from VCA is converted from a current to a
voltage by the operational amplifier before it is input to the matrix.
The transfer function of the variable de-emphasis circuit and the gain of the VCA are controlled by the
respective RMS detector circuits. Each of the RMS detector circuits passes the input signal through a
predetermined filter to properly weight it befor detecting the rms value of the weighted signal to provide a
control signal.
– 20 –
CXA1124BS/BQ, CXA1534S/Q
MUTE
C5
0.47µ
CXA1124BS/CXA1534S
22
23
24
25
2627
28
29
30
40 39 38 37 36 35 34 31
32
33
4142
2345678910 11 12 13 14 15 16 17 18 19 20 21
1
C1
0.47 to
4.7µ
R1
820 R4
820
R9
44.2k
R12
47k
R11
22k
R14
47k
R13
47k
C14
4.7µ
C12
4.7µ
C10
4.7µ
C17
4.7µ
R6
2.7k
R5
7.5k
D2
D1
dbx-TV
C18
0.047µ
R16
4.7k
C16
4.7µ
C15
4.7µ
C8
4.7µ
VCC = 4.7 to 10V
C11
1µ
R15
3.9k
C9 10µ
(TANTAL) C13 3.3µ
(TANTAL)
R10
3.3k
C7
2700p
C6
47µ
R8 43k
(METAL)
R7
5k
COMP IN
C3
0.012µ
R2
100k
C2
5600p
R3
1M
C4
4.7µ
M1 M2 FMONOSMD F SAP
MODE CONTROL SW
R17
100k
CXA1011
R OUTL OUTS OUT
R12
R9 ; (METAL)
; 47k (METAL)
//750k (CARBON)
R17
5.6k
Precautions in usage of application circuit 1
1) Use VCC at 4.7 to 10V. (recommended value: 9V)
2) Adjustment of stereo and SAP filters is executed simultaneously.
Adjustment is performed through the stereo filter (Pin 14 (I LPF) volume). Here, to obtain the most suitable
stereo separation, set the adjustment signal frequency to 22.9kHz.
3) dbx-TV connected between Pin 6 (SAP OUT) and Pin 16 (E SAP) is an option.
Connect a dbx-TV system LSI (CXA1011 for example). Then SAP or L + R signal can be output from Pin
19 (S OUT).
4) Pin 1 capacity value determines mute (or Stereo automatic select) speed when SAP carrier is OFF and
SAP discriminating stability at a low intensity electric field. Shrinking the capacitance raises MUTE speed
to minimize the switching noise. However discriminating stability is adversely affected. Inversely, when the
capacitance is increased it improves stability whereas switching noise grows bigger.
5) Pin 5 is used for fine adjustment of the free-running frequency of the SAP VCC. It is used under normal
open conditions if the DC offset at Pin 6 (SAP OUT) causes problems, with the SAP carrier either there or
not, connect a resistor of about 100kΩbetween Pin 6 and GND.
6) Use a nonpolarized capacitor for C5.
7) If a noise channel is received is at Pin 6 (SAP OUT) noise of several tens of mVp-p will be output (because
of soft mute).
Application Circuit 1
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 21 –
CXA1124BS/BQ, CXA1534S/Q
MUTE
C5
0.47µ
CXA1124BS/CXA1534S
22
23
24
25
2627
28
29
30
40 39 38 37 36 35 34 31
32
33
4142
2345678910 11 12 13 14 15 16 17 18 19 20 21
1R1
820 R6
47k R9
47k
R8
47k
R11
47k
R10
47k
C12
4.7µ
C10
4.7µ
D1
C16
0.047µ
R13
4.7k
C15
4.7µ
C14
4.7µ
C8
4.7µ
VCC = 4.7 to 10V
C11
1µ
R12
3.9k
C9 10µ
(TANTAL) C13 3.3µ
(TANTAL)
R7
3.3k
C7
2700p
C6
47µ
R5 43k
(METAL)
R4
5k
COMP IN
C3
0.012µ
R2
100k
C2
5600p
R3
1M
C4
4.7µ
FMONO
MODE CONTROL SW R OUT L OUT
R14
5.6k
Note) Use a nonpolarized capacitor for C5.
Application Circuit 2 (When SAP is not used)
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 22 –
CXA1124BS/BQ, CXA1534S/Q
0Frequency [kHz]
Gain [dB]
10
Stereo LPF Frequency characteristics
20 40 60 80 100
5
0
–5
–10
30
10
–10
–30
–40
–50
20
0
–20
1Frequency [kHz]
Gain & [dB]
Frequency characteristics
7102 5 50 10020 70
FC main
FC sub
Main LPF
Sub LPF
–20
Frequency [kHz]
20 40 60 80 100 120
–10
0
10
20
Gain [dB]
SAP Frequency characteristics and Group delay
10
30
50
70
90
20
40
60
80
100
0
Group delay [µs]
Group delay
6.2fH3.8fH
Gain
5fH
Standard level (100%)
–10 0 10
Input level [dB]
T.H.D. [%]
0.01
0.1
1.0
LINE OUT input vs.
Distortion characteristics 1 (Mono)
Input signal Mono (Pre-Emphasis ON) 1kHz
0dB = 100% Modulation level
VCC = 9V, 30kHz LPF ON, ST. mode
–10 0 10
Input level [dB]
T.H.D. [%]
0.1
1.0
10.0
LINE OUT input vs.
Distortion characteristics 2 (stereo)
Input signal Stereo L = –R (dbx-TVNR ON) 1kHz
0dB = 100% Modulation level
VCC = 9V, 15KHz LPF ON, ST. mode
Standard level (100%)
–10 0 10
Input level [dB]
T.H.D. [%]
0.1
1.0
10.0
LINE OUT input vs.
Distortion characteristics 3 (SAP)
Input signal SAP (dbx-TVNR ON) 1kHz
0dB = 100% Modulation level
VCC = 9V, 30kHz LPF ON, SAP mode
Standard level (100%)
Examples of Representative Characteristics
– 23 –
CXA1124BS/BQ, CXA1534S/Q
Package Outline Unit: mm
CXA1124BS/CXA1534S
CXA1124BS
42PIN SDIP (PLASTIC) 600mil
37.8 + 0.4
– 0.1
13.0 + 0.3
– 0.1
0.25 + 0.1
– 0.05
42 22
121
1.778 ± 0.25
15.24 ± 0.25
0° to 15°
4.6 + 0.4
– 0.1
0.5 ± 0.1
0.9 ± 0.15
3.0 MIN 0.5 MIN
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY RESIN
SOLDER PLATING
COPPER / 42 ALLOY
SDIP-42P-02
SDIP042-P-0600-A
4.4g
42PIN SDIP (PLASTIC) 600mil
36.6+ 0.4
– 0.1
13.2+ 0.3
– 0.1
0.25 + 0.1
– 0.05
42 22
121
1.778 ± 0.25
15.24 ± 0.25
0° to 15°
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY RESIN
SOLDER PLATING
COPPER / 42 ALLOY
SDIP-42P-04
∗SDIP042-P-0600-C
4.5 + 0.4
– 0.1
0.5 ± 0.1
0.9 ± 0.15
3.0 MIN 0.51 MIN
4.4g
– 24 –
CXA1124BS/BQ, CXA1534S/Q
CXA1124BQ/CXA1534Q
SONY CODE
EIAJ CODE
JEDEC CODE
M
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY RESIN
SOLDER / PALLADIUM
PLATING
COPPER / 42 ALLOY
48PIN QFP (PLASTIC)
15.3 ± 0.4
12.0 – 0.1
+ 0.4
0.8 0.3 – 0.1
+ 0.15
± 0.12
13
24
2536
37
48
112
2.2 – 0.15
+ 0.35
0.9 ± 0.2
0.1 – 0.1
+ 0.2
13.5
0.15
0.15 – 0.05
+ 0.1
QFP-48P-L04
∗QFP048-P-1212-B
0.7g
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).