User's Guide SLLU095 - March 2007 TAS5142DDV6EVM2 This user's guide describes the operation of the evaluation module for the TAS5142 digital amplifier power output stage using the TAS5086 digital audio PWM processor from Texas Instruments. The user's guide also provides measurement data and design information, including schematic, BOM, and PCB layout. Contents 1 Overview ............................................................................................. 2 2 Quick Setup Guide ................................................................................. 6 3 Protection ............................................................................................ 9 4 TAS5142DDV6EVM Performance .............................................................. 10 5 Related Documentation from Texas Instruments ............................................. 16 Appendix A Design Documents ...................................................................... 17 List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A-1 A-2 A-3 A-4 A-5 A-6 A-7 A-8 A-9 A-10 A-11 A-12 Integrated PurePath Digital Amplifier System .................................................. 4 Physical Structure for the TAS5142DDV6EVM2 (Approximate Layout)..................... 5 TAS5086 GUI Window ............................................................................. 7 THD+N vs Power (4 )........................................................................... 11 THD+N vs Power (6 )........................................................................... 11 THD+N vs Power (8 )........................................................................... 12 THD+N vs Frequency (4 ) ..................................................................... 12 THD+N vs Frequency (6 ) ..................................................................... 12 THD+N vs Frequency (8 ) ..................................................................... 12 FFT Spectrum With -60 dBFS Tone ........................................................... 13 Idle Noise FFT Spectrum ........................................................................ 13 Channel Separation ............................................................................... 13 Frequency Response ............................................................................. 13 High Current Protection .......................................................................... 14 Pop/Click ........................................................................................... 14 Output Stage Efficiency .......................................................................... 15 TAS5142DDV6EVM2 Schematic (Sheet 1 of 7) .............................................. 17 TAS5142DDV6EVM2 Schematic (Sheet 2 of 7) .............................................. 18 TAS5142DDV6EVM2 Schematic (Sheet 3 of 7) .............................................. 19 TAS5142DDV6EVM2 Schematic (Sheet 4 of 7) .............................................. 20 TAS5142DDV6EVM2 Schematic (Sheet 5 of 7) .............................................. 21 TAS5142DDV6EVM2 Schematic (Sheet 6 of 7) .............................................. 22 TAS5142DDV6EVM2 Schematic (Sheet 7 of 7) .............................................. 22 Component Layout ................................................................................ 26 Solder Side......................................................................................... 27 Component Side .................................................................................. 28 Component Placement ........................................................................... 29 Silkscreen .......................................................................................... 30 PurePath Digital, Equibit are trademarks of Texas Instruments. Pozidriv is a trademark of American Screw Company. Windows is a trademark of Microsoft Corporation. All other trademarks are the property of their respective owners. SLLU095 - March 2007 Submit Documentation Feedback TAS5142DDV6EVM2 1 www.ti.com Overview A-13 Heat Sink ........................................................................................... 31 List of Tables 1 2 3 4 5 6 7 8 9 A-1 1 TAS5142DDV6EVM2 Specification .............................................................. 2 Recommended Supply Voltages ................................................................. 6 TAS5142 Warning/Error Signal Decoding ....................................................... 9 General Test Conditions ......................................................................... 10 TAS5086 Register Settings ...................................................................... 10 Electrical Data ..................................................................................... 10 Audio Performance ............................................................................... 11 Thermal Specification............................................................................. 11 Physical Specifications ........................................................................... 11 Parts List ........................................................................................... 23 Overview The TAS5142DDV6EVM2 PurePath DigitalTM customer evaluation module demonstrates the integrated circuits TAS5142DDV and TAS5086DBT from Texas Instruments (TI). The TAS5142DDV is a high-performance, integrated stereo digital amplifier power stage designed to drive 4- speakers at up to 100 W per channel. The device incorporates TI's EquibitTM technology and is designed to be used with TI's Equibit modulators. This system requires only a simple passive demodulation filter to deliver high-quality, high-efficiency audio amplification. TAS5086DBT is a high-performance 32-bit (24-bit input) multichannel PurePath Digital pulse width modulator (PWM) based on Equibit technology with a new, fully symmetrical AD modulation scheme. This EVM is configured with 6 BTL channels. This EVM, together with a TI input-USB board, is a complete 5.1-channel digital audio amplifier system that includes digital input (S/PDIF), analog inputs, interface to PC, and DAP features like digital volume control, input and output multiplexers. Table 1. TAS5142DDV6EVM2 Specification Key Parameters 2 Values Output stage supply voltage 0 V-32 V System supply voltage 15 V-20 V Number of channels 6 x BTL Load impedance 4 -8 Output power 100 W/4 , 10 % THD+N Dynamic range >105 dB PWM processor TAS5086DBT Output stage TAS5142DDV TAS5142DDV6EVM2 SLLU095 - March 2007 Submit Documentation Feedback www.ti.com Overview This 5.1 system is designed for home theater applications such as A/V receivers, DVD receivers, DVD mini-component systems, or home theater in a box (HTIB). This document covers EVM specifications, audio performance, power efficiency measurement graphs, and design documentation that includes schematics, parts list, layout, and mechanical design. J001 The EVM is delivered with cables and input-USB board to connect to an input source and be controlled from a PC. 1.1 TAS5142DDV6EVM2 Features * * * * 6-channel PurePath Digital evaluation module Self-contained protection system (short-circuit and thermal) Standard I2S and I2C/control connector for TI input board Double-sided plated-through PCB layout SLLU095 - March 2007 Submit Documentation Feedback TAS5142DDV6EVM2 3 www.ti.com Overview POWER SUPPLY Channel 1 (BTL) 8-Channel Analog Input TAS5142 Channel 2 (BTL) USB Interface Channel 3 (BTL) Control Interface TAS5086 TAS5142 Channel 4 (BTL) 2 I C Bus Optical and Coaxial S/PDIF Input Input-USB board Channel 5 (BTL) 2 I S Bus TAS5142 Channel 6 (BTL) TAS5142DDV6EVM2 Module B0228-01 Figure 1. Integrated PurePath Digital Amplifier System 4 TAS5142DDV6EVM2 SLLU095 - March 2007 Submit Documentation Feedback www.ti.com Overview 1.2 PCB Key Map Physical structure for the TAS5142DDV6EVM2 is illustrated in Figure 2. J102 PSU Interface (J900) 2-Channel Power Stage TAS5142 3.3-V Regulator Control Interface (J40) J104 J106 Speaker Outputs 2-Channel Power Stage TAS5142 2-Channel Power Stage TAS5142 TAS5086 Speaker Outputs J103 Gate Drive Regulator Input Signal Interface (J60) PSU Interface (J901) J105 5-V Regulator J101 M0078-01 Figure 2. Physical Structure for the TAS5142DDV6EVM2 (Approximate Layout) SLLU095 - March 2007 Submit Documentation Feedback TAS5142DDV6EVM2 5 www.ti.com Quick Setup Guide 2 Quick Setup Guide This chapter describes the TAS5142DDV6EVM2 board regarding power supplies and system interfaces. The chapter provides information on handling and unpacking, absolute operating conditions, and a description of the factory default switch and jumper configuration. This chapter provides a step-by-step guide to configuring the TAS5142DDV6EVM2 for device evaluation. 2.1 Electrostatic Discharge Warning Many of the components on the TAS5142DDV6EVM2 are susceptible to damage by electrostatic discharge (ESD). Customers are advised to observe proper ESD handling precautions when unpacking and handling the EVM, including the use of a grounded wrist strap at an approved ESD workstation. CAUTION Failure to observe ESD handling procedures may result in damage to EVM components. 2.2 Unpacking the EVM On opening the TAS5142DDV6EVM2 package, check to ensure that the following items are included: * 1 pc. TAS5142DDV6EVM2 board using one TAS5086DBT and three TAS5142DDVs * 1 pc. TI input-USB board for interfacing TAS5142DDV6EVM2 with SPDIF/analog sources and PC for control * 1 pc. signal interface IDC cable for connection to an I2S front end, such as the attached TI input-USB board * 1 pc. control interface IDC cable for connection to an I2C front end, such as the attached TI input-USB board * 1 pc. cable for connecting input-USB board to a USB port on a PC for TAS5086 control by software * 1 pc. power-supply cable for two regulated power supplies (H-bridge and system supply) * 1 pc. PurePath CD-ROM If any of these items is missing, contact the Texas Instruments Product Information Center nearest you to inquire about a replacement. Connect the input-USB board to the TAS5142DDV6EVM2 using the two IDC cables provided. 2.3 Power-Supply Setup To power up the EVM, two power supplies are needed, one for system power, logic, and gate-drive, and one for the output-stage supply. Power supplies are connected to the EVM using the provided power cable red/black, white/black. Table 2. Recommended Supply Voltages Description Voltage Limitations Current Requirement Cable System power supply 15 V-20 V 0.3 A Red/black Output-stage power supply 0 V-32 V 10 A White/black CAUTION Applying voltages above the limitations given in Table 2 may cause permanent damage to your hardware. 6 TAS5142DDV6EVM2 SLLU095 - March 2007 Submit Documentation Feedback www.ti.com Quick Setup Guide Note: 2.4 The length of the power-supply cable must be minimized. Increasing the length of the PSU cable increases the distortion for the amplifier at high output levels and low frequencies. Speaker Connection CAUTION Both positive and negative speaker outputs are floating and may not be connected to ground (e.g., through an oscilloscope). 2.5 GUI Software Installation The TAS5086 GUI provides easy control of all registers in TAS5086. To install the GUI, run the setup file from the PurePath CD-ROM. After installation, turn on the power supplies and connect the USB cable to the input-USB board. Start the GUI program from the WindowsTM menu. Start-up of the GUI takes a few seconds. C001 Figure 3. TAS5086 GUI Window SLLU095 - March 2007 Submit Documentation Feedback TAS5142DDV6EVM2 7 www.ti.com Quick Setup Guide From the files menu, load the configuration file: TAS5142DDV6EVM2 Configuration (2.00).cfg The file is located on the PurePath CD-ROM. This file contains all settings for a default setup of the EVM. For easy access of the file, it is recommended to copy the file into the directory where the GUI is installed. Default is C:\Program Files\Texas Instruments Inc\TAS5086\. For more advanced use of the GUI, see the GUI User's Guide on the PurePath CD-ROM and the TAS5086 PurePath Digital Audio Six-Channel PWM Processor data sheet (SLES131). 8 TAS5142DDV6EVM2 SLLU095 - March 2007 Submit Documentation Feedback www.ti.com Protection 3 Protection This chapter describes the short-circuit protection and fault reporting circuitry of the TAS5142 device. 3.1 Short-Circuit Protection and Fault Reporting Circuitry The TAS5142 is a self-protecting device that provides fault reporting (including high-temperature protection and short-circuit protection). The TAS5142 is configured in back-end auto-recovery mode and therefore resets automatically after all errors (M1 and M3 are set low, M2 is set high); see the TAS5142 Stereo Digital Amplifier Power Stage data sheet (SLES126) for further explanation. This means that the device will protect itself after an error condition and report the error through the SD error signal. 3.2 Fault Reporting The OTW and SD outputs from the TAS5142 indicate fault conditions. See the TAS5142 Stereo Digital Amplifier Power Stage data sheet (SLES126) for a description of these pins. Table 3. TAS5142 Warning/Error Signal Decoding OTW SD 0 0 High-temperature error and/or high-current error Device Condition 0 1 High-temperature warning 1 0 Undervoltage lockout or high-current error 1 1 Normal operation, no errors/warnings The temperature warning signals at the TAS5142DDV6EVM2 board are wired-OR to one temperature warning signal (OTW - pin 22 in control interface connector). Shutdown signals are wired-OR into one shutdown signal (SD - pin 20 in control interface connector). The shutdown signals, together with the temperature warning signal, give chip state information as described in Table 3. Device fault-reporting outputs are open-drain outputs. SLLU095 - March 2007 Submit Documentation Feedback TAS5142DDV6EVM2 9 www.ti.com TAS5142DDV6EVM Performance 4 TAS5142DDV6EVM Performance Table 4. General Test Conditions General Test Conditions Notes Output stage supply voltage 32 V Laboratory power supply (EA-PS 7065-10A) System supply voltage 15 V 4 Load Impedance Input signal 1-kHz sine Sampling frequency 48 kHz Gain setting in TAS5086 0 dB AES17 and AUX-0025 Measurement filter TI input-USB board Input-USB Rev 9 S/N:898 EVM configuration file Ver 2.00 TAS5142DDV6EVM2 Configuration (2.00).cfg Table 5. TAS5086 Register Settings (1) Register Name Register Number Value Notes Oscillator trim register 0x1B 0x00 Initiate oscillator to factory trim Master volume register 0x07 0x30 Set volume to 0 dB Modulation limit register 0x10 0x04 Set maximum modulation to 96.1% Split-capacitor charge period register 0x1A 0x00 No split-capacitor charge period PWM start register 0x18 0x30 Input mux register 0x20 00 01 23 45 PWM mux register 0x25 00 01 23 45 System control register 0x05 0x20 (1) These register settings are used for all tests, unless otherwise specified. Table 6. Electrical Data Electrical Data Output power, 4 80 W 1 kHz, unclipped (0 dBFS), TA = 25C Output power, 4 100 W 1 kHz, 10% THD+N, TA = 25C Maximum peak current >10 A 1-kHz burst, 1 , ROC = 22 k Output stage efficiency Damping factor 83% 1 kHz, 2 x 100 W, 4 12 1 kHz, relative to 8- load System supply current <200 mA 1-kHz, -60-dBFS signal, with TI input board H-bridge supply current <250 mA 1-kHz, -60-dBFS signal Total board idle power consumption 10 Notes/Conditions TAS5142DDV6EVM2 11 W H-bridge supply + system supply, -60-dBFS signal SLLU095 - March 2007 Submit Documentation Feedback www.ti.com TAS5142DDV6EVM Performance Table 7. Audio Performance Audio Performance Notes/Conditions THD+N, 4 1W < 0.08% 1 kHz THD+N, 4 10 W < 0.15% 1 kHz THD+N, 4 80 W < 0.25% 1 kHz Dynamic range > 105 dB Ref: rated power, A-weighted, AES17 filter, 6-ch average < 85 Vrms A-weighted, AES17 Noise voltage Click/pop < 20 mV Mute/unmute, no signal, 4 Channel separation > 58 dB 1 kHz 1 dB 80 W/4 , unclipped (0 dBFS) Frequency response: Table 8. Thermal Specification THEATSINK (1) Thermal Specification Notes/Conditions Idle, all channels switching 40C 1 kHz, 15 min, -60-dBFS signal, TA = 25C 4 x 10 W, 4 + 2 x 21 W , 4 (1/8 power) 68C 1 kHz, 1 h, TA = 25C 2 x 80 W, 4 83C 1 kHz, 5 min, TA = 25C (1) Measured on surface of heat sink Table 9. Physical Specifications Physical Specifications Notes/Conditions 115 x 135 x 50 Width x length x height (mm) PCB dimensions Total weight 330 g Components + PCB + heat sink + mechanics Note: All electrical and audio specifications are typical values. 20 10 5 5 2 2 1 1 THD + N - % THD + N - % 10 20 Gain = 2.5 dB 0.5 0.2 0.1 Gain = 2.5 dB 0.5 0.2 0.1 0.05 0.05 0.02 0.02 0.01 0.01 0.006 0.1 0.2 0.004 0.5 1 2 5 10 20 50 100 0.2 0.5 1 2 5 10 20 50 100 Power - W Power - W G001 Figure 4. THD+N vs Power (4 ) SLLU095 - March 2007 Submit Documentation Feedback G002 Figure 5. THD+N vs Power (6 ) TAS5142DDV6EVM2 11 www.ti.com TAS5142DDV6EVM Performance 20 20 Gain = 2.5 dB 10 5 5 2 2 1 1 THD + N - % THD + N - % 10 0.5 0.2 0.1 77 W 0.5 0.2 0.1 10 W 0.05 0.05 0.02 0.02 0.01 0.01 0.005 0.003 0.005 0.003 0.2 0.5 1 5 2 10 20 50 100 20 Power - W 20 20 10 10 5 5 2 2 1 1 58 W 0.2 0.1 0.05 2k 5k 10k 20k G004 0.5 46 W 0.2 0.1 0.05 0.02 0.01 0.02 1W 1W 0.01 0.005 0.003 10 W 0.005 0.003 20 50 100 200 500 1k 2k 5k 10k 20k f - Frequency - Hz Figure 8. THD+N vs Frequency (6 ) 12 500 1k Figure 7. THD+N vs Frequency (4 ) THD + N - % THD + N - % Figure 6. THD+N vs Power (8 ) 10 W 50 100 200 f - Frequency - Hz G003 0.5 1W TAS5142DDV6EVM2 G005 20 50 100 200 500 1k 2k 5k 10k 20k f - Frequency - Hz G006 Figure 9. THD+N vs Frequency (8 ) SLLU095 - March 2007 Submit Documentation Feedback www.ti.com TAS5142DDV6EVM Performance 0 0 VREF = 18.3 V FFT Size = 16k -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 -70 dBr A dBr A VREF = 18.3 V FFT Size = 16k -10 -80 -90 -70 -80 -90 -100 -100 -110 -120 -110 -130 -120 -140 -130 -150 -140 0 2 4 6 8 10 12 14 16 18 20 f - Frequency - kHz 0 22 10 20 30 40 50 60 70 80 f - Frequency - kHz G007 Figure 10. FFT Spectrum With -60 dBFS Tone G008 Figure 11. Idle Noise FFT Spectrum Channel separation is tested for two channels, channel 1 and channel 2. Both channels use 4- loads. The channel 1 input signal is 0 dBFS; channel 2 is muted. Reference voltage is 18.3 Vrms. 20 10 10 8 0 6 Channel 1 -10 4 -20 2 dBr A -30 dBr A 8W -40 -50 0 -2 6W -60 -4 Channel 2 -70 4W -6 -80 -8 -90 -100 -10 20 50 100 200 500 1k 2k 5k 10k 20k f - Frequency - Hz Figure 12. Channel Separation SLLU095 - March 2007 Submit Documentation Feedback G009 20 50 100 200 500 1k 2k 5k 10k 20k f - Frequency - Hz G010 Figure 13. Frequency Response TAS5142DDV6EVM2 13 www.ti.com Peak Current - A TAS5142DDV6EVM Performance 20 17.5 15 12.5 10 7.5 5 2.5 0 -2.5 -5 -7.5 -10 -12.5 -15 -17.5 -20 RL = 1 W 0 500m 1m 1.5m 2m 2.5m 3m t - Time - s G011 Figure 14. High Current Protection No input signal is applied. Load is 4 . 20 16 12 Voltage - V 8 4 0 -4 -8 -12 -16 RL = 4 W -20 0 500m 1m 1.5m 2m 2.5m t - Time - s 3m 3.5m 4m G012 Figure 15. Pop/Click 14 TAS5142DDV6EVM2 SLLU095 - March 2007 Submit Documentation Feedback www.ti.com TAS5142DDV6EVM Performance Efficiency is tested with 2 channels loaded at 4 . The board has been preheated for 1 hour at 1/8 output power. 100 RL = 4 W 90 80 Efficiency - % 70 60 50 40 30 20 10 0 0 20 40 60 80 100 120 140 160 180 200 220 PO - 2-CH Output Power - W G013 Figure 16. Output Stage Efficiency SLLU095 - March 2007 Submit Documentation Feedback TAS5142DDV6EVM2 15 www.ti.com Related Documentation from Texas Instruments 5 Related Documentation from Texas Instruments The following table contains a list of data manuals that have detailed descriptions of the integrated circuits used in the design of the TAS5142DDV6EVM2. The data manuals can be obtained at the URL http://www.ti.com. 5.1 Literature Number TAS5086 SLES131 TAS5142 SLES126 TPS3825-33 SLVS165 TPS76433 SLVS180 UA78M12 SLVS059 Additional Documentation 1. 2. 3. 4. 5. 6. 7. 8. 9. 16 Part Number PC Configuration Tool for TAS5086 (TAS5086 GUI version 4.0 or later), on the PurePath CD-ROM System Design Considerations for True Digital Audio Power Amplifiers (SLAA117) Digital Audio Measurements (SLAA114) PSRR for PurePath Digital Audio Amplifiers (SLEA049) Power Rating in Audio Amplifier (SLEA047) PurePath Digital AM Interference Avoidance (SLEA040) Click and Pop Measurements Technique (SLEA044) Power Supply Recommendations for DVD-Receivers (SLEA027) Implementation of Power Supply Volume Control (SLEA038) TAS5142DDV6EVM2 SLLU095 - March 2007 Submit Documentation Feedback SLLU095 - March 2007 Submit Documentation Feedback TAS5142DDV6EVM2 Mass Market Evaluation Module A799-SCH-001.DSN 5.00 21.Nov. 2006 Tomas Bruunshuus (tbs@ti.com), Jonas Holm (jlh@ti.com) 6 x 4 ohm Speaker Loads +32V H-Bridge and +15V System Power Supplies 6 x 100W/4ohm (BTL) - all 10% THD+N 100dB Dynamic Range Setup: Performance: Copyright 2005 Texas Instruments, Inc - All rights reserved - The TI and PurePath Digital logos are trademarks of Texas Instruments. Page 1/7: Front Page and Schematic Disclaimer 2/7: Overview - Modulator, Input/Output and Headphone/Line Output Connectors 3/7: 4 Channel BTL Power Stage (FL and C) 4/7: 2 Channel BTL Power Stage (FR and RL) 5/7: 2 Channel BTL Power Stage (RR and LFE SW) 6/7: Power Supplies 7/7: Mechanics J40: 34 pin IDC Header for Control, I2C and +5V J60: 16 pin IDC Header for I2S Audio J101-J106: 2 pin 3.96mm Headers for Speakers J901: 4 pin 3.96mm Header for H-Bridge and System Power Supply Interfaces: SCHEMATIC DISCLAIMER 9.) THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE. 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Accordingly, neither TI nor its suppliers warrant the accuracy or completeness of the information, text, graphics, links or other items contained within the Materials. TI may make changes to the Materials, or to the products described therein, at any time without notice. TI makes no commitment to update the Materials. 1.) These evaluation schematics are intended for use for ENGINEERING DEVELOPMENT AND EVALUATION PURPOSES ONLY and are not considered by Texas Instruments to be fit as a basis for establishing production products or systems. This information may be incomplete in several respects, including but not limited to information relating to required design, marketing, and/or manufacturing-related protective considerations and product safety measures typically found in the end-product incorporating the goods. The schematic information and materials ("Materials") provided here are provided by Texas Instruments Incorporated ("TI") as a service to its customers and/or suppliers, and may be used for informational purposes only, and only subject to the following terms. By downloading or viewing these Materials, you are signifying your assent to these terms. A.1 Audio Configuration: 5.1 PurePath Digital Amplifier Design 1 x TAS5086, 3 x TAS5142DDV Design Name: Type: File Name: Version: Date: Design Engineer: TI NOTE1 www.ti.com Appendix A Design Documents TAS5142DDV6EVM2 Schematic Figure A-1. TAS5142DDV6EVM2 Schematic (Sheet 1 of 7) Design Documents 17 J60 J40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 GND GND R45 10k R48 10k R46 10k R47 10k R69 10k R70 10k R71 10k R72 10k R73 10k R68 10k R67 10k +5V 1 2 R43 10k 1 R44 10k 1 2 1 2 34 pins IDC Box header 16 pins IDC Box header 1 1 2 2 1 1 2 1 2 2 1 2 R58 47R 1 1 47R 2 47R 2 47R 2 47R 2 47R 2 47R 2 47R 2 R75 1 R61 1 R62 1 R63 1 R64 1 R65 1 R66 1 2 47R R57 1 47R 2 R56 1 2 47R R55 1 47R 2 2 2 1 R54 1 R60 R74 47R 47R 2 LRCLK SCLK SDIN4 SDIN3 SDIN2 SDIN1 MCLK /TW /SD SCL SDA /MUTE /PDN /RESET C10 10nF 0603 C11 100nF 0603 R10 220R 1 1 2 2 1 1 2 2 C21 100nF 0603 C12 100nF 0603 R11 220R 1 +3.3V 2 1 GND MCLK +3.3V VDD_Protect VDD Protect VDD_Protect Error Latch 1 2 2 1 2 Q50 100k 0603 R53 1 R18 18.0k GND C14 100nF 0603 1 1 1 2 9 8 7 6 5 4 3 2 1 R52 1.0k 0603 2 2 GND R42 10k 1 19 18 17 16 15 14 13 12 11 10 R40 10k 100nF 0603 10603 1 C50 R50 3.3R 0603 Q40 BC857AF C17 100nF 0603 BC857AF GVDD /RESET LRCLK SCL SDA /MUTE C22 100nF 0603 /PDN /RESET_MODULATOR C13 10nF 0603 GND 2 1 2 1 2 1 1 2 2 1 2 2 1 2 1 2 2 3 1 2 2 R51 1.0k 0603 C41 10nF 0603 1 C40 10nF 0603 GND C51 10uF 16V c2_0pd5_0 Q41 BC847 R41 10k TAS5086DBT LRCLK SCL SDA MUTE VR_OSC OSC_RES DVSS_OSC DVSS DVDD PDN RESET MCLK GND PLL_FLTP PLL_FLTM AVSS_GR AVSS AVDD VR_ANA U10 1 2 1 2 +3.3V R76 10k 2 3 2 1 1 2 3 2 1 2 VDD SCLK STEST SDOUT SDIN4 SDIN3 SDIN2 SDIN1 BKND_ERR VREG_EN DVSS_ESD VR_DIG VALID1 VALID2 PWM_6 PWM_5 PWM_4 PWM_3 /SD 20 21 SCLK SDIN4 22 SDIN3 SDIN1 /SD 23 2 24 10k C26 100nF R19 0603 1 /VALID1 SDIN2 GND +3.3V /VALID2 25 26 27 28 29 30 31 32 33 34 35 36 37 38 GND PWM_2 PWM_1 C25 100nF 0603 1 2 Design Documents 1 18 2 TAS5142DDV6EVM2 /SD /SD /SD /RESET /RESET_MODULATOR Power Supplies /RESET_MODULATOR /RESET Output Stage BTL VDD /TW VDD /SD /RESET_CD /RESET_AB /TW /VALID1 PWM_C PWM_A CHANNEL 5-6 Output Stage BTL VDD /TW VDD /SD /RESET_CD /RESET_AB /TW /VALID2 PWM_C PWM_A CHANNEL 3-4 Output Stage BTL VDD /TW VDD /SD /RESET_CD /RESET_AB /TW /VALID2 PWM_C PWM_A CHANNEL 1-2 +3.3V +5V GVDD PVDD OUT_D OUT_C OUT_B OUT_A GVDD PVDD OUT_D OUT_C OUT_B OUT_A GVDD PVDD OUT_D OUT_C OUT_B OUT_A GVDD PVDD +3.3V +5V GVDD PVDD GVDD PVDD GVDD PVDD GVDD PVDD 2 1 2 1 J103 J102 J105 J101 J106 J104 2 1 2 1 2 1 2 1 OUTPUT S002 CH 6 SPEAKER OUTPUT LFE SUBWOOFER OUTPUT REAR RIGHT CH 4 SPEAKER CH 3 SPEAKER OUTPUT REAR LEFT OUTPUT FRONT RIGHT CH 2 SPEAKER CENTER CH 5 SPEAKER CH 1 SPEAKER OUTPUT FRONT LEFT www.ti.com TAS5142DDV6EVM2 Schematic Figure A-2. TAS5142DDV6EVM2 Schematic (Sheet 2 of 7) SLLU095 - March 2007 Submit Documentation Feedback /SD M2 L L H H M1 L H L H Type 2xBTL 2xBTL 2xBTL 1xPBTL Mode Table GVDD VDD /RESET_CD /RESET_AB Description Full Protection, 2N+2 mode No OLP - Latching Shutdown, 2N + 2, No Pulse Stretcher Full Protection, 1N + 2 mode Full Protection, 1N + 2 mode (PBTL) GND PWM_A GND C104 100nF 0603 PWM_C C102 100nF 0603 R105 22k 0603 2 1 GND 1 2 1 2 /TW 1 2 C101 100nF 0603 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GND_B OUT_B PWM_B OC_ADJ OUT_D RESET_CD GND C105 100nF 0603 TAS5142DDV GVDD_C VDD NC NC GVDD_D BST_D NC PVDD_D PVDD_D GND_D PWM_C PWM_D GND_C OUT_C PVDD_C BST_C BST_B M1 M2 M3 VREG AGND PVDD_B GND_A RESET_AB GND OUT_A PVDD_A PVDD_A NC BST_A GVDD_A PWM_A SD NC NC OTW GVDD_B U100 GND 40 23 24 25 26 27 28 29 30 31 GND 2 0603 25V 2 0603 25V 2 0603 25V C107 0603 33nF 25V 1 2 C108 33nF 32 GND 1 33 34 C109 33nF 1 35 36 37 38 39 GND C110 33nF 42 41 1 43 44 1 2 1 GND GND GND GND LAYOUT NOTE PLACE ON COMPONENT SIDE C119 100nF 0603 50V C117 100nF 0603 50V C115 100nF 0603 50V C113 100nF 0603 50V L171 L170 L130 10uH 2 2 2 2 2 2 L173 L172 2 2 Kwang Sung 8020P-02-100L L151 10uH Kwang Sung 8020P-02-100L L150 10uH Kwang Sung 8020P-02-100L L131 10uH Kwang Sung 8020P-02-100L LAYOUT NOTE Lx72 AND Lx73 ARE A TRACK IN THE PCB. W: TBD MM L: TBD MM 1 1 1 1 1 1 LAYOUT NOTE Lx72 AND Lx73 ARE A TRACK IN THE PCB. W: TBD MM L: TBD MM 1 1 1 2 1 2 470nF C152 470nF C132 C154 100nF 0805 50V C153 100nF 0805 50V C134 100nF 0805 50V C133 100nF 0805 50V 1 2 1 2 1 GVDD 1 2 GND GND R155 10k 0603 R135 10k 0603 R134 10k 0603 R154 10k 0603 1 2 1 2 1 2 1 2 1 2 2 C160 1nF 0603 50V C159 1nF 0603 50V C140 1nF 0603 50V C139 1nF 0603 50V 1 2 1 2 1 2 1 2 2 1 2 1 2 1 2 GND GND 470uF C174 GND 470uF C175 LAYOUT NOTE: EMI SNUBBER PLACE NEAR SPEAKER PINS R153 3.3R 0603 C156 10nF 0603 50V C155 10nF 0603 50V R152 3.3R 0603 LAYOUT NOTE: EMI SNUBBER PLACE NEAR SPEAKER PINS R133 3.3R 0603 C136 10nF 0603 50V C135 10nF 0603 50V R132 3.3R 0603 1 1 2 2 1 1 2 2 1 1 2 2 1 1 2 2 1 SLLU095 - March 2007 Submit Documentation Feedback 2 POWER OUTPUT STAGE (BTL) S003 PVDD OUT_D OUT_C OUT_B OUT_A PVDD www.ti.com TAS5142DDV6EVM2 Schematic Figure A-3. TAS5142DDV6EVM2 Schematic (Sheet 3 of 7) Design Documents 19 /SD M2 L L H H M1 L H L H Type 2xBTL 2xBTL 2xBTL 1xPBTL Mode Table GVDD VDD /RESET_CD /RESET_AB Description Full Protection, 2N+2 mode No OLP - Latching Shutdown, 2N + 2, No Pulse Stretcher Full Protection, 1N + 2 mode Full Protection, 1N + 2 mode (PBTL) GND PWM_A GND C204 100nF 0603 PWM_C C202 100nF 0603 R205 22k 0603 2 1 GND 1 2 1 2 /TW 1 2 C201 100nF 0603 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GND_B OUT_B PWM_B OC_ADJ OUT_D RESET_CD GND C205 100nF 0603 TAS5142DDV GVDD_C VDD NC NC GVDD_D BST_D NC PVDD_D PVDD_D GND_D PWM_C PWM_D GND_C OUT_C PVDD_C BST_C BST_B M1 M2 M3 VREG AGND PVDD_B GND_A RESET_AB GND OUT_A PVDD_A PVDD_A NC BST_A GVDD_A PWM_A SD NC NC OTW GVDD_B U200 GND 40 23 24 25 26 27 28 29 30 31 GND 2 0603 25V 2 0603 25V 2 0603 25V C207 0603 33nF 25V 1 2 C208 33nF GND 1 33 32 34 C209 33nF 1 35 36 37 38 39 GND C210 33nF 41 1 43 44 42 1 2 1 GND GND GND GND LAYOUT NOTE PLACE ON COMPONENT SIDE C219 100nF 0603 50V C217 100nF 0603 50V C215 100nF 0603 50V C213 100nF 0603 50V L271 L270 L230 10uH 2 2 2 2 2 2 L273 L272 2 2 Kwang Sung 8020P-02-100L L251 10uH Kwang Sung 8020P-02-100L L250 10uH Kwang Sung 8020P-02-100L L231 10uH Kwang Sung 8020P-02-100L LAYOUT NOTE Lx72 AND Lx73 ARE A TRACK IN THE PCB. W: TBD MM L: TBD MM 1 1 1 1 1 1 LAYOUT NOTE Lx72 AND Lx73 ARE A TRACK IN THE PCB. W: TBD MM L: TBD MM 1 1 1 2 1 2 470nF C252 470nF C232 C254 100nF 0805 50V C253 100nF 0805 50V C234 100nF 0805 50V C233 100nF 0805 50V 1 2 1 2 1 GVDD 1 2 GND GND R255 10k 0603 R235 10k 0603 R234 10k 0603 R254 10k 0603 1 2 1 2 1 2 1 2 1 2 2 C260 1nF 0603 50V C259 1nF 0603 50V C240 1nF 0603 50V C239 1nF 0603 50V 1 2 1 2 1 2 1 2 2 1 2 1 2 1 2 GND GND 470uF C274 GND 470uF C275 LAYOUT NOTE: EMI SNUBBER PLACE NEAR SPEAKER PINS R253 3.3R 0603 C256 10nF 0603 50V C255 10nF 0603 50V R252 3.3R 0603 LAYOUT NOTE: EMI SNUBBER PLACE NEAR SPEAKER PINS R233 3.3R 0603 C236 10nF 0603 50V C235 10nF 0603 50V R232 3.3R 0603 1 1 2 2 1 1 2 2 1 1 2 2 1 1 2 2 Design Documents 1 20 2 POWER OUTPUT STAGE (BTL) S004 PVDD OUT_D OUT_C OUT_B OUT_A PVDD www.ti.com TAS5142DDV6EVM2 Schematic Figure A-4. TAS5142DDV6EVM2 Schematic (Sheet 4 of 7) SLLU095 - March 2007 Submit Documentation Feedback /SD M2 L L H H M1 L H L H Type 2xBTL 2xBTL 2xBTL 1xPBTL Mode Table GVDD VDD /RESET_CD /RESET_AB Description Full Protection, 2N+2 mode No OLP - Latching Shutdown, 2N + 2, No Pulse Stretcher Full Protection, 1N + 2 mode Full Protection, 1N + 2 mode (PBTL) GND PWM_A GND C304 100nF 0603 PWM_C C302 100nF 0603 R305 22k 0603 2 1 GND 1 2 1 2 /TW 1 2 C301 100nF 0603 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GND_B OUT_B PWM_B OC_ADJ OUT_D RESET_CD GND C305 100nF 0603 TAS5142DDV GVDD_C VDD NC NC GVDD_D BST_D NC PVDD_D PVDD_D GND_D PWM_C PWM_D GND_C OUT_C PVDD_C BST_C BST_B M1 M2 M3 VREG AGND PVDD_B GND_A RESET_AB GND OUT_A PVDD_A PVDD_A NC BST_A GVDD_A PWM_A SD NC NC OTW GVDD_B U300 GND 40 23 24 25 26 27 28 29 30 31 GND 2 0603 25V 2 0603 25V 2 0603 25V C307 0603 33nF 25V 1 2 C308 33nF 32 GND 1 33 34 C309 33nF 1 35 36 37 38 39 GND C310 33nF 42 41 1 43 44 1 2 1 GND GND GND GND LAYOUT NOTE PLACE ON COMPONENT SIDE C319 100nF 0603 50V C317 100nF 0603 50V C315 100nF 0603 50V C313 100nF 0603 50V L371 L370 L330 10uH 2 2 2 2 2 2 L373 L372 2 2 Kwang Sung 8020P-02-100L L351 10uH Kwang Sung 8020P-02-100L L350 10uH Kwang Sung 8020P-02-100L L331 10uH Kwang Sung 8020P-02-100L LAYOUT NOTE Lx72 AND Lx73 ARE A TRACK IN THE PCB. W: TBD MM L: TBD MM 1 1 1 1 1 1 LAYOUT NOTE Lx72 AND Lx73 ARE A TRACK IN THE PCB. W: TBD MM L: TBD MM 1 1 1 2 1 2 470nF C352 470nF C332 C354 100nF 0805 50V C353 100nF 0805 50V C334 100nF 0805 50V C333 100nF 0805 50V 1 2 1 2 1 GVDD 1 2 GND GND R355 10k 0603 R335 10k 0603 R334 10k 0603 R354 10k 0603 1 2 1 2 1 2 1 2 1 2 2 C360 1nF 0603 50V C359 1nF 0603 50V C340 1nF 0603 50V C339 1nF 0603 50V 1 2 1 2 1 2 1 2 2 1 2 1 2 1 2 GND GND 470uF C374 GND 470uF C375 LAYOUT NOTE: EMI SNUBBER PLACE NEAR SPEAKER PINS R353 3.3R 0603 C356 10nF 0603 50V C355 10nF 0603 50V R352 3.3R 0603 LAYOUT NOTE: EMI SNUBBER PLACE NEAR SPEAKER PINS R333 3.3R 0603 C336 10nF 0603 50V C335 10nF 0603 50V R332 3.3R 0603 1 1 2 2 1 1 2 2 1 1 2 2 1 1 2 2 1 SLLU095 - March 2007 Submit Documentation Feedback 2 POWER OUTPUT STAGE (BTL) S005 PVDD OUT_D OUT_C OUT_B OUT_A PVDD www.ti.com TAS5142DDV6EVM2 Schematic Figure A-5. TAS5142DDV6EVM2 Schematic (Sheet 5 of 7) Design Documents 21 SCREW631 M3x6 WASHER631 M3 SCREW635 M3x6 WASHER635 M3 STANDOFF635 M3x10 SCREW630 M3x6 WASHER630 M3 SCREW634 M3x6 WASHER634 M3 STANDOFF634 M3x10 TIC-HSINK-044_2.00 HEATSINK630 M3x10 STANDOFF636 M3 WASHER636 M3x6 SCREW636 M3 WASHER632 M3x6 SCREW632 HEAT SINK M3x10 STANDOFF637 M3 WASHER637 M3x6 SCREW637 M3 WASHER633 M3x6 SCREW633 MH603 1 MH602 1 MH601 1 MH600 1 MH607 1 MH606 1 MH605 1 MH604 1 GND A799-PCB-001_4.00 PCB1 S007 PCB Header J901 Header 4 GND 4 3 2 1 GND GND GND R940 3.30R 0805 LAYOUT NOTE: EMI SNUBBER PLACE NEAR J901 PIN 2 C940 100nF 0805 50V 0805 GND LAYOUT NOTE: EMI SNUBBER PLACE TO THE RIGHT OF U100 C900 100nF 0805 50V 0805 R900 3.30R 0805 LAYOUT NOTE: EMI SNUBBER PLACE NEAR J900 PIN 1 C956 100nF 0805 50V 0805 R953 3.30R 0805 1 1 2 2 3 1 1 2 2 1 1 2 2 1 2 GND GND C907 330uF 35V c5_0pd10_0 LAYOUT NOTE: EMI SNUBBER PLACE TO THE LEFT OF U100 C952 100nF 0805 50V 0805 R951 3.30R 0805 /RESET_MODULATOR C941 10nF 0805 50V 0805 C901 10nF 0805 50V 0805 C957 10nF 0805 50V 0805 1 2 1 1 2 2 GND GND C953 10nF 0805 50V 0805 3 2 1 1 KTP IN U900 TPS3825-33 RESET GND RESET 4 3 2 BYPASS OUT ON/OFF GND VIN OUTPUT MR 4 5 +3.3V TPS76433 EN GND IN U907 VDD 3 2 1 3 C955 10nF 0805 50V 0805 UA78M12 OUT LM2594M-5V SO8 FB NC NC C908 100nF U901 0805 0805 1 NC C909 100nF 0805 0805 U908 C922 100nF 0805 0805 GND GND LAYOUT NOTE: EMI SNUBBER PLACE NEAR J901 PIN 1 C954 100nF 0805 50V 0805 R952 3.30R 0805 1 2 1 1 2 2 1 2 1 2 GND 2 R901 10.0k 1206 GND C910 100nF 0805 0805 GND /RESET 4 5 5 6 7 8 1 2 2 1 2 1 2 1 2 1 2 1 1 2 1 L900 220uH C925 10nF 0805 2 C911 100uF 16V c2_5pd6_3 D901 10MQ040N SMA 1 GND 2 J900 1 2 1 C923 100nF 0805 0805 2 MECHANICS 1 2 C915 100nF 0805 0805 GND 1 +5V GVDD PVDD S006 +3.3V C913 100uF 16V c2_5pd6_3 10uF c2_0pd5_0 C924 GND 2 Design Documents 1 22 2 POWER SUPPLIES www.ti.com TAS5142DDV6EVM2 Schematic Figure A-6. TAS5142DDV6EVM2 Schematic (Sheet 6 of 7) Figure A-7. TAS5142DDV6EVM2 Schematic (Sheet 7 of 7) SLLU095 - March 2007 Submit Documentation Feedback www.ti.com TAS5142DDV6EVM2 Parts List A.2 TAS5142DDV6EVM2 Parts List Table A-1. Parts List Part Reference QTY Decription C10 C13 C40 C41 C135 C136 C155 C156 C235 C236 C255 C256 C335 C336 C355 C356 16 Ceramic 10-nF, 50-V, 20% X7R 0603 capacitor BC Components 0603B103M500NT C11 C12 C14 C17 C21 C22 C25 C26 C50 C101 C102 C104 C105 C201 C202 C204 C205 C301 C302 C304 C305 21 Ceramic 100-nF, 16-V, 20% X7R 0603 capacitor BC Components 0603B104M160NT C51 C924 2 Electrolytic 10-F, 16-V, 20% aluminium 2-mm o5-mm M-series general-purpose capacitor Pansonic ECA1CM100 C107 C108 C109 C110 C207 C208 C209 C210 C307 C308 C309 C310 12 Ceramic 33-nF, 25-V, 20% X7R 0603 capacitor BC Components 0603B333M250NT C113 C115 C117 C119 C213 C215 C217 C219 C313 C315 C317 C319 12 Ceramic 100-nF, 50-V, 20% X7R 0603 capacitor Vishay VJ0603Y104MXATW1BC C132 C152 C232 C252 C332 C352 6 Metal film 470-nF, 63-V, 10% polyester 5-mm (W: 4,5 mm L: 7,2 mm) capacitor Wima MKS 2 0.47uF/105/63Vdc PCM5 C133 C134 C153 C154 C234 C253 C254 C333 C353 C354 C900 C908 C910 C915 C922 C923 C952 C954 C956 23 Ceramic 100-nF, 50-V, 20% X7R 0805 capacitor BC Components 0805B104M500NT C139 C140 C159 C160 C239 C240 C259 C260 C339 C340 C359 C360 12 Ceramic 1-nF, 50-V, 10% NP0 0603 capacitor BC Components 0603N102K500NT C174 C175 C274 C275 C374 C375 6 Electrolytic 470-F, 35-V, 20% aluminium 5-mm Pansonic o10 mm FC-series low-impedance capacitor EEUFC1V471 C901 C925 C941 C953 C955 C957 6 Ceramic 10-nF, 50-V, 20% X7R 0805 capacitor BC Components 0805B103M500NT C907 1 Electrolytic 330-F, 35-V 20% aluminium 5-mm o10-mm FC-series low-impedance capacitor Pansonic EEUFC1V331 C911 C913 2 Electrolytic 100-F, 16-V, 20% aluminium 2,5-mm o6,3 mm ultramini-series capacitor Sang Jing Electronics UMR16V107M6.3X5 D901 1 1-A, 40-V Schottky diode (SMA) International Rectifier 10MQ040N HEATSINK630 1 Heat sink for 3 DDV packages, length 110 mm THF-Teknik TIC-HSINK-044(2.00) J40 1 34 pins/2 rows/2,54-mm pitch vertical male IDC Molex 87256-3411 J60 1 16 pins/2 rows/2,54-mm pitch vertical male IDC Molex 87256-1611 J101 J102 J103 J104 J105 J106 6 2 pins/1 row/3,96-mm pitch vertical male pin header JST BEP-VH J900 J901 2 4 pins/1 row/3,96-mm pitch vertical male pin header JST B4P-VH L130 L131 L150 L151 L230 L231 L250 L251 L330 L331 L350 L351 12 10-H ferrite inductor Kwang Sung 8020P-02-100L L900 1 220 H, 0.5-A, 20% (390mR) magnetically shielded ferrite inductor Coil Craft DT3316P-224 PCB1 1 TAS5142DDV6EVM2 printed circuit board (version 4.00) - Allegro Printline A799-PCB-001(4.00) Q40 Q50 2 100-mA, 45-V PNP small signal transistor (SOT-23) Philips 9335 897 40215 Q41 1 100-mA, 45-V NPN small-signal transistor (SOT-23) Philips 9335 895 70215 C233 C334 C909 C940 SLLU095 - March 2007 Submit Documentation Feedback Manufacture First MFR P/N Design Documents 23 www.ti.com TAS5142DDV6EVM2 Parts List Table A-1. Parts List (continued) Part Reference QTY Decription Manufacture First MFR P/N R10 R11 2 220-, 100-mW 5% 0603 metal film resistor BC Components DCT 0603 5% 220R R18 1 18.0-k, 100-mW, 1% 0603 metal film resistor BC Components DCT 0603 1% 18k0 R19 R40 R41 R42 R43 R44 R45 R46 R47 R48 R67 R68 R69 R70 R71 R72 R73 R76 R134 R135 R154 R155 R234 R235 R254 R255 R334 R335 R354 R355 30 10-k, 100-mW, 5% 0603 metal film resistor BC Components DCT 0603 5% 10k0 R50 R132 R133 R152 R153 R232 R233 R252 R253 R332 R333 R352 R353 13 3.3-, 100-mW, 5% 0603 metal film resistor BC Components DCT 0603 5% 3R30 R51 R52 2 1.0-k, 100-mW, 5% 0603 metal film resistor BC Components DCT 0603 5% 1k00 R53 1 100-k, 100-mW, 5% 0603 metal film resistor BC Components DCT 0603 5% 100k R54 R55 R56 R57 R58 R60 R61 R62 R63 R64 R65 R66 R74 R75 14 47-, 100-mW, 5% 0603 metal film resistor BC Components DCT 0603 5% 47R0 R105 R205 R305 3 22-k, 100-mW, 5% 0603 metal film resistor BC Components DCT 0603 5% 22k0 R900 R940 R951 R952 R953 5 3.30-, 125-mW, 1% 0805 metal film resistor BC Components DCU 0805 1% 3R30 R901 1 10.0-k, 250-mW, 1% 1206 metal film resistor BC Components DCA 1206 1% 10k0 SCREW630 SCREW631 SCREW632 SCREW633 SCREW634 SCREW635 SCREW636 SCREW637 8 M3x6, pan head, PozidrivTM, A2 screw Bossard BN 81882 M3x6 STANDOFF634 STANDOFF635 STANDOFF636 STANDOFF637 4 M3x10 aluminium standoff Ettinger 05.03.108 U10 1 6-ch PWM processor (SE, VOL, 192-kHz, I2S out) (TSSOP38) Texas Instruments TAS5086DBT U100 U200 U300 3 4-ch/2-ch/1-ch digital audio PWM power output stage (DDV44) Texas Instruments TAS5142DDV U908 1 3.3-V supply voltage supervisor (SOT23-5) Texas Instruments TPS3825-33DBVT U900 1 12-V, 500-mA positive voltage regulator (KTP) Texas Instruments UA78M12CKTPR LM2594M-5.0V U901 1 5-V, 0.5-A buck converter (SO8) National Semiconductor U907 1 3.3-V, 150-mA low-drop linear regulator (SOT23-5) Texas Instruments TPS76433DBVR WASHER630 WASHER631 WASHER632 WASHER633 WASHER634 WASHER635 WASHER636 WASHER637 8 M3 stainless steel spring washer Bossard BN 760 M3 24 Design Documents SLLU095 - March 2007 Submit Documentation Feedback www.ti.com TAS5142DDV6EVM2 PCB Specification (Version 4.00) A.3 TAS5142DDV6EVM2 PCB Specification (Version 4.00) Board identification: A799-PCB-001(4.00) Board type: Double-sided plated-through board Laminate type: FR4 Laminate thickness: 1,6 mm Copper thickness: 70 m (incl. plating exterior layer) Copper plating of holes: >25 m Minimum hole diameter : 0,3 mm Silkscreen, component side: White - remove silkscreen from solder area and pre-tinned areas Silkscreen, solder side: None Solder mask, component side: Green Solder mask solder side: Green Protective coating: Solder coating and chemical silver on free copper Electrical test: PCB must be electrically tested Manufactured to: PERFAG 2E (www.perfag.dk) Aperture table: PERFAG 10A (www.perfag.dk) Board size: 115 mm x 137 mm Comments: See drill information file (5140dri.plt.pdf). SLLU095 - March 2007 Submit Documentation Feedback Design Documents 25 www.ti.com TAS5142DDV6EVM2 PCB Layers A.4 TAS5142DDV6EVM2 PCB Layers K001 Figure A-8. Component Layout 26 Design Documents SLLU095 - March 2007 Submit Documentation Feedback www.ti.com TAS5142DDV6EVM2 PCB Layers K002 Figure A-9. Solder Side SLLU095 - March 2007 Submit Documentation Feedback Design Documents 27 www.ti.com TAS5142DDV6EVM2 PCB Layers K003 Figure A-10. Component Side 28 Design Documents SLLU095 - March 2007 Submit Documentation Feedback www.ti.com TAS5142DDV6EVM2 PCB Layers K004 Figure A-11. Component Placement SLLU095 - March 2007 Submit Documentation Feedback Design Documents 29 www.ti.com TAS5142DDV6EVM2 PCB Layers K005 Figure A-12. Silkscreen 30 Design Documents SLLU095 - March 2007 Submit Documentation Feedback www.ti.com Heat Sink Drawing A.5 Heat Sink Drawing A 2,0 mm [5plcs] 6,5 mm [4plcs] 38,1 mm 7,0 mm 3,0 mm 0,0 mm 1,6 mm 0,0 mm 11,5 mm 14,0 mm 22,0 mm 24,5 mm 36,0 mm A Cross section A-A 5,0 mm 1,02 mm 0,01 mm 0 mm 0 mm 16,9 mm 20,9 mm 38,3 mm 46,3 mm 42,3 mm 63,7 mm 71,7 mm 67,7 mm 89,1 mm 93,1 mm 110,0 mm Flatness: 0.001 MACHINE THESE EDGES AFTER ANODIZING PROFILE: TIC-HSINK-043 profile (1.00) MATERIAL: ALUMINIUM INTERNAL SCREW THREADS: M3 SURFACE: FREE OF SHARP EDGES SURFACE TREATMENT: BLACK ANODIZED TOLERANCES: 0,1 mm M0079-01 Figure A-13. Heat Sink SLLU095 - March 2007 Submit Documentation Feedback Design Documents 31 EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards. 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